WO2014201715A1 - 薄膜晶体管阵列基板及其沟道形成方法 - Google Patents

薄膜晶体管阵列基板及其沟道形成方法 Download PDF

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WO2014201715A1
WO2014201715A1 PCT/CN2013/078223 CN2013078223W WO2014201715A1 WO 2014201715 A1 WO2014201715 A1 WO 2014201715A1 CN 2013078223 W CN2013078223 W CN 2013078223W WO 2014201715 A1 WO2014201715 A1 WO 2014201715A1
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amorphous silicon
film transistor
space
thin film
array substrate
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French (fr)
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许宗义
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a thin film transistor array substrate and a channel forming method thereof.
  • Thin Film Transistor TFT has been widely used in the driving of active liquid crystal displays, and the silicon thin film materials used according to thin film transistors are generally of two types, amorphous-silicon and poly-silicon.
  • polysilicon materials have many properties superior to amorphous silicon materials.
  • Polycrystalline silicon has a larger grain, so that electrons are easily free to move in polycrystalline silicon, so the mobility of polycrystalline silicon is higher than that of amorphous silicon.
  • a thin film transistor made of polysilicon has a faster reaction time than an amorphous silicon thin film transistor.
  • a polysilicon thin film transistor (poly-Si) is used.
  • the substrate area occupied by the TFT can be smaller than the area of the substrate occupied by the amorphous silicon thin film transistor, and the aperture ratio of the liquid crystal panel is improved.
  • Liquid crystal display using polysilicon thin film transistor (poly-Si) under the same shell degree TFT LCD) can use a low wattage backlight to achieve low power consumption.
  • polycrystalline silicon thin films are mostly fabricated on a substrate using a low temperature polysilicon preparation process (Low Temperature). Poly-Silicon, LTPS).
  • the low temperature polysilicon preparation process is an excimer laser (Excimer) Laser) as a heat source.
  • Excimer laser Excimer
  • the amorphous silicon film absorbs the energy of the excimer laser and is converted into a polysilicon film.
  • Sequential Lateral Crystallization Solidification, SLS Sequential Lateral Crystallization Solidification, SLS
  • the upper temperature difference is used to achieve the lateral crystallization technique, and the laser is transmitted through the reticle to generate a laser of a specific shape.
  • the first laser first crystallizes the laterally grown crystal grains, and the second laser irradiation region overlaps with the first crystallization region.
  • the silicon film in the region irradiated by the second laser starts to melt, and the long crystalline columnar crystal particles are grown by using the first crystalline polycrystalline silicon film as a seed crystal.
  • the electron mobility of the TFT is high, for example, 300 cm 2 /V-s; however, if the channel length of the TFT is perpendicular to the grain boundary of the polysilicon film, the electron mobility of the TFT is greatly reduced to 100 cm 2 /V-s, Therefore, the SLS lateral crystallization technique in the prior art has a technical problem of electron mobility non-uniformity of the TFT.
  • the present invention constructs a channel forming method for a thin film transistor array substrate, wherein the method comprises the following steps:
  • Each of the amorphous silicon patterns forms a break space in the amorphous silicon pattern; the open space extends along a length direction, and the open space has a width perpendicular to the length direction, The width ranges from 1 to 3 microns;
  • the present invention also constructs a thin film transistor array substrate and a channel forming method thereof, the method comprising the following steps:
  • the present invention also constructs a thin film transistor array substrate, which includes:
  • the channel comprising:
  • the grain boundaries in the first crystallization zone and the second crystallization zone are both perpendicular to the interface between the first crystallization zone and the second crystallization zone.
  • the invention forms a disconnected space in the amorphous silicon layer, and the open space separates the amorphous silicon layer into the first interval and the second interval.
  • the grains of the first space and the second space will face Growing in the direction of the breaking space and intersecting in the breaking space, thereby crystallizing to form the first crystal region and the second crystal region, the grain boundaries in the first crystal region and the second crystal region and the first crystal region and the second crystal.
  • the interface between the regions is perpendicular, whereby the electron mobility of the channel can be improved and the electrical properties of the TFT are made uniform.
  • 1A-1M are schematic views showing a process of forming a channel by crystallization using an amorphous silicon film according to an embodiment of the present invention
  • FIGS. 2A to 2D are schematic views showing a process of forming a thin film transistor array substrate in accordance with a channel formed by the processes of Figs. 1A-1M.
  • FIG. 1A-1M are schematic diagrams showing processes of a channel forming method of a thin film transistor array substrate according to an embodiment of the present invention.
  • a substrate 100 is provided on which a buffer layer 101 (Buffer) is formed.
  • Buffer buffer layer 101
  • the substrate 100 is, for example, a glass substrate, a flexible plastic substrate, a wafer substrate, or a heat dissipation substrate.
  • the buffer layer 101 is preferably formed of silicon nitride (SiNx) or silicon oxide (SiO 2 ), and the buffer layer 101 mainly prevents impurities from diffusing from the substrate 100.
  • an amorphous silicon (a-Si:H) layer 102 is formed on the buffer layer 101.
  • the embodiment of the present invention preferably uses chemical vapor deposition (CVD) on the buffer layer 101.
  • the amorphous silicon layer 102 is deposited thereon, and a top view of the amorphous silicon layer 102 is shown in FIG. 1C.
  • the amorphous silicon layer 102 is subjected to a first etching process to form an amorphous silicon pattern.
  • FIG. 1D is a top view of the amorphous silicon layer 102 after the first etching process, wherein the substrate 100 having the buffer layer 101 and the amorphous silicon layer 102 defines a plurality of images thereon. a pixel region P and a plurality of TFT regions T, wherein the TFT region T is located at an angle of each pixel region P, and the amorphous silicon pattern after the first etching process includes a plurality of amorphous silicon layers 102 Each amorphous silicon layer 102 is located in the TFT region T.
  • the first etching referred to in the embodiment of the present invention may be dry etching or wet etching.
  • FIG. 1E is a schematic structural view of the amorphous silicon layer 102, wherein the amorphous silicon layer 102 is a bent structure.
  • the second etching process is continued on the amorphous silicon layer 102 after the first etching process to form a disconnection in each amorphous silicon layer 102 of the amorphous silicon layer pattern.
  • Space M is
  • FIG. 1G is a cross-sectional view taken along line G-G' of FIG. 1F
  • FIG. 1H is a top view of FIG. 1G
  • FIG. 1I is a partial enlarged view of FIG. 1H.
  • the breaking space M extends along the length direction D, and the breaking space has a width L perpendicular to the length direction D, and the width L preferably ranges from 1 to 3 um, and the breaking space M
  • the amorphous silicon layer 102 is divided into a first section 301 and a second section 302.
  • the secondary etching process may use dry etching, wet etching or laser etching, which will not be described in detail herein.
  • FIG. 1J the amorphous silicon layer 102 in which the open space M has been formed is subjected to laser irradiation treatment to form the channel 103. Please refer to FIGS. 1K, 1L, and 1M together.
  • the amorphous silicon layer corresponding to the first section 201 and the second section 202 on both sides of the disconnected space M under laser irradiation forms lateral crystal growth due to a temperature difference.
  • the dies of the first interval 201 and the second interval 202 adjacent to the disconnected space M are grown toward the disconnected space M, wherein the first interval 201 is adjacent to the The crystal grains of the disconnected space M are grown toward the disconnected space M (from left to right), and a first crystallized region N1 is formed in the disconnected space M; the second interval 202 is close to the disconnected space M The crystal grains are grown toward the disconnected space M (from right to left), and a second crystallized region N2 is formed in the disconnected space M.
  • the crystal grains of the first crystallization zone N1 and the second crystallization zone N2 meet at the central axis Q of the disconnection space M, stop growing and crystallize.
  • the grain boundaries of the grains in the first crystallization zone and the second crystallization zone N2 are perpendicular to the plane between the first crystallization zone N1 and the second crystallization zone N2, thereby greatly increasing
  • the electron mobility of the polysilicon layer formed thereafter ensures uniformity of electron mobility.
  • each of the channels 103 formed corresponds to the TFT regions T, and each of the channels 103 serves as an active layer in a thin film transistor (TFT).
  • TFT thin film transistor
  • the open space M separates the amorphous silicon layer 102 into the first interval 201 and the second interval 202, and the non-irradiation is performed by laser irradiation.
  • the grains in the first space 201 and the second space 202 close to the breaking space M will grow toward the opening space M and meet at the central axis Q of the breaking space M.
  • the scanning direction of the laser light is preferably perpendicular to the longitudinal direction D of the disconnected space M, or is parallel to the longitudinal direction of the disconnected space M, of course. It is also possible to have an angle with the longitudinal direction in the interval of 0 to 90 degrees.
  • the scanning pitch of the laser preferably ranges from 0 to 30 microns, and the scanning pitch is the distance between adjacent laser lines
  • FIGS. 2A to 2D show the processing steps of forming a thin film transistor array substrate in accordance with the polysilicon layer formed by the processes of Figs. 1A-1M.
  • a substrate 301 is provided on which a buffer layer 302 is formed.
  • the channel 303 is formed by the position where the thin film transistor (TFT) is to be formed in the TFT region by the steps 1A-1J.
  • the channel on the buffer layer 302 has a bent structure.
  • the channel is divided into an active region 303a, a source and a drain region 303b.
  • the source and the drain region 303b are disposed on both sides of the active region 303a.
  • a layer of silicon nitride or silicon oxide insulating material 304 is then formed over the buffer layer 301 to cover the channel 303.
  • a metallic conductive material is deposited on the insulating material 304.
  • the conductive material and the insulating material 304 are then patterned simultaneously to form a gate insulating layer 305 and a gate 306 continuously on the channel 303.
  • Impurities of p-type or n-type ions are then doped on the exposed portions of the channel 303, that is, the source and drain regions 303b.
  • the gate 306 acts as an ion plug to prevent impurities from penetrating into the active region 303a while doping impurities.
  • the source of the doping impurity and the drain region 303b are annealed after doping to activate ions doped in the source and drain regions 303b. Simultaneously performing the step of restoring the source and the drain region 303b to a polycrystalline state, avoiding that the semiconductor structure of the source and drain regions 303b may change from polycrystalline to amorphous due to excessive ion doping. .
  • an insulating layer 307 is formed on the entire surface of the substrate 301 to cover the gate electrode 306 and the gate insulating layer 305.
  • the insulating layer 307 is then patterned to form a first contact hole 308 and a second contact hole 309 that expose the source and the drain region 303b, respectively.
  • the insulating layer 307 may include silicon oxide and silicon nitride.
  • a metal layer is deposited on the insulating layer 307 and patterned to form a source 310 and a drain 311.
  • the source 310 contacts the source region 303b through the first contact hole 308, and the drain 311 contacts the drain region 303b through the second contact hole 309.
  • the source 310, the drain 311, the gate 306, and the channel 303 are commonly formed to form a thin film transistor.
  • the embodiment of the present invention further provides a thin film transistor array substrate.
  • the thin film transistor array substrate includes a substrate, a buffer layer formed on the substrate, and is formed in the A channel, a gate insulating layer, a gate, an insulating layer, a source, and a drain on the buffer layer.
  • the channel includes a first crystalline region and a second crystalline region; a grain boundary in the first crystalline region and the second crystalline region is between the first crystalline region and the second crystalline region
  • the interface is vertical.
  • the first crystallization zone and the second crystallization zone are formed by laser irradiation of an amorphous silicon layer on both sides of a disconnected space, the breaking space extending along a length direction, and a width perpendicular to the length direction
  • the width of the disconnected space ranges from 1 to 3 microns.
  • the channel further includes a third crystalline region and a fourth crystalline region, wherein the third crystalline region and the first crystalline region are formed of an amorphous silicon layer on the same side of the disconnected space;
  • the crystallization zone and the second crystallization zone are formed of an amorphous silicon layer on the other side of the disconnected space.
  • the amorphous silicon layer is separated into the first interval and the second interval by forming a disconnected space in the amorphous silicon layer, and the grains in the first space and the second space after being irradiated by the laser. Forming in the direction of the disconnected space and intersecting in the disconnected space, thereby crystallizing to form the first crystalline region and the second crystalline region, the grain boundaries in the first crystalline region and the second crystalline region and the first crystalline region and The interface between the two crystallization regions is perpendicular, whereby the electron mobility of the formed channel can be improved, and the electrical properties of the TFT are more uniform.

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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管阵列基板及其沟道（303）形成方法，对基板（100）上的非晶硅层（102）进行刻蚀处理形成非晶硅图形；在非晶硅图形中的每一非晶硅层（102）形成一断开空间（M）；进行激光照射使得断开空间（M）两侧的非晶硅层（102）内的晶粒在温度差的作用下朝着断开空间（M）方向生长，在断开空间（M）内结晶形成薄膜晶体管的沟道（303）。提高了沟道（303）的电子迁移率。

Description

薄膜晶体管阵列基板及其沟道形成方法 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种薄膜晶体管阵列基板及其沟道形成方法。
 背景技术
薄膜晶体管(Thin Film Transistor TFT)已广泛应用在主动式液晶显示器的驱动上，其中根据薄膜晶体管使用的硅薄膜材料通常有非晶硅（amorphous-silicon）与多晶硅(poly-silicon)两种类型。
在液晶显示器的制造中，多晶硅材料具有许多优于非晶硅材料的特性。多晶硅具有较大的晶粒(grain)，使得电子在多晶硅中容易自由移动，所以多晶硅的电子迁移率(mobility)高于非晶硅。以多晶硅制作的薄膜晶体管，其反应时间比非晶硅薄膜晶体管快。在相同分辨率的液晶显示器中，使用多晶硅薄膜晶体管(poly-Si TFT)所占用的基板面积可以比使用非晶硅薄膜晶体管所占用的基板面积小，而提高液晶面板的开口率。在相同的壳度下，使用多晶硅薄膜晶体管的液晶显示器(poly-Si TFT LCD)可以采用低瓦数的背光源，达到低耗电量的要求。
目前在基板上制作多晶硅薄膜大多利用低温多晶硅制备工艺(Low Temperature Poly-Silicon，LTPS)。低温多晶硅制备工艺是以准分子激光(Excimer Laser)作为热源。当激光照射(Irradiate)于具有非晶硅薄膜的基板上，非晶硅薄膜吸收准分子激光的能量而转变成为多晶硅薄膜。
依序侧向结晶(Sequential Lateral Solidification，SLS)技术为利用光罩或是其他方式造成在a-Si precursor 上温度高低差来达到侧向结晶技术,利用激光透过光罩产生特定形状的激光，第一道激光先结晶出侧向成长的晶粒后第二道激光照射区域与第一道结晶区域重叠一部份，通过照射非晶硅区域，第二道激光所照射区域的硅薄膜开始熔融后会以第一道结晶多晶硅薄膜为晶种成长出长柱状的结晶颗粒。
当TFT的沟道长度（channel length）平行于多晶硅薄膜的晶粒边界（grain boundary）时，电子迁移率较高，譬如为300cm2/V-s；但是如果TFT的沟道长度垂直于多晶硅薄膜的晶粒边界，则会使的TFT的电子迁移率大幅下降至100cm2/V-s, 因此现有技术中SLS侧向结晶技术有著TFT的电子迁移率不均匀性的技术问题。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列基板的沟道形成方法，旨在现有技术的TFT中沟道的电子迁移率不高、TFT电性不均匀性的技术问题。
 技术解决方案
本发明构造了一种薄膜晶体管阵列基板的沟道形成方法，其中所述方法包括以下步骤：
提供基板，在所述基板上形成非晶硅层；
对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形；
在所述非晶硅图形中的每一非晶硅层形成一断开空间；所述断开空间沿一长度方向延伸，所述断开空间具有一与所述长度方向垂直的宽度，所述宽度的范围为1~3微米；
对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于所述断开空间两侧的非晶硅层内的晶粒在温度差的作用下朝着所述断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道，其中所述激光的扫描间距的范围在0至30微米之间。
为解决上述技术问题，本发明还构造了一种薄膜晶体管阵列基板及其沟道形成方法，所述方法包括以下步骤：
提供一基板，在所述基板上形成非晶硅层；
对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形；
在所述非晶硅图形中的每一非晶硅层形成一断开空间；
对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于所述断开空间两侧的非晶硅层内的晶粒朝着所述断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道。
为解决上述技术问题，本发明还构造了一种薄膜晶体管阵列基板，其包括：
基板；
沟道，形成于所述基板上，所述沟道包括：
第一结晶区；
第二结晶区；
所述第一结晶区和所述第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直。
 有益效果
本发明通过在非晶硅层形成一断开空间，断开空间将非晶硅层分开为第一区间和第二区间，在通过激光照射后，第一空间和第二空间的晶粒会朝着断开空间的方向生长并在断开空间交汇，进而结晶形成第一结晶区和第二结晶区，第一结晶区和第二结晶区中的晶粒边界与第一结晶区和第二结晶区之间的界面垂直，由此可提高沟道的电子迁移率，并使得TFT的电性均匀。
 附图说明
图1A-1M为本发明实施例中使用非晶硅薄膜进行结晶形成沟道的过程示意图；
图2A到2D所示为按照图1A-1M的处理过程制成的沟道来形成薄膜晶体管阵列基板的过程示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参阅图1A-1M，图1A-1M为本发明实施例中薄膜晶体管阵列基板的沟道形成方法的过程示意图。
在图1A中，提供基板100，在所述基板100上形成缓冲层101（Buffer）。
其中所述基板100譬如为玻璃基板、可挠性塑料基板、晶圆基板或散热基板。所述缓冲层101优选由氮化硅(SiNx)或氧化硅(Si02)形成，所述缓冲层101主要是防止杂质从所述基板100扩散。
在图1B中，在所述缓冲层101上形成非晶硅(a-Si：H)层102，在具体实施过程中，本发明实施例优选使用化学蒸气沉积(CVD)在所述缓冲层101上沉积形成所述非晶硅层102，其中形成非晶硅层102后的俯视图请参阅图1C。
在图1D中，对所述非晶硅层102进行第一次刻蚀处理，形成非晶硅图形。
请一并参阅图1D，图1D为对所述非晶硅层102进行第一次刻蚀处理后的俯视图，其上具有缓冲层101和非晶硅层102的基板100上限定有多个象素区P和多个TFT区T，其中所述TFT区T位于在各个象素区P的角上，而经第一次刻蚀处理后的非晶硅图形包括有多个非晶硅层102，每一非晶硅层102位于TFT区T。其中本发明实施例所指的第一次刻蚀可以采用干法刻蚀或者湿法刻蚀。
请一并参阅图1E，图1E为所述非晶硅层102的结构示意图，其中所述非晶硅层102为弯折结构。
在图1F中，对经第一次刻蚀处理后的非晶硅层102继续进行第二次刻蚀处理，以在所述非晶硅层图形的每一非晶硅层102形成一断开空间M。
请一并参阅图1G和图1I，图1G为沿图1F中G-G'的剖视图，图1H为图1G的俯视图，图1I为图1H的局部放大图。其中所述断开空间M沿长度方向D延伸，且所述断开空间具有一垂直于所述长度方向D的宽度L，所述宽度L的范围优选为1~3um，所述断开空间M将所述非晶硅层102分为第一区间301和第二区间302。
其中所述二次刻蚀处理可使用干法刻蚀、湿法刻蚀或者激光刻蚀，此处不再详述。
在图1J中，对已形成断开空间M的非晶硅层102进行激光照射处理，以形成沟道103，请一并参阅图1K、1L以及1M。
在具体实施过程中，在激光照射下所述断开空间M两侧的第一区间201和第二区间202对应的非晶硅层因为温度差形成侧向长晶。
具体的，所述第一区间201和第二区间202中靠近所述断开空间M的晶粒会朝着所述断开空间M的方向进行生长，其中所述第一区间201中靠近所述断开空间M的晶粒朝向所述断开空间M生长（从左向右），并在所述断开空间M形成第一结晶区N1；所述第二区间202靠近所述断开空间M的晶粒朝向所述断开空间M生长（从右向左），并在所述断开空间M形成第二结晶区N2。所述第一结晶区N1和所述第二结晶区N2的晶粒在断开空间M的中轴Q处交汇，停止生长并结晶。显然，所述第一结晶区和所述第二结晶区N2中晶粒的晶粒边界垂直于所述第一结晶区N1和所述第二结晶区N2之间的平面，由此大幅提高了其后形成的多晶硅层的电子迁移率（mobility），并保证了电子迁移率的均匀性。
请继续参阅图1M，所述第一区间201中被激光照射的其它区域的晶粒自身结晶形成第三结晶区N3；所述第二空间202中被激光照射的其它区域的晶粒自身结晶形成第四结晶区N4。
在图1K中，形成的各个沟道103的位置对应着TFT区T，各个沟道103作为薄膜晶体管(TFT)中的有源层。
本发明实施例中，通过在非晶硅层102形成一断开空间M，该断开空间M将非晶硅层102分开为第一区间201和第二区间202，在通过激光照射所述非晶硅层102后，所述第一空间201和所述第二空间202中靠近断开空间M的晶粒会朝着断开空间M的方向生长并在断开空间M的中轴Q处交汇，进而结晶形成第一结晶区N1和第二结晶区N2，其中第一结晶区N1和第二结晶区N2中的晶粒边界与第一结晶区N1和第二结晶区N2之间的界面垂直，由此可提高其后形成的沟道的电子迁移率，并使得TFT的电性均匀。
其中，在通过激光照射所述非晶硅层102时，所述激光的扫描方向优选与所述断开空间M的长度方向D垂直，或者是与所述断开空间M的长度方向平行，当然也可以与所述长度方向的夹角在0至90度的区间内。所述激光的扫描间距优选范围在0至30微米，所述扫描间距为相邻激光线之间的距离
图2A到2D所示为按照图1A-1M的处理过程制成的多晶硅层来形成薄膜晶体管阵列基板的处理步骤。
在图2A中，提供一基板301，在所述基板301上形成缓冲层302。之后通过步骤1A-1J在TFT区内要形成薄膜晶体管（TFT）的位置形成沟道303。所述缓冲层302上的沟道具有弯折结构。所述沟道被划分成有源区303a、源极和漏极区303b。所述源极和所述漏极区303b被设置在有源区303a两侧。之后在所述缓冲层301上形成一层氮化硅或氧化硅绝缘材料304覆盖所述沟道303。
在图2B中，在所述绝缘材料304上沉积一金属导电材料。之后同时对所述导电材料和所述绝缘材料304进行构图，以在所述沟道303上连续形成栅极绝缘层305和栅极306。之后在所述沟道303的暴露部分也就是源极和漏极区303b上掺杂p-型或n-型离子的杂质。在掺杂杂质的同时，所述栅极306作为离子塞防止杂质渗入有源区303a。
在掺杂之后对掺杂杂质的所述源极和所述漏极区303b进行退火处理，激活掺杂在所述源极和所述漏极区303b内的离子。同时执行使所述源极和所述漏极区303b恢复多晶态的步骤，避免所述源极和漏极区303b的半导体构造可能会因离子掺杂过量从多晶态变成非晶态。
在图2C中，在所述基板301的整个表面上形成一个绝缘层307来覆盖所述栅极306和所述栅极绝缘层305。之后对所述绝缘层307构图形成分别暴露出所述源极和所述漏极区303b的第一接触孔308和第二接触孔309。其中所述绝缘层307可以包括氧化硅和氮化硅。
在图2D中，在所述绝缘层307上沉积一个金属层并且构图，形成源极310和漏极311。其中所述源极310通过所述第一接触孔308接触到所述源极区303b，而所述漏极311通过所述第二接触孔309接触到所述漏极区303b。所述源极310、漏极311、栅极306以及沟道303共通构成一薄膜晶体管。
本发明实施例还提供一薄膜晶体管阵列基板，请一并参阅图2A-2D以及图1A-1M，所述薄膜晶体管阵列基板包括有基板、形成于所述基板上的缓冲层、形成于所述缓冲层上的沟道、栅极绝缘层、栅极、绝缘层、源极以及漏极。
其中所述沟道包括有第一结晶区和第二结晶区；所述第一结晶区和所述第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直。
所述第一结晶区和所述第二结晶区由处于一断开空间两侧的非晶硅层经激光照射形成，所述断开空间沿一长度方向延伸，一宽度垂直于所述长度方向，所述断开空间的宽度的范围为1~3微米。
所述沟道还包括第三结晶区和第四结晶区，其中所述第三结晶区与所述第一结晶区由位于所述断开空间同一侧的非晶硅层形成；所述第四结晶区和所述第二结晶区由位于所述断开空间另一侧的非晶硅层形成。
关于所述沟道的详细形成过程请参阅图1A-1M的详细描述，此处不再赘述。
本发明实施例通过在非晶硅层形成一断开空间，断开空间将非晶硅层分开为第一区间和第二区间，在通过激光照射后，第一空间和第二空间的晶粒会朝着断开空间的方向生长并在断开空间交汇，进而结晶形成第一结晶区和第二结晶区，第一结晶区和第二结晶区中的晶粒边界与第一结晶区和第二结晶区之间的界面垂直，由此可提高形成的沟道的电子迁移率，并使得所述TFT的电性更加均匀。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
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Claims (17)

  1. 一种薄膜晶体管阵列基板的沟道形成方法，其中所述方法包括以下步骤：
    提供基板，在所述基板上形成非晶硅层；
    对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形；
    在所述非晶硅图形中的每一非晶硅层形成一断开空间；所述断开空间沿一长度方向延伸，所述断开空间具有一与所述长度方向垂直的宽度，所述宽度的范围为1~3微米；
    对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于所述断开空间两侧的非晶硅层内的晶粒在温度差的作用下朝着所述断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道，其中所述激光的扫描间距的范围在0至30微米之间。
  2. 根据权利要求1所述的薄膜晶体管阵列基板的沟道形成方法，其中所述沟道包括第一结晶区和第二结晶区，所述第一结晶区和第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直。
  3. 根据权利要求1所述的薄膜晶体管阵列基板的沟道形成方法，其中在所述非晶硅图形中的每一非晶硅层形成一断开空间的步骤具体包括：
    通过刻蚀的方式在所述非晶硅图形中的每一非晶硅层形成所述断开空间。
  4. 根据权利要求1所述的薄膜晶体管阵列基板的沟道形成方法，其中所述断开空间沿一长度方向延伸，所述激光的扫描方向与所述长度方向垂直。
  5. 根据权利要求1所述的薄膜晶体管阵列基板的沟道形成方法，其中所述断开空间沿一长度方向延伸，所述激光的扫描方向与所述长度方向平行。
  6. 根据权利要求1所述的薄膜晶体管阵列基板的沟道形成方法，其中所述断开空间沿一长度方向延伸，所述激光的扫描方向与所述长度方向的夹角为0至90度。
  7. 一种薄膜晶体管阵列基板的沟道形成方法，其中所述方法包括以下步骤：
    提供基板，在所述基板上形成非晶硅层；
    对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形；
    在所述非晶硅图形中的每一非晶硅层形成一断开空间；
    对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于所述断开空间两侧的非晶硅层内的晶粒在温度差的作用下朝着所述断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道。
  8. 根据权利要求7所述的薄膜晶体管阵列基板的沟道形成方法，其中所述断开空间沿一长度方向延伸，所述断开空间具有一与所述长度方向垂直的宽度，所述宽度的范围为1~3微米。
  9. 根据权利要求7所述的薄膜晶体管阵列基板的沟道形成方法，其中所述沟道包括第一结晶区和第二结晶区，所述第一结晶区和第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直。
  10. 根据权利要求7所述的薄膜晶体管阵列基板的沟道形成方法，其中在所述非晶硅图形中的每一非晶硅层形成一断开空间的步骤具体包括：
    通过刻蚀的方式在所述非晶硅图形中的每一非晶硅层形成所述断开空间。
  11. 根据权利要求7所述的薄膜晶体管阵列基板的沟道形成方法，其中所述断开空间沿一长度方向延伸，所述激光的扫描方向与所述长度方向垂直。
  12. 根据权利要求7所述的薄膜晶体管阵列基板的沟道形成方法，其中所述断开空间沿一长度方向延伸，所述激光的扫描方向与所述长度方向平行。
  13. 根据权利要求7所述的薄膜晶体管阵列基板的沟道形成方法，其中所述断开空间沿一长度方向延伸，所述激光的扫描方向与所述长度方向的夹角为0至90度。
  14. 根据权利要求7所述的薄膜晶体管阵列基板的沟道形成方法，其中所述激光的扫描间距的范围在0至30微米之间。
  15. 一种薄膜晶体管阵列基板，其中其包括：
    基板；
    沟道，形成于所述基板上，所述沟道包括：
    第一结晶区；
    第二结晶区；
    所述第一结晶区和所述第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直。
  16. 根据权利要求15所述的薄膜晶体管阵列基板，
    其中所述第一结晶区和所述第二结晶区由处于一断开空间两侧的非晶硅层经激光照射形成，且所述第一结晶区和所述第二结晶区形成于所述断开空间内，所述断开空间沿一长度方向延伸，所述断开空间的宽度与所述长度方向垂直，所述宽度的范围为1~3微米。
  17. 根据权利要求15所述的薄膜晶体管阵列基板，其中所述薄膜晶体管阵列基板还包括有缓冲层，所述缓冲层设置于所述基板和所述沟道之间。
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CN203367290U (zh) * 2013-06-17 2013-12-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及液晶显示器

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