WO2014201715A1 - Substrat de réseau de transistors en couches minces et procédé de formation de canal associé - Google Patents

Substrat de réseau de transistors en couches minces et procédé de formation de canal associé Download PDF

Info

Publication number
WO2014201715A1
WO2014201715A1 PCT/CN2013/078223 CN2013078223W WO2014201715A1 WO 2014201715 A1 WO2014201715 A1 WO 2014201715A1 CN 2013078223 W CN2013078223 W CN 2013078223W WO 2014201715 A1 WO2014201715 A1 WO 2014201715A1
Authority
WO
WIPO (PCT)
Prior art keywords
amorphous silicon
film transistor
space
thin film
array substrate
Prior art date
Application number
PCT/CN2013/078223
Other languages
English (en)
Chinese (zh)
Inventor
许宗义
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2014201715A1 publication Critical patent/WO2014201715A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a thin film transistor array substrate and a channel forming method thereof.
  • Thin Film Transistor TFT has been widely used in the driving of active liquid crystal displays, and the silicon thin film materials used according to thin film transistors are generally of two types, amorphous-silicon and poly-silicon.
  • polysilicon materials have many properties superior to amorphous silicon materials.
  • Polycrystalline silicon has a larger grain, so that electrons are easily free to move in polycrystalline silicon, so the mobility of polycrystalline silicon is higher than that of amorphous silicon.
  • a thin film transistor made of polysilicon has a faster reaction time than an amorphous silicon thin film transistor.
  • a polysilicon thin film transistor (poly-Si) is used.
  • the substrate area occupied by the TFT can be smaller than the area of the substrate occupied by the amorphous silicon thin film transistor, and the aperture ratio of the liquid crystal panel is improved.
  • Liquid crystal display using polysilicon thin film transistor (poly-Si) under the same shell degree TFT LCD) can use a low wattage backlight to achieve low power consumption.
  • polycrystalline silicon thin films are mostly fabricated on a substrate using a low temperature polysilicon preparation process (Low Temperature). Poly-Silicon, LTPS).
  • the low temperature polysilicon preparation process is an excimer laser (Excimer) Laser) as a heat source.
  • Excimer laser Excimer
  • the amorphous silicon film absorbs the energy of the excimer laser and is converted into a polysilicon film.
  • Sequential Lateral Crystallization Solidification, SLS Sequential Lateral Crystallization Solidification, SLS
  • the upper temperature difference is used to achieve the lateral crystallization technique, and the laser is transmitted through the reticle to generate a laser of a specific shape.
  • the first laser first crystallizes the laterally grown crystal grains, and the second laser irradiation region overlaps with the first crystallization region.
  • the silicon film in the region irradiated by the second laser starts to melt, and the long crystalline columnar crystal particles are grown by using the first crystalline polycrystalline silicon film as a seed crystal.
  • the electron mobility of the TFT is high, for example, 300 cm 2 /V-s; however, if the channel length of the TFT is perpendicular to the grain boundary of the polysilicon film, the electron mobility of the TFT is greatly reduced to 100 cm 2 /V-s, Therefore, the SLS lateral crystallization technique in the prior art has a technical problem of electron mobility non-uniformity of the TFT.
  • the present invention constructs a channel forming method for a thin film transistor array substrate, wherein the method comprises the following steps:
  • Each of the amorphous silicon patterns forms a break space in the amorphous silicon pattern; the open space extends along a length direction, and the open space has a width perpendicular to the length direction, The width ranges from 1 to 3 microns;
  • the present invention also constructs a thin film transistor array substrate and a channel forming method thereof, the method comprising the following steps:
  • the present invention also constructs a thin film transistor array substrate, which includes:
  • the channel comprising:
  • the grain boundaries in the first crystallization zone and the second crystallization zone are both perpendicular to the interface between the first crystallization zone and the second crystallization zone.
  • the invention forms a disconnected space in the amorphous silicon layer, and the open space separates the amorphous silicon layer into the first interval and the second interval.
  • the grains of the first space and the second space will face Growing in the direction of the breaking space and intersecting in the breaking space, thereby crystallizing to form the first crystal region and the second crystal region, the grain boundaries in the first crystal region and the second crystal region and the first crystal region and the second crystal.
  • the interface between the regions is perpendicular, whereby the electron mobility of the channel can be improved and the electrical properties of the TFT are made uniform.
  • 1A-1M are schematic views showing a process of forming a channel by crystallization using an amorphous silicon film according to an embodiment of the present invention
  • FIGS. 2A to 2D are schematic views showing a process of forming a thin film transistor array substrate in accordance with a channel formed by the processes of Figs. 1A-1M.
  • FIG. 1A-1M are schematic diagrams showing processes of a channel forming method of a thin film transistor array substrate according to an embodiment of the present invention.
  • a substrate 100 is provided on which a buffer layer 101 (Buffer) is formed.
  • Buffer buffer layer 101
  • the substrate 100 is, for example, a glass substrate, a flexible plastic substrate, a wafer substrate, or a heat dissipation substrate.
  • the buffer layer 101 is preferably formed of silicon nitride (SiNx) or silicon oxide (SiO 2 ), and the buffer layer 101 mainly prevents impurities from diffusing from the substrate 100.
  • an amorphous silicon (a-Si:H) layer 102 is formed on the buffer layer 101.
  • the embodiment of the present invention preferably uses chemical vapor deposition (CVD) on the buffer layer 101.
  • the amorphous silicon layer 102 is deposited thereon, and a top view of the amorphous silicon layer 102 is shown in FIG. 1C.
  • the amorphous silicon layer 102 is subjected to a first etching process to form an amorphous silicon pattern.
  • FIG. 1D is a top view of the amorphous silicon layer 102 after the first etching process, wherein the substrate 100 having the buffer layer 101 and the amorphous silicon layer 102 defines a plurality of images thereon. a pixel region P and a plurality of TFT regions T, wherein the TFT region T is located at an angle of each pixel region P, and the amorphous silicon pattern after the first etching process includes a plurality of amorphous silicon layers 102 Each amorphous silicon layer 102 is located in the TFT region T.
  • the first etching referred to in the embodiment of the present invention may be dry etching or wet etching.
  • FIG. 1E is a schematic structural view of the amorphous silicon layer 102, wherein the amorphous silicon layer 102 is a bent structure.
  • the second etching process is continued on the amorphous silicon layer 102 after the first etching process to form a disconnection in each amorphous silicon layer 102 of the amorphous silicon layer pattern.
  • Space M is
  • FIG. 1G is a cross-sectional view taken along line G-G' of FIG. 1F
  • FIG. 1H is a top view of FIG. 1G
  • FIG. 1I is a partial enlarged view of FIG. 1H.
  • the breaking space M extends along the length direction D, and the breaking space has a width L perpendicular to the length direction D, and the width L preferably ranges from 1 to 3 um, and the breaking space M
  • the amorphous silicon layer 102 is divided into a first section 301 and a second section 302.
  • the secondary etching process may use dry etching, wet etching or laser etching, which will not be described in detail herein.
  • FIG. 1J the amorphous silicon layer 102 in which the open space M has been formed is subjected to laser irradiation treatment to form the channel 103. Please refer to FIGS. 1K, 1L, and 1M together.
  • the amorphous silicon layer corresponding to the first section 201 and the second section 202 on both sides of the disconnected space M under laser irradiation forms lateral crystal growth due to a temperature difference.
  • the dies of the first interval 201 and the second interval 202 adjacent to the disconnected space M are grown toward the disconnected space M, wherein the first interval 201 is adjacent to the The crystal grains of the disconnected space M are grown toward the disconnected space M (from left to right), and a first crystallized region N1 is formed in the disconnected space M; the second interval 202 is close to the disconnected space M The crystal grains are grown toward the disconnected space M (from right to left), and a second crystallized region N2 is formed in the disconnected space M.
  • the crystal grains of the first crystallization zone N1 and the second crystallization zone N2 meet at the central axis Q of the disconnection space M, stop growing and crystallize.
  • the grain boundaries of the grains in the first crystallization zone and the second crystallization zone N2 are perpendicular to the plane between the first crystallization zone N1 and the second crystallization zone N2, thereby greatly increasing
  • the electron mobility of the polysilicon layer formed thereafter ensures uniformity of electron mobility.
  • each of the channels 103 formed corresponds to the TFT regions T, and each of the channels 103 serves as an active layer in a thin film transistor (TFT).
  • TFT thin film transistor
  • the open space M separates the amorphous silicon layer 102 into the first interval 201 and the second interval 202, and the non-irradiation is performed by laser irradiation.
  • the grains in the first space 201 and the second space 202 close to the breaking space M will grow toward the opening space M and meet at the central axis Q of the breaking space M.
  • the scanning direction of the laser light is preferably perpendicular to the longitudinal direction D of the disconnected space M, or is parallel to the longitudinal direction of the disconnected space M, of course. It is also possible to have an angle with the longitudinal direction in the interval of 0 to 90 degrees.
  • the scanning pitch of the laser preferably ranges from 0 to 30 microns, and the scanning pitch is the distance between adjacent laser lines
  • FIGS. 2A to 2D show the processing steps of forming a thin film transistor array substrate in accordance with the polysilicon layer formed by the processes of Figs. 1A-1M.
  • a substrate 301 is provided on which a buffer layer 302 is formed.
  • the channel 303 is formed by the position where the thin film transistor (TFT) is to be formed in the TFT region by the steps 1A-1J.
  • the channel on the buffer layer 302 has a bent structure.
  • the channel is divided into an active region 303a, a source and a drain region 303b.
  • the source and the drain region 303b are disposed on both sides of the active region 303a.
  • a layer of silicon nitride or silicon oxide insulating material 304 is then formed over the buffer layer 301 to cover the channel 303.
  • a metallic conductive material is deposited on the insulating material 304.
  • the conductive material and the insulating material 304 are then patterned simultaneously to form a gate insulating layer 305 and a gate 306 continuously on the channel 303.
  • Impurities of p-type or n-type ions are then doped on the exposed portions of the channel 303, that is, the source and drain regions 303b.
  • the gate 306 acts as an ion plug to prevent impurities from penetrating into the active region 303a while doping impurities.
  • the source of the doping impurity and the drain region 303b are annealed after doping to activate ions doped in the source and drain regions 303b. Simultaneously performing the step of restoring the source and the drain region 303b to a polycrystalline state, avoiding that the semiconductor structure of the source and drain regions 303b may change from polycrystalline to amorphous due to excessive ion doping. .
  • an insulating layer 307 is formed on the entire surface of the substrate 301 to cover the gate electrode 306 and the gate insulating layer 305.
  • the insulating layer 307 is then patterned to form a first contact hole 308 and a second contact hole 309 that expose the source and the drain region 303b, respectively.
  • the insulating layer 307 may include silicon oxide and silicon nitride.
  • a metal layer is deposited on the insulating layer 307 and patterned to form a source 310 and a drain 311.
  • the source 310 contacts the source region 303b through the first contact hole 308, and the drain 311 contacts the drain region 303b through the second contact hole 309.
  • the source 310, the drain 311, the gate 306, and the channel 303 are commonly formed to form a thin film transistor.
  • the embodiment of the present invention further provides a thin film transistor array substrate.
  • the thin film transistor array substrate includes a substrate, a buffer layer formed on the substrate, and is formed in the A channel, a gate insulating layer, a gate, an insulating layer, a source, and a drain on the buffer layer.
  • the channel includes a first crystalline region and a second crystalline region; a grain boundary in the first crystalline region and the second crystalline region is between the first crystalline region and the second crystalline region
  • the interface is vertical.
  • the first crystallization zone and the second crystallization zone are formed by laser irradiation of an amorphous silicon layer on both sides of a disconnected space, the breaking space extending along a length direction, and a width perpendicular to the length direction
  • the width of the disconnected space ranges from 1 to 3 microns.
  • the channel further includes a third crystalline region and a fourth crystalline region, wherein the third crystalline region and the first crystalline region are formed of an amorphous silicon layer on the same side of the disconnected space;
  • the crystallization zone and the second crystallization zone are formed of an amorphous silicon layer on the other side of the disconnected space.
  • the amorphous silicon layer is separated into the first interval and the second interval by forming a disconnected space in the amorphous silicon layer, and the grains in the first space and the second space after being irradiated by the laser. Forming in the direction of the disconnected space and intersecting in the disconnected space, thereby crystallizing to form the first crystalline region and the second crystalline region, the grain boundaries in the first crystalline region and the second crystalline region and the first crystalline region and The interface between the two crystallization regions is perpendicular, whereby the electron mobility of the formed channel can be improved, and the electrical properties of the TFT are more uniform.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

Substrat de réseau de transistors en couches minces et procédé de formation de canal (303) associé. Des couches (102) de silicium amorphe sur un substrat (100) sont soumises à un traitement de gravure pour former un motif de silicium amorphe. Un espace de déconnexion (M) est formé dans chaque couche (102) de silicium amorphe dans le motif de silicium amorphe. Un rayonnement laser est appliqué pour faire croître des cristallites dans les couches (102) amorphes sur l'un ou l'autre des côtés de l'espace de déconnexion (M), sous l'effet de la différence de température, dans la direction de l'espace de déconnexion (M) et pour les faire cristalliser dans l'espace de déconnexion (M) pour former le canal (303) d'un transistor en couches minces. Ceci augmente la mobilité des électrons du canal (303).
PCT/CN2013/078223 2013-06-17 2013-06-27 Substrat de réseau de transistors en couches minces et procédé de formation de canal associé WO2014201715A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310239235.1 2013-06-17
CN2013102392351A CN103311129A (zh) 2013-06-17 2013-06-17 薄膜晶体管阵列基板及其沟道形成方法

Publications (1)

Publication Number Publication Date
WO2014201715A1 true WO2014201715A1 (fr) 2014-12-24

Family

ID=49136206

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/078223 WO2014201715A1 (fr) 2013-06-17 2013-06-27 Substrat de réseau de transistors en couches minces et procédé de formation de canal associé

Country Status (2)

Country Link
CN (1) CN103311129A (fr)
WO (1) WO2014201715A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325688A (zh) * 2013-06-17 2013-09-25 深圳市华星光电技术有限公司 薄膜晶体管的沟道形成方法及补偿电路
CN104078365A (zh) * 2014-06-20 2014-10-01 京东方科技集团股份有限公司 低温多晶硅薄膜的制造方法、tft、阵列基板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040241921A1 (en) * 2003-05-29 2004-12-02 National Chiao Tung University Method for fabrication of polycrystallin silicon thin film transistors
JP2007080894A (ja) * 2005-09-12 2007-03-29 Mitsubishi Electric Corp レーザ結晶化方法
CN101114595A (zh) * 2006-07-26 2008-01-30 财团法人工业技术研究院 多晶硅薄膜晶体管及其制造方法
US20080171409A1 (en) * 2007-01-12 2008-07-17 Huang-Chung Cheng Method for fabricating bottom-gate low-temperature polysilicon thin film transistor
CN102646602A (zh) * 2012-04-23 2012-08-22 清华大学 多晶薄膜制备方法、多晶薄膜及由其制备的薄膜晶体管
CN203367290U (zh) * 2013-06-17 2013-12-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及液晶显示器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4364481B2 (ja) * 2002-04-22 2009-11-18 株式会社半導体エネルギー研究所 薄膜トランジスタの作製方法
KR100492152B1 (ko) * 2002-12-31 2005-06-01 엘지.필립스 엘시디 주식회사 실리콘 결정화방법
TWI374333B (en) * 2007-11-30 2012-10-11 Au Optronics Corp A mask used in a sequential lateral solidification process and a solidification method using the mask

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040241921A1 (en) * 2003-05-29 2004-12-02 National Chiao Tung University Method for fabrication of polycrystallin silicon thin film transistors
JP2007080894A (ja) * 2005-09-12 2007-03-29 Mitsubishi Electric Corp レーザ結晶化方法
CN101114595A (zh) * 2006-07-26 2008-01-30 财团法人工业技术研究院 多晶硅薄膜晶体管及其制造方法
US20080171409A1 (en) * 2007-01-12 2008-07-17 Huang-Chung Cheng Method for fabricating bottom-gate low-temperature polysilicon thin film transistor
CN102646602A (zh) * 2012-04-23 2012-08-22 清华大学 多晶薄膜制备方法、多晶薄膜及由其制备的薄膜晶体管
CN203367290U (zh) * 2013-06-17 2013-12-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及液晶显示器

Also Published As

Publication number Publication date
CN103311129A (zh) 2013-09-18

Similar Documents

Publication Publication Date Title
CN105489552B (zh) Ltps阵列基板的制作方法
CN102569412B (zh) 薄膜晶体管器件及其制造方法
WO2016074204A1 (fr) Transistor à couches minces au silicium polycristallin basse température reposant sur une structure à double grille, et son procédé de fabrication
WO2017219421A1 (fr) Substrat de réseau de transistors á couches minces et son procédé de fabrication, et dispositif d'affichage á cristal liquide
WO2018000478A1 (fr) Procédé de fabrication de transistor à couches minces et procédé de fabrication de panneau matriciel
WO2017173727A1 (fr) Procédé permettant de fabriquer un substrat matriciel à base de ltps
CN109860109A (zh) 一种薄膜晶体管及其制作方法、显示面板
KR101498136B1 (ko) 폴리실리콘 활성층을 함유한 박막트랜지스터, 그 제조방법 및 어레이 기판
WO2014201716A1 (fr) Procédé de formation de canal pour transistor en couches minces et circuit de compensation
WO2019071694A1 (fr) Procédé de fabrication d'un film de polysilicium basse température et transistor
WO2019000508A1 (fr) Substrat de matrice de transistors à couches minces et son procédé de fabrication, et dispositif d'affichage
WO2019071693A1 (fr) Procédé de fabrication de couche mince de polysilicium à basse température et transistor
WO2019071692A1 (fr) Procédé de fabrication de pellicule mince de polysilicium à basse température et transistor
WO2015131498A1 (fr) Substrat de réseau, procédé de préparation de celui-ci, panneau d'affichage et dispositif d'affichage
WO2014201715A1 (fr) Substrat de réseau de transistors en couches minces et procédé de formation de canal associé
WO2017152522A1 (fr) Transistor en couches minces à base d'oxyde de métal, son procédé de fabrication et substrat de réseau
WO2016086484A1 (fr) Transistor à couches minces au silicium polycristallin basse température et son procédé de fabrication
US11862642B2 (en) Display panel, array substrate, and manufacturing method thereof
WO2019056447A1 (fr) Substrat de réseau et son procédé de fabrication
JP2779492B2 (ja) 薄膜トランジスタ装置とその製造方法
TW200421618A (en) Low temperature poly silicon thin film transistor and method of forming poly silicon layer of the same
WO2019085011A1 (fr) Procédé de fabrication de film mince de silicium polycristallin à basse température
WO2017096660A1 (fr) Procédé de préparation de transistor en couches minces connecté à une ligne de données, et transistor en couches minces
WO2018040234A1 (fr) Substrat de réseau tft et son procédé de fabrication, et dispositif d'affichage
CN203367290U (zh) 薄膜晶体管阵列基板及液晶显示器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13887069

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13887069

Country of ref document: EP

Kind code of ref document: A1