WO2017096660A1 - Procédé de préparation de transistor en couches minces connecté à une ligne de données, et transistor en couches minces - Google Patents

Procédé de préparation de transistor en couches minces connecté à une ligne de données, et transistor en couches minces Download PDF

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Publication number
WO2017096660A1
WO2017096660A1 PCT/CN2015/099656 CN2015099656W WO2017096660A1 WO 2017096660 A1 WO2017096660 A1 WO 2017096660A1 CN 2015099656 W CN2015099656 W CN 2015099656W WO 2017096660 A1 WO2017096660 A1 WO 2017096660A1
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Prior art keywords
layer
film transistor
type
drain
thin film
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PCT/CN2015/099656
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English (en)
Chinese (zh)
Inventor
郝思坤
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深圳市华星光电技术有限公司
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Publication of WO2017096660A1 publication Critical patent/WO2017096660A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a method for fabricating a thin film transistor that is electrically connected to a data line and a thin film transistor.
  • IPS Plane Control Mode
  • the wide viewing angle LCD display allows the observer to see only the short axis of the liquid crystal molecules at any time, so the images viewed at various angles are not much different, which is a perfect improvement.
  • the viewing angle of the liquid crystal display The first generation of IPS technology proposed a new liquid crystal arrangement for the drawbacks of the TN mode, achieving a better viewing angle.
  • the second-generation IPS technology (S-IPS or Super-IPS) uses a herringbone electrode to introduce a dual-domain mode to improve the gray-scale reversal of the IPS mode at certain angles.
  • Third generation IPS technology (AS-IPS or Advanced) Super-IPS) reduces the distance between liquid crystal molecules, increases the aperture ratio, and achieves higher brightness.
  • Low temperature polysilicon (Low Temperature Poly-silicon (LTPS) thin-film transistor liquid crystal display uses excimer laser as a heat source in the packaging process. After the laser light passes through the projection system, it generates a laser beam with uniform energy distribution and is projected onto the glass substrate of the amorphous silicon structure. When the amorphous silicon structured glass substrate absorbs the energy of the excimer laser, it is converted into a polycrystalline silicon structure. Since the entire process is completed below 600 ° C, a general glass substrate can be applied.
  • LTPS-TFT LCD has high resolution, fast response speed, high brightness, high aperture ratio, etc., plus LTPS-TFT
  • the silicon crystal arrangement of the LCD is in order of a-Si, so that the electron mobility is relatively higher than 100 times, and the peripheral driving circuit can be simultaneously fabricated on the glass substrate to achieve the goal of system integration, space saving and cost of driving the IC.
  • the existing LTPS technology is mainly used in combination with the FFS liquid crystal display mode and the OLED liquid crystal display mode, and the disadvantage is that in the process of preparing the liquid crystal display, more masks are needed, and the process is required. Complex and costly. For example, when LTPS technology is used in combination with the FFS liquid crystal display mode, twelve masks or eight masks are required, as shown in FIGS. 1A and 1B; When the LTPS technology is used in combination with the OLED liquid crystal display mode, nine masks or ten masks are required, as shown in FIG. 2A and FIG.
  • AS amorphous silicon
  • Poly polysilicon
  • NCD N-type channel doping
  • P+ P-type heavily doped
  • GE gate electrode
  • ILD interlayer dielectric
  • SE source electrode
  • PV passivation layer
  • PL organic insulating layer M3: third layer metal
  • ITO indium tin oxide.
  • the technical problem to be solved by the present invention is to provide a method for fabricating a thin film transistor which is electrically connected to a data line and a thin film transistor, which has a small number of masks, a simple process, a low cost of the prepared liquid crystal display, a wide viewing angle, and is resistant to the outside world. Good pressure characteristics.
  • the present invention provides a method for fabricating a thin film transistor that is electrically connected to a data line, the thin film transistor being a low temperature polysilicon top gate thin film transistor, wherein the thin film transistor is used in combination with an IPS liquid crystal display mode.
  • the method includes the following steps: step (1), providing a substrate, depositing a buffer layer on the substrate; step (2) depositing an amorphous silicon layer on the buffer layer; and step (3), in the amorphous silicon a silicon oxide layer is deposited on the layer; in step (4), the amorphous silicon layer is subjected to excimer laser annealing treatment using the silicon oxide layer as a mask, the amorphous silicon layer is crystallized, converted into a polysilicon layer, and the a silicon oxide layer; a step (5), channel doping the polysilicon layer to form a channel doped polysilicon layer; and (6), patterning the polysilicon layer to form a polysilicon layer segment; (7) depositing a gate insulating layer on the buffer layer and the polysilicon layer segment; and (8) depositing and patterning the first metal layer on the gate insulating layer to form a corresponding polysilicon layer segment
  • step (9) the doped polysilicon layer segments to obtain two P Type or N-type heavily do
  • the material of the buffer layer is silicon nitride, silicon oxide or a combination of the two.
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride or a combination of the two.
  • the material of the gate is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the present invention further provides a method for fabricating a thin film transistor that is electrically connected to a data line, the thin film transistor being a low temperature polysilicon top gate thin film transistor, the thin film transistor being used in combination with an IPS liquid crystal display mode,
  • the method includes the following steps: step (1), providing a substrate, depositing a buffer layer on the substrate; and (2) preparing a polysilicon layer on the buffer layer; and (3) performing a channel on the polysilicon layer Doping, forming a channel doped polysilicon layer; step (4), patterning the polysilicon layer to form a polysilicon layer segment; and (5) depositing a gate on the buffer layer and the polysilicon layer segment An insulating layer; step (6), depositing and patterning a first metal layer on the gate insulating layer to form a gate above the corresponding polysilicon layer segment; and (7), doping the polysilicon layer segment, To get two P Type or N-type heavily doped region and a P disposed between two P-
  • the method for preparing a polysilicon layer comprises the steps of: (21) depositing an amorphous silicon layer on the buffer layer; and (22), in the amorphous a silicon oxide layer is deposited on the silicon layer; in step (23), the amorphous silicon layer is subjected to excimer laser annealing treatment using the silicon oxide layer as a mask, and the amorphous silicon layer is crystallized, converted into a polysilicon layer, and removed.
  • a silicon oxide layer is described.
  • the method further includes the following steps: step (10): forming a passivation layer on the interlayer insulating layer and the source and drain, and in the blunt Forming a second contact hole on the layer corresponding to the drain region to expose the drain from the second contact hole; and (11) depositing and patterning a third layer on the passivation layer
  • the metal layer forms a pixel electrode, and the pixel electrode is in contact with the drain via the second contact hole.
  • the material of the buffer layer is silicon nitride, silicon oxide or a combination of the two.
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride or a combination of the two.
  • the material of the gate is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the present invention also provides a top gate low temperature polysilicon thin film transistor electrically connected to a data line, comprising a substrate, a buffer layer disposed on the substrate, a polysilicon layer disposed on the buffer layer, and disposed on the polysilicon layer a source and a drain on the segment, a gate insulating layer disposed on the buffer layer and the polysilicon layer segment, a gate disposed on the gate insulating layer and above the polysilicon layer segment, and a gate disposed on the gate a very insulating layer and an interlayer insulating layer on the gate, the polysilicon layer segment comprising two P a type or N-type heavily doped region and a P-type or N-type lightly doped region disposed between the two P-type or N-type heavily doped regions, wherein the source and the drain are respectively connected via the first contact hole The P-type or N-type heavily doped regions are in contact.
  • the method further includes a passivation layer disposed on the interlayer insulating layer and the source and drain electrodes, and a pixel electrode disposed on the passivation layer, wherein the pixel electrode is The second contact hole is in contact with the drain.
  • the material of the buffer layer is silicon nitride, silicon oxide or a combination of the two.
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride or a combination of the two.
  • the invention has the advantages that the LTPS process and the IPS liquid crystal display mode reduce the insulating layer between the lower layer ITO and the two layers of ITO, the number of masks is small, the process is simple, and the prepared liquid crystal display has low cost, wide viewing angle and resistance. Advantages such as good external pressure characteristics.
  • FIG. 1A and FIG. 1B are schematic structural diagrams showing a combination of an LTPS technology and an FFS liquid crystal display mode
  • FIGS. 2A and 2B are schematic diagrams showing the structure of the LTPS technology combined with the OLED liquid crystal display mode
  • FIG. 3 is a schematic diagram showing the steps of a method for fabricating a thin film transistor of the present invention and data;
  • 4A-4K are process flow diagrams of a method of fabricating a thin film transistor of the present invention and data;
  • Figure 5 is a schematic view showing the steps of a method for preparing polycrystalline silicon
  • 6A to 6C are process flow diagrams of a method for preparing polycrystalline silicon
  • FIG. 7 is a schematic structural view of a top gate low temperature polysilicon thin film transistor in which the present invention is connected to a data line.
  • the thin film transistor is a low temperature polysilicon top gate thin film transistor, which is used in combination with an IPS liquid crystal display mode.
  • FIGS. 4A to 4J are presented in a simplified schematic manner in which the number of lines has been simplified, and details not related to the description are also omitted.
  • the method for preparing a thin film transistor of the present invention and the data is as follows:
  • a substrate 400 is provided on which a buffer layer 410 is deposited.
  • the substrate 400 is a transparent substrate.
  • the substrate 400 is a glass substrate or a plastic substrate.
  • the buffer layer 410 The material may be silicon nitride (SiNx), silicon oxide (SiOx), or a combination of both.
  • a polysilicon layer 420 is formed on the buffer layer 410.
  • the method for preparing the polysilicon layer 420 includes the following steps:
  • an amorphous silicon layer 411 is deposited on the buffer layer 410.
  • a silicon oxide layer 412 is deposited on the amorphous silicon layer 411.
  • the amorphous silicon layer 411 is subjected to excimer laser annealing treatment using the silicon oxide layer 412 as a mask, the amorphous silicon layer 411 is crystallized, converted into the polysilicon layer 420, and the oxidation is removed. Silicon layer 412.
  • the polysilicon layer 420 is doped by a channel to form a channel doped polysilicon layer 430.
  • N-type doping can be doped with elements such as phosphorus and arsenic, and P-type doping can be doped with elements such as boron and gallium.
  • the polysilicon layer 430 is patterned to form a polysilicon layer segment 431.
  • a gate insulating layer 440 is deposited on the buffer layer 410 and the polysilicon layer segment 431.
  • a first metal layer is deposited and patterned on the gate insulating layer 440 to form a gate 450 above the corresponding polysilicon layer segment 431.
  • the material of the gate 450 is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the polysilicon layer segment 431 is doped to obtain two P-type or N-type heavily doped regions and disposed in two P a P between a type or N type heavily doped region
  • the type or N-type lightly doped region corresponds to the source region 432, the drain region 433, and the channel region 434.
  • two P-type heavily doped regions and a P-type doped region are formed.
  • two N-type heavily doped regions and an N-type doping may be formed.
  • region. N-type doping can be doped with elements such as phosphorus and arsenic
  • P-type doping can be doped with elements such as boron and gallium.
  • an interlayer insulating layer 460 is formed on the gate insulating layer 440 and the gate 450, and the polysilicon layer is corresponding to the gate insulating layer 440 and the interlayer insulating layer 460. Segment 431 P A first contact hole 461 is formed over the type or N-type heavily doped region, respectively.
  • the material of the interlayer insulating layer 460 is silicon oxide, silicon nitride or a combination of the two.
  • a second metal layer is deposited and patterned on the interlayer insulating layer 460 to form a source 462 and a drain 463.
  • the source 462 and the drain 463 are in contact with the source region 432 and the drain region 433 of the polysilicon layer segment 431 via the first contact hole 461, respectively.
  • a passivation layer 470 is formed on the interlayer insulating layer 460 and the source 462 and the drain 463, and is formed on the passivation layer 470 corresponding to the region of the drain 463.
  • the second contact hole 471 is to expose the drain 463 from the second contact hole 471.
  • a third metal layer is deposited and patterned on the passivation layer 470 to form a pixel electrode 480, and the pixel electrode 480 is in contact with the drain 463 via the second contact hole 471. .
  • the patterning in each of the above steps is implemented by mask etching or the like in the prior art.
  • the present invention also provides a top gate low temperature polysilicon thin film transistor electrically connected to a data line.
  • the thin film transistor includes a substrate 400, a buffer layer 410 disposed on the substrate 400, a polysilicon layer segment 431 disposed on the buffer layer 410, a source 462 disposed on the polysilicon layer segment 431, and a drain 463, a gate insulating layer 440 disposed on the buffer layer 410 and the polysilicon layer segment 431, a gate 450 disposed on the gate insulating layer 440 and above the polysilicon layer segment 431, and a gate 450 disposed on the gate The insulating layer 440 and the interlayer insulating layer 460 on the gate 450.
  • the polysilicon layer segment 431 includes two P Type or N-type heavily doped region and a P disposed between two P-type or N-type heavily doped regions a type or N-type lightly doped region correspondingly forms a source region 432, a drain region 433 and a channel region 434, and the source electrode 462 and the drain electrode 463 are heavily doped with the P-type or N-type via the first contact hole 461, respectively.
  • the hetero regions are in contact.
  • the thin film transistor further includes a passivation layer 470 disposed on the interlayer insulating layer 460 and the source and drain electrodes 462 and 463, and a passivation layer 470 disposed on the passivation layer 470.
  • a pixel electrode 480 that is in contact with the drain electrode 463 via the second contact hole 471.
  • the substrate 400 is a transparent substrate.
  • the substrate 400 is a glass substrate or a plastic substrate.
  • the buffer layer 410 The material may be silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two, and the material of the interlayer insulating layer 460 is silicon oxide, silicon nitride, or a combination of the two.
  • the invention adopts the LTPS process to prepare a thin film transistor, adopts the IPS liquid crystal display mode, uses a small number of masks, and has a simple process.
  • the prepared liquid crystal display has the advantages of low cost, wide viewing angle, and good resistance to external pressure characteristics.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention porte sur un procédé de préparation de transistor en couches minces connecté à une ligne de données, et un transistor en couches minces. Le procédé comprend les étapes consistant : à fournir un substrat (400), sur lequel une couche tampon est déposée (410) ; à préparer une couche de silicium polycristallin (420) sur la couche tampon (410) ; à effectuer un dopage de canal sur la couche de silicium polycristallin (420) ; à former une section de couche de silicium polycristallin (431) ; à déposer une couche d'isolation d'électrode de grille (440) sur la couche tampon (410) et la section de couche de silicium polycristallin (431) ; à déposer et modéliser une première couche métallique sur la couche d'isolation d'électrode de grille (440) pour former une électrode de grille (450) ; à obtenir deux régions fortement dopées de type N ou de type P et une région légèrement dopée de type N ou de type P, former de façon correspondante une région de source (432), une région de drain (433) et une région de canal (434) ; à former une couche isolante intermédiaire (460) sur la couche d'isolation d'électrode de grille (440) et l'électrode de grille (450), et former un premier trou de contact (461) au-dessus de la région fortement dopée de type P ou de type N de la section de couche de silicium polycristallin (431) sur la couche d'isolation d'électrode de grille (440) et la couche d'isolation intermédiaire (460) ; à former une électrode de source (462) et une électrode de drain (463) venant respectivement en contact avec la région de source (432) et la région de drain (433) de la section de couche de silicium polycristallin (431) à travers le premier trou de contact (461).
PCT/CN2015/099656 2015-12-08 2015-12-30 Procédé de préparation de transistor en couches minces connecté à une ligne de données, et transistor en couches minces WO2017096660A1 (fr)

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Application Number Priority Date Filing Date Title
CN201510897757.XA CN105336626A (zh) 2015-12-08 2015-12-08 与数据线导通的薄膜晶体管的制备方法及薄膜晶体管
CN201510897757.X 2015-12-08

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Publication number Priority date Publication date Assignee Title
CN106129063B (zh) * 2016-07-05 2019-06-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法
CN108321122B (zh) * 2018-01-31 2021-03-02 京东方科技集团股份有限公司 Cmos薄膜晶体管及其制备方法和显示装置

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CN103996716A (zh) * 2014-04-25 2014-08-20 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制备方法、阵列基板
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CN104600028A (zh) * 2014-12-24 2015-05-06 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法及其结构
CN104779167A (zh) * 2015-04-09 2015-07-15 京东方科技集团股份有限公司 多晶硅薄膜晶体管及其制备方法、阵列基板、显示面板

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JP4736313B2 (ja) * 2002-09-10 2011-07-27 日本電気株式会社 薄膜半導体装置
KR101282897B1 (ko) * 2008-07-08 2013-07-05 엘지디스플레이 주식회사 폴리실리콘 박막트랜지스터 및 그 제조방법

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Publication number Priority date Publication date Assignee Title
US7112458B2 (en) * 2003-10-02 2006-09-26 Tpo Displays Corp. Method of forming a liquid crystal display
CN103887328A (zh) * 2012-12-21 2014-06-25 厦门天马微电子有限公司 薄膜晶体管阵列基板、液晶显示装置及制造方法
CN103996716A (zh) * 2014-04-25 2014-08-20 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制备方法、阵列基板
CN104332477A (zh) * 2014-11-14 2015-02-04 京东方科技集团股份有限公司 薄膜晶体管组件、阵列基板及其制作方法、和显示装置
CN104600028A (zh) * 2014-12-24 2015-05-06 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法及其结构
CN104779167A (zh) * 2015-04-09 2015-07-15 京东方科技集团股份有限公司 多晶硅薄膜晶体管及其制备方法、阵列基板、显示面板

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