WO2014198511A1 - Substrat pourvu d'une zone d'épargne de brasage constituée d'oxyde, de sulfure ou de nitrure, permettant de délimiter une zone de brasage, et procédé de production correspondant - Google Patents

Substrat pourvu d'une zone d'épargne de brasage constituée d'oxyde, de sulfure ou de nitrure, permettant de délimiter une zone de brasage, et procédé de production correspondant Download PDF

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Publication number
WO2014198511A1
WO2014198511A1 PCT/EP2014/060554 EP2014060554W WO2014198511A1 WO 2014198511 A1 WO2014198511 A1 WO 2014198511A1 EP 2014060554 W EP2014060554 W EP 2014060554W WO 2014198511 A1 WO2014198511 A1 WO 2014198511A1
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WIPO (PCT)
Prior art keywords
region
substrate
solder
component
area
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Application number
PCT/EP2014/060554
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German (de)
English (en)
Inventor
Erik Sueske
Steffen Orso
Original Assignee
Robert Bosch Gmbh
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Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2014198511A1 publication Critical patent/WO2014198511A1/fr

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • the invention relates to a substrate and a method for producing a
  • a substrate having a first region for a solder connection of a component, wherein the first region is located on the surface of the substrate.
  • the component By applying the component to the solder pad, it is possible that the component moves on the substrate and occupies an unscheduled position on the substrate. Furthermore, due to an unevenly wetted surface of the substrate with solder, it is possible for the component to twist or tilt due to capillary effects during application.
  • the design element of the dimple is known. These are etched into the copper surface during structuring of the substrate. The dimples are arranged so that they are the positions of the later inserted
  • the substrate has on the surface a first region for a
  • the first region is at least partially bounded by at least one second region on the surface of the substrate.
  • the at least one second region is solder-repellent.
  • the advantage here is that the soldering area is limited and the solder, in particular the solder, does not spread unhindered on the substrate. Therefore, the solder can be applied sparingly.
  • the at least one second area has a height that is different from the first area. This height is in particular greater than the height of the first area.
  • the advantage of this is that the component is neither blurred, tilted nor twisted during the soldering process, but is fixed in a position that is needed for the further processing of the component.
  • the second area encloses the first area and thus forms a kind of frame around the first area.
  • the substrate has a plurality of second regions, in particular two.
  • the second area in this case have two mutually perpendicular lines, which thus form a corner.
  • These second regions are arranged at two diagonally opposite corners of the first region.
  • the second regions are punctiform, d. H. with a small lateral extent.
  • Point-shaped areas are substantially circular or triangular or quadrangular.
  • at least one second area is arranged on each side of the first area. It is advantageous that the second regions consist of geometric shapes that are easy to manufacture.
  • the at least one second region consists of an oxide or a sulfide or a nitride.
  • a physical and / or performed a chemical surface treatment for example, oxidation or sulfiding or nitriding is performed.
  • FIG. 1 shows a substrate with a second region, which is solder-repellent, in particular solder-repellent and delimits a first region in which a component is located,
  • Figure 2 shows a substrate with two second areas, which are diagonal
  • FIG. 3 shows a substrate with several second regions in the form of
  • Circles and FIG. 4 shows a method for producing a substrate with a first
  • FIG. 1 shows a substrate 1 with a first region 2 on the surface of the substrate, which can receive solder.
  • the first area 2 is delimited by a second area 3, the second area 3 forming a kind of frame around the first area.
  • the second area 3 has the property that he
  • Solder repellent, d. H. Lotab lad is. Thus, only on the first area 2, a component 4 can be contacted by means of a soldering operation.
  • FIG. 2 shows a substrate 1 with a first region 2 and two second ones
  • Areas 5 on the surface of the substrate are solder-repellent and consist of two lines arranged at right angles to one another. With respect to the first region 2, the two second regions 5 are arranged so that they are located at two diagonally opposite corners of the first region 2. In the first area 2, a component 4 has been applied by means of a soldering operation.
  • Figure 3 shows a substrate having a first region 2 and a plurality of second regions 6 on the surface of the substrate which are solder repellent.
  • the second regions 6 are punctiform in the form of circles and surround the first region 2. In the exemplary embodiment shown, two circles are respectively arranged on each side of the first region 2.
  • a circle is arranged on each side of the first region 2 in each case.
  • the second regions are configured as a triangle or as a quadrilateral.
  • the height of the second region 3 is greater than the height of the first region 2.
  • the height of the second region 3 is smaller than the height of the first region 2. This results in less mechanical stress on the substrate.
  • FIG. 4 shows a method of manufacturing a substrate having a first area that receives solder and a second area that is solder-repellent. Both the first and second areas are on the surface of the substrate.
  • the method is started with step 400 by applying a mask to the substrate, for example by photolithography or
  • step 420 finds a
  • Oxidation takes place at the sites that represent the second areas.
  • the oxidation causes a kind of passivation of the surface of the substrate, so that the second region has the property of rejecting solder.
  • the mask is removed by solvent in step 430, so that the first area is also exposed and the substrate can be further processed.
  • the process is terminated by rinsing the substrate.
  • the surface of the substrate is copper-based, such as DBC or a punched grid.
  • DBC copper-based
  • the second regions 3 are oxidized on the surface of the substrate, since they are not covered by the mask.
  • sulfidation is performed instead of oxidation.
  • nitration is performed instead of oxidation.
  • the second areas become
  • wet-chemically oxidized or nitrided This can e.g. done by stamp printing, pickling or stencil printing.
  • the substrate is a semiconductor, in particular Si or SiC.
  • a material that is oxidisable or sulfidable or nitridable for example, materials that include copper, nickel, or silver, is applied. Thereafter, steps 420 through 440 are performed.
  • the second regions of the substrate, copper- or nickel-based are oxidized by means of an oxygen plasma.
  • a template or mask can also be used for this purpose.
  • the second regions of the substrate, copper- or nickel-based are oxidized by a laser in a targeted manner at the locations where the second regions are to be formed.
  • the substrate may be used to solder components in the first region of the substrate.
  • the second area which at least partially surrounds the first area and is also higher than the first area, acts as
  • the solder resist As a result, the component is brought into a fixed position and can neither twist, nor tilt, nor blur when applied.
  • the position of the component on the substrate for further processing is known, for example, for the electrical contacting of the component via wire bonding.
  • the oxide can be removed after soldering the component.
  • a roughened surface is formed in the second regions, to which, for example, a molding compound finds better adhesion during further processing of the substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

L'invention concerne un substrat (1) (par exemple DBC, grillage estampé ou semi-conducteur, en particulier Si ou SiC), lequel comporte sur sa surface une première zone (2) servant à une liaison brasée pour au moins un composant (4). La première zone (2) est délimitée au moins en partie par au moins une deuxième zone (3, 5, 6) sur la surface du substrat (1). La ou les deuxièmes zones (3, 5, 6) repoussent la brasure et agissent comme une épargne de brasage. La hauteur de la deuxième zone (3, 5, 6) repoussant la brasure est supérieure ou inférieure à la hauteur de la première zone (2). La deuxième zone (3, 5, 6) repoussant la brasure est produite par un traitement de surface physique et/ou chimique, en particulier par oxydation ou sulfuration ou nitruration de matériaux contenant du cuivre, du nickel ou de l'argent. Une fois le composant (4) brasé, l'oxyde peut à nouveau être retiré, ce qui permet de produire dans les deuxièmes zones (3, 5, 6) une surface rendue rugueuse à laquelle, par exemple, une masse moulée adhère mieux lors d'un traitement supplémentaire du substrat (2).
PCT/EP2014/060554 2013-06-14 2014-05-22 Substrat pourvu d'une zone d'épargne de brasage constituée d'oxyde, de sulfure ou de nitrure, permettant de délimiter une zone de brasage, et procédé de production correspondant WO2014198511A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102013211089.8A DE102013211089A1 (de) 2013-06-14 2013-06-14 Substrat mit einem Bereich zur Begrenzung eines Lotbereichs
DE102013211089.8 2013-06-14

Publications (1)

Publication Number Publication Date
WO2014198511A1 true WO2014198511A1 (fr) 2014-12-18

Family

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PCT/EP2014/060554 WO2014198511A1 (fr) 2013-06-14 2014-05-22 Substrat pourvu d'une zone d'épargne de brasage constituée d'oxyde, de sulfure ou de nitrure, permettant de délimiter une zone de brasage, et procédé de production correspondant

Country Status (2)

Country Link
DE (1) DE102013211089A1 (fr)
WO (1) WO2014198511A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04155949A (ja) * 1990-10-19 1992-05-28 Nec Yamagata Ltd 樹脂封止型半導体装置
JPH0831848A (ja) * 1994-07-19 1996-02-02 Fuji Electric Co Ltd 半導体装置の製造方法
WO2005043966A1 (fr) * 2003-11-03 2005-05-12 Eupec Barriere d'arret de brasage
US20080206928A1 (en) * 2007-02-26 2008-08-28 Fuji Electric Device Technology Co., Ltd. Soldering method and method of manufacturing semiconductor device including soldering method
DE102008042777A1 (de) * 2008-10-13 2010-04-15 Robert Bosch Gmbh Selektiver Lötstop
US20110024886A1 (en) * 2008-04-04 2011-02-03 Gem Services, Inc. Semiconductor device package having features formed by stamping
EP2573809A1 (fr) * 2010-05-18 2013-03-27 Toyota Jidosha Kabushiki Kaisha Dispositif à semi-conducteurs et son procédé de fabrication
EP2669938A2 (fr) * 2012-05-28 2013-12-04 Hitachi Ltd. Dispositif semi-conducteur avec une région d'arrêt d'écoulement de soudure sur un substrat et son procédé de fabrication

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04155949A (ja) * 1990-10-19 1992-05-28 Nec Yamagata Ltd 樹脂封止型半導体装置
JPH0831848A (ja) * 1994-07-19 1996-02-02 Fuji Electric Co Ltd 半導体装置の製造方法
WO2005043966A1 (fr) * 2003-11-03 2005-05-12 Eupec Barriere d'arret de brasage
US20080206928A1 (en) * 2007-02-26 2008-08-28 Fuji Electric Device Technology Co., Ltd. Soldering method and method of manufacturing semiconductor device including soldering method
US20110024886A1 (en) * 2008-04-04 2011-02-03 Gem Services, Inc. Semiconductor device package having features formed by stamping
DE102008042777A1 (de) * 2008-10-13 2010-04-15 Robert Bosch Gmbh Selektiver Lötstop
EP2573809A1 (fr) * 2010-05-18 2013-03-27 Toyota Jidosha Kabushiki Kaisha Dispositif à semi-conducteurs et son procédé de fabrication
EP2669938A2 (fr) * 2012-05-28 2013-12-04 Hitachi Ltd. Dispositif semi-conducteur avec une région d'arrêt d'écoulement de soudure sur un substrat et son procédé de fabrication

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