WO2014198511A1 - Substrate having a soldering resist region consisting of oxide, sulfide or nitride for delimiting a soldering region and corresponding production process - Google Patents

Substrate having a soldering resist region consisting of oxide, sulfide or nitride for delimiting a soldering region and corresponding production process Download PDF

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Publication number
WO2014198511A1
WO2014198511A1 PCT/EP2014/060554 EP2014060554W WO2014198511A1 WO 2014198511 A1 WO2014198511 A1 WO 2014198511A1 EP 2014060554 W EP2014060554 W EP 2014060554W WO 2014198511 A1 WO2014198511 A1 WO 2014198511A1
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WO
WIPO (PCT)
Prior art keywords
region
substrate
solder
component
area
Prior art date
Application number
PCT/EP2014/060554
Other languages
German (de)
French (fr)
Inventor
Erik Sueske
Steffen Orso
Original Assignee
Robert Bosch Gmbh
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Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2014198511A1 publication Critical patent/WO2014198511A1/en

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • the invention relates to a substrate and a method for producing a
  • a substrate having a first region for a solder connection of a component, wherein the first region is located on the surface of the substrate.
  • the component By applying the component to the solder pad, it is possible that the component moves on the substrate and occupies an unscheduled position on the substrate. Furthermore, due to an unevenly wetted surface of the substrate with solder, it is possible for the component to twist or tilt due to capillary effects during application.
  • the design element of the dimple is known. These are etched into the copper surface during structuring of the substrate. The dimples are arranged so that they are the positions of the later inserted
  • the substrate has on the surface a first region for a
  • the first region is at least partially bounded by at least one second region on the surface of the substrate.
  • the at least one second region is solder-repellent.
  • the advantage here is that the soldering area is limited and the solder, in particular the solder, does not spread unhindered on the substrate. Therefore, the solder can be applied sparingly.
  • the at least one second area has a height that is different from the first area. This height is in particular greater than the height of the first area.
  • the advantage of this is that the component is neither blurred, tilted nor twisted during the soldering process, but is fixed in a position that is needed for the further processing of the component.
  • the second area encloses the first area and thus forms a kind of frame around the first area.
  • the substrate has a plurality of second regions, in particular two.
  • the second area in this case have two mutually perpendicular lines, which thus form a corner.
  • These second regions are arranged at two diagonally opposite corners of the first region.
  • the second regions are punctiform, d. H. with a small lateral extent.
  • Point-shaped areas are substantially circular or triangular or quadrangular.
  • at least one second area is arranged on each side of the first area. It is advantageous that the second regions consist of geometric shapes that are easy to manufacture.
  • the at least one second region consists of an oxide or a sulfide or a nitride.
  • a physical and / or performed a chemical surface treatment for example, oxidation or sulfiding or nitriding is performed.
  • FIG. 1 shows a substrate with a second region, which is solder-repellent, in particular solder-repellent and delimits a first region in which a component is located,
  • Figure 2 shows a substrate with two second areas, which are diagonal
  • FIG. 3 shows a substrate with several second regions in the form of
  • Circles and FIG. 4 shows a method for producing a substrate with a first
  • FIG. 1 shows a substrate 1 with a first region 2 on the surface of the substrate, which can receive solder.
  • the first area 2 is delimited by a second area 3, the second area 3 forming a kind of frame around the first area.
  • the second area 3 has the property that he
  • Solder repellent, d. H. Lotab lad is. Thus, only on the first area 2, a component 4 can be contacted by means of a soldering operation.
  • FIG. 2 shows a substrate 1 with a first region 2 and two second ones
  • Areas 5 on the surface of the substrate are solder-repellent and consist of two lines arranged at right angles to one another. With respect to the first region 2, the two second regions 5 are arranged so that they are located at two diagonally opposite corners of the first region 2. In the first area 2, a component 4 has been applied by means of a soldering operation.
  • Figure 3 shows a substrate having a first region 2 and a plurality of second regions 6 on the surface of the substrate which are solder repellent.
  • the second regions 6 are punctiform in the form of circles and surround the first region 2. In the exemplary embodiment shown, two circles are respectively arranged on each side of the first region 2.
  • a circle is arranged on each side of the first region 2 in each case.
  • the second regions are configured as a triangle or as a quadrilateral.
  • the height of the second region 3 is greater than the height of the first region 2.
  • the height of the second region 3 is smaller than the height of the first region 2. This results in less mechanical stress on the substrate.
  • FIG. 4 shows a method of manufacturing a substrate having a first area that receives solder and a second area that is solder-repellent. Both the first and second areas are on the surface of the substrate.
  • the method is started with step 400 by applying a mask to the substrate, for example by photolithography or
  • step 420 finds a
  • Oxidation takes place at the sites that represent the second areas.
  • the oxidation causes a kind of passivation of the surface of the substrate, so that the second region has the property of rejecting solder.
  • the mask is removed by solvent in step 430, so that the first area is also exposed and the substrate can be further processed.
  • the process is terminated by rinsing the substrate.
  • the surface of the substrate is copper-based, such as DBC or a punched grid.
  • DBC copper-based
  • the second regions 3 are oxidized on the surface of the substrate, since they are not covered by the mask.
  • sulfidation is performed instead of oxidation.
  • nitration is performed instead of oxidation.
  • the second areas become
  • wet-chemically oxidized or nitrided This can e.g. done by stamp printing, pickling or stencil printing.
  • the substrate is a semiconductor, in particular Si or SiC.
  • a material that is oxidisable or sulfidable or nitridable for example, materials that include copper, nickel, or silver, is applied. Thereafter, steps 420 through 440 are performed.
  • the second regions of the substrate, copper- or nickel-based are oxidized by means of an oxygen plasma.
  • a template or mask can also be used for this purpose.
  • the second regions of the substrate, copper- or nickel-based are oxidized by a laser in a targeted manner at the locations where the second regions are to be formed.
  • the substrate may be used to solder components in the first region of the substrate.
  • the second area which at least partially surrounds the first area and is also higher than the first area, acts as
  • the solder resist As a result, the component is brought into a fixed position and can neither twist, nor tilt, nor blur when applied.
  • the position of the component on the substrate for further processing is known, for example, for the electrical contacting of the component via wire bonding.
  • the oxide can be removed after soldering the component.
  • a roughened surface is formed in the second regions, to which, for example, a molding compound finds better adhesion during further processing of the substrate.

Abstract

Substrate (1) (e.g. DBC, lead frame or semiconductor, in particular Si or SiC), which on the surface has a first region (2) for a soldered connection for at least one component (4), wherein the first region (2) is at least partially delimited by at least one second region (3, 5, 6) on the surface of the substrate (1), and wherein the at least one second region (3, 5, 6) repels solder agent and acts as a soldering resist. The height of the second, solder agent-repelling region (3, 5, 6) is greater or smaller than the height of the first region (2). The second, solder agent-repelling region (3, 5, 6) is produced by physical and/or chemical surface treatment, in particular by oxidation or sulfiding or nitriding of materials containing copper, nickel or silver. After the component (4) has been soldered on, the oxide can be removed again, as a result of which a roughened surface, at which a molding compound, for example, finds a better bond during further processing of the substrate (2), is formed in the second regions (3, 5, 6).

Description

Beschreibung  description
SUBSTRAT MIT EINEM AUS OXID, SULFID ODER NITRID BESTEHENDEN LOTSTOPPBEREICH ZUR BEGRENZUNG EINES LOTBEREICHS UND ENTSPRECHENDES HERSTELLUNGSVERFAHREN SUBSTRATE COMPRISED WITH OXID, SULFIDE OR NITRIDE LOT STOP SUBSTANCE FOR RESTRICTING A SOLDERING AREA AND CORRESPONDING PREPARATION METHOD
Die Erfindung betrifft ein Substrat und ein Verfahren zur Herstellung eines The invention relates to a substrate and a method for producing a
Substrats mit einem ersten Bereich für eine Lötverbindung eines Bauteils, wobei sich der erste Bereich auf der Oberfläche des Substrats befindet. A substrate having a first region for a solder connection of a component, wherein the first region is located on the surface of the substrate.
Stand der Technik State of the art
Es ist bekannt, dass Bauteile der Leistungselektronik durch einen Lötvorgang direkt auf Substrate, z. B. keramischer Isolator, wie direct bonded copper (DBC) oder Stanzgitter aufgebracht werden. Die oberseitige Kontaktierung des Bauteils erfolgt dabei über Drahtkontaktierung, Auflöten von Kupferclips oder einer It is known that components of the power electronics by a soldering process directly on substrates, eg. As ceramic insulator, such as direct bonded copper (DBC) or stamped grid are applied. The top-side contacting of the component takes place via wire bonding, soldering copper clips or a
Kombination der beiden Techniken. Combination of the two techniques.
Durch Aufbringen des Bauteils auf das Lotkissen ist es möglich, dass sich das Bauteil auf dem Substrat bewegt und eine nicht vorgesehene Position auf dem Substrat einnimmt. Des Weiteren ist es aufgrund einer ungleichmäßig benetzten Oberfläche des Substrats mit Lötmittel möglich, dass das Bauteil aufgrund der Kapillareffekte beim Aufbringen verdreht oder verkippt. By applying the component to the solder pad, it is possible that the component moves on the substrate and occupies an unscheduled position on the substrate. Furthermore, due to an unevenly wetted surface of the substrate with solder, it is possible for the component to twist or tilt due to capillary effects during application.
Bei DBC-Substraten ist das Designelement der Dimpel bekannt. Diese werden beim Strukturieren des Substrates in die Kupferoberfläche geätzt. Die Dimpel sind dabei so angeordnet, dass sie die Positionen der später eingefügten For DBC substrates, the design element of the dimple is known. These are etched into the copper surface during structuring of the substrate. The dimples are arranged so that they are the positions of the later inserted
Bauteile festlegen. Define components.
Bei Stanzgittern werden Dimpel durch Prägung erzeugt, wodurch das Stanzgitter verformt wird. Es kommt dabei zu Spannungen innerhalb des Stanzgitters und die Ebenheit des gesamten Stanzgitters wird beeinflusst. Offenbarung der Erfindung For punched grids, dimples are produced by embossing, which deforms the punched grid. This leads to stresses within the stamped grid and the flatness of the entire stamped grid is influenced. Disclosure of the invention
Das Substrat weist auf der Oberfläche einen ersten Bereich für eine The substrate has on the surface a first region for a
Lötverbindung für mindestens ein Bauteil auf. Der erste Bereich ist dabei durch mindestens einen zweiten Bereich auf der Oberfläche des Substrats wenigstens teilweise begrenzt. Erfindungsgemäß ist der mindestens eine zweite Bereich lötm ittelabweisend. Soldered connection for at least one component. The first region is at least partially bounded by at least one second region on the surface of the substrate. According to the invention, the at least one second region is solder-repellent.
Der Vorteil dabei ist, dass der Lötbereich eingegrenzt ist und sich das Lötmittel, insbesondere das Lot, nicht ungehindert auf dem Substrat ausbreitet. Daher kann das Lötmittel sparsam aufgetragen werden. The advantage here is that the soldering area is limited and the solder, in particular the solder, does not spread unhindered on the substrate. Therefore, the solder can be applied sparingly.
In einer Weiterbildung weist der mindestens eine zweite Bereich eine vom ersten Bereich verschiedene Höhe auf. Diese Höhe ist insbesondere größer als die Höhe des ersten Bereichs. In a development, the at least one second area has a height that is different from the first area. This height is in particular greater than the height of the first area.
Der Vorteil dabei ist, dass das Bauteil während des Lötvorgangs weder verschwimmt, noch verkippt, noch verdreht, sondern in einer Position fixiert wird, die für die weitere Verarbeitung des Bauteils benötigt wird. The advantage of this is that the component is neither blurred, tilted nor twisted during the soldering process, but is fixed in a position that is needed for the further processing of the component.
In einer weiteren Ausgestaltung umschließt der zweite Bereich den ersten Bereich und bildet somit eine Art Rahmen um den ersten Bereich. In a further embodiment, the second area encloses the first area and thus forms a kind of frame around the first area.
In einer Weiterbildung weist das Substrat mehrere zweite Bereiche auf, insbesondere zwei. Die zweiten Bereich weisen dabei zwei rechtwinklig zueinander angeordnete Linien auf, die somit eine Ecke bilden. Diese zweiten Bereiche sind an zwei diagonal gegenüberliegenden Ecken des ersten Bereichs angeordnet. In one development, the substrate has a plurality of second regions, in particular two. The second area in this case have two mutually perpendicular lines, which thus form a corner. These second regions are arranged at two diagonally opposite corners of the first region.
In einer weiteren Ausgestaltung sind die zweiten Bereiche punktförmig ausgestaltet, d. h. mit geringer lateraler Ausdehnung. Die Form der In a further embodiment, the second regions are punctiform, d. H. with a small lateral extent. The shape of the
punktförmigen Bereiche ist im Wesentlichen kreisförmig oder dreieckig oder viereckig. Um eine Begrenzung des ersten Bereichs zu bilden, ist jeweils mindestens ein zweiter Bereich auf jeweils einer Seite des ersten Bereichs angeordnet. Vorteilhaft ist dabei, dass die zweiten Bereiche aus geometrischen Formen bestehen, die einfach herzustellen sind. Point-shaped areas are substantially circular or triangular or quadrangular. In order to form a boundary of the first area, at least one second area is arranged on each side of the first area. It is advantageous that the second regions consist of geometric shapes that are easy to manufacture.
In einer Weiterbildung besteht der mindestens eine zweite Bereich aus einem Oxid oder einem Sulfid oder einem Nitrid. In a development, the at least one second region consists of an oxide or a sulfide or a nitride.
Zur Herstellung eines Substrats mit einem ersten Bereich auf der Oberfläche des Substrats für eine Lötverbindung für ein Bauteil und mindestens einem zweiten Bereich auf der Oberfläche des Substrats, der lötmittelabweisend ist und den ersten Bereich wenigstens teilweise begrenzt, wird im erfindungsgemäßen Verfahren eine physikalische und/oder eine chemische Oberflächenbehandlung durchgeführt. Bei der chemischen Oberflächenbehandlung wird beispielsweise eine Oxidation oder eine Sulfidierung oder eine Nitrierung durchgeführt. For producing a substrate having a first region on the surface of the substrate for a solder joint for a component and at least a second region on the surface of the substrate, which is solder repellent and at least partially limits the first region, in the process according to the invention a physical and / or performed a chemical surface treatment. In the chemical surface treatment, for example, oxidation or sulfiding or nitriding is performed.
Der Vorteil dabei ist, dass die zweiten Bereiche mit einfachen The advantage of this is that the second areas with simple
Oberflächenbehandlungen erzeugt werden. Surface treatments are generated.
Kurze Beschreibung der Zeichnungen Brief description of the drawings
Die vorliegende Erfindung wird nachfolgend anhand bevorzugter The present invention will be described below with reference to preferred
Ausführungsformen und beigefügter Zeichnungen erläutert. Es zeigen: Embodiments and attached drawings explained. Show it:
Figur 1 ein Substrat mit einem zweiten Bereich, der lötmittelabweisend, insbesondere lotabweisend ist und einen ersten Bereich begrenzt, in dem sich ein Bauteil befindet, FIG. 1 shows a substrate with a second region, which is solder-repellent, in particular solder-repellent and delimits a first region in which a component is located,
Figur 2 ein Substrat mit zwei zweiten Bereichen, die an diagonal Figure 2 shows a substrate with two second areas, which are diagonal
gegenüberliegenden Ecken des ersten Bereichs angeordnet sind,  arranged opposite corners of the first area,
Figur 3 ein Substrat mit mehreren zweiten Bereichen in Form von FIG. 3 shows a substrate with several second regions in the form of
Kreisen und Figur 4 ein Verfahren zur Herstellung eines Substrats mit einem erstenCircles and FIG. 4 shows a method for producing a substrate with a first
Bereich auf der Oberfläche des Substrats für eine Lötverbindung für ein Bauteil und mindestens einem zweiten Bereich auf der Oberfläche des Substrats. Area on the surface of the substrate for a solder joint for a component and at least a second region on the surface of the substrate.
Figur 1 zeigt ein Substrat 1 mit einem ersten Bereich 2 auf der Oberfläche des Substrats, der Lot aufnehmen kann. Der erste Bereich 2 wird von einem zweiten Bereich 3 begrenzt, wobei der zweite Bereich 3 eine Art Rahmen um den ersten Bereich bildet. Der zweite Bereich 3 hat die Eigenschaft, dass er FIG. 1 shows a substrate 1 with a first region 2 on the surface of the substrate, which can receive solder. The first area 2 is delimited by a second area 3, the second area 3 forming a kind of frame around the first area. The second area 3 has the property that he
lötmittelabweisend, d. h. lotabweisend ist. Somit kann nur auf dem ersten Bereich 2 ein Bauteil 4 mit Hilfe eines Lötvorgangs kontaktiert werden. Solder repellent, d. H. Lotabweisend is. Thus, only on the first area 2, a component 4 can be contacted by means of a soldering operation.
Figur 2 zeigt ein Substrat 1 mit einem ersten Bereich 2 und zwei zweiten FIG. 2 shows a substrate 1 with a first region 2 and two second ones
Bereichen 5 auf der Oberfläche des Substrats. Diese zweiten Bereiche 5 sind lotabweisend und bestehen aus zwei rechtwinklig zueinander angeordneten Linien. In Bezug auf den ersten Bereich 2 sind die beiden zweiten Bereiche 5 so angeordnet, dass sie sich an zwei diagonal gegenüberliegenden Ecken des ersten Bereichs 2 befinden. Im ersten Bereich 2 ist ein Bauteil 4 mit Hilfe eines Lötvorgangs aufgebracht worden. Areas 5 on the surface of the substrate. These second regions 5 are solder-repellent and consist of two lines arranged at right angles to one another. With respect to the first region 2, the two second regions 5 are arranged so that they are located at two diagonally opposite corners of the first region 2. In the first area 2, a component 4 has been applied by means of a soldering operation.
Figur 3 zeigt ein Substrat mit einem ersten Bereich 2 und mehreren zweiten Bereichen 6 auf der Oberfläche des Substrats, die lötmittelabweisend sind. Die zweiten Bereiche 6 sind punktförmig in Form von Kreisen ausgestaltet und umgeben den ersten Bereich 2. Im gezeigten Ausführungsbeispiel sind jeweils zwei Kreise an jeder Seite des ersten Bereichs 2 angeordnet. Figure 3 shows a substrate having a first region 2 and a plurality of second regions 6 on the surface of the substrate which are solder repellent. The second regions 6 are punctiform in the form of circles and surround the first region 2. In the exemplary embodiment shown, two circles are respectively arranged on each side of the first region 2.
In einem weiteren Ausführungsbeispiel ist jeweils ein Kreis auf jeder Seite des ersten Bereichs 2 angeordnet. In a further embodiment, a circle is arranged on each side of the first region 2 in each case.
In einem Ausführungsbeispiel sind die zweiten Bereiche als Dreieck oder als Viereck ausgestaltet. In one embodiment, the second regions are configured as a triangle or as a quadrilateral.
In einem Ausführungsbeispiel ist die Höhe des zweiten Bereichs 3 größer als die Höhe des ersten Bereichs 2. Somit kann sich beim Lötvorgang im ersten Bereich 2 ein Lötkissen mit einer gleichmäßigen Höhe bilden und das Bauteil 4 genau positioniert werden. In one embodiment, the height of the second region 3 is greater than the height of the first region 2. Thus, during the soldering process in the first region 2 form a solder pad with a uniform height and the component 4 are accurately positioned.
In einem weiteren Ausführungsbeispiel ist die Höhe des zweiten Bereichs 3 kleiner als die Höhe des ersten Bereichs 2. Dadurch entstehen weniger mechanische Spannungen auf dem Substrat. In a further embodiment, the height of the second region 3 is smaller than the height of the first region 2. This results in less mechanical stress on the substrate.
Figur 4 zeigt ein Verfahren zur Herstellung eines Substrats mit einem ersten Bereich, der Lötmittel aufnimmt und einem zweiten Bereich, der lotabweisend ist. Sowohl der erste als auch der zweite Bereich befinden sich auf der Oberfläche des Substrats. Das Verfahren wird mit Schritt 400 durch Aufbringen einer Maske auf das Substrat gestartet, beispielsweise durch Photolithographie oder FIG. 4 shows a method of manufacturing a substrate having a first area that receives solder and a second area that is solder-repellent. Both the first and second areas are on the surface of the substrate. The method is started with step 400 by applying a mask to the substrate, for example by photolithography or
Sputtering. In Abhängigkeit des verwendeten Lacks und der Maske werden entweder die Stellen bedeckt, die sich außerhalb der zweiten Bereiche befinden oder die Stellen bedeckt, die sich innerhalb der zweiten Bereiche befinden. Bei Negativlacken bleiben die belichteten Bereiche des Photolacks stehen und bei Positivlacken bleiben die unbelichteten Bereiche des Photolacks stehen. Die erzeugbare Höhe des zweiten Bereichs ist dabei abhängig von der Sputtering. Depending on the varnish used and the mask, either the areas that are outside the second areas or that cover the areas that are within the second areas are covered. In the case of negative varnishes, the exposed areas of the photoresist remain in place and in the case of positive varnishes the unexposed areas of the photoresist remain. The producible height of the second region is dependent on the
Lackschichtdicke und kann der Höhe des im ersten Bereich zu verlötenden Bauteils individuell angepasst. In einem folgenden Schritt 420 findet eine Lackschichtdicke and can be adjusted individually to the height of the component to be soldered in the first area. In a following step 420 finds a
Oxidation an den Stellen statt, die die zweiten Bereiche repräsentieren. Durch die Oxidation erfolgt eine Art Passivierung der Oberfläche des Substrats, sodass der zweite Bereich die Eigenschaft aufweist, Lötmittel abzuweisen. Nach Beendigung der Oxidation wird die Maske in Schritt 430 durch Lösemittel abgelöst, sodass der erste Bereich ebenfalls freigelegt wird und das Substrat weiter verarbeitet werden kann. In einem folgenden Schritt 440 wird das Verfahren durch Spülen des Substrats beendet. Oxidation takes place at the sites that represent the second areas. The oxidation causes a kind of passivation of the surface of the substrate, so that the second region has the property of rejecting solder. After completion of the oxidation, the mask is removed by solvent in step 430, so that the first area is also exposed and the substrate can be further processed. In a following step 440, the process is terminated by rinsing the substrate.
In einem Ausführungsbeispiel ist die Oberfläche des Substrats kupferbasiert, beispielsweise DBC oder ein Stanzgitter. Durch die Oxidation beispielsweise mit einer Natriumchloritlösung werden die zweiten Bereiche 3 an der Oberfläche des Substrats oxidiert, da diese von der Maske nicht verdeckt werden. In one embodiment, the surface of the substrate is copper-based, such as DBC or a punched grid. By oxidation, for example, with a sodium chlorite solution, the second regions 3 are oxidized on the surface of the substrate, since they are not covered by the mask.
In einem Ausführungsbeispiel wird anstelle der Oxidation eine Sulfidierung durchgeführt. In einem weiteren Ausführungsbeispiel wird anstelle der Oxidation eine Nitrierung durchgeführt. In one embodiment, sulfidation is performed instead of oxidation. In another embodiment, nitration is performed instead of oxidation.
In einem weiteren Ausführungsbeispiel werden die zweiten Bereiche In a further embodiment, the second areas become
nasschemisch oxidiert oder nitridiert. Dies kann z.B. durch Stempel Druck, Beizen oder Schablonen Druck erfolgen. wet-chemically oxidized or nitrided. This can e.g. done by stamp printing, pickling or stencil printing.
In einem Ausführungsbeispiel ist das Substrat ein Halbleiter, insbesondere Si oder SiC. In einem optionalen Schritt 410, der auf Schritt 400 folgt, wird ein Material aufgebracht, das oxidierbar oder sulfidierbar oder nitrierbar ist, beispielsweise Materialien die Kupfer, Nickel oder Silber beinhalten. Danach werden die Schritte 420 bis 440 ausgeführt. In one embodiment, the substrate is a semiconductor, in particular Si or SiC. In an optional step 410 following step 400, a material that is oxidisable or sulfidable or nitridable, for example, materials that include copper, nickel, or silver, is applied. Thereafter, steps 420 through 440 are performed.
In einem Ausführungsbeispiel werden die zweiten Bereiche des Substrats, kupfer- oder nickelbasiert, mit Hilfe eines Sauerstoffplasmas oxidiert. Zur Strukturierung kann hierfür auch eine Schablone oder Maske verwendet werden. In one embodiment, the second regions of the substrate, copper- or nickel-based, are oxidized by means of an oxygen plasma. For structuring, a template or mask can also be used for this purpose.
In einem weiteren Ausführungsbeispiel werden die zweiten Bereiche des Substrats, kupfer- oder nickelbasiert, durch einen Laser gezielt an den Stellen oxidiert, an denen die zweiten Bereiche entstehen sollen. In a further embodiment, the second regions of the substrate, copper- or nickel-based, are oxidized by a laser in a targeted manner at the locations where the second regions are to be formed.
Das Substrat kann dazu verwendet werden, Bauteile im ersten Bereich des Substrats aufzulöten. Der zweite Bereich, der den ersten Bereich wenigstens teilweise umgibt und auch höher als der erste Bereich ist, wirkt dabei als The substrate may be used to solder components in the first region of the substrate. The second area, which at least partially surrounds the first area and is also higher than the first area, acts as
Lötstopp. Dadurch wird das Bauteil in eine feste Position gebracht und kann sich beim Aufbringen weder verdrehen, noch verkippen, noch verschwimmen. Somit ist die Position des Bauteils auf dem Substrat für eine weitere Verarbeitung bekannt, beispielsweise für die elektrische Kontaktierung des Bauteils via Drahtbonding. Das Oxid kann nach dem Auflöten des Bauteils wieder entfernt. Dadurch entsteht in den zweiten Bereichen eine aufgeraute Fläche, an der bei einer weiteren Verarbeitung des Substrats beispielsweise eine Moldmasse eine bessere Haftung findet. The solder resist. As a result, the component is brought into a fixed position and can neither twist, nor tilt, nor blur when applied. Thus, the position of the component on the substrate for further processing is known, for example, for the electrical contacting of the component via wire bonding. The oxide can be removed after soldering the component. As a result, a roughened surface is formed in the second regions, to which, for example, a molding compound finds better adhesion during further processing of the substrate.

Claims

Ansprüche claims
1. Substrat (1), das auf der Oberfläche einen ersten Bereich (2) für eine 1. substrate (1) having on the surface a first region (2) for a
Lötverbindung für mindestens ein Bauteil (4) aufweist, wobei der erste Bereich Has solder joint for at least one component (4), wherein the first region
(2) durch mindestens einen zweiten Bereich (3) auf der Oberfläche des Substrats wenigstens teilweise begrenzt ist, dadurch gekennzeichnet, dass der mindestens eine zweite Bereich (3) lötmittelabweisend ist. (2) is at least partially delimited by at least one second region (3) on the surface of the substrate, characterized in that the at least one second region (3) is solder-repellent.
2. Substrat (1) nach Anspruch 1, dadurch gekennzeichnet, dass der mindestens eine zweite Bereich (3) eine andere Höhe aufweist, insbesondere eine größere Höhe, als der erste Bereich (2). 2. Substrate (1) according to claim 1, characterized in that the at least one second region (3) has a different height, in particular a greater height, than the first region (2).
3. Substrat (1) nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der zweite Bereich (3) derart ausgestaltet ist, dass der zweite Bereich (3) einen Rahmen um den ersten Bereich (2) bildet. 3. Substrate (1) according to one of the preceding claims, characterized in that the second region (3) is designed such that the second region (3) forms a frame around the first region (2).
4. Substrat (1) nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, dass zwei zweite Bereiche (3) derart ausgestaltet sind, dass jeweils zwei rechtwinklig zueinander angeordnete Linien an zwei diagonal gegenüberliegenden Ecken des ersten Bereichs (2) angeordnet sind. 4. substrate (1) according to any one of claims 1 or 2, characterized in that two second regions (3) are designed such that in each case two perpendicular to each other arranged lines at two diagonally opposite corners of the first region (2) are arranged.
5. Substrat (1) nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, dass die zweiten Bereiche (3) punktförmig ausgestaltet sind, insbesondere kreisförmig, wobei jeweils mindestens ein zweiter Bereich (3) auf jeweils einer Seite des ersten Bereichs (2) angeordnet ist. 5. Substrate (1) according to one of claims 1 or 2, characterized in that the second regions (3) are designed point-shaped, in particular circular, wherein in each case at least one second region (3) on each side of the first region (2). is arranged.
6. Substrat (1) nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der mindestens eine zweite Bereich (3) aus Oxid oder Sulfid oder Nitrid besteht. 6. Substrate (1) according to one of the preceding claims, characterized in that the at least one second region (3) consists of oxide or sulfide or nitride.
7. Verfahren zur Herstellung eines Substrats (1) nach einem der vorhergehenden Ansprüche mit einem ersten Bereich (2) auf der Oberfläche des Substrats (1) für eine Lötverbindung für mindestens ein Bauteil (4) und mit einem zweiten Bereich (3) auf der Oberfläche des Substrats, der den ersten Bereich (2) wenigstens teilweise begrenzt, dadurch gekennzeichnet, dass der zweite Bereich (3), der lötm ittelabweisend ist, durch physikalische und/oder chemische Oberflächenbehandlung erzeugt wird, insbesondere durch Oxidation oder Sulfidierung oder Nitrierung. 7. A method for producing a substrate according to claim 1, comprising a first area on the surface of the substrate for a solder joint for at least one component and with a second area on the substrate Surface of the substrate which at least partially delimits the first region (2), characterized in that the second region (3) which is solder-repellent is produced by physical and / or chemical surface treatment, in particular by oxidation or sulfidation or nitration.
PCT/EP2014/060554 2013-06-14 2014-05-22 Substrate having a soldering resist region consisting of oxide, sulfide or nitride for delimiting a soldering region and corresponding production process WO2014198511A1 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04155949A (en) * 1990-10-19 1992-05-28 Nec Yamagata Ltd Resin-sealed semiconductor device
JPH0831848A (en) * 1994-07-19 1996-02-02 Fuji Electric Co Ltd Production of semiconductor device
WO2005043966A1 (en) * 2003-11-03 2005-05-12 Eupec Solder stop barrier
US20080206928A1 (en) * 2007-02-26 2008-08-28 Fuji Electric Device Technology Co., Ltd. Soldering method and method of manufacturing semiconductor device including soldering method
DE102008042777A1 (en) * 2008-10-13 2010-04-15 Robert Bosch Gmbh Selective solder stop
US20110024886A1 (en) * 2008-04-04 2011-02-03 Gem Services, Inc. Semiconductor device package having features formed by stamping
EP2573809A1 (en) * 2010-05-18 2013-03-27 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method for manufacturing the same
EP2669938A2 (en) * 2012-05-28 2013-12-04 Hitachi Ltd. Semiconductor device with an oxide solder flow prevention area on a substrate and corresponding manufacturing method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04155949A (en) * 1990-10-19 1992-05-28 Nec Yamagata Ltd Resin-sealed semiconductor device
JPH0831848A (en) * 1994-07-19 1996-02-02 Fuji Electric Co Ltd Production of semiconductor device
WO2005043966A1 (en) * 2003-11-03 2005-05-12 Eupec Solder stop barrier
US20080206928A1 (en) * 2007-02-26 2008-08-28 Fuji Electric Device Technology Co., Ltd. Soldering method and method of manufacturing semiconductor device including soldering method
US20110024886A1 (en) * 2008-04-04 2011-02-03 Gem Services, Inc. Semiconductor device package having features formed by stamping
DE102008042777A1 (en) * 2008-10-13 2010-04-15 Robert Bosch Gmbh Selective solder stop
EP2573809A1 (en) * 2010-05-18 2013-03-27 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method for manufacturing the same
EP2669938A2 (en) * 2012-05-28 2013-12-04 Hitachi Ltd. Semiconductor device with an oxide solder flow prevention area on a substrate and corresponding manufacturing method

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