WO1986007191A1 - Process for manufacturing an electric circuit using hybrid technology - Google Patents

Process for manufacturing an electric circuit using hybrid technology Download PDF

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Publication number
WO1986007191A1
WO1986007191A1 PCT/DE1986/000011 DE8600011W WO8607191A1 WO 1986007191 A1 WO1986007191 A1 WO 1986007191A1 DE 8600011 W DE8600011 W DE 8600011W WO 8607191 A1 WO8607191 A1 WO 8607191A1
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WO
WIPO (PCT)
Prior art keywords
protective layer
component
adhesive
conductor tracks
bonding
Prior art date
Application number
PCT/DE1986/000011
Other languages
German (de)
French (fr)
Inventor
Klaus Küttner
Bernhard Meier
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1986007191A1 publication Critical patent/WO1986007191A1/en

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    • H05K2203/04—Soldering or other types of metallurgic bonding
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
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    • H05K2203/0582—Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a method for producing an electrical circuit in hybrid technology according to the preamble of the main claim.
  • Such circuits are generally known.
  • Base metals such as copper oxidize in the presence of atmospheric oxygen at the elevated temperatures of the hardening process, so that a protective gas atmosphere would be required.
  • the object of the invention is therefore to develop a method which allows electrical components such as semiconductor, resistance and / or capacitance chips in a conductor network made of copper or other base, bondable metals to be fastened by means of an adhesive without the bondability of the Common metal surfaces are adversely affected by the curing process of the adhesive.
  • the process according to the invention with the characterizing features of the main claim has the advantage that it is possible with simple process steps to ensure the suitability of surfaces made of base metals, in particular conductor tracks and connection surfaces, over the entire manufacturing and assembly process of an electrical circuit in hybrid technology.
  • the proposed protective layers are easy to apply and the production of a protective gas atmosphere during the curing process of adhesives, in particular epoxy adhesives, which is only partially effective anyway, can be omitted.
  • the protective layers from a photoresist, which is applied to the entire substrate in a sheet-like manner before one or more components are stuck on, and is first removed selectively, preferably by exposure and development, at the glue points.
  • a photoresist as a protective layer can either be selectively removed again for carrying out further gluing operations or other processing operations, or it can be completely removed in a simple manner, in particular using an organic solvent. It is thus achieved here that during the gluing of the components and during the heat treatment of the adhesive there are no reactions on the surfaces of base metal which are harmful to the bonding process and which could adversely affect the bonding process.
  • An expedient alternative to the full-surface coating consists in the selective application of a protective layer by screen printing only to the areas of the electrical circuit to be covered, the protective layer preferably being formed from a solder resist.
  • a silicon substrate is preferably used as the substrate, and those made of copper are particularly suitable as base conductor tracks and connection surfaces.
  • Epoxy adhesives which can be cured quickly and easily at temperatures between 100 ° C. and 400 ° C., are preferably used as the adhesive.
  • the protective layer is likewise subjected to a heat treatment for predrying, which takes place at temperatures below approx. 80 ° C.
  • the bond connections are preferably produced by welding using thermocompression or using ultrasound.
  • electrical connections between the construction elements and the conductor tracks or other soft surfaces made of copper are preferably used for bonding wires made of gold.
  • base metal which can be bonded is understood to mean those metals which have normal potentials of less than + 0.6 V in relation to hydrogen in the electrochemical voltage series. In the method according to the invention for producing an electrical circuit using hybrid technology, these include in particular copper and aluminum.
  • 10 denotes a substrate, which preferably consists of silicon.
  • a copper-clad epoxy material can also be used instead.
  • Conductor tracks 11 run on the substrate 10, and a connection area 12 is shown in between.
  • a protective layer 13 is applied to the entire substrate 10, covering the conductor tracks and the connection area, as can be seen in FIG. 1.
  • a component 15 is fastened to the connection surface 12 by means of an adhesive 14 (FIGS. 3 to 5).
  • the component 15 is connected to surfaces 17 on the conductor tracks 11 by means of bond wires 16. The method according to the invention is carried out as follows.
  • a protective layer 13 of photoresist is applied over the entire surface of the substrate 10, the conductor tracks 11 and the connection area 12 and is predried at a temperature below 80 ° C.
  • the varnish can be applied on one or both sides if the latter is easier to do using the immersion process.
  • Figure 1 shows the substrate with the applied and pre-dried protective layer.
  • solder resist can also be selectively applied using the screen printing process.
  • the arrangement would then correspond approximately to that in FIG. 2, with selectively only the regions of the conductor tracks 11 to be covered being coated with lacquer.
  • the product WEPELAN SD 2154 P, blue, from W. Peters KG can be used as a solder resist.
  • FIG. 2 shows the second method step after the protective layer according to FIG. 1 has been applied over the entire area.
  • the photoresist of the protective layer 13 has been removed by selective exposure to developer liquid.
  • the connection surface 12 is therefore free for gluing a component 15, while the surfaces 17 of the conductor tracks 11 are still covered with the protective layer 13.
  • FIG. 3 shows the state of the process in which a semiconductor IC has been glued to the connection surface 12 by means of an epoxy adhesive as the component 15 and the adhesive has been cured.
  • the adhesive cures at temperatures between 100oC and 400oC, preferably at temperatures above 120oC, generally following the instructions of the adhesive manufacturer.
  • other components can of course be glued into the circuit and other electronic components can be integrated in the silicon substrate 10.
  • FIG. 4 shows the state of the process in which the photoresist of the protective layer 13 has been completely removed by means of an organic solvent. If the photoresist should only be partially removed, this can be done by re-exposing and developing the corresponding areas.
  • FIG. 5 shows the finished electrical circuit produced by the method according to the invention, in which, for example, a semiconductor IC as component 15 is connected to the conductor tracks 11 made of copper by means of bond wires 16 made of gold.
  • the bondable but otherwise attacked surfaces of the base metal copper, which are attacked during the hardening of the adhesive, are protected by the method according to the invention during the entire bonding process, so that the bondability is not impaired and the inexpensive and electrically highly conductive conductor tracks made of copper can be used.
  • the application of the method according to the invention is not limited to the exemplary embodiment described, in particular other lacquers or substances for the protective layer 13 and other base metals can be used as conductor tracks 11.
  • aluminum conductor tracks are particularly suitable, on which preferably bond wires made of aluminum can also be fastened.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

A process for manufacturing an electric circuit using hybrid technology, in which at least one electric component (15) is secured by means of a bonding agent (14) in a printed circuit with tracks (11) made of a base metal which is suitable for bonding. The surfaces (17) of the base metal which are intended for the bonding process, preferably made of copper, are covered during the bonding proces and during the hardening of the bonding agent (14), which is performed at a high temperature, by a protective layer (13) which is removed before the bonding operation.

Description

Verfahren zur Herstellung einer elektrischen Schaltung in HybridtechnikProcess for producing an electrical circuit using hybrid technology
Stand der TechnikState of the art
Die Erfindung geht aus von einem Verfahren zur Herstellung einer elektrischen Schaltung in Hybridtechnik nach der Gattung des Hauptanspruchs. Derartige Schaltungen sind grundsätzlich bekannt. Zur Sicherung einer gleichbleibenden Qualität der Bondverbindungen bestehen dabei mindestens die Bondflächen aus Edelmetall, vorzugsweise aus Gold, weil dieses unempfindlich ist gegenüber nahezu allen während des Aushärteprozesses der Kleber auftretenden physikalischen und chemischen Vorgängen und gegenüber den beim Aushärten von den Klebern abgegebenen Stoffen. Unedlere Metalle wie z.B. Kupfer oxydieren in Gegenwart von Luftsauerstoff bei den erhöhten Temperaturen des Aushärteprozesses, so daß eine Schutzgasatmosphäre erforderlich wäre. Zusätzlich treten in der Umgebung der Klebestellen Reaktionen unedler Metalle mit aus den Klebern ausgasenden Substanzen auf, welche die Bondfähigkeit der Leiterbahnen wesentlich herabsetzen und auch durch erhöhten Schutzgasdurchsatz oder durch Evakuieren des Klebers vor oder während des Aushärtens nicht verhindert werden können.The invention relates to a method for producing an electrical circuit in hybrid technology according to the preamble of the main claim. Such circuits are generally known. To ensure a constant quality of the bond connections, there are at least the bonding surfaces made of precious metal, preferably gold, because this is insensitive to almost all physical and chemical processes occurring during the curing process of the adhesive and to the substances released by the adhesive during curing. Base metals such as copper oxidize in the presence of atmospheric oxygen at the elevated temperatures of the hardening process, so that a protective gas atmosphere would be required. In addition, reactions of base metals with substances outgassing from the adhesives occur in the vicinity of the bond points, which affect the bondability of the Significantly reduce conductor tracks and cannot be prevented by increased shielding gas throughput or by evacuating the adhesive before or during curing.
Eine naßehemische Reinigung der für die Bondvorgänge vorgesehenen Oberflächen bei Verwendung unedler Metalle ist in Regel ebenfalls nicht möglich wegen der aufgebrachten elektronischen Bauelemente. Aufgabe der Erfindung ist es daher, ein Verfahren zu entwickeln, welches es gestattet, elektrische Bauelemente wie Halbleiter-, Widerstands- und/ oder Kapazitätschips in einem Leiterbahnnetzwerk aus Kupfer oder anderen unedlen, bondfähigen Metallen mittels eines Klehers zu befestigen, ohne daß die Bondfähigkeit der Oberflächen aus unedlem Metall durch den Aushärteprozess des Klebers beeinträchtigt wird.A wet chemical cleaning of the surfaces provided for the bonding processes when using base metals is also generally not possible because of the electronic components applied. The object of the invention is therefore to develop a method which allows electrical components such as semiconductor, resistance and / or capacitance chips in a conductor network made of copper or other base, bondable metals to be fastened by means of an adhesive without the bondability of the Common metal surfaces are adversely affected by the curing process of the adhesive.
Vorteile der ErfindungAdvantages of the invention
Das erfindungsgemäße Verfahren mit den kennzeichnenden Merkmalen des Hauptanspruches hat den Vorteil, daß es mit einfachen Verfahrensschritten möglich ist, die Bjndfähigkeit von aus unedlen Metallen bestehenden Oberflächen, insbesondere Leiterbahnen und Anschlußflächen, über den gesamten Herstellung- und Montageprozess einer elektrischen Schaltung in Hybridtechnik zu sichern. Die vorgeschlagenen Schutzschichten sind leicht aufzubringen und die Herstellung einer Schutzgasatmosphäre während des Aushärteprozesses von Klebern, insbesondere von Epoxy-Klebern, welche ohnehin nur bedingt wirksam ist, kann entfallen.The process according to the invention with the characterizing features of the main claim has the advantage that it is possible with simple process steps to ensure the suitability of surfaces made of base metals, in particular conductor tracks and connection surfaces, over the entire manufacturing and assembly process of an electrical circuit in hybrid technology. The proposed protective layers are easy to apply and the production of a protective gas atmosphere during the curing process of adhesives, in particular epoxy adhesives, which is only partially effective anyway, can be omitted.
Durch die in den Unteransprüchen aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen des im Hauptanspruch angegebenen Verfahrens möglich. Insbe sondere ist es vorteilhaft, die Schutzschichten aus einem Fotolack zu bilden, welcher vor dem Aufkleben eines oder mehrerer Bauelemente flächenförmig auf das ganze Substrat aufgebracht und an den Klebestellen zunächst selektiv, vorzugsweise durch Belichten und Entwickeln, entfernt wird.Advantageous developments and improvements of the method specified in the main claim are possible through the measures listed in the subclaims. In particular In particular, it is advantageous to form the protective layers from a photoresist, which is applied to the entire substrate in a sheet-like manner before one or more components are stuck on, and is first removed selectively, preferably by exposure and development, at the glue points.
Nach dem Aufkleben des Bauelementes kann ein Fotolack als Schutzschicht entweder nochmals selektiv entfernt werden zur Durchführung weiterer Klebevorgänge oder anderer Bearbeitungsvorgänge oder er kann in einfacher Weise, insbesondere durch ein organisches Lösungsmittel, vollständig entfernt werden. Man erreicht hierbei also, daß während des Aufklebens der Bauelemente und während der Wärmbehandlung des Klebers keine für den Bondvorgang schädliche Reaktionen an den Oberflächen aus unedlem Metall auftreten, welche den Bondvorgang negativ beeinträchtigen könnten. Eine zweckmäßige Alternative zur ganzflächigen Beschichtung besteht in der selektiven Aufbringung einer Schutzschicht durch Siebdruck nur auf die abzudeckenden Bereiche der elektrischen Schaltung, wobei die Schutzschicht vorzugsweise aus einem Lötstopplack gebildet wird. Als Substrat dient vorzugsweise ein Siliciumsubstrat, als unedle Leiterbahnen und Anschlußflächen eignen sich insbesondere solche aus Kupfer. Als Kleber dienen vorzugsweise Epoxy-Kleber, welche bei Temperaturen zwischen 100ºC und 400ºC rasch und unproblematisch aushärtbar sind. Vorzugsweise wird, insbesondere zur Beschleunigung des Verfahrens, die Schutzschicht ebenfalls einer Wärmebehandlung zum Vortrocknen unterworfen, welche bei Temperaturen unter ca. 80°C erfolgt.After the component has been stuck on, a photoresist as a protective layer can either be selectively removed again for carrying out further gluing operations or other processing operations, or it can be completely removed in a simple manner, in particular using an organic solvent. It is thus achieved here that during the gluing of the components and during the heat treatment of the adhesive there are no reactions on the surfaces of base metal which are harmful to the bonding process and which could adversely affect the bonding process. An expedient alternative to the full-surface coating consists in the selective application of a protective layer by screen printing only to the areas of the electrical circuit to be covered, the protective layer preferably being formed from a solder resist. A silicon substrate is preferably used as the substrate, and those made of copper are particularly suitable as base conductor tracks and connection surfaces. Epoxy adhesives, which can be cured quickly and easily at temperatures between 100 ° C. and 400 ° C., are preferably used as the adhesive. Preferably, in particular to accelerate the process, the protective layer is likewise subjected to a heat treatment for predrying, which takes place at temperatures below approx. 80 ° C.
Die Bondverbindungen werden vorzugsweise durch Schweißen mittels Thermokompression oder mittels Ultraschall hergestellt. Als elektrische Verbindungen zwischen den Bau elementen und den Leiterbahnen oder sonstweichen Oberflächen aus Kupfer dienen vorzugsweise Bond-Drähte aus Gold. Unter unedlen, bondfähigen Metallen im Sinne der Erfindung sind solche Metalle zu verstehen, welche in der elektrochemischen Spannungsreihe Normalpotentiale gegenüber Wasserstoff von weniger als + 0,6 V besitzen. Hierzu zählen bei dem erfindungsgemäßen Verfahren zur Herstellung einer elektrischen Schaltung in Hybridtechnik insbesondere Kupfer und Aluminium.The bond connections are preferably produced by welding using thermocompression or using ultrasound. As electrical connections between the construction elements and the conductor tracks or other soft surfaces made of copper are preferably used for bonding wires made of gold. For the purposes of the invention, base metal which can be bonded is understood to mean those metals which have normal potentials of less than + 0.6 V in relation to hydrogen in the electrochemical voltage series. In the method according to the invention for producing an electrical circuit using hybrid technology, these include in particular copper and aluminum.
Zeichnungdrawing
Ein Ausführungsbeispiel einer nach dem erfindungsgemäßen Verfahren hergestellen elektrischen Schaltung ist in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Die Figuren 1 bis 5 zeigen verschiedene Stadien des Verfahrensablaufes.An embodiment of an electrical circuit manufactured by the method according to the invention is shown in the drawing and explained in more detail in the following description. Figures 1 to 5 show different stages of the process.
Beschreibung des AusführungsbeispielesDescription of the embodiment
In den Figuren ist mit 10 ein Substrat bezeichnet, welches vorzugsweise aus Silicium besteht. Stattdessen kann auch ein kupferkaschiertes Epoxy-Material verwendet werden. Auf dem Substrat 10 verlaufen Leiterbahnen 11, dazwischen ist eine Anschlußfläche 12 dargestellt.In the figures, 10 denotes a substrate, which preferably consists of silicon. A copper-clad epoxy material can also be used instead. Conductor tracks 11 run on the substrate 10, and a connection area 12 is shown in between.
Auf das gesamte Substrat 10 ist, die Leiterbahnen und die Anschlußfläche überdeckend, eine Schutzschicht 13 aufgebracht, wie aus Figur 1 ersichtlich. Mittels eines Klebers 14 wird auf der Anschlußfläche 12 ein Bauelement 15 befestigt (Figuren 3 bis 5). Das Bauelement 15 ist mittels Bond-Drähten 16 mit Oberflächen 17 auf den Leiterbahnen 11 verbunden. Das erfindungsgemäße Verfahren wird folgendermaßen durchgeführt.A protective layer 13 is applied to the entire substrate 10, covering the conductor tracks and the connection area, as can be seen in FIG. 1. A component 15 is fastened to the connection surface 12 by means of an adhesive 14 (FIGS. 3 to 5). The component 15 is connected to surfaces 17 on the conductor tracks 11 by means of bond wires 16. The method according to the invention is carried out as follows.
Auf das Substrat 10, die Leiterbahnen 11 und die Anschlußfläche 12 wird ganzflächig eine Schutzschicht 13 aus Fotolack aufgebracht und bei einer Temperatur unterhalb 80ºC vorgetrocknet. Als Fotolack dient beispielsweise das Erzeugnis AZ 1350 J Der Firma SHIPLEY. Der Lack kann einseitig oder beidseitig aufgebracht werden, wenn letzteres im Tauchverfahren einfacher möglich ist. Figur 1 zeigt das Substrat mit der aufgebrachten und vorgetrockneten Schutzschicht.A protective layer 13 of photoresist is applied over the entire surface of the substrate 10, the conductor tracks 11 and the connection area 12 and is predried at a temperature below 80 ° C. The product AZ 1350 J from SHIPLEY, for example, serves as a photoresist. The varnish can be applied on one or both sides if the latter is easier to do using the immersion process. Figure 1 shows the substrate with the applied and pre-dried protective layer.
Je nach der geforderten Abbildungsgenauigkeit der Schutzschicht kann auch selektiv ein Lötstopplack im Siebdruckverfahren aufgebracht werden. Die Anordnung würde dann etwa derjenigen in Figur 2 entsprechen, wobei selektiv nur die abzudeckenden Bereiche der Leiterbahnen 11 mit Lack überzogen sind. Als Lötstopplack kann beispielsweise das Erzeugnis WEPELAN SD 2154 P, blau, der Firma W. Peters KG verwendet werden.Depending on the required imaging accuracy of the protective layer, a solder resist can also be selectively applied using the screen printing process. The arrangement would then correspond approximately to that in FIG. 2, with selectively only the regions of the conductor tracks 11 to be covered being coated with lacquer. For example, the product WEPELAN SD 2154 P, blue, from W. Peters KG, can be used as a solder resist.
Figur 2 zeigt den zweiten Verfahrensschritt nach dem ganzflächigen Aufbringen der Schutzschicht gemäß Figur 1. An den Stellen, an denen ein Bauelement 15 eingeklebt werden soll, ist der Fotolack der Schutzschicht 13 nach selektiver Belichtung durch Entwicklerflüssigkeit herausgelöst worden. Die Anschlußfläche 12 liegt also frei zum Aufkleben eines Bauelementes 15, während die Oberflächen 17 der Leiterbahnen 11 mit der Schutzschicht 13 weiterhin bedeckt sind.FIG. 2 shows the second method step after the protective layer according to FIG. 1 has been applied over the entire area. At the points at which a component 15 is to be glued in, the photoresist of the protective layer 13 has been removed by selective exposure to developer liquid. The connection surface 12 is therefore free for gluing a component 15, while the surfaces 17 of the conductor tracks 11 are still covered with the protective layer 13.
Figur 3 zeigt den Verfahrensstand, bei dem auf die Anschlußfläche 12 mittels eines Epoxy-Klebers als Bauelement 15 ein Halbleiter-IC aufgeklebt und der Kleber ausgehärtet worden ist. Das Aushärten des Klebers erfolgt bei Temperaturen zwischen 100ºC und 400ºC, vorzugsweise bei Temperaturen oberhalb 120°C, wobei generell die Angaben des Herstellers des Klebers zu beachten sind. Außer dem dargestellten Bauelement 15 können selbstverständlich weitere Bauelemente in die Schaltung eingeklebt und andere elektronische Bauteile in dem Silicium-Substrat 10 integriert sein.FIG. 3 shows the state of the process in which a semiconductor IC has been glued to the connection surface 12 by means of an epoxy adhesive as the component 15 and the adhesive has been cured. The adhesive cures at temperatures between 100ºC and 400ºC, preferably at temperatures above 120ºC, generally following the instructions of the adhesive manufacturer. In addition to the component 15 shown, other components can of course be glued into the circuit and other electronic components can be integrated in the silicon substrate 10.
Figur 4 zeigt den Verfahrensstand, bei dem mittels eines organischen Lösungsmittels der Fotolack der Schutzschicht 13 vollständig entfernt worden ist. Soll der Fotolack nur partiell entfernt werden, so kann dies durch erneutes Belichten und Entwickeln der entsprechenden Bereiche geschehen.FIG. 4 shows the state of the process in which the photoresist of the protective layer 13 has been completely removed by means of an organic solvent. If the photoresist should only be partially removed, this can be done by re-exposing and developing the corresponding areas.
Figur 5 zeigt die fertige, nach dem erfindungsgemäßen Verfahren hergestellte elektrische Schaltung, bei der beispielsweise ein Halbleiter-IC als Bauelement 15 durch Bond-Drähte 16 aus Gold mit den Leiterbahnen 11 aus Kupfer verbunden ist. Die bondfähigen, aber ansonsten beim Aushärten des Klebers angegriffenen Oberflächen des unedlen Metalls Kupfer sind durch das erfindungsgemäße Verfahren während des gesamten Klebeprozesses geschützt, so daß die Bondfähigkeit nicht beeinträchtigt und die preiswerten und elektrisch gut leitfähigen Leiterbahnen aus Kupfer verwendet werden können. Die Anwendung des erfindungsgemäßen Verfahrens ist nicht auf das beschriebene Ausführungsbeispiel beschränkt, insbesondere können andere Lacke oder Substanzen für die Schutzschicht 13 und andere unedle Metalle als Leiterbahnen 11 verwendet werden. Neben Kupfer eignen sich insbesondere Aluminium-Leiterbahnen, auf denen vorzugsweise Bond-Drähte ebenfalls aus Aluminium befestigbar sind. FIG. 5 shows the finished electrical circuit produced by the method according to the invention, in which, for example, a semiconductor IC as component 15 is connected to the conductor tracks 11 made of copper by means of bond wires 16 made of gold. The bondable but otherwise attacked surfaces of the base metal copper, which are attacked during the hardening of the adhesive, are protected by the method according to the invention during the entire bonding process, so that the bondability is not impaired and the inexpensive and electrically highly conductive conductor tracks made of copper can be used. The application of the method according to the invention is not limited to the exemplary embodiment described, in particular other lacquers or substances for the protective layer 13 and other base metals can be used as conductor tracks 11. In addition to copper, aluminum conductor tracks are particularly suitable, on which preferably bond wires made of aluminum can also be fastened.

Claims

Ansprüche Expectations
1. Verfahren zur Herstellung einer elektrischen Schaltung in Hybridtechnik, wobei wenigstens ein elektrisches Bauelement (15), insbesondere ein Halbleiter-, Widerstandsund/oder Kapazitätschip, mittels eines Klebers ( 1 4 ) in einem Leiterbahnnetzwerk befestigt und durch Bonden mit wenigstens einer Leiterbahn (11) und/oder einem weiteren Bauelement (15) elektrisch verbunden wird, dadurch gekennzeichnet, daß die für den Bondvorgang bestimmten Flächen (11, 17) aus einem unedlen, bonfähigen Metall gebildet und während des Klebevorgangs und des bei erhöhter Temperatur durchgeführten Aushärtevorgangs des Klebers (14) durch eine Schutzschicht (13) abgedeckt werden, welche vor dem Bondvorgang entfernt wird.1. A method for producing an electrical circuit using hybrid technology, wherein at least one electrical component (15), in particular a semiconductor, resistance and / or capacitance chip, is fastened in an interconnect network by means of an adhesive (1 4) and by bonding with at least one interconnect (11 ) and / or a further component (15) is electrically connected, characterized in that the surfaces (11, 17) intended for the bonding process are formed from a base metal which is suitable for receipts and during the gluing process and the curing process of the glue (carried out at elevated temperature) 14) are covered by a protective layer (13) which is removed before the bonding process.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Schutzschicht (13) aus einem Fotolack gebildet wird, welcher vor dem Aufkleben des Bauelementes (15) flächenförmig auf ein Substrat (10) mit Leiterbahnen (11) und/oder Anschlußflächen (12) aufgebracht, an den Klebestellen zunächst selektiv entfernt und nach dem Aufkleben des Bauelementes (15) und der Wärmebehandlung des Klebers (14 ) vollends oder selektiv wieder entfernt wird. 2. The method according to claim 1, characterized in that the protective layer (13) is formed from a photoresist which, prior to the gluing of the component (15) flat on a substrate (10) with conductor tracks (11) and / or connection surfaces (12) applied, is first removed selectively at the adhesive points and is completely or selectively removed again after the component (15) and the heat treatment of the adhesive (14) have been glued on.
3. Verfahren nach Anspruch 2, dadurch gekennzeichnet, daß die selektive Entfernung des Fotolackes (15) durch Belichten und Entwickeln erfolgt, während die abschließende vollständige Entfernung des Lackes durch ein organisches Lösungsmittel bewirkt wird.3. The method according to claim 2, characterized in that the selective removal of the photoresist (15) is carried out by exposure and development, while the final complete removal of the lacquer is effected by an organic solvent.
4 . Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Schutzschicht (15) selektiv durch Siebdruck eines Lackes, insbesondere eines Lötstopp-Lackes, aufgebracht wird.4th Method according to Claim 1, characterized in that the protective layer (15) is applied selectively by screen printing a lacquer, in particular a solder-stop lacquer.
5. Verfahren nach einem der vorhergehenden Ansprüche, gekennzeichnet durch die Verwendung eines Silicium-Substrates (10) mit Leiterbahnen (11) und/oder Anschlußflächen (12) aus Kupfer.5. The method according to any one of the preceding claims, characterized by the use of a silicon substrate (10) with conductor tracks (11) and / or pads (12) made of copper.
6. Verfahren nach einem der vorhergehenden Ansprüche, gekennzeichnet, durch die Verwendung eines Epoxy-Klebers (14), welcher bei Temperaturen zwischen 100ºC und 400ºC ausgehärtet wird.6. The method according to any one of the preceding claims, characterized by the use of an epoxy adhesive (14) which is cured at temperatures between 100ºC and 400ºC.
7. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Bondverbindungen durch Schweißen mittels Thermokompression oder Ultraschall hergestellt werden.7. The method according to any one of the preceding claims, characterized in that the bond connections are made by welding by means of thermocompression or ultrasound.
8. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die elektrischen Verbindungen zwischen dem Bauelement (15) und Leiterbahnen (11) aus Kupfer durch 3ond-Drähte (16) aus Gold hergestellt werden.8. The method according to any one of the preceding claims, characterized in that the electrical connections between the component (15) and conductor tracks (11) made of copper by 3ond wires (16) are made of gold.
9. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Schutzschicht (13) bei einer Temperatur unterhalb 80ºC vorgetrocknet wird. 9. The method according to any one of the preceding claims, characterized in that the protective layer (13) is pre-dried at a temperature below 80ºC.
PCT/DE1986/000011 1985-05-18 1986-01-15 Process for manufacturing an electric circuit using hybrid technology WO1986007191A1 (en)

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DE19853517965 DE3517965A1 (en) 1985-05-18 1985-05-18 METHOD FOR PRODUCING AN ELECTRICAL CIRCUIT IN HYBRID TECHNOLOGY

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656648A1 (en) * 1993-12-03 1995-06-07 Motorola Inc. Circuit and method of using an oxide layer to attach a semiconductor die to a die pad

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3736001B2 (en) * 1996-02-29 2006-01-18 株式会社デンソー Electronic component mounting method
DE19722355A1 (en) * 1997-05-28 1998-12-03 Bosch Gmbh Robert Method of manufacturing electrical assemblies and electrical assembly
DE102008058047B4 (en) * 2008-11-18 2013-11-07 Auto-Kabel Management Gmbh Connection of electrical cables by means of ultrasonic welding

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3838984A (en) * 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
GB2125618A (en) * 1982-08-19 1984-03-07 Denki Kagaku Kogyo Kk Hybrid integrated circuit and preparation thereof
EP0139063A1 (en) * 1983-10-24 1985-05-02 SINTRA-ALCATEL Société Anonyme dite: Substition method for an electronic component connected to the conductor tracks of a substrate carrier

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4372475A (en) * 1981-04-29 1983-02-08 Goforth Melvin L Electronic assembly process and apparatus
EP0142783B1 (en) * 1983-11-11 1990-04-18 Kabushiki Kaisha Toshiba Method for producing hybrid integrated circuit
US4582722A (en) * 1984-10-30 1986-04-15 International Business Machines Corporation Diffusion isolation layer for maskless cladding process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3838984A (en) * 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
GB2125618A (en) * 1982-08-19 1984-03-07 Denki Kagaku Kogyo Kk Hybrid integrated circuit and preparation thereof
EP0139063A1 (en) * 1983-10-24 1985-05-02 SINTRA-ALCATEL Société Anonyme dite: Substition method for an electronic component connected to the conductor tracks of a substrate carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656648A1 (en) * 1993-12-03 1995-06-07 Motorola Inc. Circuit and method of using an oxide layer to attach a semiconductor die to a die pad

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