JPH0831848A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPH0831848A JPH0831848A JP6165691A JP16569194A JPH0831848A JP H0831848 A JPH0831848 A JP H0831848A JP 6165691 A JP6165691 A JP 6165691A JP 16569194 A JP16569194 A JP 16569194A JP H0831848 A JPH0831848 A JP H0831848A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor device
- copper
- oxide film
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Other Surface Treatments For Metallic Materials (AREA)
- Die Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体素体を放熱およ
び電気的接続に用いられる支持板上にはんだ付けによ
り、固着する電力用などの半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device for electric power, in which a semiconductor element is fixed on a support plate used for heat dissipation and electrical connection by soldering.
【0002】[0002]
【従来の技術】電力用半導体素子を含む半導体装置で
は、半導体素体に発生する熱の放電のため、あるいは半
導体素体上の電極への通電のため、支持板としてのセラ
ミックなどよりなる絶縁性基板上の銅被膜パターンと半
導体素体上の電極とをはんだ付けすることにより、半導
体素体を支持板に固着する。このような半導体素体と支
持板とのはんだ付けには、支持板の銅被膜表面をはんだ
により被覆し、溶融させたはんだの上に半導体素体を自
動ハンドで載せてはんだ付けするダイレクトボンディン
グ方式と、支持板の銅被膜表面の上にはんだを介して半
導体素体を載せて位置決め治具で固定し、水素還元雰囲
気炉中を通過させてはんだ付けする連続はんだ付け方式
とがある。2. Description of the Related Art In a semiconductor device including a power semiconductor element, an insulating material made of ceramic or the like as a supporting plate is used for discharging heat generated in a semiconductor element body or for energizing electrodes on the semiconductor element body. The semiconductor element body is fixed to the support plate by soldering the copper film pattern on the substrate and the electrode on the semiconductor element body. For such soldering of the semiconductor element body and the supporting plate, a direct bonding method in which the copper coating surface of the supporting plate is covered with solder and the semiconductor element body is placed on the molten solder by an automatic hand and soldered There is a continuous soldering method in which a semiconductor element body is placed on a copper coating surface of a support plate via solder, fixed by a positioning jig, and passed through a hydrogen reducing atmosphere furnace for soldering.
【0003】[0003]
【発明が解決しようとする課題】従来の方法ではんだ付
けする場合、処理温度が高すぎると溶融したはんだの粘
度が低くなり、流れ出してしまってろう付けに必要な量
が確保できなくなる。特に、多機種混合生産の場合、製
品寸法もさまざまであり、熱容量差も大きいため、全製
品に対しはんだが完全に溶け切り、なおかつはんだが流
れ出しにくい温度にすることは、上記の二つの方法のい
ずれでも非常にむづかしい。例えば、図3に示すように
セラミック基板1上の銅被膜2にはんだ3によって、半
導体チップ4をはんだ付けする場合、はんだを完全に溶
かし切るために処理温度を多少高めに設定すると、はん
だ3の流れ出しが起こり、必要なはんだ厚みが確保でき
ないばかりか、隣接の銅被膜パターン21との間の絶縁
部の沿面距離が減少することで絶縁不足という問題も発
生する。図4に示すように、溶融はんだの飛び散りによ
って生ずるはんだボール30の付着によっても銅被膜パ
ターン間の短絡問題が起こる。When soldering by the conventional method, if the processing temperature is too high, the viscosity of the molten solder becomes low, and the solder will flow out and the amount required for brazing cannot be secured. In particular, in the case of multi-model mixed production, the product dimensions are various and the difference in heat capacity is large, so it is necessary to set the temperature at which the solder has completely melted and solder is hard to flow out of the above two methods. Both are very difficult. For example, as shown in FIG. 3, when the semiconductor chip 4 is soldered to the copper coating 2 on the ceramic substrate 1 with the solder 3, if the processing temperature is set to be slightly higher in order to completely melt the solder, the solder 3 Not only the required solder thickness cannot be ensured due to the flow-out, but also the creepage distance of the insulating portion between the adjacent copper coating pattern 21 decreases, which causes a problem of insufficient insulation. As shown in FIG. 4, the short circuit problem between the copper coating patterns also occurs due to the adhesion of the solder balls 30 caused by the scattering of the molten solder.
【0004】本発明の目的は、上記の問題を解決し、半
導体素体を固着するためのろう付けの際に絶縁部の沿面
距離の減少による絶縁不足の問題、あるいは、はんだボ
ールの付着などによる短絡の問題が生じない半導体装置
の製造方法を提供することにある。An object of the present invention is to solve the above-mentioned problems and to prevent insufficient insulation due to a decrease in creepage distance of an insulating portion during brazing for fixing a semiconductor element body, or due to adhesion of solder balls. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not cause a short circuit problem.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、支持板表面の金属層領域に少なくとも
半導体素体をろう付けにより固着する工程を含む半導体
装置の製造方法において、金属層の表面を選択的に加熱
して所定の領域を残して酸化金属層を形成し、金属面の
露出する領域に半導体素体をろう付けするものとする。
金属層の表面を選択的に加熱するためにレーザ光を照射
することが有効である。金属層の厚さ方向における少な
くとも一部を銅により形成することが良い。In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, which includes a step of fixing at least a semiconductor element body to a metal layer region of a surface of a support plate by brazing, The surface of the metal layer is selectively heated to form a metal oxide layer leaving a predetermined region, and the semiconductor element body is brazed to the exposed region of the metal surface.
Irradiation with laser light is effective for selectively heating the surface of the metal layer. It is preferable that at least a part of the metal layer in the thickness direction is made of copper.
【0006】[0006]
【作用】金属層の表面に選択的加熱により酸化金属層を
形成することにより、酸化層の表面と金属層の露出面と
の間に段差が生じ、ろう付けの際に溶融したろうの表面
張力作用も加わってろうの流れ出しがなくなる。また、
はんだボールなどが飛散したときも、酸化物表面に付着
しにくくなり、付着しても付着力が低い。[Function] By forming a metal oxide layer on the surface of the metal layer by selective heating, a step is generated between the surface of the oxide layer and the exposed surface of the metal layer, and the surface tension of the molten wax during brazing. The action also adds to the flow of wax. Also,
Even when solder balls and the like are scattered, it becomes difficult to adhere to the oxide surface, and even if they adhere, the adhesive force is low.
【0007】[0007]
【実施例】以下、図3、図4を含めて共通の部分に同一
の符号を付した図を引用して本発明の実施例について説
明する。製造される半導体装置は、図5 (a) 、 (b)
に示すように電力用半導体素子としてのパワートランジ
スタチップ4を2個含むもので、セラミック基板1上の
銅被膜2のパターンの上に各チップ4がはんだ31によ
って固着されている。また、銅被膜2の上には図5
(b) に点線で示すような端子導体5が図5 (a) に点
線で示す支持板1上の位置51ではんだ32によって固
着されている。この端子導体5は樹脂容器の蓋6を貫通
して容器外に引き出されている。なお、基板1の裏面も
銅被膜7が形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. The manufactured semiconductor device is shown in FIGS.
As shown in FIG. 2, it includes two power transistor chips 4 as power semiconductor elements, and each chip 4 is fixed by solder 31 on the pattern of the copper coating 2 on the ceramic substrate 1. In addition, on the copper coating 2
The terminal conductor 5 shown by the dotted line in FIG. 5B is fixed by the solder 32 at the position 51 on the support plate 1 shown by the dotted line in FIG. The terminal conductor 5 penetrates the lid 6 of the resin container and is drawn out of the container. The copper coating 7 is also formed on the back surface of the substrate 1.
【0008】この半導体装置を製造するために図2
(a) 、 (b) に示すような支持板を用いた。この支持
板は、厚さ0.635 mmのセラミック基板1の表面に厚さ0.
3mmの銅被膜2のパターン、裏面全面に厚さ0.2mmの銅
被膜7が形成されている。次に図1 (a) 、 (b) に示
すように、この支持板の表面の銅被膜2のはんだ付けに
用いられない個所、すなわちチップ4の固着される個所
41、端子導体5の固着される個所51以外の部分にY
AGレーザ光を走査することにより局部的に加熱し、表
面に厚さ50μmの銅酸化膜8を形成した。この支持板
上に図5に示すように半導体チップ4を高温溶融はんだ
31を用いて銅被膜2の露出面41にダイレクトボンデ
ィング法あるいは連続はんだ付け法ではんだ付けした。
次に、端子導体5を低温溶融はんだ32を用いて銅被膜
2の露出面51にはんだ付けした。高温溶融はんだ31
には、融点約300℃のPb93.5%、Sn5%、Ag
1.5%の組成のはんだ、低温溶融はんだ31には、融点
約185℃のPb37%、Sn63%の組成のはんだを
用いた。いずれのはんだ付けの場合にも、はんだ付け個
所41、51の外へのはんだ31、32の流れ出しがな
く、はんだボールの付着もなかった。In order to manufacture this semiconductor device, FIG.
A supporting plate as shown in (a) and (b) was used. This support plate has a thickness of 0.
A pattern of the copper film 2 having a thickness of 3 mm and a copper film 7 having a thickness of 0.2 mm are formed on the entire back surface. Next, as shown in FIGS. 1 (a) and 1 (b), a portion which is not used for soldering the copper coating 2 on the surface of the support plate, that is, a portion 41 where the chip 4 is fixed and a terminal conductor 5 is fixed. Y in parts other than
The copper oxide film 8 having a thickness of 50 μm was formed on the surface by locally heating by scanning the AG laser beam. As shown in FIG. 5, the semiconductor chip 4 was soldered on the support plate to the exposed surface 41 of the copper coating 2 by the direct bonding method or the continuous soldering method using the high temperature melting solder 31.
Next, the terminal conductor 5 was soldered to the exposed surface 51 of the copper coating 2 using the low temperature melting solder 32. High temperature molten solder 31
Has a melting point of about 300 ° C, Pb93.5%, Sn5%, Ag
As the solder having a composition of 1.5% and the low temperature melting solder 31, a solder having a composition of Pb 37% and Sn 63% with a melting point of about 185 ° C. was used. In any case of soldering, the solders 31 and 32 did not flow out of the soldering points 41 and 51, and the solder balls did not adhere.
【0009】銅被膜2および7の表面に酸化防止のため
にNiめっきをした場合にも、レーザ光照射により表面
に銅酸化膜8を形成することができ、同様の効果が得ら
れた。Even when the surfaces of the copper coatings 2 and 7 were plated with Ni to prevent oxidation, the copper oxide film 8 could be formed on the surfaces by laser light irradiation, and the same effect was obtained.
【0010】[0010]
【発明の効果】本発明によれば、支持板表面の金属層を
レーザ光などにより選択的に加熱して金属酸化層をろう
付け部以外に形成することにより、溶融したろう材の流
れ出しがなくなり、金属層領域間の絶縁沿面距離が確保
される。また、はんだの厚みが安定し、ろう付強度も確
保される。さらに、はんだボールのような飛散したろう
材が酸化層の表面に付きにくくなり、付着しても容易に
取り除くことが可能になるため、金属層領域間の短絡が
起こることもない。According to the present invention, the metal layer on the surface of the support plate is selectively heated by a laser beam or the like to form the metal oxide layer on the portion other than the brazing portion, so that the molten brazing material does not flow out. , The insulation creepage distance between the metal layer regions is secured. Further, the thickness of the solder is stable and the brazing strength is secured. Further, scattered brazing material such as solder balls is less likely to adhere to the surface of the oxide layer and can be easily removed even if it adheres, so that no short circuit occurs between the metal layer regions.
【図1】本発明の一実施例の半導体装置支持板の酸化膜
形成後の状態を示し、 (a) が平面図、 (b) が側断面
図1A and 1B show a state after an oxide film is formed on a semiconductor device support plate according to an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a side sectional view.
【図2】図1の支持板の酸化膜形成前の状態を示し、
(a) が平面図、 (b) が側断面図2 shows a state before forming an oxide film on the support plate of FIG.
(a) is a plan view, (b) is a side sectional view
【図3】はんだの流れ出しの際の側断面図FIG. 3 is a side sectional view when solder flows out.
【図4】はんだボール付着の際の側断面図FIG. 4 is a side sectional view when solder balls are attached.
【図5】本発明の実施される半導体装置支持板の実装後
の状態を示し、 (a) が平面図、 (b) が側断面図5A and 5B show a state after mounting a semiconductor device support plate according to the present invention, where FIG. 5A is a plan view and FIG. 5B is a side sectional view.
1 セラミック基板 2、7 銅被膜 31 高温溶融はんだ 32 低温溶融はんだ 4 半導体チップ 41 半導体チップ固着個所 5 端子導体 51 端子導体固着個所 8 銅酸化膜 1 Ceramic Substrate 2, 7 Copper Coating 31 High Temperature Melting Solder 32 Low Temperature Melting Solder 4 Semiconductor Chip 41 Semiconductor Chip Fixing Point 5 Terminal Conductor 51 Terminal Conductor Fixing Point 8 Copper Oxide Film
Claims (3)
体素体をろう付けにより固着する工程を含む半導体装置
の製造方法において、金属層の表面を選択的に加熱して
所定の領域を残して酸化金属層を形成し、金属面の露出
する領域に半導体素体をろう付けすることを特徴とする
半導体装置の製造方法。1. A method of manufacturing a semiconductor device, which includes a step of fixing at least a semiconductor element body to a metal layer region on a surface of a support plate by brazing, the surface of the metal layer being selectively heated to leave a predetermined region. A method of manufacturing a semiconductor device, comprising forming a metal oxide layer and brazing a semiconductor element body to an exposed region of a metal surface.
ーザ光を照射する請求項1記載の半導体装置の製造方
法。2. The method of manufacturing a semiconductor device according to claim 1, wherein laser light is irradiated to selectively heat the surface of the metal layer.
を銅により形成する請求項1あるいは2記載の半導体装
置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein at least a part of the metal layer in the thickness direction is formed of copper.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6165691A JPH0831848A (en) | 1994-07-19 | 1994-07-19 | Production of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6165691A JPH0831848A (en) | 1994-07-19 | 1994-07-19 | Production of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0831848A true JPH0831848A (en) | 1996-02-02 |
Family
ID=15817216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6165691A Pending JPH0831848A (en) | 1994-07-19 | 1994-07-19 | Production of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0831848A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080206928A1 (en) * | 2007-02-26 | 2008-08-28 | Fuji Electric Device Technology Co., Ltd. | Soldering method and method of manufacturing semiconductor device including soldering method |
JP2008277438A (en) * | 2007-04-26 | 2008-11-13 | Ricoh Microelectronics Co Ltd | Electronic component, substrate, and method of manufacturing electronic component and substrate |
JP2011249451A (en) * | 2010-05-25 | 2011-12-08 | Nec Tohoku Ltd | Method of forming dam for damming upper stream body of printed wiring board, dam, and printed wiring board |
JP2013236037A (en) * | 2012-05-11 | 2013-11-21 | Mitsubishi Electric Corp | Semiconductor module and manufacturing method of the same |
EP2669938A2 (en) | 2012-05-28 | 2013-12-04 | Hitachi Ltd. | Semiconductor device with an oxide solder flow prevention area on a substrate and corresponding manufacturing method |
WO2014198511A1 (en) * | 2013-06-14 | 2014-12-18 | Robert Bosch Gmbh | Substrate having a soldering resist region consisting of oxide, sulfide or nitride for delimiting a soldering region and corresponding production process |
JP2015181269A (en) * | 2015-05-21 | 2015-10-15 | 京セラクリスタルデバイス株式会社 | piezoelectric device |
US10339968B2 (en) | 2017-09-08 | 2019-07-02 | Nidec Corporation | Base unit, spindle motor, and disk drive apparatus |
US11587879B2 (en) | 2020-01-23 | 2023-02-21 | Fuji Electric Co., Ltd. | Electronic apparatus and manufacturing method thereof |
-
1994
- 1994-07-19 JP JP6165691A patent/JPH0831848A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080206928A1 (en) * | 2007-02-26 | 2008-08-28 | Fuji Electric Device Technology Co., Ltd. | Soldering method and method of manufacturing semiconductor device including soldering method |
JP2008207207A (en) * | 2007-02-26 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | Method for solder joining, and method for manufacturing semiconductor device using the same |
US8273644B2 (en) | 2007-02-26 | 2012-09-25 | Fuji Electric Co., Ltd. | Soldering method and method of manufacturing semiconductor device including soldering method |
JP2008277438A (en) * | 2007-04-26 | 2008-11-13 | Ricoh Microelectronics Co Ltd | Electronic component, substrate, and method of manufacturing electronic component and substrate |
JP2011249451A (en) * | 2010-05-25 | 2011-12-08 | Nec Tohoku Ltd | Method of forming dam for damming upper stream body of printed wiring board, dam, and printed wiring board |
JP2013236037A (en) * | 2012-05-11 | 2013-11-21 | Mitsubishi Electric Corp | Semiconductor module and manufacturing method of the same |
EP2669938A2 (en) | 2012-05-28 | 2013-12-04 | Hitachi Ltd. | Semiconductor device with an oxide solder flow prevention area on a substrate and corresponding manufacturing method |
JP2013247256A (en) * | 2012-05-28 | 2013-12-09 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
EP2669938A3 (en) * | 2012-05-28 | 2014-04-09 | Hitachi Ltd. | Semiconductor device with an oxide solder flow prevention area on a substrate and corresponding manufacturing method |
US9076774B2 (en) | 2012-05-28 | 2015-07-07 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device and a method of manufacturing same |
WO2014198511A1 (en) * | 2013-06-14 | 2014-12-18 | Robert Bosch Gmbh | Substrate having a soldering resist region consisting of oxide, sulfide or nitride for delimiting a soldering region and corresponding production process |
JP2015181269A (en) * | 2015-05-21 | 2015-10-15 | 京セラクリスタルデバイス株式会社 | piezoelectric device |
US10339968B2 (en) | 2017-09-08 | 2019-07-02 | Nidec Corporation | Base unit, spindle motor, and disk drive apparatus |
US11587879B2 (en) | 2020-01-23 | 2023-02-21 | Fuji Electric Co., Ltd. | Electronic apparatus and manufacturing method thereof |
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