DE1514822A1 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents
Verfahren zur Herstellung einer HalbleiteranordnungInfo
- Publication number
- DE1514822A1 DE1514822A1 DE19651514822 DE1514822A DE1514822A1 DE 1514822 A1 DE1514822 A1 DE 1514822A1 DE 19651514822 DE19651514822 DE 19651514822 DE 1514822 A DE1514822 A DE 1514822A DE 1514822 A1 DE1514822 A1 DE 1514822A1
- Authority
- DE
- Germany
- Prior art keywords
- prongs
- semiconductor
- frame
- embedding
- shaped part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01005—Boron [B]
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- H01L2924/01074—Tungsten [W]
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- H01L2924/01079—Gold [Au]
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- H01L2924/01082—Lead [Pb]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Bipolar Transistors (AREA)
- Cold Cathode And The Manufacture (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
822
Tel ©funken Patentverwertungsgesellschaft
m.b.H.
Ulm/Donau, Elisabethenstr. 3
Ulm/Donau, Elisabethenstr. 3
Heilbronn, den 9. Juni 1965
PE/PT-M/N - Hn 71/64
"Verfahren zur Herstellung einer Halbleiteranordnung11
Für integrierte Halbleiterschaltungen verwendet man zur
Zeit Flachgehäuee, die aus Keramik oder Glas bestehen und
auf jeder Seite je fünf oder sechs eingeschmolzene Flachdurchführungen enthalten* In das Gehäuse werden die integrierten
Schaltungen in Form von Halbleiterplättchen, von denen jedes Plättchen mehrere aktive oder passive Bauelemente enthält, eingeklebt und es werden dann Bondkontakte
von den Halbleiterplättchen zu den Durchführungen hergestellt. Da es bei den integrierten Schaltungen darauf
ankommt, möglichst kleine Abmessungen zu erzielen, hängt die Dimension des fertigen,integrierten Bauelements von
der Größe dieses aeh&uses ab. Bei den bislang verwendeten
Gehäusen n»h»en diese etwa io mal so viel Platz ein, wie
die lialbleit*rplMttchem selbst.
die MiniaturisieruÄf bei gleichseitiger Vereinfachung
Herstellungsverfahrens weiter vorantreiben zu können,
wird *rfinduftgsge«**ß vorgeschlagen, daß «in zum Kontaktieren
909826/0572 badoriginal
ψ - a -
15U822
geeignetes Blech derart mit Aussparungen versehen wird, daß ein rahmenförmiger Teil mit nach innen ragenden Zinken
entsteht, auf die entweder ein Halbleiterkörper oder ein
ZuIeitungsdraht zu einer albleiterelektrode aufgelötet
wird, und daß die Zinken zusammen mit dem (den) Halbleiterkörper (η) in einen Kunststoff eingebettet und nach
dem Einbetten vom rahmenförmigen Teil des Bleches getrent
werden.
Der Vorteil dieses Verfahrens beruht darin, daß die Stanzoder geätzten Teile sehr klein gemacht werden können, und
daß man den Schutz der Kristalloberfläche und den mechanischen Halt der Durchführungen mit einem Arbeitsgang durchführen
kann. Um eine integrierte Halbleiteranordnung gemäß der Erfindung aufbauen zu können, stanzt oder ätzt man ein
geeignetes Blech so aus, daß ein rahmenförmiges Teil mit
so vielen nach innen ragenden Zinken entsteht, wie Gehäusedurchführungen erforderlich sind· Die monolitische, integrierte
Halbleiterschaltung wird in For« eines Plättchens auf einen dieser Zinken aufgelötet und von diesen Plättchen
werden dann die Bondverbindungen zu den anderen Zinken hergestellt. Je nach der Zahl der Zinken können auch zwei
oder «ehr integrierte Halbleiterplättchen »it dee erfindungagee&ß
ausgebildeten Blechteiltontaktiert werden. Nach
de» Kontaktieren wird eine Passivierung der Halbleiter-
909828/0572 _ 3 _
15H822
schaltungen vorgenommen, indem z.B. ein Glaspulver aufgesprüht und bei etwa 55o°C in einem Ofen zum Schmelzen
gebracht wird. Auf diesen Arbeitsgang kann unter Umständen verzichtet werden,und man kann direkt nach dem Kontaktieren
das System durch einen Backprozess in Kunststoff oder Glas einbetten. Dies geschieht bei- Temperaturen zwischen
15o und 2oo C bei Verwendung von Epoxydharz und bei 3<>o
bis 600 C, wenn man Glas verwendet. Dabei legt sich der Isolierstoff zwischen die Zinken und über die Halbleiterplättchen
und bildet ao eine se hut ζ axle Hülle für die integrierten
Schaltelemente und gibt den Zinken, die nach dem anschließsenden Abtrennen des rahmenförmigen Teils
als Gehäusedurchführungen dienen, den mechanischen Halt
bei gleichzeitiger, gegenseitiger Isolierung.
Eine Weiterbildung des bisher beschriebenen Verfahrens besteht darin, daß die Zinken soweit in eine Feinstruktur
übergehen, daß sie direkt auf die Kontaktstruktur der HaIbleiterplättchen
zugeschnitten sind. Die Zinken sind nun so angeordnet, daß sie beim Auflegen eines Halbleiterplättchens
direkt mit den Kontaktflecken des Plättchens in Berührung kommen. Nach dem richtigen Auflegen können die
Kontaktflecken direkt mit den sie berührenden Zinken verlötet werden, oder man kontaktiert die Kontaktflecken mit
den Zinken durch Bonden.
909826/0572
Kontaktiert man durch Bonden, so wird das Halbleiterplättchen
zuerst mit der den Kontaktflecken abgewandten Seite
auf eine Unterlage gejagt· Dann wird das Blech mit der
Kontaktierungsstruktur auf das Halbleiterplättchen gelegt
und mit Hilfe eines Druckstempels bei gleichzeitiger Anwendung von erhöhter Temperatur oder von Ultraschall
mit den Kontaktflecken in Kontakt gebracht· Passivierung
und Festlegung der Durchführungen erfolgt in der gleichen Weise trie sie bereits oben beschrieben wurde.
Das Verfahren gemäß der Erfindung soll anhand eines Ausführungsbeispiels
näher erläutert, werden·
Die Figur zeigt das ausgestanzte oder geätzte Blech mit dem rahmenförmigen Teil 1 und den Zinken 2. Auf zwei der
Zinken wurde eine auf einem Halbleiterplättchen untergebrachte integrierte Schaltung 3 aufgebracht. Von diesen
Halbleiterplättchen gehen Bondkontakte k zu den noch freien
Zinken. Im Bereich 5 werden die Zinken mit den Halbleiterplättchen in Epoxydharz oder Glas eingebettet. Anschliessend
werden die Zinken durch Abtrennen des rahmenförmigen Teils 1 an den Schnittflächen 6 und 7 elektrisch voneinander
getrennt. Die aus der Kunststoff- oder Glasmasse heraus· ragenden Zinkenenden werden nun als Gehäusedurchführungen
verwendet.
909826/0572 - 5 -
Claims (3)
- - 5 - 1314822Patentansprüchel) Verfahren zur Herstellung einer Halbleiteranordnung, insbesondere integrierte Schaltungen, dadurch gekennzeichnet, daß ein zum Kontaktieren geeignetes Blech derart mit Aussparungen versehen wird, daß ein rahmenförmiger Teil mit nach innen ragenden Zinken entsteht, auf die entweder ein Halbleiterkörper oder ein ZuIeitungsdraht zu einer Halbleiterelektrode aufgelötet wird, und daß die Zinken zusammen mit dem(den) Haibleiterkörper(n) in einen Kunststoff eingebettet und nach dem Einbetten vom rahmenförmigen Teil des Bleches getrennt werden.
- 2) Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß zum Einbetten ein aushärtbarer Kunststoff verwendet wird·
- 3) Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß zum Einbetten ein aufschmelzbares Glas verwendet wird·k) Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Aussparungen durch Ausstanzen oder Ätzen hergestellt werden.90 98 26/0 572Leerseite
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DET0026811 | 1964-08-14 | ||
DET0028783 | 1965-06-12 | ||
DET0028863 | 1965-06-24 | ||
DET0029398 | 1965-09-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE1514822A1 true DE1514822A1 (de) | 1969-06-26 |
Family
ID=27437635
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19651514822 Pending DE1514822A1 (de) | 1964-08-14 | 1965-06-12 | Verfahren zur Herstellung einer Halbleiteranordnung |
DE1514827A Expired DE1514827C2 (de) | 1964-08-14 | 1965-06-24 | Verfahren zur serienmäßigen Herstellung von Halbleiterbauelementen |
DE1514869A Expired DE1514869C3 (de) | 1964-08-14 | 1965-09-14 | Verfahren zur serienmäßigen Herstellung von Hochfrequenztransistoren |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1514827A Expired DE1514827C2 (de) | 1964-08-14 | 1965-06-24 | Verfahren zur serienmäßigen Herstellung von Halbleiterbauelementen |
DE1514869A Expired DE1514869C3 (de) | 1964-08-14 | 1965-09-14 | Verfahren zur serienmäßigen Herstellung von Hochfrequenztransistoren |
Country Status (6)
Country | Link |
---|---|
US (1) | US3281628A (de) |
JP (1) | JPS516503B1 (de) |
AT (2) | AT261004B (de) |
CH (1) | CH439501A (de) |
DE (3) | DE1514822A1 (de) |
GB (1) | GB1112604A (de) |
Families Citing this family (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3444440A (en) * | 1964-11-27 | 1969-05-13 | Motorola Inc | Multiple lead semiconductor device with plastic encapsulation supporting such leads and associated elements |
DE1514015A1 (de) * | 1965-06-01 | 1970-08-20 | Itt Ind Gmbh Deutsche | Verfahren zum Herstellen von mit einer Huelle umgebenen und mit Zuleitungen versehenen Halbleiteranordnungen |
US3413713A (en) * | 1965-06-18 | 1968-12-03 | Motorola Inc | Plastic encapsulated transistor and method of making same |
US3522490A (en) * | 1965-06-28 | 1970-08-04 | Texas Instruments Inc | Semiconductor package with heat conducting mounting extending from package on side opposite conductor extensions |
US3426423A (en) * | 1965-07-08 | 1969-02-11 | Molectro Corp | Method of manufacturing semiconductors |
DE1514881C3 (de) * | 1965-10-15 | 1975-05-28 | Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm | Verfahren zum Kontaktieren eines Halbleiterbauelementes |
US3429030A (en) * | 1965-10-23 | 1969-02-25 | Rca Corp | Method of fabricating semiconductor devices |
US3418089A (en) * | 1965-12-16 | 1968-12-24 | Berg Electronics Inc | Assembly for transistor manufacture |
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BE475135A (de) * | 1943-10-26 | 1900-01-01 | ||
US2750654A (en) * | 1950-10-03 | 1956-06-19 | Harry L Owens | Miniature rectifier |
US3025439A (en) * | 1960-09-22 | 1962-03-13 | Texas Instruments Inc | Mounting for silicon semiconductor device |
US3118016A (en) * | 1961-08-14 | 1964-01-14 | Texas Instruments Inc | Conductor laminate packaging of solid-state circuits |
US3171187A (en) * | 1962-05-04 | 1965-03-02 | Nippon Electric Co | Method of manufacturing semiconductor devices |
US3184658A (en) * | 1962-05-22 | 1965-05-18 | Texas Instruments Inc | Semiconductor device and header combination |
-
1965
- 1965-06-12 DE DE19651514822 patent/DE1514822A1/de active Pending
- 1965-06-24 DE DE1514827A patent/DE1514827C2/de not_active Expired
- 1965-07-19 AT AT669266A patent/AT261004B/de active
- 1965-07-19 AT AT663865A patent/AT254948B/de active
- 1965-08-11 GB GB34353/65A patent/GB1112604A/en not_active Expired
- 1965-08-13 CH CH1138465A patent/CH439501A/de unknown
- 1965-08-14 JP JP40049381A patent/JPS516503B1/ja active Pending
- 1965-08-16 US US486585A patent/US3281628A/en not_active Expired - Lifetime
- 1965-09-14 DE DE1514869A patent/DE1514869C3/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
AT254948B (de) | 1967-06-12 |
DE1439717A1 (de) | 1969-03-20 |
DE1514827A1 (de) | 1969-09-11 |
US3281628A (en) | 1966-10-25 |
DE1514827B2 (de) | 1972-11-16 |
CH439501A (de) | 1967-07-15 |
DE1514869A1 (de) | 1969-09-04 |
AT261004B (de) | 1968-04-10 |
DE1439717B2 (de) | 1972-11-16 |
JPS516503B1 (de) | 1976-02-28 |
DE1514869B2 (de) | 1974-06-20 |
GB1112604A (en) | 1968-05-08 |
DE1514827C2 (de) | 1981-11-19 |
DE1514869C3 (de) | 1975-01-30 |
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