WO2014175325A1 - 半導体装置及びその制御方法 - Google Patents

半導体装置及びその制御方法 Download PDF

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WO2014175325A1
WO2014175325A1 PCT/JP2014/061408 JP2014061408W WO2014175325A1 WO 2014175325 A1 WO2014175325 A1 WO 2014175325A1 JP 2014061408 W JP2014061408 W JP 2014061408W WO 2014175325 A1 WO2014175325 A1 WO 2014175325A1
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data
command
semiconductor device
control circuit
input
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PCT/JP2014/061408
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English (en)
French (fr)
Japanese (ja)
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梶谷　一彦
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ピーエスフォー ルクスコ エスエイアールエル
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites

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  • the present invention is based on the priority claim of Japanese Patent Application No. 2013-093927 (filed on Apr. 26, 2013), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a semiconductor device including a resistance change type memory cell and a control method thereof.
  • flash memories are widely used as nonvolatile semiconductor memory devices, but various semiconductor memory devices are being developed for the purpose of replacing the flash memories.
  • a resistance change type memory cell is known that uses a resistance change type element and stores information of logic 0 and logic 1 depending on its resistance state.
  • the resistance variable element There are two types of writing of the resistance variable element: writing that changes the high resistance state to the low resistance state and writing that changes the low resistance state to the high resistance state.
  • the low resistance state is logic 1 (data 1)
  • the high resistance state is logic 0 (data 0).
  • an STT-RAM Spin Transfer Torque-Random Access Memory
  • MTJ magnetic tunnel junction
  • metal oxide a metal oxide, or the like
  • Re-RAM Resitive-Random Access Memory
  • Patent Documents 1 and 2 the data read by the sense amplifier is latched in advance in order to solve the problem that the data of the memory cell that has been read in the STT-RAM is inverted due to the disturbance caused by the current at the time of reading.
  • a control system for rewriting the latched data in a memory cell is disclosed.
  • DRAM which is a volatile memory
  • a technique for performing column access using page mode and improving the data bus bandwidth between a main memory and a CPU (Central Processing Unit) is known.
  • the write time of the resistance change type memory cell is often several times longer than that of a DRAM (Dynamic Random Access Memory). For this reason, if a resistance change type memory cell having a long write time is used, the cycle time of column access becomes long, so that there is a problem that the bandwidth during the page mode operation is not improved.
  • DRAM Dynamic Random Access Memory
  • a semiconductor device is arranged corresponding to a word line, a plurality of bit lines, and an intersection position of the word line and the plurality of bit lines, one end of each of the plurality of bit lines.
  • a plurality of resistance-change memory cells connected; a plurality of data control circuits connected to the plurality of bit lines; and a command control circuit.
  • the command control circuit activates the word line in response to an input of a first command, and sends data to one or more selected data control circuits in response to an input of a second command.
  • the data held in the selected one or more data control circuits are simultaneously written in the corresponding resistance change type memory cells.
  • a method for controlling a semiconductor device comprising: a word line; a plurality of bit lines; and an intersection position of the word line and the plurality of bit lines.
  • a method for controlling a semiconductor device including a plurality of resistance change type memory cells connected to a line includes the following steps. That is, the semiconductor device control method includes a step of activating the word line in response to the input of the first command. The semiconductor device control method includes a step of holding data to be written to each of the resistance-change memory cells connected to the selected one or more bit lines in response to an input of a second command. Further, the method for controlling the semiconductor device includes a step of simultaneously writing the selected one or more data into the corresponding resistance change type memory cells in response to an input of a third command.
  • the semiconductor device of the present invention it is possible to provide a semiconductor device including a resistance change type memory cell that can contribute to the realization of an efficient page mode.
  • FIG. 1 is a block diagram illustrating an overall configuration of a semiconductor device according to a first embodiment. It is a figure which shows the structure of the whole chip
  • FIG. 1 is a circuit diagram of one sub mat of a semiconductor device according to a first embodiment. It is a wave form diagram showing operation of a submat of a semiconductor device concerning a 1st embodiment.
  • 2 is a circuit diagram of an RWC (read / write control circuit) of the semiconductor device according to the first embodiment.
  • FIG. It is a wave form diagram showing operation of a semiconductor device concerning a 1st embodiment. It is a wave form diagram showing operation of a semiconductor device concerning a 1st embodiment.
  • FIG. 6 is a circuit diagram of one sub mat of a semiconductor device according to a second embodiment. It is a wave form diagram showing operation of a sub mat of a semiconductor device concerning a 2nd embodiment.
  • FIG. 6 is a circuit diagram of an RWC (read / write control circuit) of a semiconductor device according to a second embodiment. It is a wave form diagram showing operation of a semiconductor device concerning a 2nd embodiment. It is a wave form diagram showing operation of a semiconductor device concerning a 2nd embodiment.
  • FIG. 6 is a circuit diagram of an RWC (read / write control circuit) of a semiconductor device according to a third embodiment. It is a wave form diagram showing operation of a semiconductor device concerning a 3rd embodiment. It is a wave form diagram showing operation of a semiconductor device concerning a 3rd embodiment. It is a block diagram which shows the structure of the information processing system which concerns on 4th Embodiment.
  • the semiconductor device 501 in one embodiment is arranged corresponding to the intersection of the word line 505, the plurality of bit lines 504a to d, and the word line 505 and the plurality of bit lines 504a to 504d.
  • a plurality of resistance change type memory cells 502a to 502d having one ends connected to the plurality of bit lines 504a to 504d, a plurality of data control circuits 503a to 503d connected to the plurality of bit lines 504a to 504d, and a command, respectively.
  • the command control circuit 508 activates the word line 505 in response to the input of the first command (for example, Act of FIG.
  • FIG. 11 illustrates the case where the two data control circuits 503b, 503c are selected), respectively.
  • Resistive memory cells corresponding respectively to data (506b, 506c) held in one or more selected data control circuits (eg, 503b, 503c) in response to an input of a command (eg, Pre in FIG. 11) (For example, 502b and 502c) are simultaneously written.
  • data (506b, 506c) is written to the selected data control circuit (in the case of FIG. 1, 503b, 503c) in the page access by the second command. Then, by the third command, writing can be performed only to the resistance change type memory cells (in the case of FIG. 1, 502b and 502c) connected to the selected data control circuit (503b and 503c). And an efficient page mode can be realized. As a result, the current consumption of the semiconductor device can be reduced.
  • the plurality of data control circuits 503a to 503d respectively correspond to the input of the first command (for example, Act of FIG. 11).
  • the read data 507a to d read from the resistance change type memory cells 502a to 502d are held, and one or more selected data control circuits (in FIG. 2, the case where two data control circuits 503b and 503c are selected are illustrated. 1) overwrites the read data (507b, 507c) of the data control circuit with data generated in response to the input of the second command (for example, Wt in FIG. 11), and the above data (in FIG. 1). 506b, 506c).
  • the data generated in response to the input of the second command (for example, Wt in FIG. 11) is not the read data (507b, 507c) of the data control circuit but the other read data (for example, 507a, 507d). And may be held as the data.
  • one of the plurality of data control circuits is not selected regardless of the input of the third command (for example, Pre in FIG. 11).
  • the above data control circuits (503a, 503d, etc. in the case of FIGS. 1 and 2) do not perform writing to the corresponding resistance change type memory cells (502a, 502d, etc. in FIGS. 1 and 2). It is preferable to make it.
  • the word line 505 is changed. It is preferable to deactivate.
  • the data control circuit (44b, etc.) when the column selection signal YS_i supplied to the data control circuit (44b, etc.) is in an active state, the data control circuit (44b, etc.) is selected. It may be.
  • the data control circuit (44b, etc.) detects and holds the column selection signal YS_i activated when the second command (for example, Wt in FIG. 11) is executed.
  • the output of the column selection signal detection circuit 191 and the column selection signal detection circuit 191 is in an activated state, data (Q, / of the data latch circuit 88, etc.) when the third command (for example, Pre in FIG. 11) is executed.
  • a write control circuit 192 that controls the potential of the corresponding bit line (GBL_i) based on Q).
  • the semiconductor device 1 further includes a source line (GCS_i) connected to the other ends (first terminals 68a to 68f in FIG. 8) of the plurality of resistance change type memory cells. Also good.
  • the write control circuit 192 of the data control circuit 44b performs data (data latch circuit) when the third command (for example, Pre in FIG. 11) is executed when the held column selection signal YS_i is in an activated state. 88 / Q), the potential of the source line (GCS_i or the like) may be further controlled.
  • the first fixed potential may be supplied to the other ends (the first terminals 68a to 68f of FIG. 8) of the plurality of resistance change type memory cells.
  • the read data (/ Q of the data latch circuit 88 when the read pulse signal RP is active) by the first command (for example, Act in FIG. 19) and
  • the data control circuit (244b, etc.) may be selected.
  • the data control circuit (244b, etc.) reads the read data (/ Q of the data latch circuit 88 when the read pulse signal RP is active) by the first command (Act of FIG. 119).
  • a change detection circuit 391 and a write control circuit 392 that controls the potential of the corresponding bit line (GBL_i) based on the output of the data change detection circuit 391 may be provided.
  • the first end is connected to the other end of the plurality of resistance change type memory cells (the first terminals 68a to 68f in FIG. 8).
  • the fixed potential (VCS) may be supplied.
  • a method for controlling a semiconductor device in one embodiment includes a word line 505, a plurality of bit lines 504a to 504d, a word line 505, and a plurality of bit lines 504a to 504d.
  • a method of controlling a semiconductor device comprising a plurality of resistance change type memory cells 502a to 502d arranged corresponding to intersection positions and having one end connected to a plurality of bit lines 504a to 504d, respectively. including. That is, the semiconductor device control method includes a step of activating the word line 505 (timing t0 ′ in FIG. 11) in response to an input of a first command (for example, Act in FIG. 11), and a second command.
  • Resistor connected to one or more selected bit lines for example, two bit lines 504b and 504c are selected in FIG. 1 according to the input of (for example, Wt in FIG. 11)
  • steps of holding data (506b, 506c) to be written in the changeable memory cells (502b, 502c in FIG. 1) (period T3 in FIG. 11) and a third command (for example, Pre in FIG. 11), respectively.
  • the step of simultaneously writing the selected one or more data (506b, 506c) into the corresponding resistance change type memory cells (502b, 502c in FIG. 1) (FIG. 1). Including 1 in the period T4) of the, the.
  • the control method of the semiconductor device described above includes a plurality of resistance change type memory cells 502a to 502d in response to an input of a first command (for example, Act in FIG. 11).
  • the read data 507a to d are read out and held (period T1 in FIG. 11) and the data generated in response to the input of the second command (for example, Wt in FIG. 11) are read data (507b, 507c).
  • FIG. 3 is a block diagram showing the overall configuration of the semiconductor device 1.
  • the semiconductor device 1 shown in FIG. 3 includes a memory cell array (2a to h) using a bipolar STT-RAM (Spin Transfer Torque Random Access Memory) that performs spin injection magnetization reversal writing as a resistance change type memory cell. .
  • the semiconductor device 1 also includes external clock terminals CK and / CK, a clock enable terminal CKE, command terminals / CS, / RAS, / CAS, / WE, and a data input / output terminal DQ as external terminals.
  • a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, CK and / CK are complementary signals.
  • the external clock signals CK and / CK and the clock enable signal CKE are input to the clock generation circuit 22, and the clock generation circuit 22 generates an internal clock signal required inside the semiconductor device 1 and supplies it to each unit.
  • the command terminals / CS, / RAS, / CAS and / WE are supplied with a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable signal / WE, respectively. These command signals are supplied to the command decoder 21.
  • the command decoder 21 decodes the input command signal and supplies it to the chip control circuit 20.
  • the mode register 19 sets the operation mode of the semiconductor device 1.
  • the chip control circuit 20 inputs the output of the command decoder 21 and the operation mode set in the mode register 19, generates various control signals based on them, generates an array control circuit 12, an RW (read / write) amplifier 14, The data is supplied to the latch circuit 15, data input / output buffer 16, column address buffer 17, bank and row address buffer 18.
  • the command decoder 21, mode register 19, and chip control circuit 20 described above constitute a command control circuit (corresponding to 508 in FIGS. 1 and 2).
  • the address signal ADD includes a bank address that specifies a bank, a row address that specifies a word line (configured by a main word line MWL and a sub word line SWL), and a bit line (a global bit line GBL and a local bit line LBL).
  • Column address specifying Of the address signal ADD the bank and row address are supplied to the bank and row address buffer 18, and the column address is supplied to the column address buffer 17.
  • the bank and row address buffer 18 specifies one of the banks 0 to 7 and outputs a row address.
  • the row address output from the bank and row address buffer 18 is decoded by the MWL decoder 13, and one of the main word lines MWL is selected according to this decoding.
  • the column address output from the column address buffer 17 is decoded by the column decoder 11, and a bit line corresponding to the column address is selected from the plurality of bit lines according to the decoding.
  • the data latch circuit (88 in FIG. 10) in the memory cell array corresponding to the selected bit line is connected to the RW (read / write) amplifier 14 via the I / O line pair 89.
  • the RW amplifier 14 is a read amplifier circuit and a write amplifier circuit connected to the data input / output terminal DQ which is an external terminal via the latch circuit 15 and the data input / output buffer 16.
  • an internal clock signal is supplied from the clock generation circuit 22 to the latch circuit 15 and the data input / output buffer 16, and the data input / output timing between the memory cell array and the data input / output terminal DQ is controlled.
  • FIG. 4 is a diagram illustrating a configuration of the entire chip of the semiconductor device 1 according to the first embodiment.
  • MWL main word line
  • a column decoder 11 is arranged in the central portion of the horizontal direction.
  • Array_0 to array_3 (3a to d) are arranged in four regions divided by the MWL decoder 13 and the column decoder 11.
  • FIG. 5 is a diagram showing the configuration of one bank of the semiconductor device 1, and shows the bank_0 (2a) of FIG. 4 rotated 90 degrees.
  • Each of the four arrays_0 to 3 (3a to d) is divided into 8 in the horizontal direction and 16 in the vertical direction, and is divided into a total of 128 mats MAT (43, etc.).
  • a sub word line SWL driver 45a and a sub mat sub-MAT control circuit 46a are arranged at the upper and lower ends of each MAT, and a read / write control circuit RWC (44a etc.) is arranged at the left and right ends of each MAT.
  • the sub-MAT control circuit (such as 46a) and the RWC (such as 44a) are shared between adjacent MATs.
  • FIG. 6 is a diagram showing the configuration of one array of FIG.
  • the array is divided into eight blocks BLOCK_0 to BLOCK_7 (5a to 5h) each consisting of a MAT column in which 16 MATs are arranged in the vertical direction.
  • BLOCK_0 to BLOCK_7 5a to 5h
  • the resistance change type memory cell is accessed, as shown in FIG. 6, in each of the four arrays in one bank, one segment 52 in one block is selected (the selected segment 52 Are also referred to as “activated segments”), and the read / write control circuit RWC columns 51a and 51b on both sides of the segment are activated (the activated RWC columns are also referred to as “activated RWC columns”). Therefore, a total of eight activated RWC columns are generated in one bank, and constitute an open page.
  • FIG. 7 is a diagram showing a configuration of one mat MAT43 in FIG.
  • the MAT is divided into 16 sub-MATs in the horizontal direction and 32 sub-parts in the vertical direction, and is divided into a total of 512 sub-MATs (here, 512 sub-MATs included in one mat MAT43).
  • the area configured by the above is called the MAT area 83).
  • the sub-MATs arranged in a line in the vertical direction constitute one activation segment 52 described above.
  • FIG. 7 shows the activation segments 52 within the MAT 43.
  • the sub-MAT in the activation segment 52 is arranged at the MAT end via one global bit line GBL and one global common source line GCS. Selectively connected to RWC.
  • the sub-MAT 63 in the activation segment 52 is connected to one of the RWCs 44b and 44c arranged at both ends of the row.
  • the MAT region 83 is divided into sub-MATs, and the bit lines are hierarchized into global bit lines GBL and local bit lines LBL as shown in FIG.
  • the influence of the resistance of the local bit line LBL can be reduced.
  • the influence of the resistance of the local common source line LCS made of a relatively high resistance material can be reduced.
  • the local common source line LCS can be shared by all the resistance change type memory cells in the sub-MAT, the resistance of the local common source line LCS can be further reduced.
  • 16 RWCs (32 RWCs in total) are arranged on both sides of 1MAT, and when one word line is selected, the 32 RWCs are simultaneously selected. Within one array, 512 RWCs will be selected (in FIG. 6, each of the activated RWC rows 51a, 51b includes 256 RWCs). Therefore, since one bank is composed of four arrays, when one word line is selected, 2048 RWCs are selected and a 2048-bit (256-byte) page is opened. Become.
  • the signal lines of the write pulse signal / WP are wired in the vertical direction of the drawing one by one in common with the 16 RWCs arranged at the left and right ends of the MAT in FIG.
  • the MAT adjacent to the upper and lower sides may be configured to use the same signal line, that is, one signal line may be provided in each RWC column of FIG.
  • writing is performed by simultaneously driving a number of RWCs. Therefore, the transmission of the write pulse signal / WP can use this common signal line.
  • Each of the GBL and GCS pairs is divided into even and odd numbers, the even GBL and GCS pairs are connected to the right RWC (44c, etc.), and the odd GBL and GCS pairs are connected to the left. Connected to RWC (44b etc.).
  • FIG. 8 is a diagram showing a configuration of one sub mat sub-MAT 63 in FIG.
  • the sub-MAT 63 includes an LCS (local common source line) control circuit 71, an LBL (local bit line) precharge circuit 72, a memory cell array 73, and an LBL (local bit line) selection circuit 74.
  • the memory cell array 73 is a two-dimensionally arranged memory cell array in one sub-mat sub-MAT, and has a different defined range from the bank-unit memory cell array (2a to h) in FIG. It is.
  • the memory cell array 73 includes m sub-word lines SWL0 to SWLm-1, k local bit lines LBL0 to LBLk-1, and m ⁇ k resistance change memory cells (67a to 67a) arranged at the intersections thereof. f). Note that 16 sub-MATs are connected to one pair of GBL and GCS as shown in FIG.
  • the LCS control circuit 71 includes an NMOS transistor 78 having a segment selection signal SEL connected to the gate and an NMOS transistor 77 having an inverted segment selection signal / SEL connected to the gate.
  • SEL is controlled to the low level and / SEL is controlled to the high level
  • the LCS local common source line
  • the GCS is electrically disconnected.
  • SEL is controlled to high level and / SEL is controlled to low level
  • LCS is electrically disconnected from VSS and electrically connected to GCS.
  • the LBL precharge circuit 72 is composed of k precharge NMOS transistors 79a to 79c connected to the gates of k precharge signals PC0 to PCk-1 for k LBLs (local bit lines), respectively.
  • the precharge signals PC0 to PCk-1 are controlled to a high level, LBL0 to LBLk-1 are electrically connected to the LCS and precharged to VSS. Further, when a segment is selected and activated, only the precharge signal corresponding to one selected LBL is controlled to the Low level, and the selected LBL is electrically disconnected from the LCS.
  • the LBL selection circuit 74 includes k connection signals SW0 to SWk-1 corresponding to k LBLs, each including k connection NMOS transistors 80a to 80c connected to the gates, and the semiconductor device 1 is precharged.
  • the connection signals SW0 to SWk-1 are controlled to the Low level, and each LBL is electrically disconnected from the GBL.
  • the connection signal corresponding to one selected LBL is controlled to a high level, and only the selected LBL is electrically connected to the GBL.
  • control signals / SEL, SEL, PC0 to PCk-1, SWL0 to SWLm-1, SW0 to SWk- which are control signals for the LCS control circuit 71, LBL precharge circuit 72, memory cell array 73, and LBL selection circuit 74 described above. 1 indicates that the High level is the potential VPP and the Low level is the potential VSS (see FIG. 9).
  • the LCS is electrically disconnected from the VSS and electrically connected to the GCS.
  • the selected LBL is electrically disconnected from the LCS and electrically connected to the GBL, and the remaining non-selected LBLs are electrically connected to the LCS.
  • the first terminal 68e is electrically connected to the GBL_GCS driver (reference numeral 82 in FIG. 10) via the LCS and GCS.
  • the second terminal 69e is electrically connected to the GBL_GCS driver (reference numeral 82 in FIG. 10) via LBL0 and GBL.
  • both the first terminal (68a, c, etc.) and the second terminal (69a, c, etc.) are electrically connected to the LCS. Therefore, even if the NMOS transistor (76a, c, etc.) in the resistance change memory cell is turned on, no voltage is applied to the resistance change element (75a, c, etc.) and no current flows. Therefore, even if the LCS potential is driven to VDD or VSS as will be described later, the stored information of the resistance variable element is not destroyed.
  • FIG. 10 is a circuit diagram of an RWC (read / write control circuit) of the semiconductor device 1 according to the first embodiment, and shows one (for example, 44b) of the plurality of RWCs in FIG.
  • the configuration of each RWC is the same).
  • the RWC is shared by the adjacent left and right MATs, but here, in order to simplify the description, a case where the RWC is connected to only one MAT will be described.
  • i attached to each of GBL, GCS, sense amplifier circuit SA, and data latch circuits LT, YS indicates the location of the RWC in FIG. 7 (i-th from the bottom).
  • the RWC (44b) includes a MAT write control circuit 85, a GBL_GCS driver 82, a sense latch circuit 84, and an input / output circuit 86.
  • the MAT write control circuit 85 includes a column selection signal detection circuit 191 and a write control circuit 192.
  • the column selection signal detection circuit 191 selects an RWC to be written by the precharge command Pre from among the RWCs included in the activated RWC sequence (51a, 51b) configuring the open page shown in FIGS. Plays a function.
  • the column selection signal detection circuit 191 includes a PMOS transistor (160, 162), an NMOS transistor (161, 163, 164), and an inverter circuit 178.
  • the PMOS transistor 162, the NMOS transistor 163, and the NMOS transistor 164 are connected in series between the power supply VDD and the ground.
  • the precharge signal / PC is connected to the gate of the PMOS transistor 162.
  • the drain of the PMOS transistor 162 and the drain of the NMOS transistor 163 are connected in common to the node N0. With the above structure, the node N0 can be precharged to the potential VDD in the precharge period (/ PC is at the low level).
  • the column selection signal YS_i is supplied to the gate of the NMOS transistor 163, and the write enable signal WE is supplied to the gate of the NMOS transistor 164.
  • the PMOS transistor 160 and the NMOS transistor 161 are connected in series between the power supply VDD and the ground to constitute one inverter circuit.
  • the inverter circuit is connected to an inverter circuit 178. This constitutes a latch circuit.
  • the drain of the PMOS transistor 160, the drain of the NMOS transistor 161, and the input terminal of the inverter circuit 178 are all connected to the node N0. With the above structure, the potential of the node N0 controlled by / PC, YS_i, and WE is held by the latch circuit.
  • the write control circuit 192 controls the potential of the global bit line GBL_i based on the output of the column selection signal detection circuit 191 and the data Q and / Q held in the data latch circuit 88, and the global A control signal C2 for controlling the potential of the common source line GCS_i is generated.
  • the write control circuit 192 includes a NOR logic circuit 175 and two NAND logic circuits (173, 174). One input terminal of the NOR logic circuit 175 is connected to the node N0. The write pulse signal / WP is supplied to the other input terminal of the NOR logic circuit 175. One input terminal of each of the two NAND logic circuits (173, 174) is connected to the output terminal of the NOR logic circuit 175.
  • the other input terminal of the NAND logic circuit 173 is connected to the output terminal Q of the data latch circuit 88.
  • the other input terminal of NAND logic circuit 174 is connected to output terminal / Q of data latch circuit 88. Then, the outputs of the NAND logic circuits (173 and 174) become the control signals C1 and C2, respectively.
  • the GBL_GCS driver 82 performs the function of driving the global bit line GBL_i and the global common source line GCS_i in response to the control signals C1 and C2, respectively.
  • the GBL_GCS driver 82 includes a PMOS transistor (102, 103), an NMOS transistor (104, 105), and an inverter circuit (98, 176).
  • the PMOS transistors (102, 103) are connected in series between the power supply VDD and the node Nout, and the NMOS transistors (104, 105) are connected in series between the node Nout and the ground.
  • the gates of the PMOS transistor 102 and the NMOS transistor 105 are connected to the node Nin1, and the control signal C1 is supplied from the write control circuit 192 to the node Nin1.
  • the node Nin0 is connected to the gate of the PMOS transistor 103 and is connected to the gate of the NMOS transistor 104 via the inverter circuit 98. Further, the read pulse signal RP is supplied to the node Nin0. Node Nout is connected to global bit line GBL_i.
  • control signal C2 supplied from the write control circuit 192 is connected to the global common source line GCS_i via the inverter circuit 176.
  • both the PMOS transistor 103 and the NMOS transistor 104 are turned off so that the GBL_GCS driver 82 does not perform the writing operation.
  • both the PMOS transistor 103 and the NMOS transistor 104 are turned on, and the PMOS transistor 102 and the NMOS transistor 105 connected above and below them turn on the global bit line according to the control signal C1.
  • GBL_i is driven.
  • the global common source line GCS_i is driven by logically inverting the control signal C2.
  • control signals C1 and C2 are at a low level and a high level, respectively.
  • GBL_i, and GCS_i are driven to a high level (VDD) and a low level (VSS), respectively.
  • the sense latch circuit 84 includes a sense amplifier circuit SA_i (87), a data latch circuit LT_i (88), and an NMOS transistor 101.
  • a read pulse signal RP is supplied to the gate of the NMOS transistor 101, and one of the source / drain of the NMOS transistor 101 is connected to the node Nout of the GBL_GCS driver 82.
  • the other of the source / drain of the NMOS transistor 101 is connected to the input terminal of the sense amplifier circuit 87.
  • the sense latch circuit 84 when the read pulse signal RP is controlled to a high level, the NMOS transistor 101 becomes conductive, and the input terminal of the sense amplifier circuit 87 and the global bit line GBL_i are electrically connected. It becomes a state. At this time, the sense amplifier circuit 87 compares the read current Iread flowing through the global bit line GBL_i with the reference current Iref, and the data latch circuit 88 latches the read data corresponding to the magnitude relationship.
  • the output terminals Q and / Q of the data latch circuit 88 are connected to the I / O line pair 89 via the input / output circuit 86, respectively.
  • the input / output circuit 86 includes NMOS transistors 106 and 107.
  • the gate of the NMOS transistor 106 and the gate of the NMOS transistor 107 are connected, and the connection node is connected to the terminal of the selection signal YS_i.
  • One of the source / drain of the NMOS transistors 106 and 107 is connected to the output terminals Q and / Q of the data latch circuit 88, respectively, and the other of the source / drain of the NMOS transistors 106 and 107 is connected to the I / O line pair 89, respectively. Connected.
  • the data latch circuit 88 inputs / outputs data to / from the outside via the I / O line pair 89 by the output terminals Q and / Q. Specifically, when YS_i is controlled to a high level at the time of reading (for example, when the read command Rd is executed), the read data held in the data latch circuit 88 in the RWC selected by YS_i is I / O. Read to line pair 89. Further, when YS_i is controlled to a high level at the time of writing (for example, when the write command Wt is executed), the data supplied via the I / O line pair 89 is written into the data latch circuit 88.
  • the area of the RWC necessary for performing such control increases with respect to a sense amplifier such as a DRAM, for example.
  • the wiring pitch of GBL and GCS is the wiring pitch of LBL. Therefore, the arrangement pitch of the RWCs connected to these can be reduced as compared with the DRAM.
  • FIG. 9 is a waveform diagram showing the operation of the sub-MAT (63 in FIG. 8) of the semiconductor device 1 according to the first embodiment. It is assumed that sub-MAT (63 in FIG. 8) is one of the activation segments (52 in FIG. 6). Here, it is assumed that SWL0 and LBL0 are selected as the sub word line and the local bit line, respectively.
  • the left half (A) of FIG. 9 shows the case of reading data 0 corresponding to the active command Act (read data is 0) ⁇ page access period ⁇ data 1 MAT writing corresponding to the precharge command Pre in order. The operation is shown.
  • “MAT write” refers to an operation of writing data held in the data latch circuit (88 in FIG. 10) into the corresponding resistance change type memory cell.
  • / SEL and PC0 are controlled to the potential VSS
  • SEL, SW0 and SWL0 are controlled to the potential VPP
  • LBL0 is electrically connected to GBL
  • LCS is electrically connected to GCS.
  • the potentials of GBL and LBL0 Prior to the start of the sense latch period, the potentials of GBL and LBL0 are set to the read potential Vread, and the read current Iread0 flows through the resistance change memory cell (67e in FIG. 8). Since Iread0 is a small value corresponding to the high resistance state, it is smaller than the reference current, and in the sense latch period, this current difference is sense-amplified by the sense amplifier circuit (87 in FIG. 10) and is sent to the data latch circuit (88 in FIG. 10). Data 0 (read data 0) is held. During this time, the potentials of GCS and LCS are held at VSS, and the potentials of GBL and LBL0 are held at approximately Vread.
  • MAT writing is performed when the RWC on which the writing has been performed executes the precharge command Pre. Selected as RWC (details of RWC selection will be described later). Subsequently, a MAT write period starts in response to the precharge command Pre.
  • GBL and LBL0 are driven to the potential VDD and GCS and LCS are driven to the potential VSS in response to the data 1 write in the selected RWC, the data 1 becomes MAT.
  • SWL0, SW0, and SEL are controlled to the potential VSS.
  • / SEL and PC0 are controlled to VPP, and LCS and LBL0 are precharged to VSS.
  • GCS and GBL are precharged to the potential VSS by RWC (44b in FIG. 10).
  • the right half (B) of FIG. 9 shows the operation when data 1 is read (read data is 1) ⁇ page access period ⁇ data 0 is sequentially written into MAT.
  • the operation from the precharge period to the cell selection period is the same as in the left half (A) of FIG.
  • the potentials of GBL and LBL0 are set to the read potential Vread, and a read current Iread1 flows through the resistance change type memory cell (67e in FIG. 8). Since the read current Iread1 is a large value corresponding to the low resistance state, the read current Iread1 is larger than the reference current Iref. In the sense period, this current difference is sense-amplified by the sense amplifier circuit (87 in FIG. 10), and the data latch circuit (88 in FIG. 10). ) Holds data 1. During this time, the potentials of GCS and LCS are held at VSS, and the potentials of GBL and LBL0 are held at approximately Vread.
  • the RWC in which the writing has been performed is executed when the precharge command Pre is executed. It is selected as the RWC on which MAT writing is performed (details of the RWC selection will be described later).
  • a MAT write period starts corresponding to the precharge command Pre, and when the GBL and LBL0 are driven to the potential VSS and the GCS and LCS are driven to the potential VDD corresponding to the writing of the data 0, the data 0 becomes the resistance change type in the MAT. It is written in a memory cell (67e in FIG. 8). Thereafter, the operation from the selection cancellation period to the precharge period is the same as that in the left half (A) of FIG.
  • the read data held in the data latch circuit (88 in FIG. 10) is read to the outside by the read command Rd, the read data is processed by a processing circuit (not shown), and then the write command Wt is used. It is assumed that the processed read data is written to the data latch circuit (88 in FIG. 10).
  • processing contents by the processing circuit for example, error correction processing may be performed on a plurality of read data.
  • the present invention is not limited to this, and any processing can be applied.
  • the processing circuit corresponds to 510 in FIG. 2 referred to in the outline description of the embodiment.
  • FIG. 11 shows operation waveforms when writing (overwriting) occurs in the data latch circuit (88 in FIG. 10) by the write command Wt during the page access period.
  • a bank active command Act and a row address XA are input (timing t0 in FIG. 11).
  • the precharge signal / PC is set to the high level, and the sub word line SWL (for example, SWL0 is selected) is set to the high level (potential VPP). ) Is controlled.
  • RP is controlled to High level for a certain period (period T1 in FIG.
  • the read current Iread flows through the resistance change type memory cell (67e in FIG. 8) selected via GBL_i and LBL0. This is sense-amplified by the sense amplifier circuit (87 in FIG. 10) and latched by the data latch circuit (88 in FIG. 10), so that the Q and / Q data are updated corresponding to the read data.
  • the read data read out of the RWC by the read command Rd is processed by the external processing circuit described above.
  • the read data read is inverted by the processing circuit.
  • the MAT write operation is started.
  • the write pulse signal / WP is controlled to Low level for a certain period (period T4 in FIG. 11)
  • GBL_i is set to Low level
  • GCS_i is set to High level according to the Q Low level (data 0) of the data latch circuit 88.
  • inverted data 0 is written into a resistance change memory cell (67e in FIG. 8) in the MAT.
  • SWL is controlled to the Low level, and then / PC is controlled to the Low level, the node N0 is precharged to the High level (potential VDD), and a series of page access operations is completed.
  • FIG. 11 shows the case where the precharge command Pre is applied from the outside.
  • the precharge command Pre may be automatically issued in the semiconductor device 1 after the end of the read or write operation, and in this case, the same operation as in FIG. 11 is performed.
  • FIG. 12 shows an operation waveform when writing (overwriting) does not occur in the RWC data latch circuit (88 in FIG. 10) in the page access period.
  • FIG. 12 differs from FIG. 11 in that the second page access is also performed by the read command Rd. Therefore, since the write enable signal WE is not activated and maintains the Low level, the node N0 maintains the High level. Therefore, even when the MAT write operation corresponding to the precharge command Pre is started, both GBL_i and GCS_i maintain the potential VSS. As a result, writing to the resistance change type memory cell in the MAT is not performed.
  • the resistance change corresponding to the RWC is executed when the precharge command Pre is executed, as in FIG. Writing to the type memory cell is not performed.
  • the write operation is not performed on all the resistance change type memory cells for one page, but the RWC data latch circuit (88 in FIG. 10) is performed by the write command Wt.
  • MAT writing to the corresponding resistance change type memory cell is performed only for the RWC for which writing has been performed. Therefore, the number of resistance change type memory cells that perform MAT writing can be greatly reduced, and the current consumption of the semiconductor device can be reduced.
  • the arrangement pitch of the RWC is relaxed. Therefore, the RWC can be laid out without difficulty, and the number thereof can be reduced, so that an increase in the chip area of the semiconductor device can be suppressed.
  • FIG. 13 is a circuit diagram of one sub mat (sub-MAT) 163 of the semiconductor device according to the second embodiment.
  • the local common source line LCS and the global common source line GCS are eliminated, and the first terminal of the resistance-change memory cell (first A fixed potential VCS is supplied to the terminal to which the LCS is connected in the embodiment.
  • the fixed potential VCS is set to an intermediate potential between VDD and VSS, for example.
  • the GBL precharge voltage is set to VCS.
  • FIG. 15 shows one (144b) of a plurality of RWCs in the second embodiment (the configuration of each RWC is the same).
  • the write control circuit 192 of FIG. 10 is replaced with the write control circuit 292 in FIG.
  • the GBL_GCS driver 82 in FIG. 10 is replaced with a GBL driver 282 in FIG.
  • Other parts in FIG. 15 are the same as those in FIG. 10, and therefore, the same reference numerals are given and redundant descriptions are omitted.
  • the write control circuit 292 since the write control circuit 292 does not need to control GCS_i, it is configured only by the NOR logic circuit 175, and is a smaller circuit than the write control circuit 192 (first embodiment). .
  • a control signal C 3 that is an output of the NOR logic circuit 175 is supplied to the GBL driver 282.
  • the configuration of the part of the output circuit composed of the PMOS transistors (102, 103) and the NMOS transistors (104, 105) is the same as that of the GBL_GCS driver 82 (first embodiment).
  • the gate of the NMOS transistor 104 is connected to the node Nin2
  • the gate of the PMOS transistor 103 is connected to the node Nin2 via the inverter circuit 298.
  • the GBL driver 282 a circuit in which two PMOS transistors 212 and 213 are connected in series is added between the power supply VCS and the node Nin4 (GBL_i).
  • the read pulse signal RP is supplied to the gate of the PMOS transistor 212, and the gate of the PMOS transistor 213 is connected to the node Nin2.
  • the node Nin2 is connected to the output terminal of the NOR logic circuit 175 of the write control circuit 292 and supplied with the control signal C3.
  • the GBL_i when the RP is at the high level, the GBL_i is cut off from the power supply VCS.
  • the control signal C3 When RP is at the low level and the control signal C3 is at the low level, GBL_i is set to the potential VCS.
  • GBL_i is driven by a signal obtained by inverting / Q of the data latch circuit 88. Accordingly, when / Q is at a high level (data 0), GBL_i is driven to a low level (VSS), and when / Q is at a low level (data 1), GBL_i is driven to a high level (VDD).
  • FIG. 14 shows an operation waveform of each signal when SWL0 and LBL0 are selected in one selected sub-MAT (163 in FIG. 13). 14 differs from FIG. 9 (first embodiment) in that / SEL, SEL, GCS, and LCS do not exist, the precharge potential of GBL and LBL becomes VCS, and reading of GBL and LBL. The potential at the time of writing is different from that at the time of writing.
  • the other operations are the same as those in FIG.
  • the left half (A) of FIG. 14 shows an operation when data 0 reading (read data is 0) ⁇ page access period ⁇ data 1 MAT writing is sequentially performed.
  • LBL is precharged to VCS and GBL is precharged to VCS by RWC.
  • LBL0 is connected to GBL.
  • the potentials of GBL and LBL0 are set to the read potential Vread, and the read current Iread0 flows through the resistance change type memory cell (67e in FIG. 13).
  • GBL and LBL0 return to the potential VCS, and then the page access period is reached.
  • the RWC in which the write has been performed performs the MAT write when the precharge command Pre is executed. Selected as.
  • the MAT writing period corresponding to the precharge command Pre when the GBL and LBL0 are driven to the potential VDD corresponding to the writing of the data 1 in the selected RWC, the data 1 is a resistance change type memory cell (in the MAT). 13e, etc. in FIG. 13).
  • LBL0 is precharged to the potential VCS
  • GBL is also precharged to the potential VCS by RWC.
  • the right half (B) of FIG. 14 shows an operation in the case of sequentially performing data 1 reading ⁇ page access period ⁇ data 0 MAT writing. Since the operation from the precharge period to the cell selection period is the same as that in the left half (A) of FIG.
  • the potentials of GBL and LBL0 Prior to the start of the sense latch period, the potentials of GBL and LBL0 are set to the read potential Vread, and the read current Iread1 flows through the resistance change type memory cell (eg, 67e in FIG. 13).
  • the sense latch period ends, GBL and LBL0 return to the potential VCS, and a page access period starts.
  • the RWC that has been written performs MAT writing when the precharge command Pre is executed. Selected as RWC.
  • the MAT writing period corresponding to the precharge command Pre when the GBL and LBL0 are driven to the potential VSS corresponding to the writing of data 0 in the selected RWC, the data 0 is a resistance change type memory cell in the MAT. (67e in FIG. 13) is written.
  • the subsequent operations from the selection cancellation period to the precharge period are the same as those in the left half (A) of FIG.
  • FIG. 16 shows operation waveforms when writing (overwriting) occurs in the data latch circuit of RWC (88 in FIG. 15) by the write command Wt in the page access period.
  • 16 differs from FIG. 11 (first embodiment) only in that there is no GCS_i, and that the precharge level of GBL_i and the level at the time of MAT writing are different. Since the other points of FIG. 16 are the same as those of FIG. 11, the description will be made only on the different points.
  • GBL_i is driven to Vread during a period in which RP is controlled to a high level corresponding to the active command Act.
  • GBL_i is driven to VDD or VSS corresponding to the write data (in the case of writing data 0, GBL_i is set to VSS). In the case of writing data 1, GBL_i is driven to VDD).
  • FIG. 17 shows an operation waveform when writing (overwriting) does not occur in the RWC data latch circuit (88 in FIG. 15) in the page access period.
  • FIG. 17 differs from FIG. 16 in that the second page access is also a read operation. Therefore, the write enable signal WE remains at the low level, and the node N0 maintains the high level. Therefore, GBL_i maintains the potential VCS even when the MAT write operation corresponding to the precharge command Pre is started. As a result, writing to the resistance change type memory cell in the MAT is not performed.
  • the resistance change corresponding to the RWC is executed when the precharge command Pre is executed, as in FIG. Writing to the type memory cell is not performed.
  • the current consumption of the semiconductor device can be further reduced as compared with the first embodiment.
  • the number of wirings can be greatly reduced by eliminating GCS and LCS.
  • the LCS control circuit 71 can be eliminated in each sub-MAT (eg, 163 in FIG. 13), the sub-MAT circuit can be reduced in scale.
  • a circuit for controlling GCS_i in RWC becomes unnecessary, and the write control circuit 292 of the MAT write control circuit 285 can be reduced in scale. As described above, the effect that the chip area of the semiconductor device can be reduced as a whole is obtained.
  • FIG. 18 is a block diagram illustrating an RWC (read / write control circuit) 244b according to the third embodiment.
  • RWC read / write control circuit
  • FIG. 18 the column selection signal detection circuit 191 in FIG. 15 is replaced with a data change detection circuit 391 in FIG.
  • the other parts in FIG. 18 are the same as those in FIG. 15 (second embodiment), and thus the same reference numerals are assigned and redundant description is omitted.
  • the data change detection circuit 391 in FIG. 18 is a data latch based on the read data / Q held in the data latch circuit 88 by the active command Act (first command) and the subsequent operation (for example, the operation in the page access period). This is a circuit for detecting a change in data / Q of the circuit 88. Therefore, the data change detection circuit 391 does not use the write enable signal WE used in the column selection signal detection circuit 191 (FIGS. 10 and 15) of the first and second embodiments.
  • the data change detection circuit 391 in FIG. 18 includes two NMOS transistors (163, 164) in the column selection signal detection circuit 191 (FIG. 15).
  • the circuit 302 is replaced with a part constituted by the NMOS transistor 163.
  • / Q of the data latch circuit 88 is connected to the input terminal D of the latch element 301 via the NMOS transistor 303.
  • a read pulse signal RP is input to the gate of the NMOS transistor 303.
  • the latch element 301 latches / Q of the data latch circuit 88 when the read pulse signal RP is at the high level (that is, read data / Q held in the data latch circuit 88 by the active command Act).
  • One input terminal of the EX-OR logic circuit 302 is connected to the output terminal Q of the latch element 301, and the other input terminal of the EX-OR logic circuit 302 is connected to the output terminal / Q of the data latch circuit 88. .
  • the output terminal of the EX-OR logic circuit 302 is connected to the gate of the NMOS transistor 163.
  • the potential of the node N0 is precharged to the potential VDD in advance during the precharge period (/ PC is at the low level).
  • the control circuit (not shown) makes the data Q of the latch element 301 the same as the data of / Q of the data latch circuit 88 before / PC is controlled to the Low level by the precharge command Pre.
  • the output terminal of the -OR logic circuit 302 is controlled to the Low level.
  • the write control circuit 392 activates the control signal C4 to the high level when / WP is in the activated state (low level) when the output of the data change detection circuit 391 has transitioned to the low level. To do.
  • the GBL driver 282 when the control signal C4 (control signal C3 in the second embodiment) is activated, the GBL driver 282 is based on the data / Q held in the data latch circuit 88. Thus, GBL_i is driven to the potential VDD or VSS, and MAT writing is performed.
  • GBL_i becomes the potential VCS and MAT writing is not performed.
  • FIG. 19 corresponds to FIG. 16 (second embodiment) and shows an operation waveform when data obtained by inverting read data is written in the RWC selected by the write command Wt.
  • the signal WE is not displayed in FIG.
  • the other operation waveforms are the same as those in FIG.
  • FIG. 20 is an operation waveform when the above-described inversion writing does not occur in the selected RWC (that is, when the read data is not changed by the external processing circuit).
  • the data in the data latch circuit 88 does not change from the read data by the active command Act even when the write command Wt is written in the page access period.
  • the data change detection circuit 391 does not detect a data change, GBL_i corresponding to the precharge command Pre remains at the potential VCS, and writing to the resistance change type memory cell in the MAT is not performed.
  • the read among the RWCs written to the data latch circuit (88 in FIG. 10) by the write command Wt Only the RWC in which data different from the data is written is selected, and MAT writing is performed to the corresponding resistance change type memory cell. Therefore, since the number of resistance change type memory cells for performing MAT writing can be further reduced as compared with the first and second embodiments, the current consumption of the semiconductor device can be further reduced. Is obtained.
  • the source lines are configured with a hierarchical structure of global common source lines GCS and local common source lines LCS, and each RWC has global bit lines GBL_i and global common source lines GCS_i. May be configured to be driven.
  • FIG. 21 is a block diagram showing a configuration of an information processing system according to the fourth embodiment.
  • the fourth embodiment constitutes an information processing system including the semiconductor device 1 according to each embodiment and a multi-core processor 230.
  • the multi-core processor 230 includes core_1 to core_4 (231a to d), an I / O 232, an external storage device control block 233, and an on-chip memory 234.
  • the external storage device control block 233 controls the semiconductor device 1 by exchanging command signals, address signals, and data signals with the semiconductor device 1.
  • the multi-core processor 230 it is possible to provide the multi-core processor 230 with a large-capacity, high-reliability main memory with low current consumption using resistance change type memory cells.
  • the semiconductor device disclosed in each embodiment can realize an efficient page mode even when a resistance change type memory cell having a relatively long write time is used. Therefore, the data bandwidth of the main memory bus that can maintain the performance of the multi-core processor can be secured.
  • each embodiment the case where the STT-RAM that performs spin-injection magnetization reversal writing is used as the variable resistance element has been described.
  • the present invention is not limited thereto, and for example, Re using metal oxide or the like.
  • the disclosed contents of each embodiment can be applied to a semiconductor device using a RAM (Resistive Random Access Memory) or a phase change memory (PCM).
  • RAM Resistive Random Access Memory
  • PCM phase change memory
  • the bipolar resistance change memory cell has been described.
  • the unipolar resistance change memory cell can be changed.
  • the present invention can be applied.
  • the present invention can be applied to a semiconductor memory device using resistance change type memory cells.

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JP2010244607A (ja) * 2009-04-03 2010-10-28 Elpida Memory Inc 半導体記憶装置
JP2012123875A (ja) * 2010-12-09 2012-06-28 Hitachi Ltd 半導体記憶装置

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