WO2014173078A1 - 薄膜晶体管、其制作方法和阵列基板 - Google Patents

薄膜晶体管、其制作方法和阵列基板 Download PDF

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WO2014173078A1
WO2014173078A1 PCT/CN2013/084433 CN2013084433W WO2014173078A1 WO 2014173078 A1 WO2014173078 A1 WO 2014173078A1 CN 2013084433 W CN2013084433 W CN 2013084433W WO 2014173078 A1 WO2014173078 A1 WO 2014173078A1
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Prior art keywords
layer
thin film
electrode
film transistor
drain
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PCT/CN2013/084433
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English (en)
French (fr)
Inventor
阎长江
龙君
朱孝会
谢振宇
陈旭
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北京京东方光电科技有限公司
京东方科技集团股份有限公司
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Priority to US14/348,802 priority Critical patent/US9437742B2/en
Publication of WO2014173078A1 publication Critical patent/WO2014173078A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, and an array substrate. Background technique
  • an oxide thin film transistor is mainly a oxidized thin film field effect transistor of a polycrystalline oxide semiconductor material, and an amorphous oxide semiconductor such as an indium gallium oxide (IGZO) semiconductor is used as a semiconductor layer of an oxide thin film transistor.
  • IGZO indium gallium oxide
  • Its high mobility, low sub-threshold, low current and low temperature production are of great concern to the LCD industry.
  • existing amorphous oxide semiconductor thin film transistors still have some problems to be solved, for example, it is difficult to form good electrical contact between the source and drain of the metal material and the amorphous oxide semiconductor layer.
  • the oxide thin film transistor can be applied to an X-ray flat panel detecting device.
  • the cross-sectional structure of the existing oxide thin film transistor is as shown in FIG. 1, and includes:
  • a gate insulating layer 903 formed on the gate 902 covering the entire substrate 901;
  • a signal terminal formed of a P-type layer 908, an I-type layer 909, and an N-type layer 910 formed on the drain 907;
  • first passivation layer 912 over the source drain 907, the semiconductor layer 905 and the conductive layer 911; a first electrode 913 disposed on the first passivation layer 912 and connected to the conductive layer 911;
  • a second electrode 915 is disposed on the second passivation layer 914 and the first passivation layer 912 and connected to the source.
  • the signal terminal is a photodiode having a PIN structure.
  • the first electrode 913 connected to the conductive layer 911 also has a voltage, and the liquid crystal molecules above the oxide thin film transistor are in an electric field. Controlled to flip, the PIN is correspondingly provided with a photosensitive layer (not shown in FIG.
  • a voltage is applied to the gate 902, so that an electrical signal is transmitted from the drain 907b through the ohmic contact layer 906 and the semiconductor layer 905 to the source 907a, and the second electrode 915 connected to the source 907a receives the signal, and the second electrode 915 It is connected to the detection circuit of the flat panel detecting device, so that, for example, the light intensity information of the X-rays can be detected.
  • the source and drain electrodes 907 are generally prepared from metals such as aluminum, molybdenum, titanium and indium oxide.
  • the electrical characteristics of such an oxide thin film transistor are often affected by carriers in the semiconductor layer 905, and the interface contact resistance between the source and drain electrodes 907 and the semiconductor layer 905 forms a heterojunction or a homojunction, which also greatly affects the driving current.
  • the oxide thin film transistor of the prior art is disposed between the source drain 907 and the semiconductor layer 905 by using the ohmic contact layer 906 to reduce the contact resistance, there is still a certain difference due to the valence band of the metal and the valence band of the semiconductor. resistance. Summary of the invention
  • Embodiments of the present invention provide a thin film transistor including: a gate formed on a substrate, a gate insulating layer formed on the gate and covering at least a portion of the substrate, and a semiconductor layer, a source formed on the gate insulating layer a drain and a drain, wherein a material of the semiconductor layer is an oxide semiconductor, a material of the source and the drain is doped oxide semiconductor, and the source, the drain and the semiconductor layer Same layer setting.
  • the semiconductor layer is an amorphous oxide semiconductor layer.
  • the source, the drain, and the peninsula body layer are formed from the same material layer.
  • the thin film transistor further includes a barrier layer formed on the semiconductor layer, wherein the source and drain are respectively located on both sides of the barrier layer.
  • the thin film transistor further includes a signal terminal formed on the drain, and the signal terminal is a PIN-structured photodiode, comprising: a highly doped hydrogenated amorphous silicon formed on the drain A P-type layer formed, an I-type layer formed on the P-type layer, and an N-type layer formed on the I-type layer.
  • the thin film transistor further includes: a conductive layer formed on the N-type layer of the signal terminal. In one example, the thin film transistor further includes: a first passivation layer formed on the conductive layer, wherein a first via hole corresponding to a region where the drain is located is formed in the first passivation layer Corresponding to a second via of the region where the source is located.
  • the thin film transistor further includes: a first electrode and a second electrode formed on the first passivation layer, and a second passivation layer formed on the first electrode and the second electrode, wherein The first electrode is electrically connected to the conductive layer through the first via, and the second electrode is electrically connected to the source through the second via.
  • the first passivation layer and/or the second passivation layer are comprised of a highly doped silicon nitride material.
  • Another embodiment of the present invention provides an array substrate comprising the thin film transistor of the above claims.
  • a further embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming a gate on a substrate; forming a gate insulating layer on the gate and at least a portion of the substrate; forming on the substrate on which the gate insulating layer is formed An oxide semiconductor thin film layer; and doping the oxide semiconductor thin film layer to form a source, a drain, and a semiconductor layer interposed between the source and the drain.
  • the step of doping the oxide semiconductor thin film layer to form a source, a drain, and a semiconductor layer interposed between the source and the drain therein includes: A barrier layer is formed on the oxide semiconductor thin film layer; an oxide semiconductor thin film layer on both sides of the barrier layer is doped to form a source and a drain.
  • the method of fabricating the thin film transistor further includes forming a signal terminal on the drain, and the step of doping the oxide semiconductor thin film layer on both sides of the barrier layer to form a source and a drain includes : forming a highly doped hydrogenated amorphous silicon layer on the oxide semiconductor thin film layer and the barrier layer; and patterning the highly doped hydrogenated amorphous silicon layer to form a P-type layer in the signal terminal.
  • the step of forming a signal terminal on the source includes: sequentially forming an I-type layer and an N-type layer on the P-type layer composed of highly doped hydrogenated amorphous silicon, wherein the type I The layer consists of intrinsic silicon and the N-type layer consists of N-doped silicon.
  • the fabricating method further includes: forming a conductive layer on the signal terminal. In one example, the fabricating method further includes: forming a first passivation layer on the conductive layer; A first via corresponding to a region where the drain is located and a second via corresponding to a region where the source is located are formed in the first passivation layer.
  • the fabricating method further includes: forming a first electrode and a second electrode on the first passivation layer, and forming a second passivation layer on the first electrode and the second electrode, wherein The first electrode is electrically connected to the conductive layer through the first via, and the second electrode is electrically connected to the drain through the second via.
  • FIG. 1 is a partial cross-sectional structural view of an array substrate in a conventional X-ray detecting apparatus
  • FIG. 2 is a flow chart showing a method of fabricating a thin film transistor according to an embodiment of the present invention
  • FIG. 3 is a schematic structural view of a thin film transistor after forming a gate according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of a thin film transistor after forming a semiconductor layer according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of forming a barrier layer in an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a thin film transistor after forming a source and a drain according to an embodiment of the present invention
  • FIG. 7 is a schematic structural view of a thin film transistor after forming a signal terminal according to an embodiment of the present invention
  • FIG. 9 is a schematic structural diagram of a thin film transistor after forming a second pixel electrode according to an embodiment of the present invention
  • FIG. 10 is a schematic structural view of a thin film transistor after forming a second passivation layer in an embodiment of the present invention. detailed description
  • an amorphous oxide thin film transistor is provided in the embodiment of the present invention.
  • the array substrate provided by the embodiment of the invention is an array substrate of an amorphous silicon detector.
  • the embodiments of the present invention mainly provide a thin film transistor, a manufacturing method thereof and an array substrate, which can effectively solve the problem of poor electrical contact between the source and the drain and the amorphous oxide semiconductor layer.
  • the basic idea of the embodiment of the present invention is: directly depositing a highly doped amorphous silicon film on the oxide semiconductor thin film layer on both sides of the barrier layer when forming the source and drain, increasing the current carrying at the interface of the oxide semiconductor The concentration of the sub-such that the oxide semiconductor can exhibit the electrical properties of the conductor, thereby forming a source drain.
  • FIG. 2 is a schematic flow chart of a method for fabricating a thin film transistor according to an embodiment of the present invention. As shown in FIG. 2, the manufacturing method is as follows:
  • Step 201 forming a gate on the substrate
  • a gate layer film is formed on the substrate 101 and patterned to form a gate electrode 102.
  • the gate 102 may be made of a metal material such as aluminum, copper or molybdenum.
  • the gate 102 may be formed by a wet etching process. This step may be performed by a conventional patterning process, which will not be described in detail herein.
  • Figure 3 shows.
  • Step 202 forming a gate insulating layer covering the gate electrode and at least a portion of the substrate and an oxide semiconductor thin film layer on the substrate on which the gate electrode is formed;
  • a gate insulating material such as silicon oxide may be coated on the substrate 101 on which the gate electrode 102 is formed, which may be formed by a physical sputtering sputtering deposition method, and then the gate insulating layer 103 may be formed using a conventional patterning process.
  • the amorphous oxide semiconductor material may also be selected from other materials such as bismuth indium oxide (HflnZnO) or indium gallium tin oxide (InGaSnO), which are not described here.
  • Step 203 forming a barrier layer on the substrate on which the oxide semiconductor thin film layer is formed; for example, depositing a silicon oxide film on the substrate on which the amorphous oxide semiconductor thin film layer 105 is formed, and forming by a dry etching process
  • the barrier layer 104, the barrier layer 104 can be implemented by an existing process and will not be described in detail.
  • the structure formed after this step is as shown in FIG.
  • Step 204 depositing a highly doped amorphous silicon film on the oxide semiconductor thin film layer on both sides of the barrier layer to form a source and a drain;
  • a-Si:H is deposited on the amorphous oxide semiconductor thin film layer 105 on both sides of the barrier layer 104, and thus, carriers at the interface between the amorphous oxide semiconductor thin film layer 105 and the amorphous silicon thin film As the concentration increases, the amorphous oxide semiconductor thin film layer at the interface exhibits the electrical characteristics of the conductor, thereby forming the source and drain electrodes 107, the undoped amorphous oxide semiconductor thin film layer, that is, the non-covered layer 4
  • the crystalline oxide semiconductor thin film layer is formed as the semiconductor layer 105 as shown in FIG.
  • the resistance characteristics at the interface between the semiconductor layer 105 composed of the amorphous oxide semiconductor and the source and drain electrodes 107 can be improved, and the driving current can be improved, thereby effectively solving the source and drain electrodes 107 and the amorphous oxide semiconductor layer 105.
  • the problem of poor electrical contact between them is conducive to improving the display quality of the device.
  • Step 205 forming a signal terminal (PIN) and a conductive layer on the substrate on which the active drain is formed; for example, sequentially depositing an intrinsic silicon film on the substrate on which the highly doped amorphous silicon film is deposited, N-type doping a hetero-silicon (n + Si) film and an ITO film, wet etching the ITO film, followed by dry etching of the n + Si film, the intrinsic silicon film, and the highly doped amorphous silicon (a a film of -Si:H), thereby forming a p-type layer 108, an I-type layer 109 over the p-type layer 108, and an N-type layer 110 formed over the I-type layer 109, and on the N-type layer 110 Conductive layer 111, as shown in FIG.
  • the P-type layer 108 is made of a highly doped hydrogenated amorphous silicon
  • the I-type layer 109 is made of a material of intrinsic silicon
  • the N-type layer 110 is made of an N-type doped silicon ( n + Si ).
  • Step 206 forming a first passivation layer and first and second via holes on the substrate on which the signal terminal PIN is formed;
  • a highly doped silicon nitride film is deposited on the substrate on which the PIN is formed, for example, on the conductive layer 111 on the PIN, and the first passivation layer 112 is formed by dry etching, wherein the formation Corresponding to the first via HI of the drain region and the second via H2 corresponding to the source region, the structure shown in FIG. 8 is obtained.
  • the formation of the first passivation layer 112 by using a highly doped silicon nitride film instead of the silicon oxide film used in the prior art can further improve the electrical properties of the source and drain 107 formed by the amorphous oxide semiconductor.
  • Step 207 sequentially forming a first electrode and a second electrode and a second passivation layer on the first passivation layer;
  • an ITO film is deposited on the first passivation layer 112 and wet etched to form a first An electrode 113 and a second electrode 115, the first electrode 113 is electrically connected to the conductive layer 111 through the first via HI, and the second electrode 115 passes through the second via H2 and the source Electrically connected, the structure shown in Fig. 9 is obtained.
  • the thin film transistor provided by the embodiment of the present invention includes: a gate electrode 102 formed on the substrate 101, a gate insulating layer 103 formed on the gate electrode 102 and covering the entire substrate 101, and formed on the gate insulating layer. a semiconductor layer 105 on the 103, and source and drain electrodes 107 on both sides of the semiconductor layer 105, wherein the source and drain electrodes 107 include a source 107a and a drain 107b respectively located on the two sides of the semiconductor layer 105, A barrier layer 104 formed on the semiconductor layer 105, and a signal terminal (PIN) formed on the drain 107b.
  • PIN signal terminal
  • the PIN includes: a P-type layer 108 formed of highly doped hydrogenated amorphous silicon formed on the drain electrode 107b, an I-type layer 109 formed on the P-type layer 108, and formed on the I-type layer 109.
  • the thin film transistor further includes: a conductive layer 111 formed on the N-type layer 110.
  • the source drain 107 and the semiconductor layer 105 are located in the same oxide semiconductor thin film layer and have the same thickness. That is, both the source 107a and the drain 107b are fused to the same semiconductor layer as the semiconductor layer 105, and are each formed of an oxide semiconductor material.
  • the thin film transistor further includes: a first passivation layer 112 formed on the conductive layer 111, a first via hole located in the first passivation layer 112 and corresponding to a region of the drain 107b And a second via located in the first passivation layer 112 and corresponding to the source 107a region.
  • the thin film transistor further includes: a first electrode 113 and a second electrode 115 formed on the first passivation layer 112, and a second passivation layer formed on the first electrode 113 and the second electrode 115 114, wherein the first electrode 113 is electrically connected to the conductive layer 111 through the first via hole, and the second electrode 115 is electrically connected to the source electrode 107a through the second via hole.
  • the first passivation layer 112 and the second passivation layer 114 are made of a highly doped silicon nitride material.
  • the preparation process of the thin film transistor provided by the embodiment of the present invention omits the patterning process for preparing the source and the drain compared with the prior art, thereby saving the cost of the mask and saving the process.
  • an electrical signal is transmitted from the drain 107b through the semiconductor layer 105 to the source 107a, and the second electrode 115 connected to the source 107a receives a signal, and the second electrode 115 is It is connected to the detection circuit of the flat panel detecting device, so that the light intensity information of the X-rays and the like can be detected.
  • embodiments of the present invention also provide an array substrate in which the thin film transistor is a thin film transistor as described above.
  • the highly doped amorphous silicon film is directly deposited on the oxide semiconductor thin film layer on both sides of the barrier layer.
  • the high-doped amorphous silicon contains a large amount of unsaturated hydrogen bonds, thereby causing hydrogen ions to diffuse into the amorphous metal oxide semiconductor layer, making the amorphous
  • the highly doped region of the metal oxide adjacent to the surface of the highly doped amorphous silicon film forming H ions further exhibits a conductor characteristic.
  • the amorphous oxide semiconductor film at the interface between the highly doped amorphous silicon film and the amorphous oxide semiconductor film exhibits electrical characteristics of the conductor, thereby A source and a drain are formed.
  • the valence band energy difference between the source and drain electrodes formed by the same material is less than 4 ,, and the lattice matching property is good, so the driving current signal is The influence of the method is small, and the obstacle of electron flow is reduced, thereby effectively solving the problem of poor electrical contact between the source drain and the amorphous oxide semiconductor layer, improving the electrical characteristics of the thin film transistor, and improving the display quality of the device.
  • a metal material is not additionally deposited for forming the source and drain electrodes, that is, the mask forming process of the source and drain electrodes is omitted, thereby reducing the production cost.

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Abstract

提供一种薄膜晶体管、其制作方法以及阵列基板。薄膜晶体管包括：形成于基板（101）上的栅极（102），形成于栅极（102）上并覆盖至少部分基板（101）的栅绝缘层（103），以及形成于栅绝缘层（103）上的半导体层（105'）、源极（107a）和漏极（107b）。半导体层（105'）的材料为氧化物半导体，源极（107a）、漏极（107b）的材料为掺杂的氧化物半导体。源极（107a）、漏极（107b）与半导体层（105'）同层设置。

Description

薄膜晶体管、 其制作方法和阵列基板 技术领域
本发明的实施例涉及薄膜晶体管、 其制作方法和阵列基板。 背景技术
目前， 氧化物薄膜晶体管主要为多晶氧化物半导体材料的氧化辞基薄膜 场效应晶体管， 而非晶氧化物半导体， 例如： 铟镓辞氧化物（IGZO )半导体 作为氧化物薄膜晶体管的半导体层， 其高迁移率、 低亚阀值、 低电流以及可 低温制作等优良性能备受液晶行业的关注。 但是， 现有非晶氧化物半导体薄 膜晶体管还存在一些问题有待解决， 例如： 金属材料的源漏极与非晶氧化物 半导体层之间难以形成良好的电学接触。
氧化物薄膜晶体管可应用于 X射线平板检测装置中，现有的氧化物薄膜 晶体管的剖面结构如图 1所示， 包括：
形成于基板 901上的栅极 902;
形成于栅极 902上覆盖整个基板 901的栅绝缘层 903;
形成于栅绝缘层 903上的半导体层 905;
形成于半导体层 905上的欧姆接触层 906;
形成于欧姆接触层 906上的源漏极 907;
形成于漏极 907上的由 P型层 908、 I型层 909、 N型层 910组成的信号 端子（PIN ) ；
形成于 N型层 910上的导电层 911;
覆盖于源漏极 907、 半导体层 905和导电层 911上的第一钝化层 912; 设置于第一钝化层 912上与导电层 911相连的第一电极 913;
设置于第二钝化层 914和第一钝化层 912上与源极相连的第二电极 915。 其中， 所述信号端子即为具有 PIN结构的光电二极管， 向导电层 911施 加电压后， 和导电层 911相连接的第一电极 913也因此有电压， 氧化物薄膜 晶体管上方的液晶分子在电场的控制下翻转， 在所述 PIN上还对应设置有感 光层（图 1中未示出） ， 入射光通过液晶分子层照射到感光层上， 这时， 由 于 PIN上方的导电层 911和下方的漏极 907b之间存在电压差， PIN则进入反 向导通状态， 将光信号转换成电信号， 传输到漏极 907b。
同时， 向栅极 902施加电压， 因此电信号从漏极 907b经过欧姆接触层 906和半导体层 905传输到源极 907a, 和源极 907a相连接的第二电极 915 得到信号， 并且第二电极 915和平板检测装置的检测电路相连接， 因此例如 可以检测到 X射线的光强信息。
上述源漏极 907—般采用铝， 钼， 钛及氧化铟等金属制备。 这类氧化物 薄膜晶体管的电学特性往往受半导体层 905中载流子的影响， 使源漏极 907 与半导体层 905的界面接触电阻形成异质结或同质结， 这也大大影响了驱动 电流。 虽然现有技术中的氧化物薄膜晶体管采用欧姆接触层 906设置于源漏 极 907和半导体层 905之间以减小接触电阻， 但由于金属的价带和半导体的 价带不同， 仍然存在一定的电阻。 发明内容
本发明的实施例提供一种薄膜晶体管， 包括： 形成于基板上的栅极， 形 成于栅极上并覆盖至少部分所述基板的栅绝缘层， 以及形成于栅绝缘层上的 半导体层、 源极和漏极， 其中， 所述半导体层的材料为氧化物半导体， 所述 源极、 漏极的材料为掺杂的所述氧化物半导体， 且所述源极、 漏极与所述半 导体层同层设置。
在一个示例中， 所述半导体层为非晶氧化物半导体层。
在一个示例中， 所述源极、 所述漏极以及所述半岛体层由同一材料层形 成。
在一个示例中， 所述的薄膜晶体管还包括形成在所述半导体层上的阻挡 层， 其中所述源极和漏极分别位于所述阻挡层的两侧。
在一个示例中， 所述的薄膜晶体管还包括形成于漏极上的信号端子， 所 述信号端子为 PIN结构的光电二极管， 包括： 形成于所述漏极上由高掺杂的 氢化非晶硅构成的 P型层、 形成于所述 P型层上的 I型层、 形成于 I型层上 的 N型层。
在一个示例中， 所述薄膜晶体管还包括： 形成于所述信号端子的 N型层 上的导电层。 在一个示例中，所述薄膜晶体管还包括：形成于导电层上的第一钝化层， 其中， 所述第一钝化层中形成有对应于所述漏极所在区域的第一过孔和对应 于所述源极所在区域的第二过孔。
在一个示例中， 所述薄膜晶体管还包括： 形成于第一钝化层上的第一电 极和第二电极， 以及形成于第一电极和第二电极上的第二钝化层， 其中， 所 述第一电极通过所述第一过孔和所述导电层电性连接、 所述第二电极通过第 二过孔和所述源极电性连接。
在一个示例中，所述第一钝化层和 /或所述第二钝化层由高掺杂的氮化硅 材料构成。
本发明的另一实施例提供一种阵列基板， 包括权利要求以上所述的薄膜 晶体管。
本发明的又一实施例提供一种薄膜晶体管的制作方法， 包括： 在基板上 形成栅极； 在栅极和至少部分基板上形成栅绝缘层； 在所述形成有栅绝缘层 的基板上形成氧化物半导体薄膜层； 以及对所述氧化物半导体薄膜层进行掺 杂处理以在其中形成源极、 漏极以及夹设在所述源极和所述漏极之间的半导 体层。
在一个示例中， 对所述氧化物半导体薄膜层进行掺杂处理以在其中形成 源极、 漏极以及夹设在所述源极和所述漏极之间的半导体层的步骤包括： 在 所述氧化物半导体薄膜层上形成阻挡层； 对所述阻挡层两侧的氧化物半导体 薄膜层进行掺杂处理以形成源极和漏极。
在一个示例中， 所述薄膜晶体管的制作方法还包括在所述漏极上形成信 号端子， 所述对阻挡层两侧的氧化物半导体薄膜层掺杂处理以形成源极和漏 极的步骤包括： 在氧化物半导体薄膜层和阻挡层上形成高掺杂的氢化非晶硅 层； 以及对高掺杂的氢化非晶硅层进行构图工艺， 形成所述信号端子中的 P 型层。
在一个示例中， 所述在源极上形成信号端子的步骤包括： 在所述由高掺 杂的氢化非晶硅构成的 P型层上依次形成 I型层和 N型层， 其中， I型层由 本征硅构成， N型层由 N型掺杂的硅构成。
在一个示例中， 所述制作方法还包括： 在所述信号端子上形成导电层。 在一个示例中，所述制作方法还包括：在所述导电层上形成第一钝化层； 在第一钝化层中形成对应于漏极所在区域的第一过孔和对应于源极所在 区域的第二过孔。
在一个示例中， 所述制作方法还包括： 在所述第一钝化层上形成第一电 极和第二电极， 在第一电极和第二电极上形成第二钝化层， 其中， 所述第一 电极通过所述第一过孔和所述导电层电性连接、 所述第二电极通过第二过孔 和所述漏极电性连接。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图 仅仅涉及本发明的一些实施例， 并非对本发明的限制。
图 1为现有 X射线检测装置中的阵列基板的部分剖面结构示意图； 图 2为本发明实施例的薄膜晶体管的制作方法流程示意图；
图 3为本发明实施例中形成栅极后的薄膜晶体管的结构示意图； 图 4为本发明实施例中形成半导体层后的薄膜晶体管的结构示意图； 图 5为本发明实施例中形成阻挡层后的薄膜晶体管的结构示意图； 图 6为本发明实施例中形成源漏极后的薄膜晶体管的结构示意图； 图 7为本发明实施例中形成信号端子后的薄膜晶体管的结构示意图； 图 8为本发明实施例中形成第一钝化层后的薄膜晶体管的结构示意图； 图 9 为本发明实施例中形成第二像素电极后的薄膜晶体管的结构示意 图；
图 10为本发明实施例中形成第二钝化层后的薄膜晶体管的结构示意图。 具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行清楚、完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提下 所获得的所有其他实施例， 都属于本发明保护的范围。
不同于现有技术中的多晶氧化物薄膜晶体管， 本发明实施例中提供一种 非晶氧化物薄膜晶体管。 不同于现有技术中一般的显示器中的阵列基板， 本 发明实施例提供的阵列基板为非晶硅探测器的阵列基板。 本发明的实施例主 要提供薄膜晶体管及其制作方法和阵列基板， 可有效解决源漏极与非晶氧化 物半导体层电学接触不良的问题。
本发明实施例的基本思想是： 在形成源漏极时， 直接将高掺杂的非晶硅 薄膜沉积在阻挡层两侧的氧化物半导体薄膜层上， 增加氧化物半导体的界面 处的载流子的浓度， 这样氧化物半导体可呈现导体的电学特性， 从而形成源 漏极。
下面结合附图对本发明的具体实施例作进一步详细说明。
图 2为本发明实施例的薄膜晶体管的制作方法流程示意图，如图 2所示， 制作方法如下：
步骤 201: 在基板上形成栅极；
例如， 在基板 101上形成栅极层薄膜并图形化， 形成栅极 102。 这里， 所述栅极 102可采用铝、 铜或钼等金属材料， 可采用湿法刻蚀工艺形成栅极 102,该步骤可以采用现有构图工艺，此处不再详述，形成的结构如图 3所示。
步骤 202: 在形成有栅极的基板上形成覆盖栅极和至少部分基板的栅绝 缘层以及氧化物半导体薄膜层；
例如，在形成有栅极 102的基板 101上涂覆栅极绝缘材料，例如氧化硅， 可以采用物理溅射法溅射沉积方法形成， 然后可以采用现有构图工艺形成栅 绝缘层 103。
在所述栅绝缘层 103上沉积一层非晶氧化物半导体薄膜，如： a-IGZO薄 膜， 并采用湿法刻蚀工艺形成非晶氧化物半导体薄膜层 105, 得到如图 4所 示的结构。 其中， 所述非晶氧化物半导体材料还可选为： 铪铟辞氧化物 ( HflnZnO ) 或者铟镓锡氧化物（ InGaSnO )等其他材料， 在此不——赘述。
步骤 203: 在形成有氧化物半导体薄膜层的基板上形成阻挡层； 例如， 在形成有非晶氧化物半导体薄膜层 105的基板上沉积一层二氧化 硅薄膜， 并采用干法刻蚀工艺形成阻挡层 104, 阻挡层 104可采用现有工艺 实现， 不再详述。 此步骤之后形成的结构如图 5所示。
步骤 204: 将高掺杂的非晶硅薄膜沉积在阻挡层两侧的所述氧化物半导 体薄膜层上， 以形成源极和漏极；
例如，利用等离子体增强化学气相沉积法（ PECVD )将高掺杂的非晶硅， 如： a-Si:H沉积在阻挡层 104两侧的非晶氧化物半导体薄膜层 105上， 于是， 非晶氧化物半导体薄膜层 105与所述非晶硅薄膜的界面处的载流子的浓度增 加， 此界面处的非晶氧化物半导体薄膜层则呈现出导体的电学特性， 从而形 成源漏极 107, 未被掺杂的非晶氧化物半导体薄膜层， 即被阻挡层 4覆盖的 非晶氧化物半导体薄膜层即形成为半导体层 105，， 如图 6所示。
这样， 可改善非晶氧化物半导体构成的半导体层 105，与源漏极 107之间 的界面处的电阻特性， 提高了驱动电流， 从而有效解决了源漏极 107与非晶 氧化物半导体层 105，之间电性接触不良的问题,有利于提高器件的显示品质。
在本发明的上述实施例中，不需另外沉积一层金属材料用于形成源漏极， 即省去了源漏极的掩模形成工艺， 从而降低了生产成本。
步骤 205: 在形成有源漏极的基板上形成信号端子（PIN )和导电层； 例如，在所述沉积有高掺杂的非晶硅薄膜的基板上依次沉积本征硅薄膜， N型掺杂的硅（n+Si )薄膜和 ITO薄膜， 采用湿法刻蚀所述 ITO薄膜， 之后 采用干法刻蚀 n+Si薄膜、 本征硅薄膜和所述高掺杂的非晶硅（ a-Si:H )薄膜， 从而形成 P型层 108、 P型层 108之上的 I型层 109和形成于 I型层 109之上 的 N型层 110, 以及在所述 N型层 110上的导电层 111 , 如图 7所示。 所述 P型层 108采用的材料为高掺杂的氢化非晶硅， 所述 I型层 109采用的材料 为本征硅， 所述 N型层 110采用的材料为 N型掺杂的硅（ n+Si ) 。
步骤 206:在所述形成有信号端子 PIN的基板上形成第一钝化层和第一、 二过孔；
可选择地， 在形成有所述 PIN的基板上， 例如在 PIN上的导电层 111上 沉积高掺杂的氮化硅薄膜， 并采用干法刻蚀形成第一钝化层 112, 其中形成 有对应于漏极区域的第一过孔 HI和对应于源极区域的第二过孔 H2,得到图 8所示的结构。
这里， 采用高掺杂的氮化硅薄膜替代现有技术中采用的二氧化硅薄膜形 成第一钝化层 112可进一步提高非晶氧化物半导体形成的源漏极 107的电学 性能。
步骤 207: 在所述第一钝化层上顺序形成第一电极和第二电极和第二钝 化层；
例如， 在所述第一钝化层 112上沉积一层 ITO薄膜， 并湿法刻蚀形成第 一电极 113和第二电极 115,所述第一电极 113通过所述第一过孔 HI和所述 导电层 111电性连接、 所述第二电极 115通过第二过孔 H2和所述源极电性 连接， 得到图 9所示的结构。 在所述第一电极 113和第二电极 115上沉积一 层高掺杂的氮化硅薄膜， 并采用干法刻蚀形成第二钝化层 114, 用以避免外 界环境（水、 空气等） 的影响， 得到图 10所示的结构。
下面对本发明实施例提供的所述薄膜晶体管的结构进行描述。 如图 10 所示， 本发明实施例提供的所述薄膜晶体管包括： 形成于基板 101上的栅极 102、 形成于栅极 102上并且覆盖整个基板 101的栅绝缘层 103、 形成于栅绝 缘层 103上的半导体层 105，和位于所述半导体层 105，两侧的源漏极 107, 其 中所述源漏极 107包括分别位于所述半导体层 105，两侧的源极 107a和漏极 107b, 形成于半导体层 105，上的阻挡层 104、形成于漏极 107b上的信号端子 ( PIN ) 。
其中， 所述 PIN包括： 形成于漏极 107b上的由高掺杂的氢化非晶硅构 成的 P型层 108、 形成于 P型层 108上的 I型层 109和形成于 I型层 109上 的 N型层 110。所述薄膜晶体管还包括： 形成于 N型层 110上的导电层 111。
其中， 所述源漏极 107和所述半导体层 105，位于同一氧化物半导体薄膜 层中， 且厚度相同。 也就是说， 源极 107a和漏极 107b两者与半导体层 105， 融合为同一薄膜层， 且均由氧化物半导体材料形成。
从图 10可以看出，所述薄膜晶体管还包括：形成于所述导电层 111上的 第一钝化层 112、位于第一钝化层 112中且对应于漏极 107b区域的第一过孔 和位于第一钝化层中 112中且对应于源极 107a区域的第二过孔。
可选择地， 所述薄膜晶体管还包括： 形成于第一钝化层 112上的第一电 极 113和第二电极 115, 以及形成于第一电极 113和第二电极 115上的第二 钝化层 114, 其中， 所述第一电极 113通过所述第一过孔和所述导电层 111 电性连接、 所述第二电极 115通过第二过孔和所述源极 107a电性连接。
优选的， 所述第一钝化层 112和所述第二钝化层 114选用高掺杂的氮化 硅材料。
从上述薄膜晶体管的制作方法可以看出， 本发明实施例提供的薄膜晶体 管的制备过程和现有技术相比， 省略了制备源漏极的构图工艺， 因而可以节 约掩膜版成本和节省制程。 本发明实施例中，向栅极 102施加电压后， 电信号从漏极 107b经过半导 体层 105，传输到源极 107a, 和源极 107a相连接的第二电极 115得到信号， 第二电极 115是和平板检测装置的检测电路相连接， 因此可以检测到 X射线 的光强信息等。
此外， 本发明的实施例还提供一种阵列基板， 所述阵列基板中的薄膜晶 体管采用如上所述的薄膜晶体管。
在本发明实施例提供的薄膜晶体管及其制作方法和阵列基板中， 在形成 薄膜晶体管的源漏极时， 直接将高掺杂的非晶硅薄膜沉积在阻挡层两侧的氧 化物半导体薄膜层上， 当高掺杂非晶硅沉积在氧化物半导体表面时， 由于高 掺杂非晶硅中含有大量的不饱和氢键， 从而造成氢离子向非晶金属氧化物半 导体层扩散， 使得非晶金属氧化物的靠近该高掺杂非晶硅薄膜的表面形成 H 离子的高掺杂区域进而呈导体特性。 由于高掺杂非晶硅薄膜能够提供大量载 流子， 因此在高掺杂非晶硅薄膜与非晶氧化物半导体薄膜的界面处的非晶氧 化物半导体薄膜则呈现出导体的电学特性， 从而形成源极和漏极。 此外， 在 本发明实施例提供的薄膜晶体管中， 由同种材料形成的源漏极与半导体层之 间的价带能级差均 4艮小， 且晶格匹配性较好， 因此对驱动电流信号的影响较 小， 且减少了电子流动的障碍， 从而可有效解决源漏极与非晶氧化物半导体 层之间电学接触不良的问题， 提升薄膜晶体管的电学特性， 有利于提高器件 的显示品质。
此外， 本发明的实施例中不需另外沉积一层金属材料用于形成源漏极， 即省去了源漏极的掩模形成工艺， 从而降低了生产成本。
虽然上文中已经用一般性说明及具体实施方式， 对本发明作了详尽的描 述， 但在本发明基础上， 可以对之作一些修改或改进， 这对本领域技术人员 而言是显而易见的。 因此， 在不偏离本发明精神的基础上所做的这些修改或 改进， 均属于本发明要求保护的范围。

Claims

权利要求书
1、 薄膜晶体管， 包括：
形成于基板上的栅极， 形成于栅极上并覆盖至少部分所述基板的栅绝缘 层， 以及形成于栅绝缘层上的半导体层、 源极和漏极；
其中， 所述半导体层的材料为氧化物半导体， 所述源极、 漏极的材料为 掺杂的所述氧化物半导体， 且所述源极、 漏极与所述半导体层同层设置。
2、根据权利要求 1所述的薄膜晶体管，其中所述半导体层为非晶氧化物 半导体层。
3、根据权利要求 1或 2所述的薄膜晶体管， 其中所述源极、所述漏极以 及所述半岛体层由同一材料层形成。
4、根据权利要求 1至 3中任一项所述的薄膜晶体管，还包括形成在所述 半导体层上的阻挡层， 其中所述源极和漏极分别位于所述阻挡层的两侧。
5、根据权利要求 1至 4中任一项所述的薄膜晶体管，还包括形成于漏极 上的信号端子， 所述信号端子为 PIN结构的光电二极管， 包括： 形成于所述 漏极上由高掺杂的氢化非晶硅构成的 P型层、形成于所述 P型层上的 I型层、 形成于 I型层上的 N型层。
6、根据权利要求 1至 5中任一项所述的薄膜晶体管，还包括： 形成于所 述信号端子的 N型层上的导电层。
7、 根据权利要求 1至 6中任一项所述的薄膜晶体管， 还包括： 形成于导电层上的第一钝化层， 其中， 所述第一钝化层中形成有对应于 所述漏极所在区域的第一过孔和对应于所述源极所在区域的第二过孔。
8、 根据权利要求 7所述的薄膜晶体管， 还包括：
形成于第一钝化层上的第一电极和第二电极， 以及形成于第一电极和第 二电极上的第二钝化层， 其中， 所述第一电极通过所述第一过孔和所述导电 层电性连接、 所述第二电极通过第二过孔和所述源极电性连接。
9、 根据权利要求 8所述的薄膜晶体管， 其中， 所述第一钝化层和 /或所 述第二钝化层由高掺杂的氮化硅材料构成。
10、 阵列基板， 包括权利要求 1至 9中任一项所述的薄膜晶体管。
11、 薄膜晶体管的制作方法， 包括以下步骤： 在基板上形成栅极；
在栅极和至少部分基板上形成栅绝缘层；
在所述形成有栅绝缘层的基板上形成氧化物半导体薄膜层；
对所述氧化物半导体薄膜层进行掺杂处理以在其中形成源极、 漏极以及 夹设在所述源极和所述漏极之间的半导体层。
12、根据权利要求 11所述的薄膜晶体管的制作方法， 其中， 所述对所述 氧化物半导体薄膜层进行掺杂处理以在其中形成源极、 漏极以及夹设在所述 源极和所述漏极之间的半导体层的步骤包括：
在所述氧化物半导体薄膜层上形成阻挡层；
对所述阻挡层两侧的氧化物半导体薄膜层进行掺杂处理以形成源极和漏 极。
13、根据权利要求 12所述的薄膜晶体管的制作方法，还包括在所述源级 极上形成信号端子， 其中， 所述对阻挡层两侧的氧化物半导体薄膜层掺杂处 理以形成源极和漏极的步骤包括：
在氧化物半导体薄膜层和阻挡层上形成高掺杂的氢化非晶硅层； 对高掺杂的氢化非晶硅层进行构图工艺，形成所述信号端子中的 P型层。
14、根据权利要求 13所述的薄膜晶体管的制作方法， 其中， 所述在漏极 上形成信号端子的步骤包括：
在所述由高掺杂的氢化非晶硅构成的 P型层上， 依次形成 I型层和 N型 层， 其中， I型层由本征硅构成， N型层由 N型掺杂的硅构成。
15、 根据权利要求 13或 14所述的薄膜晶体管的制作方法， 还包括： 在所述信号端子上形成导电层。
16、 根据权利要求 15所述的薄膜晶体管的制作方法， 还包括： 在所述导电层上形成第一钝化层；
在第一钝化层中形成对应于漏极所在区域的第一过孔和对应于源极所在 区域的第二过孔。
17、 根据权利要求 16所述的薄膜晶体管的制作方法， 还包括： 在所述第一钝化层上形成第一电极和第二电极， 在第一电极和第二电极 上形成第二钝化层， 其中， 所述第一电极通过所述第一过孔和所述导电层电 性连接、 所述第二电极通过第二过孔和所述漏极电性连接。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105489618B (zh) * 2016-01-22 2019-04-26 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
CN107170748B (zh) * 2017-04-20 2019-11-08 上海天马微电子有限公司 一种阵列基板、显示面板及显示设备
CN106972034B (zh) * 2017-05-27 2018-12-14 福州京东方光电科技有限公司 一种薄膜晶体管及其制作方法、阵列基板
CN107632428A (zh) * 2017-08-21 2018-01-26 合肥惠科金扬科技有限公司 一种防护型tft‑lcd液晶屏幕
CN110809825A (zh) * 2017-12-15 2020-02-18 深圳市柔宇科技有限公司 薄膜晶体管及制备方法、显示装置
CN108878572B (zh) * 2018-07-10 2021-01-26 京东方科技集团股份有限公司 感光元件、光电传感探测基板及其制造方法
CN109192701B (zh) * 2018-08-31 2020-12-08 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
TW202322375A (zh) * 2021-11-26 2023-06-01 友達光電股份有限公司 感光元件基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303020A1 (en) * 2007-05-29 2008-12-11 Hyun-Soo Shin Thin film transistor, flat panel display device having the same, and associated methods
CN102196194A (zh) * 2010-02-25 2011-09-21 索尼公司 放射线摄像装置和驱动放射线摄像装置的方法
CN102916085A (zh) * 2012-10-30 2013-02-06 上海奕瑞光电子科技有限公司 氧化物半导体薄膜探测器的制备方法及其应用
CN103018990A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种阵列基板和其制备方法、及液晶显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040135209A1 (en) * 2002-02-05 2004-07-15 Tzu-Chiang Hsieh Camera with MOS or CMOS sensor array
GB0219771D0 (en) * 2002-08-24 2002-10-02 Koninkl Philips Electronics Nv Manufacture of electronic devices comprising thin-film circuit elements
TWI266427B (en) * 2004-06-01 2006-11-11 Yamanashi Tlo Co Ltd Field-effect transistor and method of manufacturing same
JPWO2007037121A1 (ja) * 2005-09-29 2009-04-02 コニカミノルタエムジー株式会社 放射線像撮像装置および放射線像撮像装置の撮像方法
JP5015471B2 (ja) * 2006-02-15 2012-08-29 財団法人高知県産業振興センター 薄膜トランジスタ及びその製法
JP5110803B2 (ja) * 2006-03-17 2012-12-26 キヤノン株式会社 酸化物膜をチャネルに用いた電界効果型トランジスタ及びその製造方法
JP2008122659A (ja) 2006-11-13 2008-05-29 Seiko Epson Corp 液晶表示装置及び液晶表示装置の製造方法並びに電子機器
JP5286691B2 (ja) * 2007-05-14 2013-09-11 三菱電機株式会社 フォトセンサー
JP5268132B2 (ja) * 2007-10-30 2013-08-21 富士フイルム株式会社 酸化物半導体素子とその製造方法、薄膜センサおよび電気光学装置
KR101469042B1 (ko) * 2008-08-29 2014-12-05 삼성디스플레이 주식회사 엑스레이 검출 패널 및 엑스레이 검출기
JP4844627B2 (ja) * 2008-12-24 2011-12-28 ソニー株式会社 薄膜トランジスタの製造方法および表示装置の製造方法
CN102157565A (zh) * 2011-01-18 2011-08-17 北京大学深圳研究生院 一种薄膜晶体管的制作方法
TWI423673B (zh) * 2011-03-17 2014-01-11 Innolux Corp 影像感測畫素及其驅動方法
JP6013685B2 (ja) * 2011-07-22 2016-10-25 株式会社半導体エネルギー研究所 半導体装置
CN102629610A (zh) * 2012-03-27 2012-08-08 北京京东方光电科技有限公司 一种x射线检测装置的阵列基板及其制造方法
KR20130136063A (ko) * 2012-06-04 2013-12-12 삼성디스플레이 주식회사 박막 트랜지스터, 이를 포함하는 박막 트랜지스터 표시판 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303020A1 (en) * 2007-05-29 2008-12-11 Hyun-Soo Shin Thin film transistor, flat panel display device having the same, and associated methods
CN102196194A (zh) * 2010-02-25 2011-09-21 索尼公司 放射线摄像装置和驱动放射线摄像装置的方法
CN102916085A (zh) * 2012-10-30 2013-02-06 上海奕瑞光电子科技有限公司 氧化物半导体薄膜探测器的制备方法及其应用
CN103018990A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种阵列基板和其制备方法、及液晶显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
AYUMU SATO ET AL.: "Amorphous In-Ga-Zn-O thin-film transistor with coplanar homojunction structure.", THIN SOLID FILMS, vol. 518, 2009, pages 1309 - 1313 *

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