WO2014172972A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2014172972A1
WO2014172972A1 PCT/CN2013/077408 CN2013077408W WO2014172972A1 WO 2014172972 A1 WO2014172972 A1 WO 2014172972A1 CN 2013077408 W CN2013077408 W CN 2013077408W WO 2014172972 A1 WO2014172972 A1 WO 2014172972A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
array substrate
connecting line
main
auxiliary
Prior art date
Application number
PCT/CN2013/077408
Other languages
English (en)
French (fr)
Inventor
李凡
董向丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2014172972A1 publication Critical patent/WO2014172972A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • the gate scanning lines are generally arranged in a row from top to bottom, and the data lines are generally arranged in columns from left to right. Since the driving integrated circuit (IC) of the liquid crystal display is generally disposed at the bottom of the screen, the connection lines connecting the driving integrated circuit and each of the gate scanning lines have the same width and different lengths, which results in different connection lines as a whole. The difference in resistance is relatively large. This easily causes RC delay (resistance and capacitance delay), which causes a certain delay between the rising edge and the falling edge of the gate drive signal.
  • RC delay resistance and capacitance delay
  • the gate drive signal GATE1 of the nth gate scan line is at the falling edge, the gate drive signal GATE2 of the n+1th gate scan line has started to rise.
  • the TFTs corresponding to the n-th gate scan lines are not all turned off, the TFTs on the n+1th gate scan line are already turned on, and the data driver starts to output to the respective TFTs on the n+1th gate scan line.
  • the data signal causes confusion with the data signals of the respective TFTs outputted to the n-th gate scan line, which affects the screen display.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which can reduce the difference in resistance between the connection lines, reduce the RC delay phenomenon, and improve the display effect of the display device.
  • An aspect of the present invention provides an array substrate including a driving integrated circuit, a plurality of metal traces disposed in a pixel region, and a plurality of connecting lines respectively connecting the driving integrated circuit and each of the metal traces, wherein each A connecting line includes a main connecting line and a auxiliary connecting line corresponding to the main connecting line, and the auxiliary connecting line is connected in parallel with a part of the main connecting line.
  • the main connecting line and the auxiliary connecting line are located in different layers, and the main connecting line and the auxiliary connecting line are separated by an insulating layer, and the main connecting line and the auxiliary connecting line pass The via holes in the insulating layer are connected.
  • the fan-shaped routing area of the array substrate includes a first area and a second area, wherein a lateral distance between the traces of the first area is less than ⁇ , and a lateral distance between the traces of the second area is greater than 5 ⁇ , wherein the auxiliary connecting line is located in the second area.
  • one of the at least two vias connected to the corresponding auxiliary connecting line is disposed at a turning point in which the main connecting line of the second area is turned from a diagonal direction to a vertical direction, and A via is placed in the electrostatic protection area of the pixel.
  • the connecting line connects the driving integrated circuit and the gate scanning line arranged in a row on the array substrate, wherein the main connecting line is adopted
  • the gate metal layer is made of a corresponding auxiliary connecting line made of a source/drain metal layer.
  • the connecting line connects the data lines arranged in a row on the driving integrated circuit and the array substrate, wherein the main connecting line is adopted.
  • the source and drain metal layers are made, and the corresponding auxiliary connecting lines are made of a gate metal layer.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the embodiment of the invention further provides a method for fabricating an array substrate, wherein the array substrate comprises a driving integrated circuit and a plurality of metal traces arranged in the pixel region.
  • the method includes: forming a pattern of connecting a plurality of connection lines respectively connecting the driving integrated circuit and each metal trace, the pattern of the connection line including a pattern of a main connection line and a secondary connection corresponding to the main connection line a pattern of lines, the auxiliary connection line being connected in parallel with a portion of the main connection line.
  • the method when the driving integrated circuit is disposed on a lower side of the array substrate, and the connecting line connects the driving integrated circuit and the gate scanning line arranged in a row on the array substrate, the method includes: using a gate metal layer Forming a pattern of the gate scan line and the main connection line; forming a gate insulating layer, forming a via pattern on the gate insulating layer; forming a pattern of the data line and the auxiliary connection line by using the source/drain metal layer, so that the main connection line The auxiliary connecting wires are connected through the via holes.
  • the method when the driving integrated circuit is disposed on a side of the array substrate, and the connecting line connects the driving integrated circuit and the data line arranged in a row on the array substrate, the method includes: using a gate metal layer Forming a pattern of the gate scan line and the auxiliary connection line; forming a gate insulating layer, forming a via pattern on the gate insulating layer; forming a pattern of the data line and the main connection line by using the source/drain metal layer, so that the main connection line
  • the auxiliary connecting wires are connected through the via holes.
  • 1 is a schematic diagram of division of a first area and a second area in a sector-shaped routing area
  • FIG. 2 is a schematic view showing a position of a via hole connecting a main connection line and an auxiliary connection line according to an embodiment of the present invention
  • FIG. 3 is a schematic view showing a connection line formed by using a gate metal layer on a substrate according to an embodiment of the present invention
  • Schematic diagram of a gate insulating layer
  • FIG. 5 is a schematic diagram of forming a semiconductor layer pattern according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of forming a connection line by using a source/drain metal layer according to an embodiment of the present invention
  • FIG. 7 is a schematic view of forming a passivation layer according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of forming a transparent conductive layer pattern according to an embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view showing the mutual position of the main connecting line and the auxiliary connecting line according to the embodiment of the present invention
  • FIG. 10 is a schematic plan view showing the mutual position of the main connecting line and the auxiliary connecting line according to the embodiment of the present invention
  • FIG. 12 is a schematic view of a trace of a prior art array substrate.
  • the implementation of the present invention provides an array substrate, a manufacturing method thereof, and a display device, which can reduce the difference in resistance between the connection lines, reduce the RC delay phenomenon, and improve the display effect of the display device.
  • the array substrate of the embodiment of the invention includes a driving integrated circuit, a plurality of metal traces disposed in the pixel region, and a plurality of connecting lines of different lengths connecting the driving integrated circuit and each of the metal traces.
  • Each of the connection lines includes a main connection line and a sub-connection line corresponding to the main connection line, and the auxiliary connection line is connected in parallel with a portion of the main connection line.
  • the main and auxiliary cables can be on the same layer or on different layers.
  • the main connecting line and the auxiliary connecting line are located at different layers, and the main connecting line and the auxiliary connecting line are separated by an insulating layer, and the main connecting line and the auxiliary connecting line
  • the connecting lines are connected through the via holes in the intermediate insulating layer, so that the spacing between the auxiliary connecting lines and the main connecting lines needs to be left in the same layer, thereby reducing the occupation of the connecting lines (horizontal ) Space.
  • the auxiliary connecting wires are formed on the same layer as the main connecting wires, they are spaced apart from each other, for example, connected to each other in parallel at at least two positions.
  • the resistance value of the auxiliary connecting line is mainly affected by the length of the auxiliary connecting line, and thus the resistance value of the connecting line can be adjusted by adjusting the length of the auxiliary connecting line. Since the auxiliary connecting line is connected in parallel with a part of the main connecting line, the auxiliary connecting line can change the resistance value of each connecting line, so that the difference of the resistance values between the connecting lines becomes smaller, thereby reducing the RC delay phenomenon and further improving Display the display effect of the device. For example, the deviation between the total resistance values of the respective connecting lines is made less than or equal to 0.1%.
  • the reference line has a resistance of 1 ⁇
  • the deviation resistance is only 0.001 ⁇ .
  • the deviation of the resistance values between the respective connecting lines is small, and when the signal is transmitted, the signal attenuation of each of the connecting lines is also very close, and the RC delay phenomenon can be greatly reduced.
  • the connection line connecting the driving integrated circuit and each metal trace includes a main connection line and a secondary connection line corresponding to the main connection line, and the auxiliary connection line is connected to the main connection A part of the line is connected in parallel.
  • the resistance value of each connection line can be changed by the auxiliary connection line, so that the difference in resistance value between the respective connection lines becomes small, the RC delay phenomenon is reduced, and the display effect of the display device is improved.
  • the driving integrated circuit of the liquid crystal display is generally disposed on the lower side of, for example, a rectangular screen, such that the connection is made for the connection line connecting the driving integrated circuit and each of the gate scanning lines.
  • the widths of the lines are the same and the lengths are different. Therefore, the difference in the resistance of the different connection lines is relatively large, and the RC delay is easily generated, resulting in a certain delay between the rising edge and the falling edge of the gate driving signal.
  • connection line connecting the driving integrated circuit and the gate scan line is composed of a main connection line and a auxiliary connection line corresponding to the main connection line, and the auxiliary connection line is connected in parallel with a part of the main connection line. Connection, adjust the resistance value of the connection line through the auxiliary connection line, reduce the difference in resistance between the connection lines, and reduce the RC delay phenomenon.
  • the fan-shaped routing area of the connecting line on the array substrate can be divided into a first area and a second area. In the first area, the routing is dense, and in the second area, the routing is arranged. More relaxed.
  • the first and second regions are compared side by side in Figure 1, but it is not meant that the locations of the two regions on the array substrate are juxtaposed to each other.
  • the auxiliary connecting line is disposed in the second area, because if the auxiliary connecting line is disposed at the first area, since the lateral distance between the lines of the first area does not exceed ⁇ . ⁇ , it is bound to be
  • the main connection line and the auxiliary connection line are mutually influenced, and the accuracy of the exposure machine is more difficult to meet the requirements of the patterning process; if the auxiliary connection line is disposed at the second area, since the lateral distance between the lines of the second area is greater than 5 ⁇ , So it won’t make the lines between each other influences.
  • the main connection line and the auxiliary connection line are located in different layers, and the main connection line and the auxiliary connection line are separated by an insulating layer.
  • the main connection line and the auxiliary connection line may be formed of a gate metal layer and a source/drain metal layer, respectively, and the main connection line and the auxiliary connection line may be connected through the transparent conductive layer 105 at the via hole in the intermediate insulating layer. Since the auxiliary connecting line is connected in parallel with the main connecting line, there can be at least two connections for one connecting line. As shown in the examples of FIGS.
  • one place where the via 103 is provided is, for example, at the ESD (electrostatic protection) of each pixel because the space there is relatively large; another one of the vias 103 is provided The place is at the turning point where the line changes from oblique to vertical, and the space here is also relatively large. If the space is small, the connection line can be designed as a serpentine trace, as shown in the example in Figure 10.
  • auxiliary connecting lines connecting the scanning lines from the top to the bottom are shorter and shorter, that is, the longer the main connecting lines are, the longer the auxiliary connecting lines are connected in parallel, and the more the connecting line resistance is reduced;
  • the driving integrated circuit is generally designed on the side (left side or right side) of the rectangular screen, so that the connection line connecting the driving integrated circuit and each column of data lines is It is said that the widths of the connecting lines are the same and the lengths are different, so that the difference of the resistance of the different connecting lines is relatively large, and the RC delay is easily generated, which causes a certain delay between the rising edge and the falling edge of the data driving signal.
  • the connection line connecting the data lines arranged in the row on the driving integrated circuit and the array substrate may also be a main connection line and a secondary connection corresponding to the main connection line.
  • the line is composed of a parallel connection of a part of the main connecting line, so that the difference in the resistance of the connecting line can be reduced, and the RC delay phenomenon can be alleviated.
  • adjacent connecting lines can be designed in different layers.
  • adjacent main connecting lines may be designed in different layers, as shown in FIG. 9, when the connecting line is connected to the driving integrated circuit and the gate scanning line, the even column main The connection line 201 may be made of a source/drain metal layer, the auxiliary connection line 202 corresponding to the even column main connection line 201 may be made of a gate metal layer, and the odd column main connection line 101 may be made of a gate metal layer, and an odd number.
  • the auxiliary connecting line 102 corresponding to the main connecting line 101 may be made of a source/drain metal layer; or the odd-numbered main connecting line may be made of a source/drain metal layer, and the auxiliary connecting line corresponding to the odd-numbered main connecting line may be used.
  • the gate metal layer is formed, the even-numbered main connection lines can be made of a gate metal layer, and the auxiliary connection lines corresponding to the even-numbered main connection lines can be made of a source-drain metal layer.
  • the even-numbered main connection line when the connection line is connected to the driving integrated circuit and the data line, the even-numbered main connection line may be made of a source/drain metal layer, and the auxiliary connection line corresponding to the even-numbered main line may be made of a gate metal layer.
  • the odd-numbered main connection line may be made of a gate metal layer, and the auxiliary connection line corresponding to the odd-numbered main connection line may be made of a source/drain metal layer; or the odd-numbered main connection line may be made of a source/drain metal layer, and an odd number
  • the auxiliary connecting lines corresponding to the main connecting lines of the column may be made of a gate metal layer, the even-numbered main connecting lines may be made of a gate metal layer, and the auxiliary connecting lines corresponding to the even-numbered main connecting lines may be made of a source/drain metal layer.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the structure and working principle of the array substrate are the same as those in the above embodiment, and will not be described herein.
  • the structure of other parts of the display device may be based on known or future developed techniques, which will not be described in detail herein.
  • the display device may be a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED (Organic Light Emitting Diode) panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • a liquid crystal panel an electronic paper
  • OLED Organic Light Emitting Diode
  • the embodiment of the present invention further provides a method for fabricating the above-mentioned array substrate.
  • the array substrate includes a driving integrated circuit and a plurality of metal traces disposed in the pixel region.
  • the pattern of the connecting line includes a pattern of the main connecting line and a auxiliary connecting line corresponding to the main connecting line
  • the auxiliary connecting line is connected in parallel with a part of the main connecting line.
  • the patterning process mentioned in the present disclosure is, for example, a photolithography process including steps of coating, exposure, development, etching, photoresist stripping, and the like.
  • the gate metal layer may be used as the main connecting line, at a position corresponding to the main connecting line, A source/drain metal layer is used to form a secondary connection line overlapping the main connection line, and a gate insulation layer is between the main connection line and the auxiliary connection line, and the main connection line and the auxiliary connection line pass through the transparent conduction in the via hole in the gate insulation layer.
  • the source/drain metal layer may be used
  • the main connecting line is formed, and at the corresponding position of the main connecting line, the auxiliary metal line is formed by the gate metal layer, and the main connecting line and the auxiliary connecting line are the gate insulating layer, the main connecting line and the auxiliary connecting line.
  • the wires are connected through a transparent conductive layer in vias in the gate insulating layer.
  • connection line connects the drive integrated circuit and the gate scan line.
  • the manufacturing method of this embodiment includes the following steps Sl-S6.
  • a transparent substrate 1 is provided, which may be a glass substrate or a quartz substrate.
  • a gate metal layer 2 may be evaporated or deposited on the substrate 1, and then patterned by a patterning process, such as masking, exposure, etching, and photoresist removal, to form a pattern of the gate metal layer 2, the gate metal layer.
  • the pattern of 2 includes a gate scan line and a main connection line; the gate metal layer may be made of chromium (Cr), phase (Mo), aluminum (A1), copper (Cu), tungsten (W), germanium (Nd), and any of them. alloy.
  • Step S2 As shown in FIG. 4, a gate insulating layer 3 is formed on the substrate subjected to the step S1, and for example, the gate insulating layer 3 may be formed by evaporation or deposition.
  • Step S3 As shown in FIG. 5, a semiconductor layer 4 is evaporated or deposited on the substrate subjected to the step S2, and then the semiconductor layer 4 is formed through a process such as masking, exposure, etching, and photoresist removal by a patterning process. Graphics.
  • Step S4 As shown in FIG. 6, the source/drain metal layer 5 is evaporated or deposited on the substrate subjected to the step S3, and then the source and drain are formed through a process of masking, exposure, etching, and photoresist removal by a patterning process.
  • the pattern of the metal layer 5, the pattern of the source/drain metal layer 5 includes a source electrode, a drain electrode, a data line, and an auxiliary connection line; the source/drain metal layer may be made of chromium (Cr), phase (Mo), aluminum (A1), or copper ( Cu), tungsten (W), niobium (Nd) and any alloy thereof.
  • Step S5 as shown in FIG. 7, the passivation layer 6 is evaporated or deposited on the substrate subjected to the step S4, and a via pattern is formed through a patterning process step such as masking, exposure, etching, and photoresist removal.
  • the holes penetrate the passivation layer 6 and the gate insulating layer 3.
  • Step S6 As shown in FIG. 8, a transparent conductive layer 7 is deposited or deposited on the substrate subjected to the step S5, and the transparent conductive layer 7 may be made of ITO or IZO. Then, a pattern of the transparent conductive layer 7 is formed by a patterning process step such as masking, exposure, etching, and photoresist removal.
  • the pattern of the transparent conductive layer 7 includes a pixel electrode and a connection structure, and the connection structure turns on the main connection line through the via hole. 101 and auxiliary connection line 102.
  • the above embodiment only uses the TN panel as an example to illustrate the technical solution of the embodiment.
  • the array substrate of the present invention and the method of fabricating the same can also be applied to panels such as ADS and FFS.
  • adjacent connecting lines can be designed in different layers.
  • adjacent main connecting lines can be designed in different layers.
  • a source/drain metal layer can be used.
  • the even-numbered main connection line 201 is formed, and the auxiliary metal line 202 can be used to form the auxiliary connection line 202 corresponding to the even-numbered main connection line 201.
  • the gate-metal layer can be used to form the odd-numbered main connection line 101, and the source-drain metal layer can be used.
  • the auxiliary connection line 102 corresponding to the odd-numbered main connection line 101 is formed; or, the source-drain metal layer may be used to form the odd-numbered main connection line, and the gate metal layer may be used to form the auxiliary connection line corresponding to the odd-numbered main connection line.
  • the gate metal layer may be used to form the even-numbered main connection line, and the source-drain metal layer may be used to form the auxiliary connection line corresponding to the even-numbered main connection line.
  • the source-drain metal layer may be used to form the even-numbered column main connection line, and the gate metal layer may be used to form the auxiliary connection line corresponding to the even-numbered column main connection line, which may be adopted.
  • the gate metal layer is made of an odd-numbered column main connection line, and the source-drain metal layer can be used to form an auxiliary connection line corresponding to the odd-numbered column main connection line; or, the source-drain metal layer can be used to form the odd-numbered column main connection line, and the gate can be used.
  • the metal layer is made of a secondary connecting line corresponding to the odd-numbered main connecting line, and the gate metal layer can be used to form the even-numbered main connecting line, and the source-drain metal layer can be used to form the auxiliary connecting line corresponding to the even-numbered main connecting line.
  • the fabrication of the main connection line and the auxiliary connection line is completed simultaneously with the fabrication of the array substrate electrode, which saves the fabrication steps of the array substrate, but the technical solution of the present invention is not limited thereto, and the other is through a special patterning process.
  • the technical solution for making the main connection line and the auxiliary connection line is also within the scope of the present invention.
  • the difference in the total resistance between the connecting lines can be reduced, the RC delay phenomenon can be reduced, and the display effect of the display device can be improved.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及其制造方法、显示装置。该阵列基板包括驱动集成电路、布置在像素区域的多条金属走线以及分别连接驱动集成电路与每一金属走线的多条连接线。每一连接线包括一主连接线（101，201）和与主连接线对应的辅助连接线（102，202），辅助连接线（102，202）与主连接线（101，201）的一部分并联连接。能够使得各条连接线（101，201，102，202）之间的电阻值差异变小，减轻电阻电容延迟现象，进而提高显示装置的显示效果。

Description

阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、 显示装置。 背景技术
在现有的液晶显示器中， 栅扫描线一般是从上而下成行排列， 数据线一 般是从左到右成列排列。 由于液晶显示器的驱动集成电路（IC )一般设置在 屏幕下方， 所以对于连接驱动集成电路与每一行栅扫描线的连接线来说， 连 接线的宽度相同而长度不同， 这造成了不同连接线整体电阻的差异比较大。 这样容易产生 RC delay (电阻电容延迟） ， 导致栅极驱动信号的上升沿和下 降沿都有一定的延时。
如果栅极驱动信号的延时比较严重， 那么当第 n行栅扫描线的栅极驱动 信号 GATE1 正处于下降沿时，而第 n+1行栅扫描线的栅极驱动信号 GATE2 已经开始上升。 这样， 第 n行栅扫描线对应的各个 TFT还没有全部关断， 第 n+1 行栅扫描线上的各个 TFT已经开启， 数据驱动器开始向第 n+1行栅 扫描线上的各个 TFT输出数据信号， 造成与输出到第 n行栅扫描线对应的 各个 TFT的数据信号发生混淆， 影响画面显示。 发明内容
本发明的实施例提供了一种阵列基板及其制作方法、 显示装置， 能够降 低连接线间的电阻差异， 减轻 RC delay现象， 提高显示装置的显示效果。
本发明的一方面提供了一种阵列基板， 包括驱动集成电路、 布置在像素 区域的多条金属走线以及分别连接所述驱动集成电路与每一金属走线的多条 连接线， 其中， 每一连接线包括一主连接线和与所述主连接线对应的辅连接 线， 所述辅连接线与所述主连接线的一部分并联连接。
在一个示例中， 所述主连接线与所述辅连接线位于不同层， 且所述主连 接线与所述辅连接线之间隔有绝缘层， 所述主连接线与所述辅连接线通过所 述绝缘层中的过孔相连接。 在一个示例中，所述阵列基板的扇形走线区包括有第一区域和第二区域， 所述第一区域走线间的横向距离小于 Ιμιη, 所述第二区域走线间的横向距离 大于 5μιη, 其中， 所述辅连接线位于所述第二区域中。
在一个示例中， 所述主连接线与对应辅连接线连接的至少两个过孔中， 其中一个过孔设置在所述第二区域主连接线由斜向转为垂直走向的转折处， 另一个过孔设置在像素的静电保护区域。
在一个示例中， 在所述驱动集成电路设置在阵列基板的下侧时， 所述连 接线连接所述驱动集成电路和阵列基板上成行排列的栅扫描线， 其中， 所述 主连接线为采用栅金属层制成，与其对应的辅连接线为采用源漏金属层制成。
在一个示例中， 在所述驱动集成电路设置在阵列基板的侧边时， 所述连 接线连接所述驱动集成电路和阵列基板上成列排列的数据线， 其中， 所述主 连接线为采用源漏金属层制成， 与其对应的辅连接线为采用栅金属层制成。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。
本发明实施例还提供了一种阵列基板的制作方法， 所述阵列基板包括驱 动集成电路、 布置在像素区域的多条金属走线。 所述方法包括： 形成分别连 接所述驱动集成电路与每一金属走线的多条连接线的图形， 所述连接线的图 形包括主连接线的图形和与所述主连接线对应的辅连接线的图形， 所述辅连 接线与所述主连接线的一部分并联连接。
在一个示例中， 在所述驱动集成电路设置在阵列基板的下侧， 所述连接 线连接所述驱动集成电路和阵列基板上成行排列的栅扫描线时， 所述方法包 括： 利用栅金属层形成栅扫描线和主连接线的图形； 形成栅绝缘层， 在所述 栅绝缘层上形成过孔图形； 利用源漏金属层形成数据线和辅连接线的图形， 使得所述主连接线与所述辅连接线通过所述过孔相连接。
在一个示例中， 在所述驱动集成电路设置在阵列基板的侧边， 所述连接 线连接所述驱动集成电路和阵列基板上成列排列的数据线时，所述方法包括： 利用栅金属层形成栅扫描线和辅连接线的图形； 形成栅绝缘层， 在所述栅绝 缘层上形成过孔图形； 利用源漏金属层形成数据线和主连接线的图形， 使得 所述主连接线与所述辅连接线通过所述过孔相连接。 附图说明 为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为扇形走线区域中第一区域和第二区域的划分示意图；
图 2为本发明实施例连接主连接线和辅连接线的过孔的位置示意图； 图 3为本发明实施例在基板上利用栅金属层形成连接线的示意图； 图 4为本发明实施例形成栅绝缘层的示意图；
图 5为本发明实施例形成半导体层图形的示意图；
图 6为本发明实施例利用源漏金属层形成连接线的示意图；
图 7为本发明实施例形成钝化层的示意图；
图 8为本发明实施例形成透明导电层图形的示意图；
图 9为本发明实施例主连接线和辅连接线相互位置的截面示意图； 图 10为本发明实施例主连接线和辅连接线相互位置的平面示意图； 图 11为本发明实施例过孔的位置示意图；
图 12为现有技术阵列基板的走线示意图。
附图标记
1 基板 2栅金属层 3 栅绝缘层 4半导体层
5 源漏金属层 6钝化层 7透明导电层
101、 201 主连接线 102、 202辅连接线 103 过孔 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面 列举的元件或者物件及其等同， 并不排除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电 性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等 仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置 关系也可能相应地改变。
本发明的实施提供了一种阵列基板及其制作方法、 显示装置， 能够降低 连接线间的电阻差异， 减轻 RC delay现象， 提高显示装置的显示效果。
本发明实施例的阵列基板， 包括驱动集成电路、 布置在像素区域的多条 金属走线以及分别连接所述驱动集成电路与每一金属走线的多条长度不等的 连接线。 每一连接线包括主连接线和与所述主连接线对应的辅连接线， 所述 辅连接线与所述主连接线的一部分并联连接。
主连接线和辅连接线可以位于同一层， 也可以位于不同层。 作为本发明 的一个实施例， 所述主连接线与所述辅连接线位于不同层， 且所述主连接线 与所述辅连接线之间隔有绝缘层， 所述主连接线与所述辅连接线通过该中间 绝缘层中的过孔相连接， 这样可以避免在辅连接线与主连接线形成在同一层 时需要在二者之间留出的间距， 因此了减少连接线占用的 （水平） 空间。 如 果辅连接线与主连接线形成在同一层上时， 二者彼此隔开， 例如在至少两个 位置彼此连接从而并联。
假设其中一条连接线的电阻总值为 R, 主连接线的电阻值为 R，， 辅连接 线的电阻值为 R", 根据并联电路的电阻值计算公式： 1/R = 1/R，+1/R"。 可 以看出， 通过调整辅连接线的电阻值能够调节连接线的电阻值。 需要说明的 是， 根据电阻的计算公式 R = p L/S, 其中， p为金属走线的电阻率， S为金 属走线的截面积， L为金属走线的长度。 对于辅连接线而言， 在使用材料确 定截面积确定的情况下， 辅连接线的电阻值主要受辅连接线长度的影响， 因 此通过调节辅连接线的长度可以调节连接线的电阻值。 由于辅连接线与所述 主连接线的一部分并联连接， 通过辅连接线能够改变各条连接线的电阻值， 使得各条连接线之间的电阻值差异变小， 减轻 RC delay现象， 进而提高显示 装置的显示效果。 例如，使得各条连接线的电阻总值之间偏差小于或者等于 0.1 %。举例来 说,假设参考连接线的电阻值为 1 Ω ,当偏差为 0.1 %时，偏差电阻值仅为 0.001 Ω。 此时， 各条连接线之间电阻值的偏差是很小的， 在进行信号传输时， 各 条连接线上的信号衰减情况也会因此变得非常接近， 能够极大减轻 RC delay 现象。
当然， 理想情况是使得各条连接线的电阻总值相同。 使用相同电阻总值 的连接线进行信号传输时， 各条连接线上的信号衰减情况会变得一致， 此时 会使得显示面板的显示效果大大提高。
本发明实施例的阵列基板中， 连接驱动集成电路与每一金属走线的连接 线包括一主连接线和与所述主连接线对应的辅连接线， 所述辅连接线与所述 主连接线的一部分并联连接。 这样通过辅连接线能够改变各条连接线的电阻 值， 使得各条连接线之间的电阻值差异变小， 减轻 RC delay现象， 进而提高 显示装置的显示效果。
下面结合附图以及具体的实施例对本发明进行详细介绍。
如上所述， 现有的液晶显示器的阵列基板中， 液晶显示器的驱动集成电 路一般设置在例如长方形屏幕的下侧， 这样对于连接驱动集成电路与每一行 栅扫描线的连接线来说， 这些连接线的宽度相同而长度不同， 因此造成了不 同连接线电阻的差异比较大， 容易产生 RC delay, 导致栅极驱动信号的上升 沿和下降沿都有一定的延时。 为此， 在本发明实施例的阵列基板中， 连接驱 动集成电路和栅扫描线的连接线由主连接线和与主连接线对应的辅连接线组 成， 辅连接线与主连接线的一部分并联连接， 通过辅连接线调节连接线的电 阻值， 降低连接线间的电阻差异， 减轻 RC delay现象。
如图 1所示， 阵列基板上的连接线的扇形走线区域可以分为第一区域和 第二区域， 在第一区域中走线排布比较密集， 而在第二区域中走线排布比较 宽松。 图 1中将第一和第二区域并排进行比较， 但并非表示这两个区域在阵 列基板上的位置是彼此并列的。 本发明的一些实施例中将辅连接线设置在第 二区域中， 因为如果将辅连接线设置在第一区域处， 则由于第一区域走线间 的横向距离不超过 Ι.Ομιη, 势必会使主连接线和辅连接线互相产生影响， 而 且曝光机的精度比较难以满足构图工艺的要求； 如果将辅连接线设置在第二 区域处， 由于第二区域走线间的横向距离大于 5μιη, 因此不会使走线间互相 影响。
本发明的实施例中， 主连接线和辅连接线位于不同层， 且主连接线与辅 连接线之间隔有绝缘层。 例如， 主连接线和辅连接线可以分别由栅金属层和 源漏金属层形成， 并且主连接线和辅连接线可以通过中间绝缘层中过孔处的 透明导电层 105进行连接。 由于辅连接线是与主连接线并联， 那么对于一个 连接线来说可以有至少两个连接处。 如图 2、 10、 11、 12的示例所示， 设置 过孔 103的一个地方例如是在每个像素的 ESD (静电保护）处， 因为该处的 空间比较大； 设置过孔 103的另一个地方是在走线由斜向转变为垂直走向的 转折处， 这里的空间也比较大。 如果空间比较小， 则可以将连接线设计为蛇 形走线， 可如图 10的示例所示。
由图 11可以看出，从上往下连接栅扫描线的辅连接线越来越短， 即主连 接线越长的时候， 并联的辅连接线越长， 连接线电阻减少的越多； 主连接线 越短的时候， 并联的辅连接线越短， 连接线电阻减少的越少， 这样可以有效 调节连接线间的电阻差异， 达到连接线电阻均衡的作用。
进一步地， 现有的一些液晶显示装置中， 比如数码相机， 驱动集成电路 一般设计在长方形屏幕的侧边（左侧或右侧） ， 这样对于连接驱动集成电路 与每一列数据线的连接线来说， 连接线的宽度相同， 长度不同， 因此造成了 不同连接线电阻的差异比较大， 容易产生 RC delay, 导致数据驱动信号的上 升沿和下降沿都有一定的延时。对于此种情况，本发明实施例的阵列基板中， 连接所述驱动集成电路和阵列基板上成列排列的数据线的连接线也可以由主 连接线和与所述主连接线对应的辅连接线组成， 所述辅连接线与所述主连接 线的一部分并联连接，从而可以减小连接线电阻的差异，减轻 RC delay现象。
进一步地， 在现有的一些阵列基板中， 为了减少连接线的间距， 节省连 接线的占用空间， 可以将相邻的连接线设计在不同层。 对于此种情况， 本发 明的另一些实施例中， 可以将相邻的主连接线设计在不同层， 如图 9所示， 在设置连接线连接驱动集成电路和栅扫描线时， 偶数列主连接线 201可以采 用源漏金属层制成， 与偶数列主连接线 201对应的辅连接线 202可以采用栅 金属层制成， 而奇数列主连接线 101可以采用栅金属层制成， 与奇数列主连 接线 101对应的辅连接线 102可以采用源漏金属层制成； 或者， 奇数列主连 接线可以采用源漏金属层制成， 与奇数列主连接线对应的辅连接线可以采用 栅金属层制成， 偶数列主连接线可以采用栅金属层制成， 与偶数列主连接线 对应的辅连接线可以采用源漏金属层制成。
进一步地， 例如， 在连接线连接驱动集成电路和数据线时， 偶数列主连 接线可以采用源漏金属层制成， 与偶数列主连接线对应的辅连接线可以采用 栅金属层制成， 奇数列主连接线可以采用栅金属层制成， 与奇数列主连接线 对应的辅连接线可以采用源漏金属层制成； 或者奇数列主连接线可以采用源 漏金属层制成， 与奇数列主连接线对应的辅连接线可以采用栅金属层制成， 偶数列主连接线可以采用栅金属层制成， 与偶数列主连接线对应的辅连接线 可以采用源漏金属层制成。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。 该阵 列基板的结构以及工作原理同上述实施例， 在此不再赘述。 另外， 显示装置 其他部分的结构可以采用已知或将来开发出来的技术， 对此本文不再详细描 述。
该显示装置可以为液晶面板、 电子纸、 OLED (有机发光二极管）面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等具有任何显示功能的 产品或部件。
本发明的实施例还提供了一种上述阵列基板的制作方法， 所述阵列基板 包括驱动集成电路、 布置在像素区域的多条金属走线， 本发明实施例的制作 方法可以采用例如用于现有阵列基板的制作工艺， 所述方法包括如下步骤。
通过构图工艺形成分别连接所述驱动集成电路与每一金属走线的多条连 接线的图形， 所述连接线的图形包括主连接线的图形和与所述主连接线对应 的辅连接线的图形， 所述辅连接线与所述主连接线的一部分并联连接。
需要说明的是， 在本公开中所提及的构图工艺例如是包括涂胶、 曝光、 显影、 刻蚀、 光刻胶剥离等步骤的光刻工艺。
在驱动集成电路设置在阵列基板的下侧时， 连接线连接驱动集成电路和 阵列基板上成行排列的栅扫描线时， 可以采用栅金属层制成主连接线， 在主 连接线对应的位置， 采用源漏金属层制成与主连接线重叠的辅连接线， 主连 接线和辅连接线之间为栅绝缘层， 主连接线和辅连接线通过栅绝缘层中的过 孔中的透明导电层连接； 在驱动集成电路设置在阵列基板的侧边时， 连接线 连接驱动集成电路和阵列基板上成列排列的数据线时， 可以采用源漏金属层 制成主连接线， 在主连接线对应的位置， 采用栅金属层制成与主连接线重叠 的辅连接线， 主连接线和辅连接线之间为栅绝缘层， 主连接线和辅连接线通 过栅绝缘层中的过孔中的透明导电层连接。
下面以应用于 TN面板的阵列基板为例， 结合图 3-图 8对本发明一个实 施例的阵列基板的制作方法进行详细介绍。 本实施例中， 连接线连接驱动集 成电路和栅扫描线。 本实施例的制作方法包括以下步骤 Sl-S6。
步骤 S1: 如图 3所示， 提供一透明基板 1 , 该基板 1可以为玻璃基板或 石英基板。 例如， 在基板 1上可以蒸镀或沉积一层栅金属层 2, 然后， 通过 构图工艺经掩膜、 曝光、 刻蚀和光刻胶去除等工艺步骤形成栅金属层 2的图 形，栅金属层 2的图形包括栅扫描线和主连接线；栅金属层可以采用铬（ Cr )、 相 （Mo ) 、 铝（A1 ) 、 铜 （Cu ) 、 钨（W ) 、 钕（Nd )及其任意的合金。
步骤 S2: 如图 4所示， 在经过步骤 S1的基板上形成栅绝缘层 3, 例如 可以以蒸镀或沉积的方式形成栅绝缘层 3。
步骤 S3: 如图 5所示， 在经过步骤 S2的基板上蒸镀或沉积一层半导体 层 4, 然后通过构图工艺经掩膜、 曝光、 刻蚀和光刻胶去除等工艺步骤形成 半导体层 4的图形。
步骤 S4: 如图 6所示， 在经过步骤 S3的基板上蒸镀或沉积源漏金属层 5, 然后， 通过构图工艺经掩膜、 曝光、 刻蚀和光刻胶去除等工艺步骤形成源 漏金属层 5的图形， 源漏金属层 5的图形包括源电极、 漏电极、 数据线和辅 连接线； 源漏金属层可以采用铬（Cr ) 、 相 （Mo ) 、 铝（A1 ) 、 铜（ Cu ) 、 钨（W ) 、 钕（Nd )及其任意的合金。
步骤 S5: 如图 7所述， 在经过步骤 S4的基板上蒸镀或沉积钝化层 6, 并经掩膜、 曝光、 刻蚀和光刻胶去除等构图工艺步骤形成过孔图形， 该过孔 贯穿钝化层 6和栅绝缘层 3。
步骤 S6: 如图 8所示， 在经过步骤 S5的基板上蒸镀或沉积一层透明导 电层 7, 透明导电层 7可以采用 ITO或 IZO。 然后， 通过掩膜、 曝光、 刻蚀 和光刻胶去除等构图工艺步骤形成透明导电层 7的图形， 透明导电层 7的图 形包括像素电极和连接结构， 连接结构通过过孔导通主连接线 101和辅连接 线 102。
上述实施例仅以 TN面板为例，说明了本实施例的技术方案。 进一步地， 本发明的阵列基板及其制作方法还可以应用于 ADS、 FFS等面板中。
进一步地， 在现有的一些阵列基板中， 为了减少连接线的间距， 节省连 接线的占用空间， 可以将相邻的连接线设计在不同层。 对于此种情况， 本发 明的实施例中， 可以将相邻的主连接线设计在不同层， 如图 9所示， 在连接 线连接驱动集成电路和栅扫描线时， 可以采用源漏金属层制成偶数列主连接 线 201 , 可以采用栅金属层制成与偶数列主连接线 201对应的辅连接线 202, 可以采用栅金属层制成奇数列主连接线 101 , 可以采用源漏金属层制成与奇 数列主连接线 101对应的辅连接线 102; 或者， 可以采用源漏金属层制成奇 数列主连接线， 可以采用栅金属层制成与奇数列主连接线对应的辅连接线， 可以采用栅金属层制成偶数列主连接线， 可以采用源漏金属层制成与偶数列 主连接线对应的辅连接线。
进一步地， 在连接线连接驱动集成电路和数据线时， 可以采用源漏金属 层制成偶数列主连接线， 可以采用栅金属层制成与偶数列主连接线对应的辅 连接线， 可以采用栅金属层制成奇数列主连接线， 可以采用源漏金属层制成 与奇数列主连接线对应的辅连接线； 或者， 可以采用源漏金属层制成奇数列 主连接线， 可以采用栅金属层制成与奇数列主连接线对应的辅连接线， 可以 采用栅金属层制成偶数列主连接线， 可以采用源漏金属层制成与偶数列主连 接线对应的辅连接线。
上述实施例中， 主连接线和辅连接线的制作是与阵列基板电极的制作同 时完成，节省了阵列基板的制作步骤，但是本发明的技术方案并不局限于此， 其它通过专门的构图工艺来制作主连接线和辅连接线的技术方案同样在本发 明的保护范围之内。
本发明实施例的阵列基板的制作方法， 能够使得各条连接线之间的电阻 总值差异变小， 减轻 RC delay现象， 进而提高显示装置的显示效果。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种阵列基板， 包括驱动集成电路、布置在像素区域的多条金属走线 以及分别连接所述驱动集成电路与每一金属走线的多条连接线， 其中， 每一 连接线包括一主连接线和与所述主连接线对应的辅连接线， 所述辅连接线与 所述主连接线的一部分并联连接。
2. 根据权利要求 1所述的阵列基板， 其中， 所述主连接线与所述辅连接 线位于不同层， 且所述主连接线与所述辅连接线之间隔有绝缘层， 所述主连 接线与所述辅连接线通过所述绝缘层中的过孔相连接。
3. 根据权利要求 1或 2所述的阵列基板， 其中， 所述阵列基板的扇形走 线区包括有第一区域和第二区域,所述第一区域走线间的横向距离小于 Ιμιη, 所述第二区域走线间的横向距离大于 5μιη, 其中， 所述辅连接线位于所述第 二区域中。
4. 根据权利要求 3所述的阵列基板， 其中， 所述主连接线与对应辅连接 线连接的至少两个过孔中， 其中一个过孔设置在所述第二区域主连接线由斜 向转为垂直走向的转折处， 另一个过孔设置在像素的静电保护区域。
5. 根据权利要求 3所述的阵列基板， 其中， 在所述驱动集成电路设置在 阵列基板的下侧时， 所述连接线连接所述驱动集成电路和阵列基板上成行排 列的栅扫描线， 其中， 所述主连接线为采用栅金属层制成， 与其对应的辅连 接线为采用源漏金属层制成。
6. 根据权利要求 3所述的阵列基板， 其中， 在所述驱动集成电路设置在 阵列基板的侧边时， 所述连接线连接所述驱动集成电路和阵列基板上成列排 列的数据线， 其中， 所述主连接线为采用源漏金属层制成， 与其对应的辅连 接线为采用栅金属层制成。
7. —种显示装置， 包括如权利要求 1-6中任一项所述的阵列基板。
8. 一种阵列基板的制作方法， 所述阵列基板包括驱动集成电路、 布置在 像素区域的多条金属走线， 所述方法包括：
形成分别连接所述驱动集成电路与每一金属走线的多条连接线的图形， 所述连接线的图形包括主连接线的图形和与所述主连接线对应的辅连接线的 图形， 所述辅连接线与所述主连接线的一部分并联连接。
9.根据权利要求 8 所述的阵列基板的制作方法，其中，在所述驱动集成 电路设置在阵列基板的下侧， 所述连接线连接所述驱动集成电路和阵列基板 上成行排列的栅扫描线时， 所述方法包括：
利用栅金属层形成栅扫描线和主连接线的图形；
形成栅绝缘层， 在所述栅绝缘层中形成过孔图形；
利用源漏金属层形成数据线和辅连接线的图形， 使得所述主连接线与所 述辅连接线通过所述过孔相连接。
10.根据权利要求 8 所述的阵列基板的制作方法， 其中， 在所述驱动集 成电路设置在阵列基板的侧边， 所述连接线连接所述驱动集成电路和阵列基 板上成列排列的数据线时， 所述方法包括：
利用栅金属层形成栅扫描线和辅连接线的图形；
形成栅绝缘层， 在所述栅绝缘层中形成过孔图形；
利用源漏金属层形成数据线和主连接线的图形， 使得所述主连接线与所 述辅连接线通过所述过孔相连接。
PCT/CN2013/077408 2013-04-26 2013-06-18 阵列基板及其制作方法、显示装置 WO2014172972A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310149512.XA CN103219319B (zh) 2013-04-26 2013-04-26 阵列基板及其制作方法、显示装置
CN201310149512.X 2013-04-26

Publications (1)

Publication Number Publication Date
WO2014172972A1 true WO2014172972A1 (zh) 2014-10-30

Family

ID=48816984

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/077408 WO2014172972A1 (zh) 2013-04-26 2013-06-18 阵列基板及其制作方法、显示装置

Country Status (2)

Country Link
CN (1) CN103219319B (zh)
WO (1) WO2014172972A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714376B (zh) * 2019-12-04 2020-12-21 友達光電股份有限公司 顯示裝置

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150017192A (ko) * 2013-08-06 2015-02-16 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN103500744B (zh) * 2013-08-30 2016-12-28 京东方科技集团股份有限公司 一种阵列基板、其制备方法及显示装置
US9741745B2 (en) 2013-08-30 2017-08-22 Boe Technology Group Co., Ltd. Array substrate, method for manufacturing the same and display device
CN105448935B (zh) 2016-01-04 2018-11-30 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN106252358B (zh) * 2016-08-25 2019-05-03 武汉华星光电技术有限公司 具有静电保护功能的显示面板
CN106448587B (zh) * 2016-10-08 2019-09-20 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN107910333A (zh) * 2017-10-27 2018-04-13 武汉华星光电半导体显示技术有限公司 阵列基板及显示装置
CN108535928A (zh) * 2018-04-13 2018-09-14 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板和显示装置
CN111583844A (zh) * 2019-02-18 2020-08-25 上海和辉光电有限公司 一种显示面板及其驱动方法、显示装置
CN110993617A (zh) * 2019-12-03 2020-04-10 武汉华星光电技术有限公司 阵列基板、显示面板及显示装置
CN111681554B (zh) * 2020-06-30 2022-03-25 上海中航光电子有限公司 显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1832184A (zh) * 2006-02-24 2006-09-13 广辉电子股份有限公司 有源元件阵列基板
CN1945838A (zh) * 2006-10-27 2007-04-11 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN102237355A (zh) * 2010-04-30 2011-11-09 瀚宇彩晶股份有限公司 薄膜晶体管阵列基板和液晶面板
CN102645808A (zh) * 2012-04-20 2012-08-22 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3949897B2 (ja) * 2001-01-29 2007-07-25 株式会社日立製作所 液晶表示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1832184A (zh) * 2006-02-24 2006-09-13 广辉电子股份有限公司 有源元件阵列基板
CN1945838A (zh) * 2006-10-27 2007-04-11 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN102237355A (zh) * 2010-04-30 2011-11-09 瀚宇彩晶股份有限公司 薄膜晶体管阵列基板和液晶面板
CN102645808A (zh) * 2012-04-20 2012-08-22 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714376B (zh) * 2019-12-04 2020-12-21 友達光電股份有限公司 顯示裝置

Also Published As

Publication number Publication date
CN103219319B (zh) 2015-11-25
CN103219319A (zh) 2013-07-24

Similar Documents

Publication Publication Date Title
WO2014172972A1 (zh) 阵列基板及其制作方法、显示装置
US9927911B2 (en) Touch display panel and fabrication method thereof, and touch display apparatus
KR102089074B1 (ko) 표시패널용 어레이 기판 및 그 제조방법
US8772780B2 (en) Array substrate structure of display panel and method of making the same
US9933902B2 (en) Touch panel and touch screen display device
WO2016078272A1 (zh) 一种基板及其制造方法、显示装置
WO2016119373A1 (zh) 阵列基板、触控面板及阵列基板的制作方法
US20150318305A1 (en) An array substrate and a method for manufacturing the same
CN214098387U (zh) 显示面板及显示装置
WO2018040578A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
US9664969B2 (en) TFT-LCD display panel based on HSD structure and manufacturing method
US20190131316A1 (en) Via-hole Connection Structure And Method Of Manufacturing The Same, And Array Substrate And Method Of Manufacturing The Same
JP2014149429A (ja) 液晶表示装置および液晶表示装置の製造方法
WO2020015070A1 (zh) 阵列基板
US20210200013A1 (en) Display panel and display apparatus having a plurality of first wirings and a plurality of second wirings
WO2016021318A1 (ja) アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法
US10879277B2 (en) Display panel and manufacturing method thereof and display device
US8270178B2 (en) Active device array substrate
WO2014176876A1 (zh) 显示面板及其制作方法、液晶显示器
US9869917B2 (en) Active matrix substrate and method for manufacturing the same
CN114690921A (zh) 显示面板、显示装置及制作显示面板的方法
WO2015096369A1 (zh) 阵列基板及其制造方法、显示装置
CN104835827B (zh) 显示面板
US10042220B2 (en) Liquid-crystal display device
WO2015051642A1 (zh) 阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13883087

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 11-01-2016)

122 Ep: pct application non-entry in european phase

Ref document number: 13883087

Country of ref document: EP

Kind code of ref document: A1