WO2014169601A1 - 低温多晶硅的制作方法、低温多晶硅薄膜和薄膜晶体管 - Google Patents

低温多晶硅的制作方法、低温多晶硅薄膜和薄膜晶体管 Download PDF

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WO2014169601A1
WO2014169601A1 PCT/CN2013/085683 CN2013085683W WO2014169601A1 WO 2014169601 A1 WO2014169601 A1 WO 2014169601A1 CN 2013085683 W CN2013085683 W CN 2013085683W WO 2014169601 A1 WO2014169601 A1 WO 2014169601A1
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laser
amorphous silicon
temperature polysilicon
layer
silicon layer
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田雪雁
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H10K71/421—Thermal treatment, e.g. annealing in the presence of a solvent vapour using coherent electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2922—Materials being non-crystalline insulating materials, e.g. glass or polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H10P14/3816—Pulsed laser beam
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Definitions

  • Embodiments of the present invention relate to a method of fabricating low temperature polysilicon, a low temperature polysilicon film based thereon, and a thin film transistor having the low temperature polysilicon film. Background technique
  • the active matrix organic light-emitting diode panel has the advantages of high image quality, short response time of moving image, low power consumption, wide viewing angle and ultra-light and ultra-thin, making it the preferred choice for future display technology.
  • AMOLED's backplane technology the fabrication of polysilicon layers includes excimer laser annealing (ELA), solid phase crystallization (SPC) and metal induced crystallization (MIC).
  • ELA excimer laser annealing
  • SPC solid phase crystallization
  • MIC metal induced crystallization
  • a method for realizing the production of an active layer of a transistor in a backplane is an excimer laser annealing (ELA) method.
  • the excimer laser annealing (ELA) process is a relatively complex annealing process.
  • ELA excimer laser annealing
  • the control of grain size and grain uniformity has been a hot topic in the field of technology. Because the number and distribution of polycrystalline silicon grains covered by the channel region of the low-temperature polysilicon thin film transistor, that is, the uniformity problem, will directly affect the electrical properties of the low-temperature polysilicon thin film transistor, such as mobility, mobility, and threshold voltage uniformity. Wait.
  • the thickness distribution of the amorphous silicon film is usually uneven, and the amorphous silicon film is usually thick in the middle thin portion or thin in the middle thick portion. Even amorphous silicon films with better uniformity may have different distributions of film thicknesses.
  • Conventional embodiments of the present invention provide a method for fabricating low-temperature polysilicon, comprising: forming a buffer layer on a substrate; forming an amorphous silicon layer on the buffer layer; performing heat treatment after forming the amorphous silicon layer; And according to the thickness distribution of the amorphous silicon layer, it is divided into a plurality of regions and subjected to laser annealing treatment to form a polysilicon layer.
  • the thickness distribution of the amorphous silicon layer it is divided into at least one film layer thickness region and at least one film layer thin region for laser annealing treatment; wherein, when performing laser annealing treatment, the film layer thickness is The laser energy density used in the zone is greater than the laser energy density used in the thin zone of the film layer Degree.
  • the amorphous silicon layer is divided into three regions, the thinner middle region is the second region, and the thicker two portions are the first region and the third region, respectively; the laser annealing condition in the first region
  • the laser pulse frequency is about 200-400 Hz, the overlap rate is about 92%-98%, the laser energy density is about 240-250 mJ/cm 2
  • the laser annealing condition in the second zone is: the laser pulse frequency is about 200-400Hz, the overlap ratio is about 92%-98%, the laser energy density is about 230-240 mJ/cm 2
  • the laser annealing condition in the third zone is: the laser pulse frequency is about 200-400HZ, and the overlap ratio is about 92%-98%, the laser energy density is about 240-250 mJ/cm 2 .
  • the amorphous silicon layer is divided into three regions, the thicker central region is the second region, and the thinner two sides are the first region and the third region, respectively; laser annealing in the first region
  • the conditions are: laser pulse frequency is about 200-400HZ, overlap rate is about 92%-98%, laser energy density is about 220-250 mJ/cm 2 ; laser annealing condition in the second zone is: laser pulse frequency is about 200-400 Hz, the overlap ratio is about 92%-98%, the laser energy density is about 260-280 mJ/cm 2 ; the laser annealing condition in the third zone is: the laser pulse frequency is about 200-400 Hz, the overlap ratio is About 92%-98%, the laser energy density is about 250-270 mJ/cm 2 .
  • the buffer layer comprises a silicon oxide film layer of about 50-150 nm thick deposited on the substrate of the substrate and a silicon oxide film layer of about 100-350 nm thick deposited later.
  • an amorphous silicon layer of about 30-50 nm is deposited on the buffer layer.
  • the amorphous silicon layer is subjected to heat treatment for about 0.5 to 3 hours at a temperature of about 400 to 500 °C.
  • the amorphous silicon layer is subjected to laser annealing treatment using an excimer laser.
  • the excimer laser is ruthenium chloride or ruthenium fluoride or an argon fluoride excimer laser.
  • Embodiments of the present invention also provide a low temperature polysilicon film prepared based on the above method, comprising a buffer layer and a polysilicon layer sequentially formed on the same side of the substrate.
  • Embodiments of the present invention also provide a thin film transistor including the above low temperature polysilicon film.
  • FIG. 2 is a schematic structural view of a substrate of a village in the present invention.
  • FIG. 3 is a thickness distribution diagram of an amorphous silicon layer according to Embodiment 1 of the present invention.
  • FIG. 4 is a comparative diagram of the polycrystalline silicon grain distribution prepared by the method of the first embodiment and the conventional method;
  • FIG. 5 is a thickness distribution diagram of the amorphous silicon layer according to the second embodiment of the present invention.
  • Figure 6 is a comparison of the polycrystalline silicon grain distribution prepared by the method of the second embodiment and the conventional method.
  • an embodiment of the present invention provides a method for fabricating a low temperature (generally referred to as a temperature below 600 ° C) polysilicon (LTPS), comprising: forming (eg, depositing) a buffer layer on a substrate of a substrate. 20; forming, for example, depositing an amorphous silicon layer 30 on the buffer layer 20; performing heat treatment after forming the amorphous silicon layer; and dividing the amorphous silicon layer 30 into a plurality of regions for laser annealing treatment according to the thickness distribution. Annealing is performed on different regions using lasers of different energies to convert the amorphous silicon layer into a polysilicon layer.
  • LTPS low temperature polysilicon
  • the substrate substrate 10 may be pre-cleaned first.
  • the pre-cleaning can be carried out in various ways, for example, by washing with a cleaning liquid or by using a wind knife.
  • the buffer layer 20 can function, for example, to prevent metal ions in the substrate substrate 10 from diffusing to the prepared LTPS active region, reducing defect centers and reducing leakage current generation; and a suitable buffer layer can improve the back surface of the polysilicon. Quality, prevents leakage current at the back interface of polysilicon; proper buffer layer thickness reduces heat transfer, slows the cooling rate of silicon heated by laser, and helps to form larger crystalline grains.
  • the heat treatment can dehydrogenate the amorphous silicon layer 30 to prevent laser annealing of the amorphous silicon layer 30. Hydrogen explosion occurs.
  • the buffer layer 20 may be deposited on the substrate 10 by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the buffer layer 20 includes a double buffer layer in which a silicon nitride (SiN x ) thin film layer 21 of about 50 to 150 nm thick and a silicon oxide (SiO 2 ) thin film layer 22 of about 100 to 350 nm are sequentially formed on the substrate substrate 10.
  • the function of the double buffer layer is as follows: silicon oxide is more suitable for forming polycrystalline silicon than silicon nitride. Silicon nitride has better effect on blocking pollutants from the substrate of the village, so the amorphous silicon layer is selected.
  • the upper layer of the buffer layer of the contact surface is silicon oxide, and the lower layer of the surface in contact with the substrate substrate is silicon nitride.
  • the buffer layer 20 can also be a single-layer SiO 2 film layer. The effect of using a double buffer layer is better than the effect of using a single layer of Si0 2 buffer layer.
  • An amorphous silicon layer 30 of about 30 to 50 nm is formed on the buffer layer 20 by a deposition method. After the step of depositing the amorphous silicon layer on the buffer layer is completed, the amorphous silicon layer is subjected to heat treatment for about 0.5 to 3 hours at a temperature of about 400 to 500 °C.
  • the amorphous silicon layer is subjected to laser annealing treatment using an excimer laser, for example, laser annealing treatment using an excimer laser such as xenon chloride (XeCl), cesium fluoride or argon fluoride.
  • an excimer laser such as xenon chloride (XeCl), cesium fluoride or argon fluoride.
  • the thickness distribution of the amorphous silicon layer 30 at least one film thickness region and at least one film thin region are divided into laser annealing treatment.
  • the thick layer of the film means that the thickness of the amorphous silicon layer in this region is relatively thick, and the thin portion of the thin film refers to the relatively thin thickness of the amorphous silicon layer in this region. It is generally divided according to the thickness distribution of the entire amorphous silicon layer.
  • the laser energy density employed in the film thickness region is greater than the laser energy density employed in the thin film region.
  • the method for fabricating low-temperature polysilicon considers the inconsistency of laser energy absorption by amorphous silicon of different thicknesses, and divides the amorphous silicon layer into a plurality of regions for different laser annealing treatment, and can be used for each region.
  • a suitable laser annealing treatment process condition is selected to obtain a large-sized and uniformly distributed polycrystalline silicon film over the entire substrate range.
  • the substrate substrate 10 used in one embodiment of the present invention is covered with an organic light-emitting diode panel 11 over the entire substrate substrate 10.
  • an organic light-emitting diode panel 11 over the entire substrate substrate 10.
  • Amorphous silicon layer on the substrate of the village When the thickness distribution is "the middle is thin and the two sides are thick", as shown in FIG. 3, the amorphous silicon layer can be divided into three regions, and the thinner region (for example, the thickness is less than 400 angstroms) is the second region. B1, the two sides of the thicker (for example, the thickness is greater than or equal to 400 angstroms) are the first area A1 and the third area C1, respectively, and the method for performing laser annealing treatment includes:
  • the laser annealing conditions in the first zone A1 are: laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, laser overlap rate is about 92%-98%, and laser energy density is about 240-250 mJ/cm 2
  • the laser annealing conditions in the second zone B1 are: laser pulse frequency is about 200-400HZ, preferably about 300 Hz, laser overlap rate is about 92%-98%, laser energy density is about 230-240 mJ/cm 2
  • the laser annealing conditions in the third zone C1 are: laser pulse frequency is about 200-400HZ, preferably about 300 Hz, laser overlap rate is about 92%-98%, laser energy density is about 240-250 mJ/cm 2 . Thicker and thinner are opposite. Therefore, the value of dividing the thicker and thinner regions is not limited to 400 angstroms, and may be other values.
  • FIG. 4 is a schematic comparison diagram of a polycrystalline silicon grain size distribution F1 prepared by a method for preparing a low-temperature polysilicon produced by the method of the present invention, which is prepared by a conventional method of preparing a polycrystalline silicon grain size F1.
  • the polycrystalline silicon crystal grains prepared by the method of the embodiment are substantially large crystal grains of uniform size, and the grain size of the ordinary method is different, the crystal grains of the central region are larger, and the crystal grains of the both sides are larger. The grain is smaller.
  • the difference between this embodiment and the first embodiment is that the distribution of the three regions of the amorphous silicon layer on the substrate of the substrate is different, and the distribution of the embodiment is "the center is thick and the two sides are thin". As shown in FIG. 5, the middle portion of the thinner (for example, the thickness is less than 400 angstroms) is the second zone B2, and the two sides of the thicker (for example, the thickness is greater than or equal to 400 angstroms) are the first zone A2 and the third zone C2, respectively.
  • the laser annealing treatment method includes:
  • the laser annealing conditions in the first zone A2 are: the laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, the laser overlap ratio is about 92%-98%, and the laser energy density is about 220-250 mJ/cm 2 .
  • the laser annealing conditions in the second zone B2 are: the laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, the laser overlap rate is about 92%-98%, and the laser energy density is about 260-280 mJ/cm. 2 ;
  • the laser annealing conditions in the third zone C2 are: laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, laser overlap rate is about 92%-98%, laser energy density is about 250-270 mJ/ Cm2.
  • polycrystalline silicon grain size distribution F2 prepared by the method for preparing a polycrystalline silicon low-temperature polysilicon produced by the method of the present invention, which is prepared by a conventional method for preparing a polycrystalline silicon grain size F2; Indicate the comparison chart.
  • the polycrystalline silicon crystal grains prepared by the method of the embodiment are substantially large crystal grains of uniform size, and the grain size of the ordinary method is different, the crystal grains of the central region are larger, and the crystal grains of the both sides are larger. The grain is smaller.
  • the embodiment of the present invention also provides a low temperature polycrystalline silicon film prepared based on the above low temperature polysilicon fabrication method, comprising a buffer layer 20 and an amorphous silicon layer 30 which are sequentially formed on the same side of the substrate substrate 10.
  • Embodiments of the present invention also provide a thin film transistor including the above low temperature polysilicon film.
  • the thin film transistor includes a gate electrode, a gate insulating layer, an active layer using the above low temperature polysilicon film, a source and a drain, and the thin film transistor may be of various types such as a top gate type, a bottom gate type, or the like.
  • the amorphous silicon layer is divided into a plurality of regions for laser annealing treatment, so that polycrystalline silicon in each region can obtain a large crystal grain size, and the polycrystalline silicon crystal grains in the entire substrate range The size is evenly distributed. Based on the low-temperature polysilicon film and the thin film transistor of the method, the polycrystalline silicon is a uniform large crystal grain.

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Abstract

一种低温多晶硅的制作方法，包括：在衬底基板（10）上沉积缓冲层（20）；在缓冲层上沉积非晶硅层（30）；在形成非晶硅层后进行热处理；以及根据非晶硅层的厚度分布情况分为多个区进行激光退火处理，形成多晶硅层。还提供了基于低温多晶硅的制作方法所制备的低温多晶硅薄膜以及具有该薄膜的薄膜晶体管。通过低温多晶硅的制作方法，多晶硅的每个区域内的多晶硅都能得到大的晶粒尺寸，并且整个基板范围内的多晶硅晶粒尺寸的分布均匀。

Description

低温多晶硅的制作方法、 低温多晶硅薄膜和薄膜晶体管 技术领域
本发明的实施例涉及一种低温多晶硅的制作方法、 基于该方法的低温多 晶硅薄膜以及具有该低温多晶硅薄膜的薄膜晶体管。 背景技术
有源矩阵有机发光二极体面板（AMOLED )凭据高画质、 移动图像响应 时间短、 低功耗、 宽视角及超轻超薄等优点， 成为未来显示技术的优先选择。 在 AMOLED 的背板技术中， 制作多晶硅层的技术包括准分子激光退火 ( ELA ), 固相晶化（SPC )和金属诱导晶化（MIC )等多种制作方法。 目前， 能实现背板中晶体管的有源层产量化的方法是准分子激光退火（ELA )方法。
准分子激光退火（ELA )工艺是一种相对比较复杂的退火过程。 在多晶 硅薄膜中， 晶粒尺寸及晶粒均匀性的控制一直是该技术领域研究的热点。 因 为低温多晶硅薄膜晶体管的沟道区所覆盖的多晶硅晶粒数量及分布情况， 即 均匀性问题， 将直接影响到低温多晶硅薄膜晶体管的电学性能， 例如迁移率 大小、 迁移率及阈值电压的均匀性等。
非晶硅薄膜的厚度分布通常是不均勾的， 非晶硅薄膜通常为中部薄边缘 部厚或者为中部厚边缘部薄的情况。 即使均匀性比较好的非晶硅薄膜， 也会 存在薄膜厚度不一的分布情况。
因此， 如何控制非晶硅转变为理想的多晶硅， 即使多晶硅薄膜晶粒尺寸 较大并且分布均匀， 一直是难以攻克的技术难题。 发明内容
常规本发明的实施例提供了一种低温多晶硅的制作方法， 其包括： 在村 底基板上形成緩沖层； 在所述緩沖层上形成非晶硅层； 在形成非晶硅层后进 行热处理； 以及根据所述非晶硅层的厚度分布情况将其分成多个区进行激光 退火处理， 形成多晶硅层。
进一步地， 例如， 根据所述非晶硅层的厚度分布情况将其分成至少一个 膜层厚区和至少一个膜层薄区进行激光退火处理； 其中， 进行激光退火处理 时， 所述膜层厚区采用的激光能量密度大于所述膜层薄区采用的激光能量密 度。
进一步地， 例如， 将所述非晶硅层分成三个区， 较薄的中部区域为第二 区， 较厚的两边部分别为第一区和第三区； 在第一区的激光退火条件为： 激 光脉沖频率为约 200-400 Hz , 重叠率为约 92%-98% , 激光能量密度为约 240-250 mJ/cm2;在第二区的激光退火条件为： 激光脉沖频率为约 200-400Hz, 重叠率为约 92%-98% , 激光能量密度为约 230-240 mJ/cm2; 在第三区的激光 退火条件为： 激光脉沖频率为约 200-400HZ, 重叠率为约 92%-98%, 激光能 量密度为约 240-250 mJ/cm2。
进一步地， 例如， 将所述非晶硅层分成三个区， 较厚的中部区域为第二 区， 较薄的两边部区分别为第一区和第三区； 在第一区的激光退火条件为： 激光脉沖频率为约 200-400HZ , 重叠率为约 92%-98% , 激光能量密度为约 220-250 mJ/cm2;在第二区的激光退火条件为： 激光脉沖频率为约 200-400Hz, 重叠率为约 92%-98% , 激光能量密度为约 260-280 mJ/cm2; 在第三区的激光 退火条件为： 激光脉沖频率为约 200-400 Hz, 重叠率为约 92%-98%, 激光能 量密度为约 250-270 mJ/cm2。
进一步地， 例如， 所述緩沖层包括在所述村底基板上依次沉积的约 50-150nm厚的氧化硅薄膜层和之后沉积的约 100-350nm厚的二氧化硅薄膜 层。
进一步地， 例如， 所述緩沖层上沉积约 30-50nm非晶硅层。
进一步地， 例如， 在所述緩沖层上沉积非晶硅层后， 在约 400-500°C的温 度下， 对所述非晶硅层进行约 0.5-3小时的热处理。
进一步地， 例如， 对上述非晶硅层采用准分子激光器进行激光退火处理。 进一步地， 例如， 所述准分子激光器为氯化氙或氟化氪或氟化氩准分子 激光器。
本发明的实施例还提供一种基于上述方法制备的低温多晶硅薄膜， 其包 括在所述村底基板的同一侧依次形成的緩沖层和多晶硅层。
本发明的实施例还提供一种薄膜晶体管， 其包括上述的低温多晶硅薄膜。 附图说明
以下将结合附图对本发明的实施例进行更详细的说明， 以使本领域普通 技术人员更加清楚地理解本发明， 其中： 图 1是本发明低温多晶硅制作工艺原理图；
图 2是本发明中村底基板的结构示意图；
图 3是本发明实施例一的非晶硅层厚度分布图；
图 4是实施例一的方法与常规方法所制备的多晶硅晶粒分布对比图； 图 5是本发明实施例二的非晶硅层厚度分布图；
图 6是实施例二的方法与常规方法所制备的多晶硅晶粒分布对比图。
附图标记： 10、 村底基板； 11、 液晶面板； 20、 緩沖层； 21、 SiNx薄膜 层； 22、 Si02薄膜层; 30、 非晶硅层。 具体实施方式
为了使本发明的实施例的目的、 技术方案和优点更加清楚， 下面将结合 本发明实施例的附图对本发明的实施例的技术方案进行清楚、 完整的描述。 显然， 所描述的实施例仅是本发明的一部分示例性实施例， 而不是全部的实 施例。 基于所描述的本发明的示例性实施例， 本领域普通技术人员在无需创 造性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
下面将结合附图和实施例， 对本发明的具体实施方式作进一步详细描述。 如图 1所示，本发明的一个实施例提供了一种低温（一般指 600°C以下的 温度）多晶硅（LTPS )的制作方法， 其包括： 在村底基板上形成（例如沉积） 緩沖层 20; 在緩沖层 20上形成（例如沉积）非晶硅层 30; 在形成非晶硅层 后进行热处理； 以及根据非晶硅层 30的厚度分布情况将其分成多个区进行激 光退火处理。 对不同的区采用不同能量的激光进行退火处理， 把非晶硅层转 变成多晶硅层。
如果村底基板 10的洁净度不满足要求， 也可以首先对村底基板 10进行 预清洗。 该预清洗可以采用多种方式， 例如可以使用清洗液进行清洗或者使 用风刀吹净等。
緩沖层 20可以起到如下作用， 例如， 防止村底基板 10中的金属离子扩 散至所制备的 LTPS有源区， 降低缺陷中心和减少漏电流的产生；合适的緩沖 层可以改善多晶硅背面界面的质量， 防止在多晶硅背面界面处产生漏电流； 适当的緩沖层厚度降低了热传导， 减緩被激光加热的硅的冷却速率， 有助于 形成较大的结晶晶粒。
热处理可以使非晶硅层 30脱氢， 防止在对非晶硅层 30进行激光退火时 发生氢爆。
例如， 可以采用等离子体增强化学气相沉积（PECVD )法在村底基板 10 上沉积緩沖层 20。
緩沖层 20包括在村底基板 10上依次形成约 50-150nm厚的氮化硅（SiNx ) 薄膜层 21和约 100-350nm厚的二氧化硅（ Si02 )薄膜层 22的双层緩沖层。 设置该双层緩沖层的作用是： 氧化硅较氮化硅更助于形成晶相较好的多晶硅， 氮化硅对阻挡来自村底基板的污染物效果更佳， 所以选择与非晶硅层接触的 表面的緩沖层上层为氧化硅， 与村底基板接触的表面的下层为氮化硅。 需要 指出的是： 緩沖层 20还可以为单层 Si02薄膜层。采用双层緩沖层的效果优于 采用单层 Si02緩沖层的效果。
在緩沖层 20上采用沉积的方法形成约 30-50nm非晶硅层 30。 在完成緩 沖层上沉积非晶硅层的步骤后， 在约 400-500 °C的温度下， 对非晶硅层进行约 0.5-3小时的热处理。
最后， 对非晶硅层采用准分子激光器进行激光退火处理， 例如采用氯化 氙（XeCl )、 氟化氪、 氟化氩等准分子激光器进行激光退火处理。
根据非晶硅层 30的厚度分布情况分成至少一个膜层厚区和至少一个膜层 薄区进行激光退火处理。 膜层厚区指此区域的非晶硅层的厚度相对较厚， 膜 层薄区指此区域的非晶硅层的厚度相对较薄。 一般根据整个非晶硅层的厚度 分布情况进行划分。
在进行激光退火处理时， 在所述膜层厚区采用的激光能量密度大于在所 述膜层薄区采用的激光能量密度。
本发明实施例的低温多晶硅的制作方法， 考虑了不同厚度的非晶硅对激 光能量吸收的不一致性， 来将非晶硅层划分为多个区进行不同的激光退火处 理， 可针对每个区选择合适的激光退火处理工艺条件， 从而在整个基板范围 内， 得到大尺寸并且分布均匀的多晶硅薄膜。
如图 2所示， 对于本发明一个实施例所采用的村底基板 10, 在整个村底 基板 10上排布满了有机发光二极体面板 11。考虑到非晶硅薄膜的厚度分布的 不均匀性， 根据村底基板厚度分布的一般规律， 下面列举两个示例性的实施 例进行说明：
实施例一
本实施例是在上述技术方案的基础上实施的。 当村底基板上的非晶硅层 的厚度分布为 "中部薄、 两边部厚"的情况时， 如图 3 所示， 可将非晶硅层分 成三个区，较薄（例如，厚度小于 400埃）的中部区域为第二区 B1 ,较厚（例 如， 厚度大于等于 400埃） 的两边部区分别为第一区 A1和第三区 C1 , 对其 进行激光退火处理的方法包括：
在第一区 A1的激光退火条件为： 激光脉沖频率为约 200-400 Hz,优先采 用约 300 Hz, 激光重叠率为约 92%-98%, 激光能量密度为约 240-250 mJ/cm2; 在第二区 B1的激光退火条件为： 激光脉沖频率为约 200-400HZ, 优先采 用约 300 Hz, 激光重叠率为约 92%-98%, 激光能量密度为约 230-240 mJ/cm2; 在第三区 C1的激光退火条件为： 激光脉沖频率为约 200-400HZ, 优先采 用约 300 Hz, 激光重叠率为约 92%-98%, 激光能量密度为约 240-250 mJ/cm2。 较厚和较薄是相对的， 因此， 划分较厚较薄区的数值不限于 400埃， 也可以 是其它数值。
图 4为本实施例的低温多晶硅制作方法所制备的多晶硅晶粒尺寸分布 F1 与常规的普通没有分多个区域进行制备的方法所制备多晶硅晶粒尺寸分布 E1 的示意对比图。 本实施例的方法所制备的多晶硅晶粒基本上为大小均匀的大 晶粒， 而普通的方法所制备的晶粒尺寸大小不一， 中部区的晶粒较大， 而两 侧部区的晶粒较小。
实施例二
本实施例与实施例一的区别在于， 村底基板上的非晶硅层的三个区的分 布情况不同， 本实施例的分布为"中部厚、 两边部薄"。 如图 5所示， 较薄（例 如， 厚度小于 400埃） 的中部区域为第二区 B2, 较厚（例如， 厚度大于等于 400埃） 的两边部分分别为第一区 A2和第三区 C2, 该激光退火处理的方法 包括：
在第一区 A2的激光退火条件为： 激光脉沖频率为约 200-400 Hz,优先采 用约 300 Hz,激光重叠率为约 92%-98%, 激光能量密度为约 220-250 mJ/cm2; 在第二区 B2的激光退火条件为： 激光脉沖频率为约 200-400 Hz, 优先采 用约 300 Hz, 激光重叠率为约 92%-98%, 激光能量密度为约 260-280 mJ/cm2; 在第三区 C2的激光退火条件为： 激光脉沖频率为约 200-400 Hz,优先采 用约 300 Hz,激光重叠率为约 92%-98%,激光能量密度为约 250-270 mJ/cm2。
图 6为本实施例的低温多晶硅制作方法所制备的多晶硅晶粒尺寸分布 F2 与常规的普通没有分多个区域进行制备的方法所制备多晶硅晶粒尺寸分布 E2 示意对比图。 本实施例的方法所制备的多晶硅晶粒基本上为大小均匀的大晶 粒， 而普通的方法所制备的晶粒尺寸大小不一， 中部区的晶粒较大， 而两侧 部区的晶粒较小。
本发明的实施例还提供一种基于上述低温多晶硅制作方法制备的低温多 晶硅薄膜， 其包括在村底基板 10的同一侧依次形成的緩沖层 20和非晶硅层 30。
本发明的实施例还提供一种薄膜晶体管， 其包括上述低温多晶硅薄膜。 例如， 该薄膜晶体管包括栅极、 栅绝缘层、 使用上述低温多晶硅薄膜的有源 层、 源极和漏极， 该薄膜晶体管可以为多种类型， 例如顶栅型、 底栅型等。
本发明实施例的低温多晶硅的制作方法， 将非晶硅层分成多个区进行激 光退火处理， 使得每个区域内的多晶硅都能得到大的晶粒尺寸， 并且整个基 板范围内的多晶硅晶粒尺寸的分布均匀。 基于该方法的低温多晶硅薄膜以及 薄膜晶体管， 其多晶硅为均匀的大晶粒。
以上所述仅是本发明的示例性实施方式， 显然， 本领域的普通技术人员 在不脱离本发明的精神和范围的前提下可以对本发明进行各种改动和变型， 而且本发明也意图包含属于本发明权利要求范围之内的这些修改和变型及其 任何等同物。

Claims

权利要求书
1、 一种低温多晶硅的制作方法， 包括：
在村底基板上形成緩沖层；
在所述緩沖层上形成非晶硅层；
在形成所述非晶硅层后进行热处理； 以及
根据所述非晶硅层的厚度分布情况将其分成多个区进行激光退火处理， 形成多晶硅层。
2、 如权利要求 1所述的低温多晶硅的制作方法， 其中， 根据所述非晶硅 层的厚度分布情况分成至少一个膜层厚区和至少一个膜层薄区进行激光退火 处理； 并且， 在进行激光退火处理时， 对所述膜层厚区采用的激光能量密度 大于对所述膜层薄区采用的激光能量密度。
3、 如权利要求 1或 2所述的低温多晶硅的制作方法， 其中， 将所述非晶 硅层分成三个区， 较薄的中部区域为第二区， 较厚的两边部区分别为第一区 和第三区；
在第一区的激光退火条件为： 激光脉沖频率为约 200-400 Hz, 重叠率为 约 92%-98%, 激光能量密度为约 240-250 mJ/cm2;
在第二区的激光退火条件为： 激光脉沖频率为约 200-400HZ, 重叠率为约 92%-98%, 激光能量密度为约 230-240 mJ/cm2; 以及
在第三区的激光退火条件为： 激光脉沖频率为约 200-400HZ, 重叠率为约
92%-98%, 激光能量密度为约 240-250 mJ/cm2。
4、 如权利要求 1或 2所述的低温多晶硅的制作方法， 其中， 将所述非晶 硅层分成三个区， 较厚的中部区域为第二区， 较薄的两边部区分别为第一区 和第三区；
在第一区的激光退火条件为： 激光脉沖频率为约 200-400HZ, 重叠率为约
92%-98%, 激光能量密度为约 220-250 mJ/cm2;
在第二区的激光退火条件为： 激光脉沖频率为约 200-400HZ, 重叠率为约 92%-98%, 激光能量密度为约 260-280 mJ/cm2; 以及
在第三区的激光退火条件为： 激光脉沖频率为约 200-400 Hz, 重叠率为 约 92%-98%, 激光能量密度为约 250-270 mJ/cm2。
5、 如权利要求 1-4任一项所述的低温多晶硅制作方法， 其中， 所述緩沖 层包括在所述村底基板上依次沉积的约 50-150nm厚的氧化硅薄膜层和之后 沉积的约 100-350nm厚的二氧化硅薄膜层。
6、 如权利要求 1-5任一项所述的低温多晶硅制作方法， 其中所述緩沖层 上沉积有约 30-50nm非晶硅层。
7、 如权利要求 1-6任一项所述的低温多晶硅制作方法， 其中， 在所述緩 沖层上沉积非晶硅层后， 在约 400-500 °C的温度下， 对所述非晶硅层进行约 0.5-3小时的热处理。
8、 如权利要求 1-7任一项所述的低温多晶硅制作方法， 其中对所述非晶 硅层采用准分子激光器进行激光退火处理。
9、 如权利要求 8所述的低温多晶硅制作方法， 其中所述准分子激光器为 氯化氙或氟化氪或氟化氩准分子激光器。
10、 一种基于所述权利要求 1-9任一项所述的方法制备的低温多晶硅薄 膜， 包括在所述村底基板的同一侧依次形成的緩沖层和多晶硅层。
11、 一种薄膜晶体管， 包括如权利要求 10所述的低温多晶硅薄膜。
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