WO2014166162A1 - 薄膜层及其制作方法、显示用基板、液晶显示器 - Google Patents

薄膜层及其制作方法、显示用基板、液晶显示器 Download PDF

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Publication number
WO2014166162A1
WO2014166162A1 PCT/CN2013/077441 CN2013077441W WO2014166162A1 WO 2014166162 A1 WO2014166162 A1 WO 2014166162A1 CN 2013077441 W CN2013077441 W CN 2013077441W WO 2014166162 A1 WO2014166162 A1 WO 2014166162A1
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Prior art keywords
layer
film layer
thin film
sub
layers
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English (en)
French (fr)
Inventor
姜清华
李小和
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US14/361,131 priority Critical patent/US9502571B2/en
Publication of WO2014166162A1 publication Critical patent/WO2014166162A1/zh
Anticipated expiration legal-status Critical
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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Definitions

  • Embodiments of the present invention relate to a thin film layer, a method of fabricating the same, a display substrate including the thin film layer, and a liquid crystal display including the display substrate. Background technique
  • a thin film transistor In a thin film transistor liquid crystal display (TFT-LCD), a thin film transistor is used as a core component of a display, and the yield of the manufacturing process directly determines the cost and reliability of the thin film transistor liquid crystal display.
  • TFT-LCD thin film transistor liquid crystal display
  • the fabrication of each thin film layer of the thin film transistor is a critical step.
  • the slope of the edge of the film layer directly affects the coverage of the film layer deposited next. When the edge of the film is too steep or even vertical, the film layer deposited next will often cause poor coverage or even breakage; Slope relaxation, poor coverage or wire breakage can be largely avoided, so the control of the edge of the film layer is the key to the thin film transistor process.
  • each film layer is prepared by the same process parameters in the preparation, resulting in uniformity of crystallinity and density of each film layer.
  • a film layer is prepared on the substrate 3. 2.
  • the crystallinity and density of the formed film layer 2 are uniform, and when the photoresist 1 is exposed, the same acid concentration (wet etching) or plasma intensity (dry method) is performed. Etching)
  • the etching rate of the thin film layer 2 is also substantially the same.
  • the effect diagram after etching is as shown in FIG. 2, and the edge slope of the thin film layer 2 is relatively steep, which is disadvantageous for the deposition of the thin film layer 4 in the next process, and is easy to generate a step. Poor coverage or even disconnection, as shown in Figure 3. Summary of the invention
  • One of the objects of the present invention is to solve the problem that the edge of the film layer obtained by the prior art is too steep or even vertical, which leads to the problem that the film layer deposited nextly is prone to poor step coverage or even wire breakage, and provides a well-covered film layer.
  • One embodiment of the present invention provides a film layer comprising a plurality of sub-layers of different densities, wherein the density of the sub-layers above is less than the density of the sub-layers underneath.
  • each of the sub-layers of the thin film layer has a thickness of from 1 nm to 500 nm. In one example, each of the sub-layers of the thin film layer has a thickness of 10 nm to 50 nm.
  • each of the sub-layers of the film layer has the same thickness.
  • the sub-layer of the film layer is at least 3 layers.
  • the thin film layer is any one of an aluminum layer, a copper layer, an indium tin oxide layer, an oxidized layer, a SiNx layer, and an SiOx layer.
  • the sub-layers of the film layer are of the same material.
  • Another embodiment of the present invention provides a method of fabricating a thin film layer, including:
  • the setting initial process conditions includes: setting initial magnetron sputtering power, gas flow rate, generation temperature, sputtering pressure, and target pitch,
  • the at least one process condition is adjusted according to the influence of the change of each process condition on the density of the film layer, and at least two are formed in which the density is sequentially decreased according to the initial sub-layer.
  • Subsequent sublayers include:
  • the second sub-layer is formed by adjusting the magnetron sputtering power and/or reducing the gas flow rate; forming one or more subsequent sub-layers by adjusting the magnetron sputtering power and/or reducing the gas flow rate.
  • the setting initial process conditions includes: setting an initial plasma power, a gas flow rate, a generation temperature,
  • the at least one process condition is adjusted according to the influence of the change of each process condition on the density of the film layer, and at least two are formed in which the density is sequentially decreased according to the initial sub-layer.
  • Subsequent sublayers include:
  • the second sub-layer is formed by adjusting the plasma power and/or reducing the gas flow rate; forming one or more subsequent sub-layers by adjusting the plasma power and/or reducing the gas flow.
  • Yet another embodiment of the present invention provides a thin film transistor comprising: at least one thin film layer as described above.
  • At least one of the thin film layers is a gate insulating layer of the thin film transistor, At least one of the source layer and the source and drain electrode layers.
  • Still another embodiment of the present invention provides a substrate for display comprising: a substrate and a plurality of pixel structures disposed on the substrate; wherein the pixel structure includes at least one thin film layer as described above.
  • the display substrate is an array substrate, and one of the film layers in each pixel structure is a gate insulating layer or a passivation layer.
  • Still another embodiment of the present invention provides a liquid crystal display comprising the display substrate as described above.
  • each thin film layer is a sub-layer having a plurality of different densities
  • the etching rate of each sub-layer is under the same acid concentration or plasma intensity in the subsequent etching process. Differently, the etching rate is inversely proportional to the density. After the same etching time, the etching length is different, which will make the edge of the film layer more gentle. Since the slope of the edge of the film layer is moderated, the film coverage of the next process is good, and the wire breakage phenomenon does not occur.
  • the liquid crystal display prepared by the method of the present invention has high yield and high reliability.
  • Figure 1 is a schematic view of a thin film layer prior to etching in a thin film layer of a prior art thin film transistor.
  • FIG. 2 is a schematic view of a thin film layer after etching in a thin film layer of a prior art thin film transistor.
  • FIG. 3 is a schematic view of the film layer of the prior art thin film transistor after the film layer is covered in the next process.
  • FIG. 4 is a schematic view showing a film layer before etching in a thin film layer of a thin film transistor according to Embodiment 1 of the present invention.
  • Fig. 5 is a schematic view showing the film layer after etching in the thin film layer of the thin film transistor in the first embodiment of the present invention.
  • This embodiment provides a thin film layer comprising a plurality of sublayers of different densities, wherein the densities of the upper sublayers are less than the densities of the sublayers underneath.
  • This embodiment provides a method for fabricating a thin film layer, and a thin film transistor including the thin film layer.
  • the glass substrate is placed in a magnetron sputtering chamber, and the DC sputtering power of the magnetron sputtering device is controlled.
  • the DC sputtering power of the above magnetron sputtering parameters is adjusted to 75 KW, the Ar flow rate is 800 sccm, the sputtering pressure is 0.3 Pa, the target spacing is 60 mm, the substrate temperature is 200 ° C, and the deposition time is 18 s, forming a density.
  • a moderate thickness of 50nm A1 film layer as shown in Figure 4, the film layer density of the moderate portion 22;
  • the DC sputtering power of the above magnetron sputtering parameters is adjusted to 70 KW, the Ar flow rate is 800 sccm, the sputtering pressure is 0.3 Pa, the target spacing is 60 mm, the substrate temperature is 200 ° C, and the deposition time is 15 s, forming a density.
  • the A1 film layer is composed of three layers having different densities and a reduced density from the substrate to one side. For example, it is also possible to divide more sub-layers depending on the actual thickness of the film layer, which is advantageous for forming a more gentle edge slope.
  • control parameters can also be adjusted according to the material of the target material and the thickness of the sub-layer, which belongs to the prior art.
  • A1 film layer may be another metal layer or a metal oxide film layer, for example, any of a copper layer, an indium tin oxide layer, and an oxidized layer.
  • the thickness of the sub-layer can be selected according to specific application requirements.
  • the thickness of the sub-layer of the thin film layer may also be from 1 nm to 500 nm.
  • the thickness of the sub-layer of the thin film layer may also be from 10 nm to 50 nm.
  • the thickness of the sub-layers of the A1 film layer may be the same, which is advantageous for forming a relatively gentle edge slope.
  • the sublayer of the A1 film layer is at least 3 layers, which is advantageous for forming a relatively gentle edge slope.
  • the etching solution is a mixture of phosphoric acid, nitric acid and acetic acid, and the ratio of the substances in the three substances is 69:10:2.5, the oscillation speed of the glass substrate in the etching liquid is 3000 mm/min, and the etching time is 15 s.
  • the etching rate is inversely proportional to the density. After the same etching time, the etching length is different, and the obtained pattern is as shown in the figure.
  • a thin film transistor is obtained by fabricating other necessary structural layers in the thin film transistor, for example, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode layer, and the like by a plurality of the above-described patterning methods.
  • the specific materials and process parameters of the films of different layers are different.
  • the layer structure which does not cause poor coverage of the layers can also be manufactured by a conventional method (that is, the deposited film has uniform density and no density gradient).
  • the patterning method of the present embodiment is not limited to the fabrication of the layer structure in the thin film transistor, and it can also be used to fabricate other structures.
  • This embodiment provides a method for fabricating a thin film layer, and a thin film transistor including the thin film layer.
  • 1) Plasma-enhanced chemical vapor deposition to form thin film layers with different density sub-layers will be placed in the deposition chamber on the glass substrate by controlling the plasma power to 20 kW, 13 ⁇ 4 flow rate is 50000 sccm, Si flow rate is 6000 sccm, NH 3 The flow rate is 20000sccm, the substrate temperature (generation temperature) is 360 ° C, and the deposition time is 15 s, forming a dense density SiNx layer having a thickness of 200 nm;
  • the above plasma power is adjusted to 16 KW, 3 ⁇ 4 flow rate is 46000 sccm, Si flow rate is 5500 sccm, NH 3 flow rate is 18500 sccm, the substrate temperature is 360 ° C, and the deposition time is 20 s, forming a lower density SiNx layer with a thickness of 200 nm. .
  • the SiNx layer is composed of three layers having different densities which are reduced in density from the substrate to one side.
  • the above plasma enhanced chemical vapor deposition apparatus can also be selected according to a specific purpose, and the control parameters can also be adjusted according to the thickness of the film material and the sublayer.
  • the SiNx layer described above may be another non-metallic thin film layer, for example, or may be an SiOx layer.
  • the thickness of the sub-layer of the film layer can be selected according to specific application requirements.
  • the thickness of the sub-layer of the film layer may also be from 1 nm to 500 nm. More preferably, the thickness of the sub-layer of the film layer may also be 10nm-50nm.
  • the thickness of the sub-layers of the film layer can be the same, which is advantageous for forming a relatively gentle edge slope.
  • the sub-layer of the film layer is at least 3 layers, which is advantageous for forming a relatively gentle edge slope.
  • the power of the dry etching plasma etching apparatus is 8 KW
  • the chamber pressure is 50 mT
  • the SF 6 flow rate is 800 sccm
  • the 0 2 flow rate is 1000 sec
  • the Cl 2 flow rate is 7000 sccm
  • the etching time is For 30s.
  • the above SiNx thin film layers having different density sublayers have different etching rates at the same plasma intensity, and the etching rate is inversely proportional to the density. After the same etching time, the etching length is different. A film edge slope similar to that shown in Fig. 5 can be obtained.
  • a thin film transistor is obtained by fabricating other necessary structural layers in the thin film transistor, for example, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode layer, and the like by a plurality of the above-described patterning methods.
  • the specific materials and process parameters of the films of different layers are different.
  • the layer structure which does not cause poor coverage of the layers can also be manufactured by a conventional method (that is, the deposited film has uniform density and no density gradient).
  • the patterning method of the present embodiment is not limited to the fabrication of the layer structure in the thin film transistor, and it can also be used to fabricate other structures.
  • the material of the sub-layers in each of the film layers is the same.
  • the embodiment provides a substrate for display, comprising: a substrate and a plurality of pixel structures disposed on the substrate; the pixel structure includes at least one of the above-mentioned thin film layers.
  • the display substrate is an array substrate, and one of the film layers in each pixel structure is a gate insulating layer.
  • the display substrate is an array substrate, and one of the film layers in each pixel structure may also be a passivation layer.
  • This embodiment provides a liquid crystal display including the above-described display substrate.
  • the above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention.
  • the scope of the present invention is defined by the appended claims.

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Abstract

提供了一种薄膜层及其制作方法、显示用基板、液晶显示器。根据本发明的实施例可解决现有方法制得的薄膜层边缘坡度过陡甚至垂直，导致下一步沉积的薄膜层容易产生台阶覆盖不良甚至断线的问题。本发明实施例的薄膜层包括多个不同致密度的子层，其中，在上的子层的致密度小于在下的子层的致密度。采用本发明实施例的薄膜层制备的薄膜晶体管和薄膜晶体管液晶显示器的良品率高、可靠性高。

Description

薄膜层及其制作方法、 显示用基板、 液晶显示器 技术领域
本发明的实施例涉及一种薄膜层及其制作方法、 含有该薄膜层的显示用 基板、 含有该显示用基板的液晶显示器。 背景技术
在薄膜晶体管液晶显示器（TFT-LCD ) 中， 薄膜晶体管作为显示器的核 心部件， 其制造工艺的良品率直接决定薄膜晶体管液晶显示器的成本和可靠 性。 现有的薄膜晶体管制备工艺中， 薄膜晶体管的各薄膜层的制备又是关键 的步骤。 薄膜层边缘坡度的大小直接影响下一步沉积的薄膜层的覆盖性的好 坏， 薄膜边缘坡度过陡甚至垂直时， 往往会导致下一步沉积的薄膜层覆盖不 良甚至发生断线； 而如果薄膜边缘坡度緩和， 覆盖不良或断线的情况就可以 大幅度的避免， 所以薄膜层边缘坡度的控制是薄膜晶体管工艺中的关键。
在现有 TFT-LCD工艺中， 每个薄膜层在制备中采用相同工艺参数制备， 导致每个薄膜层的结晶度和致密度是一致的， 如图 1所示， 在基板 3上制备 薄膜层 2,形成的薄膜层 2的结晶度和致密度是均匀一致的， 当涂覆光刻胶 1 曝光后， 进行独刻时， 同样的酸浓度（湿法刻蚀）或等离子体强度（干法刻 蚀 )对薄膜层 2蚀刻速率也会大致相同， 蚀刻后的效果图如图 2所示， 薄膜 层 2的边缘坡度会比较陡， 不利于下一工序的薄膜层 4的沉积， 容易产生台 阶覆盖不良甚至断线现象， 如图 3所示。 发明内容
本发明的目的之一是解决现有方法制得的薄膜层边缘坡度过陡甚至垂 直， 导致下一步沉积的薄膜层容易产生台阶覆盖不良甚至断线的问题， 提供 一种覆盖良好的薄膜层。
本发明的一个实施例提供一种薄膜层， 包括多个不同致密度的子层， 其 中， 在上的子层的致密度小于在下的子层的致密度。
在一个示例中， 所述的薄膜层的每个子层的厚度为 lnm-500nm。 在一个示例中， 所述的薄膜层的每个子层的厚度为 10nm-50nm。
在一个示例中， 所述的薄膜层的每个子层的厚度相同。
在一个示例中， 所述的薄膜层的子层至少为 3层。
在一个示例中， 所述的薄膜层是铝层、 铜层、 氧化铟锡层、 氧化辞层、 SiNx层、 SiOx层中的任意一种。
在一个示例中， 所述薄膜层的子层的材料相同。
本发明的另一个实施例提供一种薄膜层的制作方法， 包括：
设置初始工艺条件， 形成所述薄膜层的初始子层；
按照每一个工艺条件的变化对所述薄膜层致密度大小的影响， 调节所述 至少一个工艺条件， 形成以所述初始子层为基准、 致密度依排列顺序依次减 小的至少两个后续子层。
在一个示例中，所述设置初始工艺条件包括：设置初始的磁控溅射功率、 气体流量、 生成温度、 溅射压力和靶基间距，
所述按照每一个工艺条件的变化对所述薄膜层致密度大小的影响， 调节 所述至少一个工艺条件， 形成以所述初始子层为基准、 致密度依排列顺序依 次减小的至少两个后续子层包括：
采用降低磁控溅射功率和 /或降低气体流量的调节方式， 形成第二子层； 采用降低磁控溅射功率和 /或降低气体流量的调节方式，形成一个或多个 后续子层。
在一个示例中，所述设置初始工艺条件包括：设置初始的等离子体功率、 气体流量、 生成温度，
所述按照每一个工艺条件的变化对所述薄膜层致密度大小的影响， 调节 所述至少一个工艺条件， 形成以所述初始子层为基准、 致密度依排列顺序依 次减小的至少两个后续子层包括：
采用降低等离子体功率和 /或降低气体流量的调节方式， 形成第二子层； 采用降低等离子体功率和 /或降低气体流量的调节方式，形成一个或多个 后续子层。
本发明的又一个实施例提供一种薄膜晶体管， 包括： 至少一个如上所述 的薄膜层。
在一个示例中， 至少一个所述薄膜层为所述薄膜晶体管的栅绝缘层、 有 源层和源漏电极层中的至少之一。
本发明的又一个实施例提供一种显示用基板， 包括： 基板以及设置在所 述基板上的多个像素结构； 其中， 所述像素结构包括至少一个如上所述的薄 膜层。
在一个示例中， 所述显示用基板为阵列基板， 每一像素结构中的一个所 述薄膜层为栅绝缘层或钝化层。
本发明的又一个实施例提供一种液晶显示器， 包括如上所述的显示用基 板。
本发明实施例提供的薄膜层， 由于每个薄膜层是具有多个不同致密度的 子层， 在后继的刻蚀过程中在相同的酸液浓度或者等离子体强度下， 每个子 层的蚀刻速率是不同的，蚀刻速率与致密度成反比，经过相同的刻蚀时间后， 刻蚀长度不同， 将使获得薄膜层边缘坡度较为緩和。 由于薄膜层边缘坡度緩 和， 下一工序的薄膜层覆盖时覆盖性良好， 不会产生断线现象。
采用本发明的方法制备的液晶显示器的良品率高、 可靠性高。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的薄膜晶体管的薄膜层制备过程中薄膜层刻蚀前的示意 图。
图 2为现有技术的薄膜晶体管的薄膜层制备过程中薄膜层刻蚀后的示意 图。
图 3为现有技术的薄膜晶体管的薄膜层制备过程中下一工序薄膜层覆盖 后的示意图。
图 4为本发明实施例 1中薄膜晶体管的薄膜层制备过程中薄膜层刻蚀前 的示意图。
图 5为本发明实施例 1中薄膜晶体管的薄膜层制备过程中薄膜层刻蚀后 的示意图。
图 6为本发明实施例 1中薄膜晶体管的薄膜层制备过程中下一工序薄膜 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例 1
本实施例提供一种薄膜层，该薄膜层包括多个不同致密度的子层，其中， 在上的子层的致密度小于在下的子层的致密度。
实施例 2
本实施例提供一种薄膜层的制作方法， 含该薄膜层的薄膜晶体管。
1 )采用磁控溅射形成具有不同致密度子层的薄膜层
将玻璃基板置于磁控溅射室， 通过控制磁控溅射装置的直流溅射功率为
80KW, Ar流量为 900sccm, 溅射气压为 0.3pa, 靶基间距为 60mm, 村底温 度（生成温度）为 200。C, 沉积时间为 20s, 形成致密度较大的厚度为 70nm 的 A1薄膜层， 即如图 4所示， 薄膜层致密度较大部分 23;
接着调节上述磁控溅射参数的直流溅射功率为 75KW , Ar 流量为 800sccm, 溅射气压为 0.3pa, 靶基间距为 60mm, 村底温度为 200°C , 沉积 时间为 18s, 形成致密度适中的厚度为 50nm的 A1薄膜层， 即如图 4所示， 薄膜层致密度适中部分 22;
最后调节上述磁控溅射参数的直流溅射功率为 70KW , Ar 流量为 800sccm, 溅射气压为 0.3pa, 靶基间距为 60mm, 村底温度为 200°C , 沉积 时间为 15s, 形成致密度较低的厚度为 30nm的 A1薄膜层， 即如图 4所示， 薄膜层致密度较低部分 21。
这样 A1薄膜层由致密度不同的、 从基板向一侧致密度降低的 3层组成。 例如， 也可以根据薄膜层的实际厚度分成更多的子层， 有利于形成更为緩和 的边缘坡度。
可以理解的是， 上述磁控溅射装置也可以根据具体的目的选用其它类型 的， 控制参数也可以根据靶材材质、 子层的厚度的不同进行调整， 属于现有 技术的范畴。
可以理解的是,上述的 A1薄膜层可以是其它金属层或者金属氧化物薄膜 层、 例如， 可以是铜层、 氧化铟锡层、 氧化辞层中的任意一种。
可以理解的是， 子层的厚度可以根据具体应用需要进行选取， 例如， 薄 膜层的子层的厚度也可以为 lnm-500nm, 优选的， 薄膜层的子层的厚度也可 以为 10nm-50nm。
例如， A1薄膜层的子层的厚度也可以相同， 有利于形成较为平緩的边缘 坡度。
例如， A1薄膜层的子层至少为 3层， 有利于形成较为平緩的边缘坡度。
2 )对上述制备的具有不同致密度子层的 A1薄膜层进行涂覆光刻胶 1 , 完成曝光步骤。
3 )将制备的具有不同致密度子层的 A1薄膜层进行湿法刻蚀。
例如， 刻蚀液为磷酸、 硝酸和醋酸的混合液， 三者的物质的量浓度比例 为 69： 10： 2.5, 玻璃基板在刻蚀液里的振荡速度 3000mm/min, 刻蚀时间为 15s。 上述的具有不同致密度子层的 A1薄膜层的每个子层在酸溶液独刻速率 是不同的， 蚀刻速率与致密度成反比， 经过相同的刻蚀时间后， 刻蚀长度不 同， 获得如图 5所示的薄膜层边缘坡度。
4 )进行剥除光刻胶的步骤，按上述的方法进行下一工序的制备， 由于薄 膜层边缘坡度緩和， 此时下一工序的薄膜层覆盖时， 覆盖性良好， 如图 6所 示， 得到作为薄膜晶体管栅极层的 A1薄膜层。
通过多次上述的构图方法制造薄膜晶体管中的其它必要结构层， 例如， 栅绝缘层、 有源层、 欧姆接触层、 源电极、 漏电极层等， 获得薄膜晶体管。 当然， 其中不同层的薄膜的具体材料、 工艺参数等不同； 同时， 对于不会产 生阶覆盖不良现象的层结构， 也可用常规的方法制造（即沉积的薄膜密度均 匀， 没有密度梯度） 。
当然， 本实施例的构图方法也并不限用于制造薄膜晶体管中的层结构， 其也可用于制造其他的结构。
实施例 3
本实施例提供一种薄膜层的制作方法， 含该薄膜层的薄膜晶体管。 1 )采用等离子体增强化学气相沉积法形成具有不同致密度子层的薄膜层 将在玻璃基板置于沉积腔室， 通过控制等离子体功率为 20KW, 1¾流量 为 50000sccm, Si 流量为 6000sccm, NH3流量为 20000sccm,村底温度（生 成温度）为 360°C ,沉积时间为 15s,形成致密度较大的厚度为 200nm的 SiNx 层；
接着调节上述等离子体功率为 18KW, ¾流量为 48000sccm, Si 流量 为 5700sccm, NH3流量为 19500sccm, 村底温度为 360°C , 沉积时间为 20s, 形成致密度适中的厚度为 200nm的 SiNx层；
最后调节上述等离子体功率为 16KW, ¾流量为 46000sccm, Si 流量 为 5500sccm, NH3流量为 18500sccm, 村底温度为 360°C , 沉积时间为 20s, 形成致密度较低的厚度为 200nm的 SiNx层。
这样 SiNx层由致密度不同的、 从基板向一侧致密度降低的 3层组成。 优选的， 也可以根据薄膜层的实际厚度分成更多的层， 有利于形成更为緩和 的边缘坡度。
可以理解的是， 上述等离子体增强化学气相沉积装置也可以根据具体的 目的选用其它类型的， 控制参数也可以根据薄膜材质、 子层的厚度的不同进 行调整。
可以理解的是， 上述的 SiNx层可以是其它非金属薄膜层、 例如， 也可 以是 SiOx层。
可以理解的是， 薄膜层的子层的厚度可以根据具体应用需要进行选取， 例如， 薄膜层的子层的厚度也可以为 lnm-500nm, 更优选的， 薄膜层的子层 的厚度也可以为 10nm-50nm。
例如， 薄膜层的子层的厚度也可以相同， 有利于形成较为平緩的边缘坡 度。
例如， 薄膜层的子层至少为 3层， 有利于形成较为平緩的边缘坡度。
2 )对上述的制备的具有不同致密度子层的 SiNx层进行涂覆光刻胶 1 , 完成曝光步骤。
3 )将制备的具有不同致密度子层的 SiNx层进行干法刻蚀。
例如，控制干法蚀刻等离子刻蚀装置的功率为 8KW,腔体压力为 50mT, SF6流量为 800sccm, 02流量为 lOOOOsccm, Cl2流量为 7000sccm, 刻蚀时间 为 30s。上述的具有不同致密度子层的 SiNx薄膜层每个子层在相同的等离子 强度下的蚀刻速率是不同的， 蚀刻速率与致密度成反比，经过相同的刻蚀时 间后， 刻蚀长度不同， 也能获得类似图 5所示的薄膜层边缘坡度。
4 )进行剥除光刻胶的步骤，按上述的方法进行下一工序的制备， 由于薄 膜层边缘坡度緩和， 此时下一工序的薄膜层覆盖时， 覆盖性良好；
通过多次上述的构图方法制造薄膜晶体管中的其它必要结构层， 例如， 栅绝缘层、 有源层、 欧姆接触层、 源电极、 漏电极层等， 获得薄膜晶体管。 当然， 其中不同层的薄膜的具体材料、 工艺参数等不同； 同时， 对于不会产 生阶覆盖不良现象的层结构， 也可用常规的方法制造（即沉积的薄膜密度均 匀， 没有密度梯度） 。
当然， 本实施例的构图方法也并不限用于制造薄膜晶体管中的层结构， 其也可用于制造其他的结构。
在上述各实施例中， 例如， 每个薄膜层中的子层的材料均相同。
实施例 4
本实施例提供一种显示用基板， 包括： 基板以及设置在所述基板上的多 个像素结构； 所述像素结构包括至少一个上述的薄膜层。
例如， 所述显示用基板为阵列基板， 每一像素结构中的一个所述薄膜层 为栅绝缘层。
例如， 所述显示用基板为阵列基板， 每一像素结构中的一个所述薄膜层 也可以为钝化层。
实施例 5
本实施例提供一种液晶显示器， 该液晶显示器包括上述的显示用基板。 以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1.一种薄膜层， 包括多个不同致密度的子层， 其中， 在上的子层的致密 度小于在下的子层的致密度。
2.如权利要求 1所述的薄膜层， 其中， 所述的薄膜层的每个子层的厚度 为 lnm-500nm。
3.如权利要求 2所述的薄膜层， 其中， 所述的薄膜层的每个子层的厚度 为 10nm-50nm„
4.如权利要求 1-3 中任一项所述的薄膜层， 其中， 所述的薄膜层的每个 子层的厚度相同。
5.如权利要求 1-4 中任一项所述的薄膜层， 其中， 所述的薄膜层的子层 至少为 3层。
6.如权利要求 1-5中任一项所述的薄膜层， 其中， 所述的薄膜层是铝层、 铜层、 氧化铟锡层、 氧化辞层、 SiNx层、 SiOx层中的任意一种。
7.如权利要求 1-6 中任一项所述的薄膜层， 其中， 所述薄膜层的子层的 材料相同。
8.—种薄膜层的制作方法， 包括：
设置初始工艺条件， 形成所述薄膜层的初始子层；
按照每一个工艺条件的变化对所述薄膜层致密度大小的影响， 调节所述 至少一个工艺条件， 形成以所述初始子层为基准、 致密度依排列顺序依次减 小的至少两个后续子层。
9.根据权利要求 8所述的制作方法， 其中， 所述设置初始工艺条件包括： 设置初始的磁控溅射功率、 气体流量、 生成温度、 溅射压力和靶基间距， 所述按照每一个工艺条件的变化对所述薄膜层致密度大小的影响， 调节 所述至少一个工艺条件， 形成以所述初始子层为基准、 致密度依排列顺序依 次减小的至少两个后续子层包括：
采用降低磁控溅射功率和 /或降低气体流量的调节方式， 形成第二子层； 采用降低磁控溅射功率和 /或降低气体流量的调节方式，形成一个或多个 后续子层。
10.根据权利要求 8所述的制作方法，其中，所述设置初始工艺条件包括： 设置初始的等离子体功率、 气体流量、 生成温度，
所述按照每一个工艺条件的变化对所述薄膜层致密度大小的影响， 调节 所述至少一个工艺条件， 形成以所述初始子层为基准、 致密度依排列顺序依 次减小的至少两个后续子层包括：
采用降低等离子体功率和 /或降低气体流量的调节方式， 形成第二子层； 采用降低等离子体功率和 /或降低气体流量的调节方式，形成一个或多个 后续子层。
11.一种薄膜晶体管， 包括： 至少一个如权利要求 1-7中任一项所述的薄 膜层。
12.如权利要求 11所述的薄膜晶体管， 其中， 至少一个所述薄膜层为所 述薄膜晶体管的栅绝缘层、 有源层和源漏电极层中的至少之一。
13.—种显示用基板，包括：基板以及设置在所述基板上的多个像素结构； 其中， 所述像素结构包括至少一个如权利要求 1-7中任一项所述的薄膜层。
14.根据权利要求 13所述的显示用基板， 其中， 所述显示用基板为阵列 基板， 每一像素结构中的一个所述薄膜层为栅绝缘层或钝化层。
15.—种液晶显示器， 包括如权利要求 13或 14所述的显示用基板。
PCT/CN2013/077441 2013-04-11 2013-06-19 薄膜层及其制作方法、显示用基板、液晶显示器 Ceased WO2014166162A1 (zh)

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