CN105655347A - 一种tft背板、其制备方法及显示装置 - Google Patents

一种tft背板、其制备方法及显示装置 Download PDF

Info

Publication number
CN105655347A
CN105655347A CN201610003204.XA CN201610003204A CN105655347A CN 105655347 A CN105655347 A CN 105655347A CN 201610003204 A CN201610003204 A CN 201610003204A CN 105655347 A CN105655347 A CN 105655347A
Authority
CN
China
Prior art keywords
layer
etching
interlayer insulating
metal
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610003204.XA
Other languages
English (en)
Inventor
徐岩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
Kunshan Guoxian Photoelectric Co Ltd
Original Assignee
Kunshan Guoxian Photoelectric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Guoxian Photoelectric Co Ltd filed Critical Kunshan Guoxian Photoelectric Co Ltd
Priority to CN201610003204.XA priority Critical patent/CN105655347A/zh
Publication of CN105655347A publication Critical patent/CN105655347A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种TFT背板的制备工艺,包括如下步骤:S1:在基板上依次形成缓冲层、半导体层、栅极绝缘层、第一金属层,所述第一金属层经刻蚀形成栅极层;S2、在步骤S1的基础上沉积电容绝缘材料层,再溅镀形成第二金属层,刻蚀所述第二金属层形成电容层,再以电容层做掩膜版刻蚀电容绝缘材料层以暴露半导体层两端的部分区域,形成电容绝缘层;S3、在步骤S2的基础上沉积层间绝缘层,刻蚀层间绝缘层和栅极绝缘层形成接触孔使所述半导体层暴露;S4、在步骤S3的基础上沉积金属材料,刻蚀后形成源漏极。本发明提供的工艺通过减少刻孔工艺总膜层厚度,降低刻孔工艺难度,进而提高TFT电气特性稳定性。

Description

一种TFT背板、其制备方法及显示装置
技术领域
本发明涉及平板显示领域,具体涉及一种TFT背板、其制备方法及显示装置。
背景技术
目前在低温多晶硅技术LTPS(LowTemperaturePoly-silicon)流程中接触孔的刻蚀工艺存在如下技术问题:
需要刻蚀的膜层很厚(层间介质层ILD:绝缘层 ),接触孔深且越往下孔径越小,反应过程中容易出现反应物不能及时排出而发生刻蚀停止现象;若通过延长刻蚀时间或增大偏置电源(BiasPower)来避免刻蚀停止,则会导致线宽损失(CDLoss)比较大,影响器件电学性能;
为解决上述技术问题,现有技术中对接触孔采用湿刻和干刻工艺相结合的方式,即先在干刻区进行干法刻蚀,刻蚀掉层间介质层和部分第一绝缘层,然后再将刻蚀器件运送到湿刻区进行湿法刻蚀,刻蚀掉剩余的第一绝缘层。由于湿法刻蚀能有效避免多晶硅层过刻,但需要增加待刻蚀器件在干刻区和湿刻区之间的运送工艺,工艺较繁琐。
发明内容
本发明所要解决的技术问题是现有TFT背板制备过程中接触孔刻蚀工艺难度较大导致其电学性能下降的问题,从而提供一种TFT背板的制备工艺,此工艺通过减少刻孔工艺总膜层厚度,降低刻孔工艺难度,进而提高TFT电气特性稳定性。
为解决上述技术问题,本发明是通过以下技术方案实现的:
一种TFT背板的制备工艺,包括如下步骤:
S1:在基板上依次形成缓冲层、半导体层、栅极绝缘层、第一金属层,所述第一金属层经刻蚀形成栅极层;
S2、在步骤S1的基础上沉积电容绝缘材料层,再溅镀形成第二金属层,刻蚀所述第二金属层形成电容层,再以电容层做掩膜版刻蚀电容绝缘材料层以暴露半导体层两端的部分区域,形成电容绝缘层;
S3、在步骤S2的基础上沉积层间绝缘层,刻蚀层间绝缘层和栅极绝缘层形成贯穿层间绝缘层和栅极绝缘层的接触孔;
S4、在步骤S3的基础上沉积金属材料,刻蚀后形成源漏极。
所述的步骤S2为:
在步骤S1的基础上沉积电容绝缘材料层,再溅镀形成第二金属Mo层,刻蚀所述第二金属Mo层形成电容层,在同一干刻机腔室内通过工艺参数的条件后,再以电容层做掩膜版刻蚀CI材料层以暴露半导体层两端的部分区域,形成电容绝缘层。
采用碳氟化合物刻蚀气体对层间绝缘层和栅极绝缘层进行刻蚀。
所述接触孔的孔径为2~5μm,所述接触孔的深度为400~1000nm。
所述层间绝缘层为氧化硅层SiOx,所述层间绝缘层为氮化硅层SiNx。
所述的栅极绝缘层为氧化硅层SiOx,所述的电容绝缘层为氮化硅层SiNx,所述半导体层为多晶硅层。
所述的缓冲层包括在基板上形成的第一缓冲层和第二缓冲层,所述的第一缓冲层为氮化硅层SiNx,所述的第二缓冲层为氧化硅层SiOx。
一种运用所述的制备工艺制备的TFT背板。
一种显示装置,所述显示装置包含有所述的TFT背板。
本发明相对于现有技术具有如下有益效果:
本发明所述的TFT背板的制备工艺是在栅极层上沉积电容绝缘材料层CI,再溅镀形成第二金属层,先将所述第二金属层刻蚀形成电容层后,在同一干刻机腔室内,进行工艺参数及条件变更,继续以电容层的图形作为掩膜版,进行下层电容绝缘材料层CI刻蚀,以暴露半导体层两端如的部分区域,形成电容绝缘层CI。在层间绝缘层ILD沉积完成后,进行接触孔刻蚀工艺,由于电容绝缘层CI在前层已经刻蚀完成,此处接触孔刻蚀工艺只需要需要将层间绝缘层ILD及栅极绝缘层GI层刻蚀完成即可,刻蚀膜层总厚度降低,降低工艺难度,增加电气特性稳定性。
附图说明
为了使本发明的内容更容易被清楚的理解,下面根据本发明的具体实施例并结合附图,对本发明作进一步详细的说明,其中
图1是本发明TFT背板的结构示意图;
其中附图标记为:
01-第一缓冲层、02-第二缓冲层,03-半导体层,04-栅极绝缘层、05-栅极层、06-电容绝缘层、07-电容层,08层间绝缘层,10-第一接触孔,11-第二接触孔,12-第三接触孔。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明实施方式作进一步地详细描述。
本发明可以以许多不同的形式实施,而不应该被理解为限于在此阐述的实施例。相反,提供这些实施例,使得本公开将是彻底和完整的,并且将把本发明的构思充分传达给本领域技术人员,本发明将仅由权利要求来限定。在附图中,为了清晰起见,会夸大层和区域的尺寸和相对尺寸。应当理解的是,当元件例如层、区域或基板被称作“设置在”或“设置在”另一元件“上”时,该元件可以直接设置在所述另一元件上,或者也可以存在中间元件。相反,当元件被称作“直接设置在”或“直接设置在”另一元件上时,不存在中间元件。
一种TFT背板的制备工艺,如图1所示,包括如下步骤:
S1:在基板上依次形成缓冲层、半导体层03、栅极绝缘层04、第一金属层,所述第一金属层经刻蚀形成栅极层05;
S2、在步骤S1的基础上沉积电容绝缘材料层,再溅镀形成第二金属层,刻蚀所述第二金属层形成电容层07,再以电容层07做掩膜版刻蚀电容绝缘材料层以暴露半导体层03两端的部分区域,形成电容绝缘层06;
S3、在步骤S2的基础上沉积层间绝缘层,在预定位置用碳氟化合物刻蚀气体刻蚀层间绝缘层08和栅极绝缘层04形成贯穿层间绝缘层08和栅极绝缘层04接触孔,对层间绝缘层08、层间绝缘层08和栅极绝缘层04进行刻蚀。所述的接触孔包括第一接触孔10,第二接触孔11和第三接触孔12,所述第一接触孔10贯穿所述层间绝缘层08和栅极绝缘层04使所述半导体层03暴露;所述的第二接触孔11贯穿所述层间绝缘层08和栅极绝缘层04使所述电容层07暴露;所述的第三接触孔12贯穿所述层间绝缘层08和栅极绝缘层04使所述栅极层05暴露;
S4、在步骤S3的基础上沉积金属材料Ti/Al/Ti,刻蚀后形成源漏极。
具体地,所述的步骤S2为:
在步骤S1的基础上沉积电容绝缘材料层,再溅镀形成第二金属Mo层,刻蚀所述第二金属Mo层形成电容层07,在同一干刻机腔室内通过工艺参数的条件后,再以电容层07做掩膜版刻蚀电容绝缘层06以暴露半导体层03两端的部分区域,形成电容绝缘层06。
所述接触孔的孔径为2~5μm,所述接触孔的深度为400~1000nm。
所述层间绝缘层08为氧化硅层SiOx,所述层间绝缘层08为氮化硅层SiNx。
所述的栅极绝缘层04为氧化硅层SiOx,所述的电容绝缘层06为氮化硅层SiNx,所述半导体层03为多晶硅层。
所述的缓冲层包括在基板上形成的第一缓冲层01和第二缓冲层02,所述的第一缓冲层01为氮化硅层SiNx,所述的第二缓冲层02为氧化硅层SiOx。
应用例
如图1所示,本发明制备的TFT背板中制备的第一缓冲层01为氮化硅层SiNx,厚度为所述第二缓冲层02氧化硅层SiOx,厚度为所述半导体层03为多晶硅层,厚度为所述栅极绝缘层04为氧化硅层SiOx,厚度为所述栅极层05为金属Mo层,厚度为所述电容绝缘层06为氮化硅层SiNx,厚度为所述电容层07为金属Mo层,厚度为所述层间绝缘层08为氧化硅层SiOx,厚度为所述层间绝缘层08为氮化硅层SiNx,厚度为
其制备方法包括下述步骤:
S1:在基板上依次沉积缓冲层,半导体层03、栅极绝缘层04和第一金属层,具体地:
通过等离子体增强化学气相沉积法(PECVD)在基板00上依次形成厚度为的第一缓冲层01(氮化硅层SiNx),厚度为的第二缓冲层02(氧化硅层SiOx),厚度为的所述非晶硅层,通过对非晶硅层进行激光晶化形成多晶硅层,再通过刻蚀工艺图案化,形成半导体层03;
通过等离子体增强化学气相沉积法(PECVD)形成覆盖所述半导体层03且厚度为的栅极绝缘层04(氧化硅层SiOx);通过等离子体增强化学气相沉积法在所述栅极绝缘层04上依次形成厚度为的第一金属层,所述第一金属层经刻蚀形成栅极层05
S2、在步骤S1的基础上沉积氮化硅层SiNx形成电容绝缘材料层,再溅镀形成第二金属层Mo层,刻蚀所述第二金属层Mo层形成电容层07,在同一干刻机腔室内通过工艺参数的条件后,再以电容层07做掩膜版刻蚀电容绝缘层06以暴露半导体层03两端的部分区域,形成电容绝缘层06。
S3、在步骤S2的基础上沉积氧化硅层SiOx形成层间绝缘层08,在预定位置用碳氟化合物刻蚀气体刻蚀层间绝缘层08和栅极绝缘层04形成贯穿层间绝缘层08和栅极绝缘层04接触孔,对层间绝缘层08、层间绝缘层08和栅极绝缘层04进行刻蚀。所述的接触孔包括第一接触孔10,第二接触孔11和第三接触孔12,所述第一接触孔10贯穿所述层间绝缘层08和栅极绝缘层04使所述半导体层03暴露;所述的第二接触孔11贯穿所述层间绝缘层08和栅极绝缘层04使所述电容层07暴露;所述的第三接触孔12贯穿所述层间绝缘层08和栅极绝缘层04使所述栅极层05暴露;
所述接触孔的孔径为2~5μm,所述接触孔的深度为400~1000nm。
S4、在步骤S3的基础上沉积金属材料Ti/Al/Ti,刻蚀后形成源漏极。
一种显示装置,所述显示装置包含上述方法制备得到的TFT背板,还包括在所述的TFT背板依次层叠设置的第一电极层(阳极)、有机发光单元和第二电极层(阴极),所述的有机发光单元包括堆叠设置的第一有机功能层、发光层和第二有机功能层,所述第一有机功能层包括空穴注入层和/或空穴传输层,所述的第二有机功能层包括电子传输层和/或电子注入层。所述显示装置选用的材料、规格、制备方法同现有技术,不为本发明创造的必要技术特征,本实施例中不再赘述。
显然,上述实施例仅仅是为清楚地说明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明的保护范围之中。

Claims (9)

1.一种TFT背板的制备工艺,其特征在于,包括如下步骤:
S1:在基板上依次形成缓冲层、半导体层(03)、栅极绝缘层(04)、第一金属层,所述第一金属层经刻蚀形成栅极层(05);
S2、在步骤S1的基础上沉积电容绝缘材料层,再溅镀形成第二金属层,刻蚀所述第二金属层形成电容层(07),再以电容层(07)做掩膜版刻蚀电容绝缘材料层以暴露半导体层(03)两端的部分区域,形成电容绝缘层(06);
S3、在步骤S2的基础上沉积层间绝缘层,刻蚀层间绝缘层(08)和栅极绝缘层(04)形成贯穿层间绝缘层(08)和栅极绝缘层(04)的接触孔;
S4、在步骤S3的基础上沉积金属材料,刻蚀后形成源漏极。
2.根据权利要求1所述的TFT背板的制备工艺,其特征在于,所述的步骤S2为:
在步骤S1的基础上沉积电容绝缘材料层,再溅镀形成第二金属Mo层,刻蚀所述第二金属Mo层形成电容层(07),在同一干刻机腔室内通过工艺参数的条件后,再以电容层(07)做掩膜版刻蚀CI材料层以暴露半导体层(03)两端的部分区域,形成电容绝缘层(06)。
3.根据权利要求2所述的TFT背板的制备工艺,其特征在于,采用碳氟化合物刻蚀气体对层间绝缘层(08)和栅极绝缘层(04)进行刻蚀。
4.根据权利要求3所述的TFT背板的制备工艺,其特征在于,所述接触孔的孔径为2~5μm,所述接触孔的深度为400~1000nm。
5.根据权利要求4所述的TFT背板的制备工艺,其特征在于,所述层间绝缘层(08)为氧化硅层SiOx,所述层间绝缘层(08)为氮化硅层SiNx。
6.根据权利要求1-5任一项所述的TFT背板的制备工艺,其特征在于,所述的栅极绝缘层(04)为氧化硅层SiOx,所述的电容绝缘层(06)为氮化硅层SiNx,所述半导体层(03)为多晶硅层。
7.根据权利要求1-5任一项所述的TFT背板的制备工艺,其特征在于,所述的缓冲层包括在基板上形成的第一缓冲层(01)和第二缓冲层(02),所述的第一缓冲层(01)为氮化硅层SiNx,所述的第二缓冲层(02)为氧化硅层SiOx。
8.一种由权利要求1-7任一项所述的制备工艺制备的TFT背板。
9.一种显示装置,其特征在于,所述显示装置包含有权利要求8所述的TFT背板。
CN201610003204.XA 2016-01-04 2016-01-04 一种tft背板、其制备方法及显示装置 Pending CN105655347A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610003204.XA CN105655347A (zh) 2016-01-04 2016-01-04 一种tft背板、其制备方法及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610003204.XA CN105655347A (zh) 2016-01-04 2016-01-04 一种tft背板、其制备方法及显示装置

Publications (1)

Publication Number Publication Date
CN105655347A true CN105655347A (zh) 2016-06-08

Family

ID=56491384

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610003204.XA Pending CN105655347A (zh) 2016-01-04 2016-01-04 一种tft背板、其制备方法及显示装置

Country Status (1)

Country Link
CN (1) CN105655347A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206620A (zh) * 2016-09-05 2016-12-07 昆山国显光电有限公司 薄膜晶体管阵列基板及其制备方法和显示器件
CN108873528A (zh) * 2018-07-27 2018-11-23 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141811A1 (en) * 2001-12-29 2003-07-31 Lg. Philips Lcd Co., Ltd. Active matrix organic luminescence display device and manufacturing method for the same
US20050101062A1 (en) * 2003-11-12 2005-05-12 Chun-Gi You Thin film transistor array panel and manufacturing method thereof
CN1988164A (zh) * 2005-12-23 2007-06-27 三菱电机株式会社 薄膜晶体管装置及其制造方法以及显示装置
CN102096223A (zh) * 2009-12-09 2011-06-15 三星移动显示器株式会社 显示装置及其制造方法
CN103247690A (zh) * 2012-02-01 2013-08-14 三星显示有限公司 半导体器件和包括该半导体器件的平板显示器
CN104716091A (zh) * 2013-12-13 2015-06-17 昆山国显光电有限公司 阵列基板的制备方法、阵列基板和有机发光显示器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141811A1 (en) * 2001-12-29 2003-07-31 Lg. Philips Lcd Co., Ltd. Active matrix organic luminescence display device and manufacturing method for the same
US20050101062A1 (en) * 2003-11-12 2005-05-12 Chun-Gi You Thin film transistor array panel and manufacturing method thereof
CN1988164A (zh) * 2005-12-23 2007-06-27 三菱电机株式会社 薄膜晶体管装置及其制造方法以及显示装置
CN102096223A (zh) * 2009-12-09 2011-06-15 三星移动显示器株式会社 显示装置及其制造方法
CN103247690A (zh) * 2012-02-01 2013-08-14 三星显示有限公司 半导体器件和包括该半导体器件的平板显示器
CN104716091A (zh) * 2013-12-13 2015-06-17 昆山国显光电有限公司 阵列基板的制备方法、阵列基板和有机发光显示器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
应根裕,王健: "《光电显示原理及系统》", 31 August 2015, 清华大学出版社 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206620A (zh) * 2016-09-05 2016-12-07 昆山国显光电有限公司 薄膜晶体管阵列基板及其制备方法和显示器件
CN106206620B (zh) * 2016-09-05 2019-02-15 昆山国显光电有限公司 薄膜晶体管阵列基板及其制备方法和显示器件
CN108873528A (zh) * 2018-07-27 2018-11-23 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板
CN108873528B (zh) * 2018-07-27 2021-03-30 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板

Similar Documents

Publication Publication Date Title
WO2016173322A1 (zh) 一种阵列基板及其制作方法、及显示装置
CN104064688B (zh) 具有存储电容的tft基板的制作方法及该tft基板
CN103000694B (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示装置
US9935183B2 (en) Multilayer passivation or etch stop TFT
CN103165471A (zh) 薄膜晶体管及其制作方法和显示装置
CN103579115B (zh) 互补式薄膜晶体管及其制备方法、阵列基板、显示装置
WO2014012334A1 (zh) 阵列基板的制造方法及阵列基板、显示装置
US20150171224A1 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
CN103972299B (zh) 一种薄膜晶体管及其制作方法、显示基板、显示装置
CN106057827A (zh) 一种阵列基板及其制备方法、显示装置
US20150097179A1 (en) Display substrate and method of manufacturing a display substrate
CN202957251U (zh) 一种薄膜晶体管、阵列基板和显示装置
CN104979215A (zh) 低温多晶硅薄膜晶体管及其制备方法
CN105185695A (zh) 氧化物半导体薄膜的制备方法和薄膜晶体管的制备方法
US9123588B2 (en) Thin-film transistor circuit substrate and method of manufacturing the same
CN105047607A (zh) 氧化物半导体tft基板的制作方法及其结构
US9508762B2 (en) Array substrate, method of manufacturing array substrate and display device
US9252284B2 (en) Display substrate and method of manufacturing a display substrate
CN104377246A (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN105552035B (zh) 低温多晶硅tft阵列基板的制作方法及其结构
CN105655347A (zh) 一种tft背板、其制备方法及显示装置
WO2019095408A1 (zh) 阵列基板及其制作方法、显示面板
EP3627543B1 (en) Method for manufacturing tft substrate
CN107393830A (zh) 薄膜晶体管的制备方法
US10790317B2 (en) Flexible display device and method of manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160608