WO2014161226A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2014161226A1
WO2014161226A1 PCT/CN2013/076710 CN2013076710W WO2014161226A1 WO 2014161226 A1 WO2014161226 A1 WO 2014161226A1 CN 2013076710 W CN2013076710 W CN 2013076710W WO 2014161226 A1 WO2014161226 A1 WO 2014161226A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
gate
display panel
line
Prior art date
Application number
PCT/CN2013/076710
Other languages
English (en)
French (fr)
Inventor
邵贤杰
李小和
Original Assignee
合肥京东方光电科技有限公司
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 合肥京东方光电科技有限公司, 京东方科技集团股份有限公司 filed Critical 合肥京东方光电科技有限公司
Priority to US14/366,236 priority Critical patent/US9406251B2/en
Priority to EP13861497.9A priority patent/EP2983039B1/en
Publication of WO2014161226A1 publication Critical patent/WO2014161226A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136268—Switch defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to a display panel, and more particularly to a display panel capable of detecting a short circuit failure. Background technique
  • the display panel is increasingly accepted by the public based on its low voltage, low radiation, light weight and small size. For display panel designers and producers, it is expected to produce high quality, low cost, and low quality products.
  • the peripheral circuit of the display panel often needs to save space or other factors, and it is necessary to optimally set the peripheral circuit path. Regardless of how the peripheral circuit changes, it is indispensable to have two parts as a display panel. One part is to connect the integrated circuit (IC) and the peripheral wiring area of the pixel area. Its function is to transmit the signal output by the IC to the pixel area, so that the display panel is normal.
  • the display screen; the other part is the pixel area of the display screen area. As long as any part of the two parts is broken or short-circuited, the display panel will show a line-like defect. The maintenance personnel need to move in the inching manner to move from the IC to the end of the pixel area along the line defect to find the defect. Click to fix it.
  • Embodiments of the present invention provide a display panel that can accurately and quickly detect whether there is a short circuit or a broken circuit, and a specific position where a defect occurs.
  • an embodiment of the present invention provides a display panel including a pixel area and a peripheral wiring area, wherein a detection switch is disposed between the pixel area and the peripheral wiring area, and the detection switch and the pixel area are Grid lines and/or data lines - correspondingly, the detection switch is for Controls the connection and disconnection of the pixel area and the peripheral wiring area.
  • the detecting switch includes a first thin film transistor, the peripheral wiring region is a gate wiring region, and a gate of the first thin film transistor is connected to a first external control signal, and a source of the first thin film transistor Connected to the signal line of the gate line wiring region, the drain of the first thin film transistor is connected to the gate line of the pixel region.
  • the display panel further includes a third thin film transistor and a fourth thin film transistor disposed on a side of the display panel opposite to the first thin film transistor, and a gate of the third thin film transistor is connected to the evaluation indication signal terminal.
  • a source of the third thin film transistor is connected to a third external signal line, a drain of the third thin film transistor is connected to an odd row gate line;
  • a gate of the fourth thin film transistor is connected to an evaluation indication signal terminal, The source of the fourth thin film transistor is connected to the fourth external signal line, and the drain of the fourth thin film transistor is connected to the even row gate line.
  • the detecting switch comprises a second thin film transistor
  • the peripheral wiring area is a data line wiring area
  • a gate of the second thin film transistor is connected to a second external control signal
  • a source of the second thin film transistor Connected to the signal line of the data line wiring area, the drain of the second thin film transistor is connected to the data line of the pixel area.
  • the display panel further includes a fifth thin film transistor and a sixth thin film transistor disposed on a side of the display panel opposite to the second thin film transistor, and the gate of the fifth thin film transistor is connected to the evaluation indication signal terminal a source of the fifth thin film transistor is connected to the fifth external signal line, a drain of the fifth thin film transistor is connected to an odd column data line; a gate of the sixth thin film transistor and an evaluation indication signal terminal Connecting, a source of the sixth thin film transistor is connected to the sixth external signal line, and a drain of the sixth thin film transistor is connected to the even-numbered data line.
  • the detecting switch includes a first thin film transistor and a second thin film transistor
  • the peripheral wiring region includes a gate line wiring region and a data line wiring region
  • a gate of the first thin film transistor is connected to the first external control signal
  • a source of the first thin film transistor is connected to a signal line of the gate line wiring region
  • a drain of the first thin film transistor is connected to a gate line of the pixel region
  • a gate of the second thin film transistor and a second external control signal The source of the second thin film transistor is connected to the signal line of the data line wiring region
  • the drain of the second thin film transistor is connected to the data line of the pixel region.
  • the display panel further includes: a third thin film transistor and a fourth thin film transistor disposed on a side of the display panel opposite to the first thin film transistor, disposed on the display panel and the first a fifth thin film transistor and a sixth thin film transistor on opposite sides of the thin film transistor, a gate of the third thin film transistor is connected to an evaluation indication signal terminal, and a source of the third thin film transistor is connected to a third external signal line a drain of the third thin film transistor is connected to an odd row gate line; a gate of the fourth thin film transistor is connected to an evaluation indication signal terminal, and a gate of the fourth thin film transistor is connected to a fourth external signal line, a drain of the fourth thin film transistor is connected to an even-numbered gate line; a gate of the fifth thin film transistor is connected to an evaluation indication signal terminal, and a source of the fifth thin film transistor is connected to the fifth external signal line a drain of the fifth thin film transistor is connected to an odd column data line; a gate of the sixth thin film transistor is connected to an evaluation indication signal terminal
  • Embodiments of the present invention also provide a display device including the above display panel.
  • the display panel provided by the embodiment of the present invention controls the connection and disconnection of the pixel region and the peripheral wiring region by providing a detection switch between the pixel region and the peripheral wiring region, by observing odd lines in the case of connection and disconnection/
  • the display of the column and its adjacent even row/column pixels is used to determine whether there is a break/short circuit failure and a specific location where the defect occurs.
  • FIG. 1 is a schematic view showing a configuration of a display panel according to a first embodiment of the present invention
  • FIG. 2 is a view showing a configuration of a display panel according to a second embodiment of the present invention
  • FIG. 3 is a view showing the first aspect of the present invention.
  • a display panel provided by an embodiment of the present invention includes a pixel area and a peripheral wiring area
  • a detection switch is disposed between the pixel region and the peripheral wiring region, and the detection switch corresponds to a gate line of the pixel region, and the detection switch is configured to control connection and disconnection between the pixel region and the peripheral wiring region.
  • the detecting switch includes a first thin film transistor, a gate of the first thin film transistor is connected to the first external control signal, and a source of the first thin film transistor is connected to a signal line of the gate wiring area, the first thin film A drain of the transistor is connected to a gate line of the pixel region.
  • the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain is used as the signal output, and vice versa.
  • Fig. 1 shows a schematic view of the configuration of a display panel 100 according to a first embodiment of the present invention.
  • a display panel 100 according to a first embodiment of the present invention includes a pixel area A at the center, a peripheral wiring area (including a gate line wiring area 5 and a data line wiring area 9) outside the pixel area A, and a pixel area.
  • the data line 10 and the gate line 11 in the pixel area A are respectively connected to the signal line wiring area 9 and the signal line line of the gate line wiring area 5 in the peripheral wiring area.
  • a common electrode wiring 7 is also provided on the display panel 100.
  • the short-circuiting ring 14 and the anti-static circuit 6 connected thereto are short-circuit patterns provided on the edge of the pixel region of the display panel for preventing static electricity generated during the manufacturing process of the display panel, which are utilized in the pixel region and the periphery proposed by the embodiment of the present invention.
  • the detection switch provided between the wiring areas is independent of the inventive idea of detecting the short circuit/open circuit, and will not be described in detail herein.
  • the first thin film transistor 12 and the third are further disposed on the display panel 100 in the first embodiment of the present invention.
  • the gate of the first thin film transistor 12 is connected to the first external signal line GS, the source of the first thin film transistor 12 is connected to the signal line of the gate line wiring region, and the drain of the first thin film transistor 12 is The gate lines of the pixel regions are connected.
  • the third thin film transistor 3 and the fourth thin film transistor 4 are disposed on the display panel 100 and disposed on a side opposite to the first thin film transistor 12, and the gate of the third thin film transistor 3 is connected to the evaluation indication signal terminal EN, and the third The source of the thin film transistor 3 is connected to the third external signal line GO, the drain of the third thin film transistor 3 is connected to the odd-numbered gate line; the gate of the fourth thin film transistor 4 is connected to the evaluation indicating signal terminal EN The source of the fourth thin film transistor 4 is connected to the fourth external signal line GE, and the drain of the fourth thin film transistor 4 is connected to the even-numbered gate lines.
  • Step 1 Check if there is a short circuit/open circuit in the display panel
  • the pulse signal is alternately applied to the third external signal line GO and the fourth external signal line GE to observe whether there is a phenomenon in which two adjacent rows of pixel units are simultaneously displayed or whether a corresponding row of the applied signal has a pixel unit that cannot be normally displayed.
  • the fourth row of pixels is displayed simultaneously with the third row, such as simultaneous display, indicating that the adjacent two rows of pixels have a short circuit, such as The adjacent two rows of pixel units are alternately displayed with the third external signal line GO and the fourth external signal line GE at the same frequency, indicating that the adjacent two rows of pixels are not short-circuited.
  • a signal is applied to the third row of pixel units to display the third row of pixel units, one or more of the pixel units in the third row of pixel units cannot be normally displayed, indicating that an open circuit exists.
  • scan detection or jog detection is performed on pixels that cannot be displayed normally, and the specific location where the disconnection occurs is determined and repaired.
  • the second step judging whether the pixel area A is short-circuited or the peripheral wiring area is short-circuited;
  • Step 3 Repair the short-circuit area. If a short circuit occurs in the pixel area, the adjacent two gate lines short-circuited in the pixel area are scanned to determine the specific short-circuit position, and the short-circuit position is entered. If the short circuit occurs in the peripheral wiring area, the signal line corresponding to the gate line short-circuited to the pixel area in the peripheral wiring area is scanned to determine the specific position of the short circuit, and the short-circuit position is repaired.
  • All of the thin film transistors described above may be N-type thin film transistors or P-type thin film transistors. If an N-type thin film transistor is used, a high level is applied when the thin film transistor is required to be turned on, and is applied when the thin film transistor is required to be turned off. Low level; if it is a P-type thin film transistor, a low level is applied when the thin film transistor is required to be turned on, and a high level is applied when the thin film transistor is required to be turned off.
  • the high voltage of the external signal terminal GS is generally in the range of 15V to 50V, and the low voltage is in the range of -20V to 0V; the third external signal line GO and the fourth external signal The voltage of line GE is the same as the gate voltage when the display panel is operating.
  • Another display panel includes a pixel area and a peripheral wiring area, and a detection switch is disposed between the pixel area and the peripheral wiring area, and the detection switch corresponds to a data line of the pixel area, and the detection switch Used to control the connection and disconnection of the pixel area and the peripheral wiring area.
  • the detecting switch includes a second thin film transistor, the peripheral wiring area is a data line wiring area, the gate of the second thin film transistor is connected to the second external control signal, and the source of the second thin film transistor and the data line wiring area The signal lines are connected, and the drain of the second thin film transistor is connected to the data line of the pixel region.
  • Fig. 2 shows a schematic view of the configuration of a display panel 200 according to a second embodiment of the present invention.
  • the display panel 200 according to the second embodiment of the present invention shown in FIG. 2 is different from the configuration of the display panel 100 according to the first embodiment of the present invention shown in FIG. 1 in that the display panel 200 is in the pixel area A and A second thin film transistor 13 is disposed between the data line wiring regions 9 in the peripheral wiring region.
  • the gate of the second thin film transistor 13 is connected to the second external signal terminal DS to control the switching state of the second thin film transistor 13 by applying a signal to the second external signal terminal DS.
  • the second thin film transistor 13 is for controlling connection and disconnection of the wiring area around the data line and the pixel area.
  • a fifth thin film transistor 1 and a sixth thin film transistor 2 which are disposed on the side opposite to the data line wiring region 9 on the display panel 200, and a fifth thin film transistor 1 are further included.
  • a gate is connected to the evaluation indicating signal terminal EN, a source of the fifth thin film transistor 1 is connected to the fifth external signal line DO, and a drain of the fifth thin film transistor 1 is connected to an odd column data line;
  • the sixth film The gate of the transistor 2 is connected to the evaluation indicating signal terminal EN, the source of the sixth thin film transistor 2 is connected to the sixth external signal line DE, and the drain of the sixth thin film transistor 2 and the even-numbered column data Wire connection.
  • Step 1 Detect whether there is an open/short circuit in the display panel
  • scan detection or inching detection is performed on the pixel unit that cannot be normally displayed, and the specific position of the disconnection is determined and repaired.
  • the second step judging whether the pixel area A is short-circuited or the peripheral wiring area is short-circuited;
  • Step 3 Repair the short-circuit area. If a short circuit occurs in the pixel area, the adjacent two data lines short-circuited in the pixel area are scanned to determine the specific short-circuit position, and the short-circuit position is repaired; if the short-circuit occurs in the peripheral wiring area, the pixel is in the peripheral wiring area. The signal line corresponding to the data line of the area short circuit is scanned to determine the specific position of the short circuit, and the short circuit position is repaired.
  • a third display panel provided by the embodiment of the present invention includes a pixel area and a peripheral wiring area, and a detection switch is disposed between the pixel area and the peripheral wiring area, and the detection switch and the pixel line and the data line of the pixel area correspond to each other.
  • the detection switch is used to control the connection and disconnection of the pixel area and the peripheral wiring area.
  • the detecting switch includes a first thin film transistor and a second thin film transistor
  • the peripheral wiring region includes a gate line wiring region and a data line wiring region
  • a gate of the first thin film transistor is connected to the first external control signal line
  • a source of a thin film transistor is connected to a signal line of the gate line wiring region
  • a drain of the first thin film transistor is connected to a gate line of the pixel region
  • a gate of the second thin film transistor is connected to a second external control signal
  • the source of the second thin film transistor is connected to the signal line of the data line wiring region
  • the drain of the second thin film transistor is connected to the data line of the pixel region.
  • FIG. 3 shows a schematic diagram of the configuration of a display panel 300 according to a third embodiment of the present invention.
  • the display panel 300 includes a first thin film transistor 12 and a second thin film transistor 13.
  • the gate of the first thin film transistor 12 is connected to the first external control signal line GS, and the source and gate wiring of the first thin film transistor 12 are connected.
  • the signal lines of the region 5 are connected, the drain of the first thin film transistor 12 is connected to the gate line 11 of the pixel region; and the gate of the second thin film transistor 13 is connected to the second external control signal line DS, and the second thin film transistor 13 is connected.
  • the source is connected to the signal line of the data line wiring region 9, and the drain of the second thin film transistor 13 is connected to the data line 10 of the pixel region.
  • the display panel 300 further includes a third thin film transistor 3 and a fourth thin film transistor 4 disposed on a side of the display panel 300 opposite to the first thin film transistor 12, and disposed on the display panel 300.
  • a fifth thin film transistor 1 and a sixth thin film transistor 2 on a side opposite to the second thin film transistor 13 a gate of the third thin film transistor 3 is connected to an evaluation indicating signal terminal EN, and a source of the third thin film transistor 3 is
  • the third external signal line GO is connected, the drain of the third thin film transistor 3 is connected to the odd-numbered gate lines; the gate of the fourth thin film transistor 4 is connected to the evaluation indicating signal terminal EN, and the gate and the fourth thin film transistor 4 are connected.
  • the external signal line GE is connected, the drain of the fourth thin film transistor 4 is connected to the even row gate line; the gate of the fifth thin film transistor 1 is connected to the evaluation indicating signal terminal EN, and the source and the fifth external signal of the fifth thin film transistor 1 are connected.
  • the line DO is connected, the drain of the fifth thin film transistor 1 is connected to the odd column data line; the gate of the sixth thin film transistor 2 is connected to the evaluation indicating signal terminal EN, and the source of the sixth thin film transistor 2 and the sixth external signal line DE Connected, the drain of the sixth thin film transistor 2 is connected to the even-numbered column data lines.
  • the process of short-circuiting or disconnecting the gate line and the data line using the display panel is substantially the same as the detection process in the first and second embodiments, and will not be described again.
  • the detection order may not be fixed, and the data line may be detected first, then the gate line may be detected, or the gate line may be detected first, and then the data line is detected, which is not limited.
  • a thin film transistor as a switch for detecting is disposed on a side of the pixel area of the display panel near the peripheral wiring area, so that the current for detecting passes through the peripheral area while passing through the pixel area, thereby It can be easily judged whether a short circuit appears in the pixel area or in the peripheral wiring area.

Abstract

一种显示面板和显示装置，包括像素区域（A）和周边布线区域，其特征在于，所述像素区域（A）和周边布线区域之间设置有检测开关，所述检测开关与像素区域（A）的栅线（11）和/或数据线（10）均一一对应，所述检测开关用于控制像素区域（A）和周边布线区域的连接与断开。采用该显示面板，能够准确、快速的检测是否有短路或断路不良及不良发生的具体位置，在检测过程中仅需对小区域的信号线进行寸动检测，节省了检测时间，提高了检测效率。

Description

显示面板和显示装置 技术领域
本发明涉及一种显示面板， 尤其涉及一种能够检测短路不良的显示面 板。 背景技术
显示面板基于其低电压、 辐射小、 重量轻以及体积小等优点现越来越 被大众所接受。 而对于显示面板设计及制作者来说， 期望的是制作出高质 量、 低成本、 少瑕疵的产品。
显示面板的外围电路常因需节省空间或其他因素， 需要对外围电路路 径做最佳设置。 而无论外围电路如何变化， 作为显示面板有两部分必不可 少， 一部分是连接集成电路（IC ) 与像素区域的周边布线区域， 其功能是 将 IC输出的信号传入像素区域， 使显示面板正常显示画面； 另一部分是 显示画面区域的像素区域。 只要这两部分中的任何一部分发生断路或短 路， 显示面板显示就会出现线状不良， 需维修人员以寸动方式， 沿该线状 不良从 IC处一直移动到像素区域末端， 来寻找该缺陷点进行修复。 而现 有的不良点的寻找方式速度有限， 严重增加人力成本， 浪费产能； 长时间 的寻找易造成维修人员的疲劳， 降低缺陷点的搜寻效率。 随着工艺的发展 以及市场的需求， 现在显示面板逐渐向窄、 薄、 轻方向发展； 这对面板内 部线路的要求越来越严格， 为了实现窄边框， 需要线路尽可能的细， 间距 尽可能的小。 随着线路的变细， 间距变小， 面板内部发生短路与断路的可 能性随之增加，此时对于短路与断路的定位与维修就十分重要。对于断路， 已有很多方法， 而对于短路不良的判定， 为数不多。 发明内容
本发明的实施例提供了一种显示面板， 采用该显示面板设计能够准确 地、 快速的检测出是否有短路和断路不良， 及发生不良的具体位置。
为此， 本发明的实施例提供了一种显示面板， 包括像素区域和周边布 线区域，其特征在于，所述像素区域和周边布线区域之间设置有检测开关， 所述检测开关与像素区域的栅线和 /或数据线——对应，所述检测开关用于 控制像素区域和周边布线区域的连接与断开。
优选地， 所述检测开关包括第一薄膜晶体管， 所述周边布线区域为栅 线布线区域， 所述第一薄膜晶体管的栅极与第一外接控制信号连接， 所述 第一薄膜晶体管的源极与所述栅线布线区域的信号线连接， 所述第一薄膜 晶体管的漏极与所述像素区域的栅线连接。
优选地， 所述显示面板还包括设置在显示面板与第一薄膜晶体管相对 的一侧的第三薄膜晶体管和第四薄膜晶体管， 所述第三薄膜晶体管的栅极 与评估指示信号端子连接， 所述第三薄膜晶体管的源极与第三外接信号线 连接， 所述第三薄膜晶体管的漏极与奇数行栅线连接； 所述第四薄膜晶体 管的栅极与评估指示信号端子连接， 所述第四薄膜晶体管的源极与第四外 接信号线连接， 所述第四薄膜晶体管的漏极与偶数行栅线连接。
优选地， 所述检测开关包括第二薄膜晶体管， 所述周边布线区域为数 据线布线区域， 所述第二薄膜晶体管的栅极与第二外接控制信号连接， 所 述第二薄膜晶体管的源极与所述数据线布线区的信号线连接， 所述第二薄 膜晶体管的漏极与所述像素区域的数据线连接。
优选地， 所述显示面板还包括设置在显示面板与所述第二薄膜晶体管 相对的一侧的第五薄膜晶体管和第六薄膜晶体管， 所述第五薄膜晶体管的 栅极与评估指示信号端子连接， 所述第五薄膜晶体管的源极与所述第五外 接信号线连接， 所述第五薄膜晶体管的漏极与奇数列数据线连接； 所述第 六薄膜晶体管的栅极与评估指示信号端子连接， 所述第六薄膜晶体管的源 极与所述第六外接信号线连接， 所述第六薄膜晶体管的漏极与所述偶数列 数据线连接。
优选地， 所述检测开关包括第一薄膜晶体管和第二薄膜晶体管， 以及 所述周边布线区域包括栅线布线区域和数据线布线区域； 第一薄膜晶体管 的栅极与第一外接控制信号连接， 第一薄膜晶体管的源极与所述栅线布线 区域的信号线连接， 第一薄膜晶体管的漏极与所述像素区域的栅线连接； 以及第二薄膜晶体管的栅极与第二外接控制信号连接， 第二薄膜晶体管的 源极与所述数据线布线区的信号线连接， 第二薄膜晶体管的漏极与所述像 素区域的数据线连接。
优选地， 所述显示面板还包括： 设置在显示面板与第一薄膜晶体管相 对的一侧的第三薄膜晶体管和第四薄膜晶体管、 设置在显示面板与所述第 二薄膜晶体管相对的一侧的第五薄膜晶体管和第六薄膜晶体管， 所述第三 薄膜晶体管的栅极与评估指示信号端子连接， 所述第三薄膜晶体管的源极 与第三外接信号线连接， 所述第三薄膜晶体管的漏极与奇数行栅线连接； 所述第四薄膜晶体管的栅极与评估指示信号端子连接， 所述第四薄膜晶体 管的栅极与第四外接信号线连接， 所述第四薄膜晶体管的漏极与偶数行栅 线连接； 所述第五薄膜晶体管的栅极与评估指示信号端子连接， 所述第五 薄膜晶体管的源极与所述第五外接信号线连接， 所述第五薄膜晶体管的漏 极与奇数列数据线连接； 所述第六薄膜晶体管的栅极与评估指示信号端子 连接， 所述第六薄膜晶体管的源极与所述第六外接信号线连接， 所述第六 薄膜晶体管的漏极与所述偶数列数据线连接。
本发明的实施例还提供了一种显示装置， 其包括上述的显示面板。 本发明的实施例提供的显示面板， 通过在像素区域和周边布线区域之 间设置有检测开关， 控制像素区域和周边布线区域的连接与断开， 通过观 察在连接和断开情况下奇数行 /列和与其相邻偶数行 /列像素的显示来判断 是否有断路 /短路不良的发生和不良发生的具体位置。 附图说明
通过结合附图的以下描述， 将会更容易地理解本发明的实施例并且更 容易地理解其伴随的优点和特征， 其中：
图 1示出了根据本发明第一实施例的显示面板的构造的示意图； 图 2示出了根据本发明第二实施例的显示面板的构造的示意图； 以及 图 3示出了根据本发明第三实施例的显示面板的构造的示意图。 具体实施方式
为了使本发明实施例的内容更加清楚和易于理解， 下面结合附图对本 发明的具体实施例进行详细描述。 在本发明实施例中， 以示例方式， 对本 发明实施例提出的显示面板进行了说明， 但是本发明不限于所公开的具体 容对本发明实施例进行修改和变型， 这些修改和变型也应当属于由权利要 求限定的本发明保护的范围。
本发明的实施例提供的一种显示面板， 包括像素区域和周边布线区 域， 像素区域和周边布线区域之间设置有检测开关， 检测开关与像素区域 的栅线——对应， 所述检测开关用于控制像素区域和周边布线区域的连接 与断开。
具体地， 检测开关包括第一薄膜晶体管， 第一薄膜晶体管的栅极与第 一外接控制信号连接， 第一薄膜晶体管的源极与所述栅线布线区域的信号 线连接， 所述第一薄膜晶体管的漏极与所述像素区域的栅线连接。
由于这里采用的开关晶体管的源极、 漏极是对称的， 所以其源极、 漏 极是可以互换的。 在本发明实施例中， 为区分晶体管除栅极之外的两极， 将其中一极称为源极， 另一极称为漏极。 若选取源极作为信号输入端、 则 漏极作为信号输出端， 反之亦然。
图 1示出了根据本发明第一实施例的显示面板 100的构造的示意图。 如图 1所示， 根据本发明第一实施例的显示面板 100包括处于中央的像素 区域 A、 像素区域 A外部的周边布线区域（包括栅线布线区域 5和数据线 布线区域 9 )、 像素区域 A内的数据线 10和栅线 11、 短路环 14、 栅极数 据线防静电电路 6和线路图案（pattern on line, PLG ) 8。 其中， 像素区域 A内的数据线 10和栅线 11分别与周边布线区域内的数据线布线区域 9和 栅线布线区域 5的信号线连接。 在显示面板 100上还设置了共用电极布线 7。 短路环 14和与其相连的防静电电路 6是用于防止显示面板制造过程中 产生的静电而设置在显示面板的像素区域边缘的短路图形， 其与本发明实 施例提出的利用在像素区域和周边布线区域之间设置的检测开关来对短 路 /断路进行检测的发明思想无关， 在此不进行详细描述。
为了使得本发明实施例的显示面板能够进行开关式检测从而对显示 面板 100上的线路问题进行检测， 在本发明第一实施例中的显示面板 100 上还设置了第一薄膜晶体管 12、 第三薄膜晶体管 3、 第四薄膜晶体管 4。
其中， 第一薄膜晶体管 12的栅极与第一外接信号线 GS连接， 第一薄 膜晶体管 12的源极与所述栅线布线区域的信号线连接， 所述第一薄膜晶 体管 12的漏极与所述像素区域的栅线连接。 第三薄膜晶体管 3和第四薄 膜晶体管 4设置在显示面板 100上， 且设置在与第一薄膜晶体管 12相对 的一侧， 第三薄膜晶体管 3的栅极与评估指示信号端子 EN连接， 第三薄 膜晶体管 3的源极与第三外接信号线 GO连接， 第三薄膜晶体管 3的漏极 与奇数行栅线连接； 第四薄膜晶体管 4的栅极与评估指示信号端子 EN连 接， 所述第四薄膜晶体管 4的源极与第四外接信号线 GE连接， 所述第四 薄膜晶体管 4的漏极与偶数行栅线连接。
应用本显示面板进行检测的过程具体如下：
第一步： 检测显示面板中是否有短路 /断路不良；
具体过程为：
1、 给第一外接信号线 GS施加信号， 使第一薄膜晶体管 12导通；
2、 给评估指示信号端子 EN施加信号， 使第三薄膜晶体管 3和第四 薄膜晶体管 4导通；
3、 给第三外接信号线 GO和第四外接信号线 GE交替施加脉沖信号， 观察是否有相邻两行像素单元同时显示的现象或施加信号的对应行是否 有不能正常显示的像素单元。
例如： 在给第三行像素单元施加信号使第三行像素单元显示的同时， 第四行像素是否与第三行同时显示， 如同时显示， 说明这相邻的两行像素 有短路， 如相邻两行像素单元与第三外接信号线 GO和第四外接信号线 GE同频率交替显示， 则说明该相邻两行像素没有短路。 或在给第三行像 素单元施加信号使第三行像素单元显示时， 第三行像素单元中有一个或多 个像素单元不能正常显示， 则说明有断路存在。
如为断路情况， 则对不能正常显示的像素进行扫描检测 （或寸动检 测）， 确定断路发生的具体位置， 并进行修复。
如有短路情况， 则进行第二步和第三步：
第二步： 判断是像素区域 A短路还是周边布线区域短路；
具体过程如下：
1、 给第一外接信号线 GS施加信号， 使第一薄膜晶体管 12截止；
2、 给评估指示信号端子 EN施加信号， 使第三薄膜晶体管 3和第四 薄膜晶体管 4导通；
3、 给第三外接信号线 GO和第四外接信号线 GE交替施加脉沖信号， 同时， 输入使各像素单元显示相同灰度的数据信号， 观察在第一步中出现 短路的相邻两行像素单元是否还同时显示， 如同时显示， 说明短路发生在 像素区域， 如不再同时显示， 说明短路发生在周边布线区域。
第三步： 对短路区域进行修复。 如短路发生在像素区域， 对像素区域 发生短路的相邻的两条栅线进行扫描， 确定具体短路位置， 对短路位置进 行修复； 如短路发生在周边布线区域， 则对周边布线区域中与像素区域短 路的栅线对应的信号线进行扫描， 确定短路的具体位置， 对短路位置进行 修复。
以上所述的所有薄膜晶体管可以为 N型薄膜晶体管，也可以为 P型薄 膜晶体管， 若为 N型薄膜晶体管， 则在需要薄膜晶体管导通时， 施加高电 平， 在需要薄膜晶体管截止时施加低电平； 如为 P型薄膜晶体管， 则在需 要薄膜晶体管导通时施加低电平， 在需要薄膜晶体管截止时施加高电平。
采用上述的液晶面板设计， 能够准确、 快速的检测是否有短路或断路 不良及不良发生的具体位置， 在检测过程中仅需对小区域的信号线进行寸 动检测， 节省了检测时间， 提高了检测效率。
对于 8"的 1280x800的显示面板而言， 外接信号端子 GS的高电压一 般在 15V至 50V的范围内， 而低电压在 -20V至 0V的范围内； 第三外接 信号线 GO和第四外接信号线 GE的电压与显示面板工作时栅极电压相同。
本发明的实施例提供的另一种显示面板， 包括像素区域和周边布线区 域， 像素区域和周边布线区域之间设置有检测开关， 检测开关与像素区域 的数据线——对应， 所述检测开关用于控制像素区域和周边布线区域的连 接与断开。
具体的， 检测开关包括第二薄膜晶体管， 周边布线区域为数据线布线 区域， 第二薄膜晶体管的栅极与第二外接控制信号连接， 第二薄膜晶体管 的源极与所述数据线布线区的信号线连接， 第二薄膜晶体管的漏极与所述 像素区域的数据线连接。
图 2示出了根据本发明第二实施例的显示面板 200的构造的示意图。 图 2所示的根据本发明第二实施例的显示面板 200与图 1所示的根据 本发明第一实施例的显示面板 100的构造不同之处在于，显示面板 200中， 在像素区域 A与周边布线区域中的数据线布线区域 9之间设置了第二薄膜 晶体管 13。 第二薄膜晶体管 13的栅极与第二外接信号端子 DS相连， 以 通过在第二外接信号端子 DS上施加信号来控制第二薄膜晶体管 13的开关 状态。 第二薄膜晶体管 13用于控制数据线周边布线区与像素区域的连接 与断开。
在显示面板 200中，还包括在显示面板 200上与数据线布线区域 9相 对一侧设置的第五薄膜晶体管 1和第六薄膜晶体管 2, 第五薄膜晶体管 1 的栅极与评估指示信号端子 EN连接， 第五薄膜晶体管 1的源极与第五外 接信号线 DO连接， 所述第五薄膜晶体管 1的漏极与奇数列数据线连接； 所述第六薄膜晶体管 2的栅极与评估指示信号端子 EN连接， 所述第六薄 膜晶体管 2的源极与所述第六外接信号线 DE连接， 所述第六薄膜晶体管 2的漏极与所述偶数列数据线连接。
应用本显示面板进行检测的过程具体如下：
第一步： 检测显示面板中是否有断路 /短路；
具体过程为：
1、 给第一外接信号线 DS施加信号， 使第二薄膜晶体管 13导通； 2、 给评估指示信号端子 EN施加信号， 使第五薄膜晶体管 1和第六 薄膜晶体管 2导通；
3、 给第五外接信号线 DO和第六外接信号线 DE交替施加脉沖信号， 同时给栅线输入信号， 使各行中用于控制像素显示的像素薄膜晶体管均导 通， 观察是否有相邻两列像素单元同时显示的现象或是否有像素单元不能 正常显示。
例如： 在给第三列像素单元施加信号使第三列像素单元显示的同时， 第四列像素是否与第三列同时显示， 如同时显示， 说明这相邻的两列像素 有短路， 如相邻两列像素单元与第五外接信号线 DO和第六外接信号线 DE同频率交替显示， 则说明该相邻两列像素没有短路。 如在给第三列像 素单元施加信号使第三列像素单元显示时， 第三列中有一个或多个像素单 元不能正常显示， 则说明有断路现象存在。
如有断路情况， 则对该不能正常显示的像素单元进行扫描检测（或寸 动检测）， 确定断路的具体位置， 并进行修复。
如有短路情况， 则进行第二步和第三步：
第二步： 判断是像素区域 A短路还是周边布线区域短路；
具体过程如下：
1、 给第二外接信号线 DS施加信号， 使第二薄膜晶体管 13截止；
2、 给评估指示信号端子 EN施加信号， 使第五薄膜晶体管 1和第六 薄膜晶体管 2导通；
3、 给第五外接信号线 DO和第六外接信号线 DE交替施加脉沖信号， 观察在第一步中出现短路的相邻两列像素单元是否还同时显示， 如同时显 示， 说明短路发生在像素区域， 如不再同时显示， 说明短路发生在周边布 线区域。
第三步： 对短路区域进行修复。 如短路发生在像素区域， 对像素区域 发生短路的相邻的两条数据线进行扫描， 确定具体短路位置， 对短路位置 进行修复； 如短路发生在周边布线区域， 则对周边布线区域中与像素区域 短路的数据线对应的信号线进行扫描， 确定短路的具体位置， 对短路位置 进行修复。
采用上述的液晶面板设计， 能够准确、 快速的检测是否有短路或断路 不良及不良发生的具体位置， 在检测过程中仅需对小区域的信号线进行寸 动检测， 节省了检测时间， 提高了检测效率。
本发明的实施例提供的第三种显示面板， 包括像素区域和周边布线区 域， 像素区域和周边布线区域之间设置有检测开关， 检测开关与像素区域 的栅线和数据线均——对应， 检测开关用于控制像素区域和周边布线区域 的连接与断开。
具体的， 检测开关包括第一薄膜晶体管和第二薄膜晶体管， 以及所述 周边布线区域包括栅线布线区域和数据线布线区域； 第一薄膜晶体管的栅 极与第一外接控制信号线连接， 第一薄膜晶体管的源极与所述栅线布线区 域的信号线连接， 第一薄膜晶体管的漏极与像素区域的栅线连接； 以及第 二薄膜晶体管的栅极与第二外接控制信号连接， 第二薄膜晶体管的源极与 所述数据线布线区的信号线连接， 第二薄膜晶体管的漏极与所述像素区域 的数据线连接。
图 3示出了根据本发明第三实施例的显示面板 300的构造的示意图。 如图 3 ,显示面板 300包括第一薄膜晶体管 12和第二薄膜晶体管 13 , 第一薄膜晶体管 12的栅极与第一外接控制信号线 GS连接，第一薄膜晶体 管 12的源极与栅线布线区域 5的信号线连接， 第一薄膜晶体管 12的漏极 与所述像素区域的栅线 11连接； 以及第二薄膜晶体管 13的栅极与第二外 接控制信号线 DS连接， 第二薄膜晶体管 13的源极与所述数据线布线区 9 的信号线连接， 第二薄膜晶体管 13的漏极与所述像素区域的数据线 10连 接。
显示面板 300还包括设置在显示面板 300上与第一薄膜晶体管 12相 对的一侧的第三薄膜晶体管 3和第四薄膜晶体管 4、 设置在显示面板 300 与所述第二薄膜晶体管 13相对的一侧的第五薄膜晶体管 1和第六薄膜晶 体管 2, 第三薄膜晶体管 3的栅极与评估指示信号端子 EN连接， 第三薄 膜晶体管 3的源极与第三外接信号线 GO连接， 第三薄膜晶体管 3的漏极 与奇数行栅线连接； 第四薄膜晶体管 4的栅极与评估指示信号端子 EN连 接， 第四薄膜晶体管 4的栅极与第四外接信号线 GE连接， 第四薄膜晶体 管 4的漏极与偶数行栅线连接； 第五薄膜晶体管 1的栅极与评估指示信号 端子 EN连接， 第五薄膜晶体管 1的源极与第五外接信号线 DO连接， 第 五薄膜晶体管 1的漏极与奇数列数据线连接； 第六薄膜晶体管 2的栅极与 评估指示信号端子 EN连接， 第六薄膜晶体管 2的源极与第六外接信号线 DE连接， 第六薄膜晶体管 2的漏极与所述偶数列数据线连接。
采用该显示面板对栅线和数据线进行短路或断路不良检测的过程与 实施例 1和 2中的检测过程基本相同， 再此不再赘述。
但在检测时， 其检测顺序可以不固定， 既可以先检测数据线， 再检测 栅线， 也可以先检测栅线， 再检测数据线， 对此不作限定。
采用上述的液晶面板设计， 能够准确、 快速的检测是否有短路或断路 不良及不良发生的具体位置， 在检测过程中仅需对小区域的信号线进行寸 动检测， 节省了检测时间， 提高了检测效率。
以上， 示出了根据本发明的显示面板的三个实施例。 其中， 在显示面 板的像素区域上靠近周边布线区域的一侧上设置了用于进行检测的作为 开关的薄膜晶体管， 使得用于进行检测的电流在经过像素区域的同时也经 过周边布线区域， 从而能够容易地判断短路出现在像素区域内还是出现在 周边布线区域内。
的普通技术人员应当理解， 可以对本发明实施例的技术方案进行修改或者 等同替换， 而不脱离本发明实施例技术方案的精神和范围。

Claims

权 利 要 求 书
1、 一种显示面板， 包括像素区域和周边布线区域， 其特征在于， 所 述像素区域和周边布线区域之间设置有检测开关， 所述检测开关与像素 区域的栅线和 /或数据线——对应， 所述检测开关用于控制像素区域和周 边布线区域的连接与断开。
2、 根据权利要求 1所述的显示面板， 其特征在于， 所述检测开关包 括第一薄膜晶体管， 所述周边布线区域为栅线布线区域， 所述第一薄膜 晶体管的栅极与第一外接控制信号连接， 所述第一薄膜晶体管的源极与 所述栅线布线区域的信号线连接， 所述第一薄膜晶体管的漏极与所述像 素区域的栅线连接。
3、 根据权利要求 2所述的显示面板， 其特征在于， 所述显示面板还 包括设置在显示面板与第一薄膜晶体管相对的一侧的第三薄膜晶体管和 第四薄膜晶体管，所述第三薄膜晶体管的栅极与评估指示信号端子连接， 所述第三薄膜晶体管的源极与第三外接信号线连接， 所述第三薄膜晶体 管的漏极与奇数行栅线连接； 所述第四薄膜晶体管的栅极与评估指示信 号端子连接， 所述第四薄膜晶体管的源极与第四外接信号线连接， 所述 第四薄膜晶体管的漏极与偶数行栅线连接。
4、 根据权利要求 1所述的显示面板， 其特征在于， 所述检测开关包 括第二薄膜晶体管， 所述周边布线区域为数据线布线区域， 所述第二薄 膜晶体管的栅极与第二外接控制信号线连接， 所述第二薄膜晶体管的源 极与所述数据线布线区的信号线连接， 所述第二薄膜晶体管的漏极与所 述像素区域的数据线连接。
5、 根据权利要求 4所述的显示面板， 其特征在于， 所述显示面板还 包括设置在显示面板与所述第二薄膜晶体管相对的一侧的第五薄膜晶体 管和第六薄膜晶体管， 所述第五薄膜晶体管的栅极与评估指示信号端子 连接， 所述第五薄膜晶体管的源极与所述第五外接信号线连接， 所述第 五薄膜晶体管的漏极与奇数列数据线连接； 所述第六薄膜晶体管的栅极 与评估指示信号端子连接， 所述第六薄膜晶体管的源极与所述第六外接 信号线连接， 所述第六薄膜晶体管的漏极与所述偶数列数据线连接。
6、 根据权利要求 1所述的显示面板， 其特征在于， 所述检测开关包 括第一薄膜晶体管和第二薄膜晶体管， 以及所述周边布线区域包括栅线 布线区域和数据线布线区域；
第一薄膜晶体管的栅极与第一外接控制信号连接， 第一薄膜晶体管 的源极与所述栅线布线区域的信号线连接， 第一薄膜晶体管的漏极与所 述像素区域的栅线连接； 以及
第二薄膜晶体管的栅极与第二外接控制信号线连接， 第二薄膜晶体 管的源极与所述数据线布线区的信号线连接， 第二薄膜晶体管的漏极与 所述像素区域的数据线连接。
7、 根据权利要求 6所述的显示面板， 其特征在于， 所述显示面板还 包括： 设置在显示面板与第一薄膜晶体管相对的一侧的第三薄膜晶体管 和第四薄膜晶体管、 设置在显示面板与所述第二薄膜晶体管相对的一侧 的第五薄膜晶体管和第六薄膜晶体管， 所述第三薄膜晶体管的栅极与评 估指示信号端子连接， 所述第三薄膜晶体管的源极与第三外接信号线连 接， 所述第三薄膜晶体管的漏极与奇数行栅线连接； 所述第四薄膜晶体 管的栅极与评估指示信号端子连接， 所述第四薄膜晶体管的栅极与第四 外接信号线连接， 所述第四薄膜晶体管的漏极与偶数行栅线连接； 所述 第五薄膜晶体管的栅极与评估指示信号端子连接， 所述第五薄膜晶体管 的源极与所述第五外接信号线连接， 所述第五薄膜晶体管的漏极与奇数 列数据线连接； 所述第六薄膜晶体管的栅极与评估指示信号端子连接， 所述第六薄膜晶体管的源极与所述第六外接信号线连接， 所述第六薄膜 晶体管的漏极与所述偶数列数据线连接。
8、 一种显示装置， 包括权利要求 1-7任一所述的显示面板。
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