WO2014153921A1 - 非晶硅光电装置及其制造方法 - Google Patents

非晶硅光电装置及其制造方法 Download PDF

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WO2014153921A1
WO2014153921A1 PCT/CN2013/082185 CN2013082185W WO2014153921A1 WO 2014153921 A1 WO2014153921 A1 WO 2014153921A1 CN 2013082185 W CN2013082185 W CN 2013082185W WO 2014153921 A1 WO2014153921 A1 WO 2014153921A1
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layer
substrate
photosensor
patterning process
gate electrode
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PCT/CN2013/082185
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English (en)
French (fr)
Inventor
谢振宇
陈旭
徐少颖
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北京京东方光电科技有限公司
京东方科技集团股份有限公司
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Priority to US14/357,722 priority Critical patent/US9741893B2/en
Publication of WO2014153921A1 publication Critical patent/WO2014153921A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14665—Imagers using a photoconductor layer
    • H01L27/14676—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
    • H01L31/03762—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic Table

Definitions

  • Amorphous silicon photovoltaic device and manufacturing method thereof are Amorphous silicon photovoltaic device and manufacturing method thereof.
  • the present disclosure relates to an amorphous silicon photovoltaic device and a method of fabricating the same. Background technique
  • amorphous silicon optoelectronic devices are mainly used in the field of X-ray diffraction (XRD) detection, such as hospitals, airports, subways, etc., and can be used for the detection of dangerous goods.
  • 1A and 1B are respectively a plan view of a conventional amorphous silicon photovoltaic device and a schematic cross-sectional view taken along line BB of Fig. 1A. As shown in FIG.
  • the amorphous silicon photovoltaic device is formed on a glass substrate 23, which is mainly composed of two parts, and a part is a photodiode-structured photosensor, and the photodiode-structured photosensor comprises: n-type amorphous silicon ( n + a-Si ) layer 10 , amorphous silicon ( a-Si ) layer 11 , p-type amorphous silicon (p + a-Si ) layer 12 and conductive layer 13 , photodiode-structured photosensors are mainly used for receiving light And using a photovoltaic effect to generate a current; the other part is a thin film transistor mainly comprising a gate electrode layer 14, a semiconductor layer including a first insulating layer 15 and an amorphous silicon layer 16, a barrier layer 17, a source/drain electrode layer 18, The protective layer 19 and the transparent conductive layer 20, the main function of the thin film transistor is a switch and a current signal for transmitting the photosensor.
  • Figs. 1A and 1B are cross-sectional views taken along line B-B of Fig. 1A
  • Figs. 9 and 10 are cross-sectional views taken along line C-C of Fig. 1A.
  • a gate electrode layer 14 is formed on the glass substrate 23 by the first mask process.
  • a semiconductor layer is formed on the gate electrode layer 14 and the glass substrate 23 by a second mask process, the semiconductor layer including a first insulating layer 15 and an amorphous silicon layer 16, the first insulating layer 15 being located The upper layer of the gate electrode layer 14 and the amorphous silicon layer 16 are located on the upper layer of the first insulating layer 15.
  • a barrier layer 17 is formed on the semiconductor layer by a third mask process.
  • a source/drain electrode layer 18 is formed on the barrier layer 17 and the semiconductor layer by a fourth mask process.
  • a photodiode-structured photosensor is formed on the source/drain electrode layer 18 by using a fifth mask process, the photosensor comprising: an n-type amorphous silicon (n + a-Si) layer 10, An amorphous silicon (a-Si) layer 11, a p-type amorphous silicon (p + a-Si) layer 12, and a conductive layer 13.
  • a first passivation layer 19 is deposited on the above structure, and a sixth mask is utilized. In the process, via holes are formed in the first passivation layer 19 over the conductive layer 13 of the photosensor and the source/drain electrode layer 18 of the thin film transistor, respectively.
  • a conductive layer 20 is formed on the first passivation layer 19 by a seventh mask process.
  • a via which reaches the gate electrode layer 14 is formed as a region of the gate line which is a part of the gate electrode layer 14 as the second passivation layer 21.
  • a transparent conductive layer 22 is formed over the via hole of the second passivation layer 21 by the ninth mask process.
  • the present disclosure provides an amorphous silicon photovoltaic device and a method of fabricating the same, which can reduce the manufacturing process of the amorphous silicon photovoltaic device, improve manufacturing efficiency, and reduce cost.
  • a method of fabricating an amorphous silicon photovoltaic device includes: performing a first patterning process, forming a gate electrode layer on a substrate, a photosensor of a photodiode structure, and the photosensor a pattern of the contact layer below, the contact layer is not completely covered by the photosensor, the contact layer is disposed in the same layer as the gate electrode layer and has the same material; performing a second patterning process, obtained in the first patterning process Forming an insulating layer, a semiconductor layer, and a source/drain electrode layer on the substrate; and forming a first passivation layer on the substrate obtained by the second patterning process, performing a third patterning process in the first passivation layer Forming a first via hole exposing the contact layer, the photosensor, and the source/drain electrode layer portion.
  • the method further includes: performing a fourth patterning process, forming a conductive layer on the substrate obtained by the third patterning process, the conductive layer covering the first via and the source electrode and the The semiconductor layer region between the drain electrodes is connected to the source electrode or the drain electrode in the source/drain electrode layer.
  • the method further includes: forming a second passivation layer on the substrate obtained by the fourth patterning process, performing a fifth patterning process, and forming at least a portion of the gate line region in the second passivation layer a second via hole; performing a sixth patterning process, forming a first transparent conductive layer covering the second via hole on the substrate obtained by the fifth patterning process.
  • the step of performing a first patterning process, forming a pattern of a gate electrode layer, a photodiode, and a contact layer under the photosensor on the substrate includes: Forming the gate electrode layer, the semiconductor layer, the transparent conductive layer, and the photoresist; and performing exposure development processing, etching processing, and ashing on the substrate subjected to the above processing to form a gate electrode layer, a gate line contact layer, and a photo sensor .
  • the step of performing exposure and development processing on the substrate subjected to the above processing comprises: partially exposing a photoresist located above the gate electrode layer, the gate line, and the contact layer region not covered by the photo sensor to form a photoresist Partially exposed areas; the photoresist over the photosensor is not exposed at all, forming a completely unexposed area; and the photoresist coated on the other areas is completely exposed to form a fully exposed area.
  • the substrate subjected to the above processing is subjected to an etching process and an ashing process to: etch the second transparent conductive layer in the photosensor of the photodiode structure, and the second transparent region of the fully exposed region
  • the conductive layer is etched away; the semiconductor layer in the photosensor of the photodiode structure is etched to etch away the semiconductor layer in the photosensor of the photodiode structure in the fully exposed region; and the gate electrode layer is etched, Etching the gate electrode layer of the fully exposed region; ashing the photoresist in the partially exposed region by an ashing process; etching the second transparent conductive layer in the photosensor of the photodiode structure, and partially exposing the portion Etching the second transparent conductive layer; etching the semiconductor layer in the photosensor of the photodiode structure, etching the semiconductor layer in the photosensor of the photodiode structure in the partially exposed region; and leaving the remaining on the substrate
  • the photoresist is completely stripped off.
  • an amorphous silicon photovoltaic device including a substrate, a thin film transistor and a photodiode-structured photosensor disposed at different positions on the substrate, and a contact layer, the contact layer being located Below the photosensor, the contact layer is not completely covered by the photosensor, and the contact layer is disposed in the same layer as the gate electrode layer of the thin film transistor and has the same material.
  • a first passivation layer is overlaid on the photosensor and the thin film transistor, and the contact layer, the photosensor, and the thin film transistor are disposed in the first passivation a first via exposed from a portion of the source/drain electrode layer, and a conductive layer disposed over the first passivation layer, the conductive layer covering the first via and located in the thin film transistor a semiconductor layer region between the source electrode and the drain electrode, and the contact layer is in communication with a source electrode or a drain electrode in the thin film transistor.
  • FIG. 1A and 1B are a plan view of a conventional amorphous silicon photovoltaic device and a schematic cross-sectional view taken along line B-B of Fig. 1A;
  • 2-10 are schematic cross-sectional views showing structures obtained at various stages in a manufacturing process of a conventional amorphous silicon photovoltaic device
  • FIG. 11 is a schematic flow chart of a method for manufacturing an amorphous silicon photovoltaic device according to the present disclosure
  • 12A and 12B are a plan view schematically showing a resultant structure after mask exposure development processing in the first masking process of the present disclosure, and a schematic cross-sectional view taken along line B - B in Fig. 12A;
  • 13A-13F are schematic cross-sectional views showing the structure obtained in each stage of the etching process after the mask exposure development process in the first mask process of the present disclosure
  • 14A and 14B are a plan view showing a structure obtained after stripping of a photoresist in the first masking process of the present disclosure, and a cross-sectional view taken along line B-B in Fig. 14A;
  • Figure 15A is a plan view showing the structure obtained after the second mask process of the present disclosure.
  • 15B and 15C are schematic cross-sectional views of the structure obtained after the second mask process of the present disclosure taken along lines B-B and C-C in Fig. 15A, respectively;
  • Figure 16A is a plan view showing the structure obtained after the third mask process of the present disclosure.
  • 16B and 16C are schematic cross-sectional views of the structure obtained after the third mask process of the present disclosure taken along lines B-B and C-C in Fig. 16A;
  • FIG. 17A is a plan view schematically showing a structure obtained after the fourth mask process of the present disclosure
  • FIGS. 17B and 17C are schematic cross-sectional views of the structure obtained after the fourth mask process of the present disclosure taken along lines BB and CC of FIG. 17A. ;
  • Figure 18A is a plan view schematically showing a structure obtained after the fifth mask process of the present disclosure
  • Figure 18C is a schematic cross-sectional view of the structure obtained after the fifth mask process of the present disclosure taken along line C-C of Figure 18A;
  • Figure 19 is a schematic cross-sectional view showing the structure obtained after the sixth mask process of the present disclosure
  • 20 is a schematic cross-sectional view of an amorphous silicon photovoltaic device of the present disclosure.
  • a first patterning process forming a gate electrode layer, a photosensor of a photodiode structure, and a pattern of a contact layer under the photosensor on the substrate, the contact layer is not completely covered by the photosensor, and the contact layer and the gate electrode layer
  • the same layer is disposed and the materials are the same;
  • the second patterning process is performed, and the patterns of the insulating layer, the semiconductor layer, and the source/drain electrode layers are sequentially formed on the structure obtained by the first patterning process; and the structure obtained in the second patterning process
  • a first passivation layer is formed thereon, and a third patterning process is performed, and a first via hole exposing a portion of the contact layer, the photosensor, and the source/drain electrode layer is formed in the first passivation layer.
  • the patterning process may be specifically a mask process, and the substrate may be specifically a glass substrate.
  • the semiconductor layer may specifically include: an amorphous silicon layer, an n-type amorphous silicon layer, and/or a P-type amorphous silicon layer.
  • the transparent conductive layer may specifically be an indium tin oxide (ITO) layer.
  • FIG. 11 is a flow diagram of a method for fabricating an amorphous silicon photovoltaic device of the present disclosure.
  • the method includes the following steps: Step 101: Perform a first mask process, forming a gate electrode and a gate line of a thin film transistor, a photosensor of a photodiode structure, and a contact layer under the photosensor on a substrate Graphics.
  • the contact layer is not completely covered by the photosensor, and the contact layer is disposed in the same layer as the gate electrode layer and has the same material.
  • the step of performing a first mask process, forming a gate electrode of the thin film transistor, a sensor of the photodiode structure, and a pattern of the contact layer under the photosensor on the substrate may specifically include: sequentially forming a gate electrode layer on the substrate, a semiconductor layer, a transparent conductive layer, and a photoresist; and a gate electrode, a contact layer, and a photosensor for forming a thin film transistor by performing exposure development processing, etching treatment, and ashing on the above structure.
  • the exposure and development processing described above may specifically include: forming a partial exposure region of the photoresist over the gate electrode, the gate line, and the contact layer region not covered by the photosensor corresponding to the thin film transistor by using a half mask technique; The photoresist over the sensor is not exposed at all, forming a completely unexposed area; the photoresist coated in the other areas is completely exposed to form a fully exposed area.
  • the substrate subjected to the above-mentioned processing is subjected to etching treatment and ashing treatment to: etch the transparent conductive layer in the photosensor of the photodiode structure, and etch away the transparent conductive layer in the completely exposed region;
  • the semiconductor layer in the photosensor of the diode structure is etched to etch away the semiconductor layer in the photosensor of the photodiode structure in the fully exposed region;
  • the gate electrode layer is etched to form the gate electrode layer in the fully exposed region Etching off; using a ashing process to ash a portion of the exposed area of the photoresist; etching the transparent conductive layer in the photosensor of the photodiode structure, etching the transparent conductive layer of the partially exposed area;
  • the semiconductor layer in the photosensor of the diode structure is etched to etch away the semiconductor layer in the photosensor of the photodiode structure in the partially exposed region; the remaining photoresist on the substrate is completely stripped off.
  • the gate electrode layer 14 is deposited by magnetron sputtering on the glass substrate 23, and then the n-type amorphous silicon layer 10 is sequentially deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition).
  • the material of the gate electrode layer 14 may be a single layer film of an aluminum-niobium alloy (AlNd), or an aluminum (A1), or a copper (Cu), a phase (Mo), a molybdenum-tungsten (MoW) alloy, or a chromium (Cr).
  • a composite film composed of any combination of (AlNd), aluminum (Al), copper (Cu), phase (Mo), molybdenum tungsten (MoW) alloy, and chromium (Cr) may be used.
  • the conductive layer 13 is a transparent conductive film, and can be formed, for example, of a material such as ITO or ruthenium. Then, a layer of photoresist 24 is applied over the deposited conductive layer 13 by a coater.
  • FIG. 12A and 12B are respectively a plan view schematically showing a structure obtained by mask exposure development processing in the first mask process and a cross-sectional view taken along line ⁇ - ⁇ in Fig. 12A.
  • FIG. 12B using a half mask technique Formed as photoresist 24.
  • a partial exposure region of the photoresist 24 is formed in a via connection region between the gate electrode layer 14 and the photosensor structure of the light emitting diode structure, which is formed in FIG. 1, and a light is formed in a region of the light sensor of the light emitting diode structure.
  • the completely unexposed areas of the glue 24 are formed; in other areas on the substrate 23, a fully exposed area of the photoresist 24 is formed.
  • the etching process of the conductive layer 13 in the photosensor of the photodiode structure is performed.
  • the etching of the conductive layer 13 is performed by wet etching, and the conductive layer 13 in the fully exposed region is etched away to obtain FIG. 13A.
  • the semiconductor layer in the photodiode structure photosensor of the structure shown in FIG. 13A is etched, and the n-type amorphous silicon layer 10, the amorphous silicon layer 11 and the p-type non-etched are performed by dry etching.
  • the etching of the crystalline silicon layer 12 etches the semiconductor layer in the photosensor of the photodiode structure in the fully exposed region, thereby obtaining the structure shown in Fig. 13B.
  • the gate electrode layer 14' of the structure shown in FIG. 13B is etched, where the gate electrode layer 14 is etched by wet etching, and the gate electrode layer 14 of the fully exposed region is etched away.
  • the structure shown in Fig. 13C is obtained, that is, the gate electrode 14 and the contact layer 14" are formed.
  • the photoresist 24 of the partially exposed region of the structure shown in Fig. 13C is grayed out by an ashing process, as shown in Fig. 13D.
  • the structure is shown.
  • the etching process of the conductive layer 13 in the photosensor of the photodiode structure is performed again, and the etching of the conductive layer 13 is generally performed by wet etching, and the conductive layer 13 in the partially exposed region is engraved. Etching, the structure shown in Fig. 13E is obtained. Then, the semiconductor layer in the photodiode structure photosensor of the structure shown in Fig. 13E is etched, and the n-type amorphous silicon layer is performed by dry etching. 10. etching of the amorphous silicon layer 11 and the p-type amorphous silicon layer 12, etching the semiconductor layer in the photodiode structure photosensor in the partially exposed region, and obtaining the structure shown in FIG.
  • Fig. 14A is a plan view
  • Fig. 14B is a view along Fig. 14A.
  • Step 102 performing a second mask process. Specifically, in the structure obtained in step 101, the second mask process is continued.
  • the insulating layer 15, the amorphous silicon layer 16, and the n-type amorphous silicon layer 10 are sequentially deposited by enhanced chemical vapor deposition, and the source/drain electrodes are deposited by magnetron sputtering.
  • a photoresist to the structure subjected to the above treatment, forming a photoresist pattern of the source/drain electrode pattern after exposure and development, forming a source/drain electrode pattern by wet etching, and performing dry etching on the film
  • the n-type amorphous silicon 10 of the transistor channel is etched, and the photoresist is stripped to finally obtain an insulating layer 15, an amorphous silicon layer 16, and an n type as shown in FIGS. 15A-15C.
  • Fig. 15A is a plan view
  • Figs. 15B and 15C are schematic cross-sectional views taken along line BB and line CC in Fig. 15A, respectively.
  • Step 103 performing a third masking process, forming a via hole of the passivation layer exposing the contact layer, the photosensor, and the partial region of the source/drain electrode layer on the structure obtained by the second masking process.
  • the first passivation layer 19 is deposited by plasma enhanced chemical vapor deposition.
  • the third mask process is continued, that is, the photoresist is coated on the via connection region of the source, the photodiode structure, and the photodiode region, and the via pattern for the first passivation layer is formed after exposure and development. Photoresist.
  • a first via 24 is formed in the first passivation layer 19 by a dry etching process, and the photoresist is stripped to obtain a structure as shown in Figs. 16A-16C.
  • Fig. 16A is a plan view
  • Figs. 16B and 16C are schematic cross-sectional views taken along line B-B and line C-C in Fig. 16A, respectively.
  • Step 104 performing a fourth mask process to form a conductive layer on the structure obtained by the third mask process.
  • the fourth mask process is continued, and a metal film is deposited on the obtained structure by magnetron sputtering, and the structure after depositing the metal film is coated with a photoresist, and exposed and developed.
  • the photoresist for forming a pattern of the conductive layer is formed, after the photoresist is wet-etched and stripped, the conductive layer 20 is formed on the resultant structure to obtain a structure as shown in Figs. 17A-17C.
  • Fig. 17A is a plan view
  • Figs. 17B and 17C are schematic cross-sectional views taken along line B-B and line C-C in Fig. 17A, respectively.
  • Step 105 forming a second passivation layer on the structure obtained by the fourth mask process, and then performing a fifth mask process to form a passivation layer via hole exposing at least a portion of the gate line region.
  • the second passivation layer 21 is deposited by plasma enhanced chemical vapor deposition, and the fifth mask process is continued, and a photoresist is coated on the peripheral signal guiding region of the obtained structure.
  • a second via hole 25 is formed in the second passivation layer 21, and the photoresist is stripped to obtain a structure as shown in FIGS. 18A and 18C.
  • Step 106 performing a sixth mask process, forming a transparent conductive layer 22 covering the second via holes 25 of the second passivation layer 21 on the structure obtained by the fifth mask process.
  • a transparent conductive film such as ITO is deposited by magnetron sputtering, and the sixth mask process is continued to obtain a structure as shown in FIG. 19, thus, in the second passivation.
  • a transparent conductive layer 22 made of, for example, ITO is formed on the second via 25 of the layer 21.
  • the present disclosure also provides an amorphous silicon photovoltaic device comprising a substrate, a thin film transistor disposed on the substrate, and a photosensor of a photodiode structure; a contact layer located under the photosensor, not completely covered by the photosensor Covering, the contact layer is disposed in the same layer as the gate electrode in the thin film transistor and The materials are the same.
  • the amorphous silicon photovoltaic device includes a substrate 23, a thin film transistor including a gate electrode 14 disposed on the substrate 23, and an n-type amorphous silicon layer 10, an amorphous silicon layer 11, and a p-type amorphous silicon layer. 12 light sensor.
  • the contact layer 14" is disposed under the photosensor and is not completely covered by the photosensor, and the contact layer 14" is disposed in the same layer as the gate electrode 14 of the thin film transistor and has the same material.
  • a first passivation layer 19 is covered over the photosensor and the thin film transistor, and a via hole is provided in the first passivation layer 19 to expose a partial region of the contact layer.
  • a conductive layer 20 is disposed over the first passivation layer 19, the conductive layer 20 covering the vias, and the contact layer 14" is in communication with the source or drain electrodes in the thin film transistor.

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Abstract

一种非晶硅光电装置及其制造方法。非晶硅光电装置包括基板（23）、设置在基板（23）上不同位置的薄膜晶体管和光电二极管结构的光传感器、以及接触层（14"），接触层（14"）位于光传感器下方，接触层（14"）未被光传感器完全覆盖，接触层（14"）与薄膜晶体管中的栅电极（14）层同层设置且材料相同。能够简化非晶硅光电装置的制造流程，提高制造效率，降低成本。

Description

非晶硅光电装置及其制造方法 技术领域
本公开涉及一种非晶硅光电装置及其制造方法。 背景技术
目前，非晶硅光电装置主要应用于 X射线衍射（ XRD, X-Ray Diffraction ) 检测领域， 如医院、 机场、 地铁等， 具体可用于进行危险物品的检测等。 图 1 A和 1B分别是常规的非晶硅光电装置的平面示意图和沿图 1 A中的 B-B线 所取得截面示意图。 如图 1B 所示， 该非晶硅光电装置形成于玻璃基板 23 上， 其主要由两部分构成， 一部分是光电二极管结构的光传感器， 该光电二 极管结构的光传感器包括： n型非晶硅 ( n+ a-Si )层 10、 非晶硅（ a-Si )层 11、 p型非晶硅（p+ a-Si )层 12和导电层 13, 光电二极管结构的光传感器主 要用于接收光， 并利用光伏效应产生电流； 另一部分是薄膜晶体管， 薄膜晶 体管主要包括栅电极层 14、 包括第一绝缘层 15和非晶硅层 16的半导体层、 阻挡层 17、 源 /漏电极层 18、 保护层 19和透明导电层 20, 薄膜晶体管的主 要作用是开关和用于传递光传感器产生的电流信号。
下面， 将参考图 2-10描述如图 1A和 1B所示的非晶硅光电装置的制造 方法。 图 2-8为沿图 1A的线 B-B所取的截面视图， 图 9和 10为沿图 1A的 线 C-C所取的截面视图。
如图 2所示，利用第一次掩膜工艺，在玻璃基板 23上形成栅电极层 14。 如图 3所示， 利用第二次掩膜工艺，在栅电极层 14和玻璃基板 23上形 成半导体层， 该半导体层包括第一绝缘层 15和非晶硅层 16, 第一绝缘层 15 位于栅电极层 14的上层， 非晶硅层 16位于第一绝缘层 15的上层。
如图 4所示， 利用第三次掩膜工艺， 在半导体层上形成阻挡层 17。 如图 5所示， 利用第四次掩膜工艺， 在阻挡层 17和半导体层上形成源 / 漏电极层 18。
如图 6所示， 利用第五次掩膜工艺， 在源 /漏电极层 18上形成光电二极 管结构的光传感器， 该光传感器包括： n型非晶硅（n+a-Si )层 10、 非晶硅 ( a-Si )层 11、 p型非晶硅（p+a-Si )层 12和导电层 13。
如图 7所示， 在上述的结构上沉积第一钝化层 19, 并利用第六次掩膜 工艺， 分别在光传感器的导电层 13和薄膜晶体管的源 /漏电极层 18上方在 第一钝化层 19中形成过孔。
如图 8所示，利用第七次掩膜工艺，在第一钝化层 19上形成导电层 20。 如图 9所示， 利用第八次掩膜工艺， 对于作为栅电极层 14的一部分的 栅线的区域， 在作为第二钝化层 21中形成到达栅电极层 14的过孔。
如图 10所示， 接着， 利用第九次掩膜工艺， 在第二钝化层 21的过孔上 方形成透明导电层 22。
如上所述， 利用常规工艺， 需要采用九次掩膜工艺才能完成整个非晶硅 光电装置的制造， 因此该工艺过程十分复杂， 成本较高， 效率较低。 发明内容
有鉴于此，本公开提供一种非晶硅光电装置及其制造方法， 能够筒化非 晶硅光电装置的制造流程， 提高制造效率， 降低成本。
根据本公开的一个方面，提供了一种非晶硅光电装置的制造方法，其包 括： 进行第一次构图工艺， 在基板上形成栅电极层、 光电二极管结构的光传 感器及位于所述光传感器下方的接触层的图形，所述接触层未被所述光传感 器完全覆盖， 所述接触层与栅电极层同层设置且材料相同； 进行第二次构图 工艺， 在第一次构图工艺得到的基板上依次形成绝缘层、 半导体层和源 /漏 电极层的图形； 以及在第二次构图工艺得到的基板上形成第一钝化层， 进行 第三次构图工艺， 在第一钝化层中形成使所述接触层、 所述光传感器、 所述 源 /漏电极层部分区域暴露出来的第一过孔。
根据一个示例， 该方法还包括： 进行第四次构图工艺， 在第三次构图工 艺得到的基板上形成导电层，所述导电层覆盖所述第一过孔及位于所述源电 极和所述漏电极之间的半导体层区域， 并使所述接触层与所述源 /漏电极层 中的源电极或漏电极相连通。
根据一个示例，该方法还包括： 在第四次构图工艺得到的基板上形成第 二钝化层， 进行第五次构图工艺， 在第二钝化层中形成至少使栅线部分区域 暴露出来的第二过孔； 进行第六次构图工艺， 在第五次构图工艺得到的基板 上形成用于覆盖所述第二过孔的第一透明导电层。
根据一个示例， 所述进行第一次构图工艺， 在基板上形成栅电极层、 光 电二极管及位于所述光传感器下方的接触层的图形的步骤包括：在基板上依 次形成所述栅电极层、 半导体层、 透明导电层和光刻胶； 以及对经过上述处 理的基板进行曝光显影处理、 刻蚀处理、 灰化处理形成栅电极层、 栅线接触 层及光传感器。
根据一个示例，所述对经过上述处理的基板进行曝光显影处理的步骤包 括： 对位于所述栅电极层、栅线及未被光传感器覆盖的接触层区域上方的光 刻胶进行部分曝光， 形成部分曝光区域； 对位于所述光传感器上方的光刻胶 完全不曝光，形成完全不曝光区域；以及对其他区域涂覆的光刻胶完全曝光， 形成完全曝光区域。
根据一个示例，所述对经过上述处理的所述基板进行刻蚀处理、灰化处 理为： 对光电二极管结构的光传感器中第二透明导电层的刻蚀处理， 将完全 曝光区域的第二透明导电层刻蚀掉；对光电二极管结构的光传感器中的半导 体层进行刻蚀处理，将完全曝光区域的光电二极管结构的光传感器中的半导 体层刻蚀掉；对栅电极层进行刻蚀处理，将完全曝光区域的栅电极层刻蚀掉； 采用灰化工艺将部分曝光区域的光刻胶灰化掉；对光电二极管结构的光传感 器中第二透明导电层的刻蚀处理， 将部分曝光区域的第二透明导电层刻蚀 掉； 对光电二极管结构的光传感器中的半导体层进行刻蚀处理， 将部分曝光 区域的光电二极管结构的光传感器中的半导体层刻蚀掉； 以及将基板上剩余 的光刻胶完全剥离掉。
根据本公开的一个方面， 提供了一种非晶硅光电装置， 其包括基板、 设 置在所述基板上的不同位置的薄膜晶体管和光电二极管结构的光传感器、以 及接触层， 所述接触层位于所述光传感器的下方， 所述接触层未被所述光传 感器完全覆盖，所述接触层与所述薄膜晶体管中的栅电极层同层设置且材料 相同。
根据一个示例，在所述光传感器与所述薄膜晶体管的上方覆盖有第一钝 化层， 在所述第一钝化中设置有使所述接触层、 所述光传感器、 所述薄膜晶 体管中的源 /漏电极层部分区域暴露出来的第一过孔， 以及在所述第一钝化 层的上方设置有导电层，所述导电层覆盖所述第一过孔及位于所述薄膜晶体 管中的源电极和所述漏电极之间的半导体层区域，并使所述接触层与所述薄 膜晶体管中的源电极或漏电极相连通。
根据本公开的技术方案， 能够筒化非晶硅光电装置的制造流程，提高制 造效率， 降低成本。 附图说明
为了更清楚地说明本公开或现有技术中的技术方案，下面将对本公开提 供的技术方案或现有技术描述中所需要使用的附图作筒单地介绍，显而易见 地，下面描述中的附图仅仅是本公开的技术方案的部分具体实施方式图示说 明， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以 根据这些附图获得其他的附图。
图 1A和 1B是常规非晶硅光电装置的平面示意图和沿图 1A中的线 B-B 所取的截面示意图；
图 2-10为常规非晶硅光电装置的制造工艺中的各阶段所获得的结构的 截面示意图；
图 11是本公开实现非晶硅光电装置制造方法的流程示意图；
图 12A和 12B是本公开的第一次掩膜工艺中掩膜曝光显影处理后的所 得结构的平面示意图和沿图 12 A中的线 B - B所取的截面示意图；
图 13A-13F是本公开第一次掩膜工艺中掩膜曝光显影处理后蚀刻处理 的各阶段所得的结构的截面示意图；
图 14A和 14B是本公开第一次掩膜工艺中光刻胶剥离后所得结构的平 面示意图以及沿图 14A中的线 B-B所取的截面示意图；
图 15A是本公开第二次掩膜工艺后所得结构的平面示意图；
图 15B和图 15C分别是本公开第二次掩膜工艺后所得结构沿图 15A中 的线 B-B和 C-C所取的截面示意图；
图 16A是本公开第三次掩膜工艺后所得结构的平面示意图；
图 16B和图 16C是本公开第三次掩膜工艺后所得的结构沿图 16A中的 线 B-B和 C-C所取的截面示意图；
图 17A是本公开第四次掩膜工艺后所得的结构的平面示意图； 图 17B和图 17C是本公开第四次掩膜工艺后所得的结构沿图 17A的线 B-B和 C-C所取的截面示意图；
图 18A是本公开第五次掩膜工艺后所得的结构的平面示意图； 图 18C是本公开第五次掩膜工艺后所得的结构沿图 18A中的线 C-C所 取的截面示意图；
图 19是本公开第六次掩膜工艺中后所得的结构的截面示意图； 图 20是本公开的非晶硅光电装置的截面示意图。 具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本公开一部分实施例， 而 不是全部的实施例。基于本公开中的实施例， 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例， 都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "连接" 或者 "相 连"等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电性的 连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右" 等仅用于表示 相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置关系也相应 地改变。
根据本公开进行第一次构图工艺，在基板上形成栅电极层、光电二极管 结构的光传感器及位于光传感器下方的接触层的图形，接触层未被光传感器 完全覆盖， 接触层与栅电极层同层设置且材料相同； 进行第二次构图工艺， 在第一次构图工艺得到的结构上依次形成绝缘层、 半导体层和源 /漏电极层 的图形； 以及在第二次构图工艺得到的结构上形成第一钝化层， 进行第三次 构图工艺， 在第一钝化层中形成使接触层、 光传感器及源 /漏电极层部分区 域暴露出来的第一过孔。
下面通过附图及具体实施例对本公开再做进一步的详细说明。
本文所述构图工艺可以具体为掩膜工艺， 所述基板可以具体为玻璃基 板，半导体层可以具体包括： 非晶硅层、 n型非晶硅层、和 /或 P型非晶硅层。 透明导电层可以具体为氧化铟锡（ITO )层。
本公开提供一种非晶硅光电装置的制造方法， 图 11是本公开实现非晶 硅光电装置的制造方法的流程示意图。 如图 11所示， 该方法包括以下步骤： 步骤 101 , 进行第一次掩膜工艺， 在基板上形成薄膜晶体管的栅电极和 栅线、 光电二极管结构的光传感器及位于光传感器下方的接触层的图形。 这里，接触层未被所述光传感器完全覆盖，接触层与栅电极层同层设置 且材料相同。
这里， 进行第一次掩膜工艺， 在基板上形成薄膜晶体管的栅电极、 光电 二极管结构的传感器及位于光传感器下方的接触层的图形的步骤可具体包 括： 在基板上依次形成栅电极层、 半导体层、 透明导电层和光刻胶； 以及对 上述的结构进行曝光显影处理、 刻蚀处理、 灰化处理形成薄膜晶体管的栅电 极、 接触层及光传感器。
这里， 上述的曝光显影处理可具体包括： 采用半掩膜技术， 在对应薄膜 晶体管的栅电极、栅线及未被光传感器覆盖的接触层区域上方形成光刻胶的 部分曝光区域； 对位于光传感器上方的光刻胶完全不曝光， 形成完全不曝光 区域； 对其他区域涂覆的光刻胶完全曝光， 形成完全曝光区域。
这里， 对经过上述处理的所述基板进行刻蚀处理、 灰化处理为： 对光电 二极管结构的光传感器中透明导电层的刻蚀处理，将完全曝光区域的透明导 电层刻蚀掉； 对光电二极管结构的光传感器中的半导体层进行刻蚀处理， 将 完全曝光区域的光电二极管结构的光传感器中的半导体层刻蚀掉；对栅电极 层进行刻蚀处理， 将完全曝光区域的栅电极层刻蚀掉； 采用灰化工艺将部分 曝光区域的光刻胶灰化掉；对光电二极管结构的光传感器中透明导电层的刻 蚀处理， 将部分曝光区域的透明导电层刻蚀掉； 对光电二极管结构的光传感 器中的半导体层进行刻蚀处理，将部分曝光区域的光电二极管结构的光传感 器中的半导体层刻蚀掉； 将基板上剩余的光刻胶完全剥离掉。
例如， 首先， 在玻璃基板 23上采用磁控溅射的方法沉积栅电极层 14，， 再采用增强型化学气相沉积法（PECVD, Plasma Enhanced Chemical Vapor Deposition )依次沉积 n型非晶硅层 10、 非晶硅层 11、 p型非晶硅层 12和导 电层 13。栅电极层 14，的材料可以为铝钕合金（ AlNd )、或铝（ A1 )、或铜（ Cu )、 相 （Mo )、 钼钨（MoW )合金、 或铬（Cr ) 的单层膜， 也可以为 （AlNd )、 铝 （Al )、 铜 （Cu )、 相 （Mo )、 钼钨（MoW )合金、 铬（Cr ) 的任意组合 所构成的复合膜。 导电层 13为透明导电薄膜， 例如可以利用 ITO、 ΙΖΟ等 材料形成。 然后， 利用涂覆机在沉积的导电层 13上涂覆一层光刻胶 24。
对经过上述处理的结构进行掩膜曝光显影处理。 图 12A和 12B分别为 利用第一次掩膜工艺中的掩膜曝光显影处理后所得结构的平面示意图和沿 图 12A中的线 Β-Β所取的截面示意图。 如图 12B所示， 采用半掩膜技术形 成光刻胶 24。 在将形成图 1所示的栅电极层 14，和发光二极管结构的光传感 器的结构之间的过孔连接区域形成光刻胶 24的部分曝光区域； 在发光二极 管结构的光传感器的区域形成光刻胶 24的完全不曝光区域；在基板 23上其 他区域中则形成光刻胶 24的完全曝光区域。
在对图 12A和 12B所示的结构进行过掩膜曝光显影处理后， 进行如下 处理。 首先， 进行光电二极管结构的光传感器中导电层 13的刻蚀处理， 一 般采用湿法刻蚀方式进行该导电层 13的刻蚀， 将完全曝光区域中的导电层 13刻蚀掉， 得到图 13A所示的结构。 然后， 对图 13A所示的结构的光电二 极管结构的光传感器中的半导体层进行刻蚀处理，这里采用干法刻蚀方式进 行 n型非晶硅层 10、非晶硅层 11和 p型非晶硅层 12的刻蚀，将完全曝光区 域的光电二极管结构的光传感器中的半导体层刻蚀完毕，由此得到图 13B所 示的结构。 然后， 对图 13B所示的结构的栅电极层 14'进行刻蚀处理， 这里 采用湿法刻蚀方式进行该栅电极层 14的刻蚀， 将完全曝光区域的栅电极层 14刻蚀掉， 得到图 13C所示的结构， 即形成了栅电极 14和接触层 14"。 然 后，采用灰化工艺对图 13C所示的结构的部分曝光区域的光刻胶 24灰化掉， 得到如图 13D 所示的结构。 然后， 再次进行光电二极管结构的光传感器中 导电层 13的刻蚀处理， 一般采用湿法刻蚀方式进行该导电层 13的刻蚀， 将 部分曝光区域中的导电层 13刻蚀掉， 得到图 13E所示的结构。 然后， 对图 13E所示的结构的光电二极管结构的光传感器中的半导体层进行刻蚀处理， 这里采用干法刻蚀方式进行 n型非晶硅层 10、 非晶硅层 11、 p型非晶硅层 12 的刻蚀， 将部分曝光区域中的光电二极管结构的光传感器中的半导体层 刻蚀完毕， 得到图 13F所示的结构。 最后， 对图 13F所示的结构进行剥离工 艺， 将剩余的光刻胶 24完全剥离掉， 得到如图 14A和图 14B所示的结构。 图 14A为平面示意图， 图 14B为沿图 14A的线 B-B所取的截面示意图。
步骤 102, 进行第二次掩膜工艺。 具体的， 在步骤 101得到的结构上， 继续进行第二次掩膜工艺。 在图 14A和 14B所示的结构上， 采用增强型化 学气相沉积法依次沉积绝缘层 15、 非晶硅层 16、 n型非晶硅层 10, 并采用 磁控溅射法沉积源 /漏电极层 18。 对经过上述处理的结构上涂覆光刻胶， 曝 光显影后形成源 /漏电极图形的光刻胶图案， 采用湿法刻蚀后形成源 /漏电极 图形， 再进行干法刻蚀， 对薄膜晶体管沟道的 n型非晶硅 10进行刻蚀， 剥 离光刻胶最后得到如图 15A-15C所示的包括绝缘层 15、 非晶硅层 16、 n型 非晶硅层 10和源 /漏电极层 18的结构。 图 15A为平面图， 图 15B和图 15C 分别为图 15A中的线 B-B和线 C-C所取的截面示意图。
步骤 103, 进行第三次掩膜工艺， 在第二次掩膜工艺得到的结构上形成 使接触层、 光传感器、 源 /漏电极层部分区域暴露出来的钝化层的过孔。 例 如， 在步骤 102得到结构上， 采用等离子增强型化学气相沉积法沉积第一钝 化层 19。 继续进行第三次掩膜工艺， 即在源极、 光电二极管结构的光传感 器的过孔连接区域和光电二极管区域上涂覆光刻胶，曝光显影后形成用于第 一钝化层过孔图形的光刻胶。 采用干法刻蚀工艺在第一钝化层 19中形成第 一过孔 24,剥离光刻胶后得到如图 16A-16C所示的结构。 图 16A为平面图， 图 16B和 16C分别为图 16A中的线 B-B和线 C-C所取的截面示意图。
步骤 104, 进行第四次掩膜工艺， 在第三次掩膜工艺得到的结构上形成 导电层。 例如， 在步骤 103得到结构上， 继续进行第四次掩膜工艺， 在所得 结构上采用磁控溅射的方法沉积一层金属薄膜，对沉积金属薄膜后的结构涂 覆光刻胶， 曝光显影后形成用于导电层图形的光刻胶， 采用湿法刻蚀和剥离 光刻胶后， 在所得结构上形成导电层 20, 得到如图 17A-17C所示的结构。 图 17A为平面图，图 17B和 17C分别为图 17A中的线 B-B和线 C-C所取的 截面示意图。
步骤 105, 在第四次掩膜工艺得到的结构上形成第二钝化层， 并随后进 行第五次掩膜工艺，形成至少使栅线部分区域暴露出来的钝化层过孔。例如， 在步骤 104得到的结构上，采用等离子增强型化学气相沉积法沉积第二钝化 层 21 , 继续进行第五次掩膜工艺， 在所得结构的周边信号引导区域上涂覆 光刻胶， 将其曝光显影并采用干法刻蚀工艺后在第二钝化层 21 中形成第二 过孔 25 , 剥离光刻胶后得到如图 18A和图 18C所示的结构。
步骤 106, 进行第六次掩膜工艺， 在第五次掩膜工艺得到的结构上形成 覆盖第二钝化层 21种的第二过孔 25的透明导电层 22。 例如， 在步骤 105 得到的结构上，采用磁控溅射的方法沉积例如 ITO的透明导电薄膜，继续进 行第六次掩膜工艺， 得到如图 19所示的结构， 如此， 在第二钝化层 21的第 二过孔 25上形成例如由 ITO制成的透明导电层 22。
本公开还提供了一种非晶硅光电装置，其包括基板、设置在基板上的薄 膜晶体管和光电二极管结构的光传感器； 接触层， 其位于所述光传感器的下 方， 并未被光传感器完全覆盖， 接触层与薄膜晶体管中的栅电极同层设置且 材料相同。 例如如图 20所示， 非晶硅光电装置包括基板 23 , 设置于基板 23 上包括栅电极 14的薄膜晶体管和包括 n型非晶硅层 10、 非晶硅层 11和 p 型非晶硅层 12的光传感器。接触层 14"设置于光传感器下方并未被光传感器 完全覆盖， 且接触层 14"与薄膜晶体管的栅电极 14同层设置且材料相同。
这里， 在光传感器与薄膜晶体管的上方覆盖有第一钝化层 19, 在第一 钝化层 19中设置有过孔， 使接触层的部分区域暴露出来。 这里， 在第一钝 化层 19上方设置有导电层 20, 导电层 20覆盖该过孔， 并使接触层 14"与薄 膜晶体管中的源电极或漏电极相连通。
以上实施方式仅用于说明本公开， 而并非对本公开的限制，有关技术领 域的普通技术人员， 在不脱离本公开的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本公开的范畴， 本公开的专 利保护范围应由权利要求限定。

Claims

权利要求书
1、 一种非晶硅光电装置的制造方法， 包括：
进行第一次构图工艺，在基板上形成栅电极层、光电二极管结构的光传 感器及位于所述光传感器下方的接触层的图形，所述接触层未被所述光传感 器完全覆盖， 所述接触层与栅电极层同层设置且材料相同；
进行第二次构图工艺， 在第一次构图工艺得到的基板上依次形成绝缘 层、 半导体层和源 /漏电极层的图形； 以及
在第二次构图工艺得到的基板上形成第一钝化层， 进行第三次构图工 艺， 在第一钝化层中形成使所述接触层、 所述光传感器、 所述源 /漏电极层 部分区域暴露出来的第一过孔。
2、 根据权利要求 1所述的方法， 还包括：
进行第四次构图工艺，在第三次构图工艺得到的基板上形成导电层，所 述导电层覆盖所述第一过孔及位于所述源电极和所述漏电极之间的半导体 层区域， 并使所述接触层与所述源 /漏电极层中的源电极或漏电极相连通。
3、 根据权利要求 2所述的方法， 还包括：
在第四次构图工艺得到的基板上形成第二钝化层， 进行第五次构图工 艺， 在第二钝化层中形成至少使栅线部分区域暴露出来的第二过孔； 以及 进行第六次构图工艺，在第五次构图工艺得到的基板上形成用于覆盖所 述第二过孔的第一透明导电层。
4、 根据权利要求 1至 3任一项所述的方法， 其中， 所述进行第一次构 图工艺， 在基板上形成栅电极层、 光电二极管及位于所述光传感器下方的接 触层的图形的步骤包括：
在基板上依次形成所述栅电极层、 半导体层、 透明导电层和光刻胶； 以 及
对经过上述处理的基板进行曝光显影处理、刻蚀处理、灰化处理形成栅 电极层、 栅线接触层及光传感器。
5、 根据权利要求 4所述的方法， 其中， 所述对经过上述处理的基板进 行曝光显影处理的步骤包括：
对位于所述栅电极层、栅线及未被光传感器覆盖的接触层区域上方的光 刻胶进行部分曝光， 形成部分曝光区域； 对位于所述光传感器上方的光刻胶完全不曝光， 形成完全不曝光区域； 以及
对其他区域涂覆的光刻胶完全曝光， 形成完全曝光区域。
6、 根据权利要求 5所述的方法， 其中， 所述对经过上述处理的所述基 板进行刻蚀处理、 灰化处理为：
对光电二极管结构的光传感器中第二透明导电层的刻蚀处理，将完全曝 光区域的第二透明导电层刻蚀掉；
对光电二极管结构的光传感器中的半导体层进行刻蚀处理，将完全曝光 区域的光电二极管结构的光传感器中的半导体层刻蚀掉；
对栅电极层进行刻蚀处理， 将完全曝光区域的栅电极层刻蚀掉； 采用灰化工艺将部分曝光区域的光刻胶灰化掉；
对光电二极管结构的光传感器中第二透明导电层的刻蚀处理，将部分曝 光区域的第二透明导电层刻蚀掉；
对光电二极管结构的光传感器中的半导体层进行刻蚀处理，将部分曝光 区域的光电二极管结构的光传感器中的半导体层刻蚀掉； 以及
将基板上剩余的光刻胶完全剥离掉。
7、 一种非晶硅光电装置， 包括基板、 设置在所述基板上的不同位置的 薄膜晶体管和光电二极管结构的光传感器、 以及接触层， 所述接触层位于所 述光传感器的下方， 所述接触层未被所述光传感器完全覆盖， 所述接触层与 所述薄膜晶体管中的栅电极层同层设置且材料相同。
8、 根据权利要求 7所述的非晶硅光电装置， 其中， 在所述光传感器与 所述薄膜晶体管的上方覆盖有第一钝化层，在所述第一钝化中设置有使所述 接触层、 所述光传感器、 所述薄膜晶体管中的源 /漏电极层部分区域暴露出 来的第一过孔， 以及
在所述第一钝化层的上方设置有导电层，所述导电层覆盖所述第一过孔 及位于所述薄膜晶体管中的源电极和所述漏电极之间的半导体层区域，并使 所述接触层与所述薄膜晶体管中的源电极或漏电极相连通。
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