WO2015090008A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2015090008A1
WO2015090008A1 PCT/CN2014/078923 CN2014078923W WO2015090008A1 WO 2015090008 A1 WO2015090008 A1 WO 2015090008A1 CN 2014078923 W CN2014078923 W CN 2014078923W WO 2015090008 A1 WO2015090008 A1 WO 2015090008A1
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Prior art keywords
photoresist
conductive pattern
layer
pattern
insulating layer
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PCT/CN2014/078923
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English (en)
French (fr)
Inventor
孙宏达
陈海晶
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京东方科技集团股份有限公司
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Publication of WO2015090008A1 publication Critical patent/WO2015090008A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • the uneven pattern of the conductive pattern will affect the display performance of the column substrate.
  • an array substrate often uses indium tin oxide (yttrium oxide) to form a pixel electrode, but when ITO is deposited, ITO crystals are easily formed due to temperature rise caused by long-term sputtering, and this phenomenon increases with the thickness of the ITO film. More and more obvious. Since the etching of the crystalline germanium is difficult, it is prone to residual germanium when the pattern of the pixel electrode is subsequently etched by the germanium film.
  • each film layer 3 of the array substrate including a gate electrode, a gate insulating layer, an active layer, a source/drain electrode layer, and the like is formed, and then fabricated.
  • the ITO film layer should be completely removed in the region 5 where the ITO film is removed between the regions 7 (i.e., adjacent ITO pattern regions) where the ITO film is left adjacent. Remove to expose the underlying passivation layer.
  • the ITO layer is formed to form a pixel electrode pattern, since etching of the crystalline ITO is difficult, as shown in FIG.
  • the technical problem to be solved by the present invention is to provide an array substrate, a manufacturing method thereof, and a display device.
  • the method of fabricating the array substrate can ensure that there is no residue around the etched conductive pattern, thereby reducing the influence of etch residue on the performance of the display device.
  • a method of fabricating an array substrate including:
  • the insulating layer under the conductive pattern is patterned by using a mask for forming a conductive pattern
  • a conductive layer is deposited, and the conductive layer is patterned into the conductive pattern by using the mask for forming a conductive pattern.
  • patterning the insulating layer under the conductive pattern by using a mask for forming the conductive pattern comprises:
  • the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions.
  • the depositing a conductive layer, patterning the conductive layer by using a mask for forming a conductive pattern to form the conductive pattern includes:
  • Coating a photoresist on the conductive layer exposing the photoresist by using the mask for forming a conductive pattern, so that the photoresist forms a second photoresist unretained region and a second photoresist a second region, wherein the second photoresist remaining region corresponds to a region where the conductive pattern is located, and the second photoresist unretained region corresponds to a region other than the conductive pattern, and performing development processing, The photoresist in the unretained region of the second photoresist is completely removed, and the thickness of the photoresist in the second photoresist remaining region remains unchanged;
  • the conductive layer of the second photoresist unretained region is completely engraved by a candle-cutting process, and the remaining photoresist is peeled off to form the conductive pattern.
  • the conductive pattern is a source electrode, a drain electrode, a data line, a gate electrode, a » line or a pixel electrode.
  • the embodiment of the present invention further provides an array substrate fabricated by the above method, wherein the insulating layer under the at least one conductive pattern includes an insulating layer pattern corresponding to the conductive pattern, the conductive pattern and the insulating layer The edges of the graphic are aligned.
  • the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions. Further, there is a slope at the edge of the insulating layer pattern corresponding to the conductive pattern.
  • the conductive pattern is a source electrode, a drain electrode, a data line, a gate electrode, a wire or a pixel electrode.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • Embodiments of the present invention have the following advantageous effects: in the above solution, before the conductive pattern is formed, the insulating layer under the conductive pattern is patterned by using a mask plate for forming a conductive pattern, so that the insulating layer under the conductive pattern has and is electrically conductive.
  • the pattern of the insulation layer corresponding to the figure.
  • the conductive film layer at the slope is thin due to the slope at the edge of the insulating layer pattern, so that the process of etching the conductive pattern becomes easier, even if the conductive film layer under the slope has The residue will also be blocked by the residual-free slope, which will provide a good insulation effect.
  • a barrier layer will be formed on the periphery of the conductive pattern, so that the conductive pattern is separated from the remaining portion of the etching, so that the etching effect is reflected. The effect of etching residue on the performance of the display device is reduced.
  • 1 is a schematic cross-sectional view of a conventional array substrate
  • FIG. 2 is a schematic plan view of the ITO etching without residue
  • Figure 3 is a top plan view showing the residual ITO etching
  • FIG. 4 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the deposition of a transparent conductive layer on an array substrate according to an embodiment of the present invention
  • FIG. 6 is a top plan view showing an edge portion of an ITO according to an embodiment of the present invention.
  • the embodiment of the present invention provides an array substrate, a manufacturing method thereof, and a display device, in which the etching residue around the conductive pattern affects the performance of the display device in the prior art.
  • the array substrate can be fabricated in such a manner that no residue remains on the periphery of the conductive pattern after engraving, thereby reducing the influence of the etching residue on the performance of the display device.
  • the embodiment of the invention provides a method for fabricating an array substrate. As shown in FIG. 4, the embodiment includes:
  • Step 10h Before the conductive pattern is formed, the insulating layer under the conductive pattern is patterned by using a mask for forming a conductive pattern;
  • Step 102 depositing a conductive layer, wherein the conductive layer is patterned to form the conductive pattern.
  • the mask for forming the conductive pattern is patterned on the insulating layer under the conductive pattern, so that the insulating layer under the conductive pattern has an insulating layer corresponding to the conductive pattern.
  • Graphics After depositing the conductive film layer on the insulating layer, the conductive film layer at the slope is thin due to the slope at the edge of the insulating layer pattern, so that the process of etching the conductive pattern becomes easier, even if the conductive film layer under the slope has Residues will also be blocked by the residual-free slope, which will provide a good insulation effect.
  • a barrier layer will be formed on the periphery of the conductive pattern to separate the conductive pattern from the residual portion of the etching, so that the etching effect is reflected. The effect of etching residue on the performance of the display device is reduced.
  • patterning the insulating layer under the conductive pattern by using a mask for forming the conductive pattern comprises:
  • the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions.
  • the depositing a conductive layer, and patterning the conductive layer by using the mask for forming a conductive pattern to form the conductive pattern comprises:
  • Coating a photoresist on the conductive layer exposing the photoresist by using a mask for forming a conductive pattern, so that the photoresist forms a photoresist unretained region and a photoresist retention region, wherein the light
  • the photoresist retention area corresponds to the area where the conductive pattern is located
  • the photoresist unretained area corresponds to the area other than the conductive pattern
  • the development process is performed, and the photoresist in the unretained area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the reserved area remains unchanged;
  • the conductive layer of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form the conductive pattern.
  • the conductive pattern is a source electrode, a drain electrode, a data line, a gate electrode, a » line or a pixel electrode.
  • the conductive pattern may be a source electrode, a drain electrode, and a data line
  • the array substrate includes an insulating layer under the source electrode, the drain electrode, and the data line
  • the insulating layer may be an etch barrier layer.
  • the source electrode, the drain electrode and the etch stop layer under the data line are patterned by using a mask plate for fabricating the source electrode, the drain electrode and the data line.
  • Conductive graphics include:
  • a source electrode, a drain electrode, and a data line metal layer on the patterned candle barrier layer Coating a photoresist on the source electrode, the drain electrode, and the data line metal layer, and exposing the photoresist by using a mask for fabricating the source electrode, the drain electrode, and the data line to form a photoresist for photolithography a non-retained area of the glue and a photoresist-retained area, wherein the photoresist-retained area corresponds to a region where the source electrode, the drain electrode, and the data line are located, and the unretained area of the photoresist corresponds to a region other than the source electrode and the drain electrode data line.
  • the photoresist in the unretained area of the photoresist is completely removed, and the thickness of the photoresist in the photoresist remaining area remains unchanged;
  • the source electrode, the drain electrode, and the data line metal layer of the unretained region of the photoresist are completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the source electrode, the drain electrode, and the data line.
  • the array substrate includes an insulating layer under the »electrode and the gate line
  • the conductive pattern may be a pattern of a gate electrode and a gate line
  • the insulating layer under the conductive pattern may be a gate electrode and » a buffer layer under the line
  • a mask layer of the electrode and the gate line is patterned to pattern the buffer layer under the gate electrode and the gate line, and a part of the buffer layer is etched away, so that the buffer layer includes Corresponding to the pattern of the gate electrode and the gate line;
  • patterning the conductive layer by using a mask for forming a conductive pattern to form the conductive pattern comprises:
  • Coating a photoresist on the gate metal layer exposing the photoresist by using a mask electrode and a line mask to form a photoresist unretained region and a photoresist retention region.
  • the photoresist retention region corresponds to a region where the gate electrode and the gate line are located
  • the photoresist unretained region corresponds to a region other than the gate electrode and the gate line, and development processing is performed, and the photoresist in the unreserved region of the photoresist is Completely removed, the photoresist thickness of the photoresist retention area remains unchanged;
  • the gate metal layer of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is peeled off to form a pattern of the gate electrode and the gate line.
  • the array substrate includes a passivation layer under the pixel electrode
  • the conductive pattern may be a pattern of a pixel electrode
  • the insulating layer under the conductive pattern may be a passivation layer under the pixel electrode.
  • patterning the insulating layer under the conductive pattern by using a mask for forming the conductive pattern comprises: Before the pattern of the pixel electrode is formed, the passivation layer under the pixel electrode is patterned by using a mask plate for fabricating the pixel electrode, and a part of the passivation layer is etched away, so that the passivation layer includes a pattern corresponding to the pixel electrode;
  • the mask patterning the conductive pattern to form the conductive pattern to form the conductive pattern comprises:
  • the photoresist retention area corresponds to the area where the pixel electrode is located, the photoresist unretained area corresponds to the area other than the pixel electrode, and the development process is performed, and the photoresist in the unretained area of the photoresist is completely removed, and the photoresist retention area is completely removed.
  • the thickness of the photoresist remains unchanged;
  • the pixel electrode layer of the unretained region of the photoresist is completely engraved by the engraving process, and the remaining photoresist is stripped to form a pattern of the pixel electrode.
  • the insulating layer under the conductive pattern is patterned by using a mask for forming a conductive pattern, so that the insulating layer under the conductive pattern has an insulating layer pattern corresponding to the conductive pattern.
  • the conductive film layer at the slope is thin due to the slope at the edge of the insulating layer pattern, so that the process of etching the conductive pattern becomes easier, even if the conductive film layer under the slope has The residue will also be blocked by the residual-free slope, which will provide a good insulation effect.
  • a barrier layer will be formed on the periphery of the conductive pattern, so that the conductive pattern is separated from the remaining portion of the etching, so that the etching effect is reflected. The effect of etching residue on the performance of the display device is reduced.
  • the following describes the array substrate of the present invention and the manufacturing method thereof by taking the conductive pattern as the pixel electrode and the insulating layer under the conductive pattern as the passivation layer as an example:
  • a conventional pixel electrode is usually made of an indium tin oxide (A?) material.
  • A indium tin oxide
  • ITO indium tin oxide
  • an ITO film layer is first formed on a substrate by a sputtering process. In this process, ITO crystals are easily formed due to temperature rise caused by long-term sputtering.
  • the technical solution of the invention is based on the formation of the imaging pixel before the deposition of the deposition film layer.
  • the mask layer of the electrode electrode of the electrode is etched once and under the blunt passivation layer under the film layer , forming a slope degree at the edge of the edge of the pixel-like electrode electrode formed in the form of a conformal shape, thereby depositing a film on the blunt passivation layer Layers from time to time, due to the existence of a sloped slope at the edge of the blunt passivation layer pattern, the ⁇ )) film layer at the slope slope is more than the other
  • the film layer on the flat and flat surface is thin, so that the over-process variation of the layer of the etched etch film is made easier and easier, that is, even if the oblique slope is lower than the slope
  • the side of the ⁇ '' ⁇ film layer has residual residue, and will also Blocked by the slope of the slope which is left without residual residue, it serves as a good good good
  • the spacer is separated from the strip, so that the pixel electrode is separated from the portion left by the etching residue, so that the etching is performed.
  • the effect of the effect is obtained in the body, and the reduction and the small effect of the etching residue remain on the performance performance of the display device. .
  • the method for fabricating the array substrate substrate board of the embodiment of the present invention may include the following steps:
  • Step aa providing a substrate substrate plate 44, the substrate substrate plate is a transparent transparent substrate plate, specifically, may be Glass-glass-based substrate board or quartz quartz-based substrate board;
  • Steps are formed on the substrate substrate board 44 to form a gate electrode electrode and a gate grid line;
  • the gate metal layer can be CCuu, AAUU AAgg, MMoo, CCrr, NNdd, NNii, , MMnn, TT, WW, and the like, and the alloy gold of these gold metal genus
  • the grating metal metal layer may be a single layer structure or A multi-layered layer structure, such as CCuu ⁇ MMoo, TTii ⁇ CCuu ⁇ TTii, ⁇ 11 ⁇ , and the like. .
  • the photolithography adhesive is completely removed to remove, and the photolithography adhesive retains the thickness of the photolithographic adhesive in the region of the retention zone to remain unchanged; After etching, the etching process is completely etched away, and the grating etched metal is not etched. Peeling the release film ,, thin film bare Keke gum from the remaining residual gum is formed into a shape ,, ** wire line and the gate electrode and the gate electrode pattern shape of FIG. .
  • Steps are formed on the backing substrate substrate board through the step bb to form a gate insulating layer
  • the method can be used to enhance the chemical vapor phase deposition method by mining or the like, in the lining substrate at the step bb after the step bb
  • the gate plate is deposited on the base substrate with a thickness of about 22000000 66000000AA, and the gate insulating layer can be selected.
  • 3 ⁇ 43 ⁇ 4 Oxide oxide, Nitrogen nitride or Nitrogen oxynitride, »»Insulation layer may be a single layer, a double layer or a multilayer layer Structure.
  • the insulating layer of the cabinet may be SSiiNNxx, SSiiOOxx or SSii((OONN))xx. .
  • a transparent metal oxide semiconductor layer having a thickness of about 20-1000 A may be deposited by ffi magnetron sputtering, thermal evaporation or other film formation method on the substrate of the step C.
  • Amorphous IGZO, HIZO, IZO, InZnO, ZnO, Ti02, SnO, CdSnO or other metal oxide semiconductor materials may be used.
  • a photoresist is coated on the transparent metal oxide semiconductor layer, exposed, developed, and the transparent metal oxide semiconductor layer is etched, and the photoresist is stripped to form a pattern of an active layer composed of a transparent metal oxide semiconductor layer.
  • Step e forming an etched ffi barrier layer on the substrate substrate subjected to step d;
  • an etch barrier layer may be deposited on the substrate subjected to step d by plasma enhanced chemical vapor deposition, a photoresist is coated on the etched ffi barrier layer, exposed, developed, and etched to form an etch barrier layer, and The photoresist is stripped to form a pattern of etch barrier layers.
  • the etch barrier layer can be exposed, developed, and etched by using the same mask as the active layer.
  • the etch barrier material may be selected from the group consisting of ffi oxides, nitrides or oxynitrides, and the engraved barrier layer may be a single layer, a double layer or a multilayer structure.
  • the etch barrier layer may be SiNx, SiOx or Si(ON)x.
  • Step f forming a source electrode, a drain electrode, a data line, and a data line on the etch barrier layer; specifically, may be deposited by magnetron sputtering, thermal evaporation, or other film formation methods on the substrate substrate subjected to the step e
  • a layer of source and drain metal having a thickness of about 2000-6000 A, and the source and drain metal layers may be metals such as Cu, Al, Ag, Mo, Cr, Nd, M, Mn, Ti, Ta, W, and alloys of these metals.
  • the source/drain metal layer may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, ⁇ 1 ⁇ , and the like.
  • the unretained area of the photoresist corresponds to the area other than the above-mentioned pattern; and the developing process is performed, and the photoresist in the unreserved area of the photoresist is completely removed.
  • the thickness of the photoresist in the photoresist retention area remains unchanged; the source/drain metal film of the unretained region of the photoresist is completely etched by the etching process, and the remaining photoresist is stripped to form a data line, a source electrode, and a drain electrode. Graphics.
  • Step g forming a passivation layer 2 on the substrate substrate subjected to step f;
  • a passivation layer material having a thickness of 400-5000 A is deposited on the substrate substrate subjected to the step f by magnetron sputtering, thermal evaporation, PECVD or other film forming method, wherein the passivation layer material may be an oxide, Nitride or oxynitride.
  • the passivation layer may be SiNx, SiOx or Si(ON)x.
  • the passivation layer may be a single layer structure or a two layer structure composed of ffi silicon nitride and silicon oxide.
  • Coating a layer of photoresist on the passivation layer exposing the photoresist by using a ffi mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist is not
  • the remaining area corresponds to the area of the via of the passivation layer, and the photoresist retention area corresponds to the area other than the via; for the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the photoresist remains in the area
  • the thickness of the photoresist remains unchanged; the passivation layer material of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the passivation layer 2 including vias, wherein
  • the etching time of the etching process is a first preset time.
  • Step h performing a second engraving on the passivation layer by using a mask plate for fabricating the pixel electrode; applying a layer of photoresist on the passivation layer after step g; using a mask plate for photolithography
  • the adhesive is exposed to form a photoresist unretained region and a photoresist-retained region, wherein the photoresist-retained region corresponds to a region where the pattern of the pixel electrode is located, and the photoresist-unretained region corresponds to the pattern other than the above-mentioned pattern
  • the developing process is performed, the photoresist in the unreserved area of the photoresist is completely removed, and the thickness of the photoresist in the photoresist remaining area remains unchanged; the opaque portion of the unretained area of the photoresist is etched by the etching process Layering the material, stripping the remaining photoresist, forming a passivation layer pattern corresponding to the pixel electrode pattern, wherein the etching
  • the passivation layer includes a passivation layer pattern corresponding to the pixel electrode, the passivation layer thickness under the pixel electrode is greater than the passivation layer thickness of the other regions, and the edge of the passivation layer pattern corresponding to the pixel electrode has a slope.
  • Step The pixel electrode 10 is formed on the base substrate 4 which has passed through step h.
  • an ITO film layer having a thickness of 300 to 1500 A is deposited on the base substrate 4 subjected to the step h by magnetron sputtering, thermal evaporation or another film formation method to form a structure as shown in FIG.
  • Applying a layer of photoresist on the ITO film layer exposing the photoresist by using a pixel electrode mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist is retained
  • the region corresponds to the region of the pattern of the pixel electrode, and the unretained region of the photoresist corresponds to the region other than the above-mentioned pattern; the development process, the photoresist in the unreserved region of the photoresist is completely removed, and the photoresist is preserved in the photoresist-retained region.
  • the thickness of the glue remains unchanged; the transparent conductive layer of the unretained area of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the pixel electrode, and the pixel electrode passes through the pass and drain electrodes of the passivation layer.
  • Sexual connection As shown in FIG. 5, when depositing the ruthenium layer, the thickness of the ruthenium layer facing the target is a, and at the slope of the passivation layer, the thickness of the ruthenium layer facing the target laterally is b, b is a. There is a significant reduction. After the development process, the photoresist covers the portion above the slope, that is, the region where the ITO layer needs to be retained.
  • the ffi is used for etching the etching layer of the a-thick layer, and dry etching
  • the etching degree in each direction is uniform, so the etching effect at the slope is obviously superior to the etching effect of the portion of the ruthenium layer facing the target, and the ruthenium layer at the slope can be Completely removed, no ITO or ITO crystals remain, and finally, as shown in FIG. 6, a spacer-free spacer 8 is formed on the periphery of the pixel electrode 10, so that the pixel electrode 8 is separated from the etching residual portion 9, so that the etching effect is obtained.
  • the pixel electrode is not limited to the material, and the indium zinc oxide (IZO) or the like may be formed into a pixel electrode by the above-described method of manufacturing the array substrate.
  • IZO indium zinc oxide
  • the method for fabricating the array substrate of the present invention is described by taking an etched germanium layer as an example.
  • the insulating layer under the metal layer or the metal oxide layer is pre-etched by using a mask for forming a metal layer or a metal oxide layer, so that the insulating layer has a pattern with a metal layer or a metal Corresponding pattern of the oxide layer pattern, there is a slope at the edge of the metal layer pattern or the metal oxide layer pattern to be formed, so that a thin metal layer or metal can be formed at the slope when the metal layer or the metal oxide layer is subsequently deposited.
  • a residual layer is formed on the periphery of the metal layer pattern or the metal oxide layer pattern, and the metal layer pattern or the metal oxide layer pattern and etching are formed.
  • the residual portions are separated, which reduces the influence of the etching residue on the performance of the display device.
  • the embodiment of the present invention further provides an array substrate according to the above manufacturing method.
  • the insulating layer under the at least one conductive pattern of the array substrate includes an insulating layer pattern corresponding to the conductive pattern, and the conductive pattern and the conductive pattern Align the edges of the insulation pattern.
  • the thickness of the insulating layer under the conductive pattern is greater than the thickness of the insulating layer at other regions. Further, there is a slope at the edge of the insulating layer pattern corresponding to the conductive pattern.
  • the conductive pattern may be a source electrode, a drain electrode, a data line, a gate electrode, a gate line or a pixel electrode.
  • the insulating layer under the conductive pattern has an insulating layer pattern corresponding to the conductive pattern.
  • a conductive film layer is deposited on the insulating layer of the array substrate to form a conductive pattern, There is a slope at the edge of the insulating layer pattern, and the conductive film layer at the slope is very thin, so that the process of etching the conductive pattern becomes easier. Even if the conductive film layer under the slope remains, it will be blocked by the residual-free slope.
  • the array substrate includes an insulating layer under the source electrode, the drain electrode and the data line, the insulating layer may be an etch barrier layer, and the insulating layer under the conductive pattern is an etch barrier layer
  • the source electrode, the drain electrode and the etch stop layer under the data line of the array substrate have an etch barrier pattern corresponding to the source electrode, the drain electrode, the data line and the data line, and the source electrode and the drain electrode The data lines are aligned with the edges of the etch barrier.
  • the array substrate includes an insulating layer under the »electrode and the gate line
  • the conductive pattern may be a pattern of a gate electrode and a gate line
  • the insulating layer under the conductive pattern may be a gate electrode and » A buffer layer under the line
  • a buffer layer under the gate electrode and the gate line of the array substrate has a buffer layer pattern corresponding to the gate electrode and the gate line, and the gate electrode and the gate line are aligned with edges of the buffer layer pattern.
  • the array substrate includes an insulating layer under the pixel electrode
  • the conductive pattern may be a pattern of a pixel electrode
  • the insulating layer under the conductive pattern may be a passivation layer under the pixel electrode.
  • the passivation layer under the pixel electrode of the array substrate has a passivation layer pattern corresponding to the pixel electrode, and the pixel electrode is aligned with the edge of the passivation layer.
  • Embodiments of the present invention also provide a display device including the column substrate as described above.
  • the structure and working principle of the column substrate are the same as those in the above embodiment, and are not described herein again.
  • the structure of other parts of the display device can be referred to the prior art, and will not be described in detail herein.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED (Organic Light Emitting Diode) panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like having any display function.

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Abstract

提供了一种阵列基板及其制作方法、显示装置。该阵列基板的制作方法包括：提供衬底基板（4），在衬底基板（4）上形成栅电极、栅绝缘层、有源层、源漏电极层等膜层（3），在膜层（3）上形成钝化层（2），在制作导电图形之前，利用制作像素电极的掩膜板对钝化层（2）进行构图，与像素电极对应的钝化层图形边缘存在有斜坡；沉积透明导电层（1），利用制作像素电极的掩膜板对所述透明导电层（1）进行构图形成所述导电图形。斜坡处的透明导电层（1）厚度比其他平坦处的透明导电层（1）薄，能够保证在刻蚀后导电图形的周边无残留。

Description

阵列基板及其制作方法、 显示装置 本发明涉及显示技术领域， 特别涉及一种阵列基板及其制作方法、 显示 装置。 在液晶显示器 （Liquid Crystal Disp y, LCD) 阵列基板和有机发光二极 管 (Organic Light- Emitting Diode, OLED) 阵列基板的制作过程中， 导电图 形刻馊不均匀将会对 列基板的显示性能造成影响。 例如， 阵列基板常常使 ^氧化铟锡 （ΠΌ) 来制作像素电极， 但是在沉积 ITO 时， 容易因长期溅射 导致的温度升高而形成 ITO结晶， 并随 ITO薄膜的厚度增加， 这种现象愈加 明显。 由于晶态 ΙΤΌ的刻蚀比较困难， 在随后刻蚀 ΠΌ薄膜形成像素电极的 图形时， 容易发生 ΙΤΌ残留。
图 1所示为较常见的 列基板结构，在衬底基板 4上制作有包括栅电极、 栅绝缘层、 有源层、 源漏电极层等在内的阵列基板各膜层 3， 之后制作有钝 化层 2和 ITO层 1。 ITO经过构图工艺后， 理想的状况如图 2所示， 在相邻 保留 ITO薄膜的区域 7 (也即为相邻 ITO图形区域） 之间的去除 ITO薄膜的 区域 5中 ITO膜层应该被完全去除， 露出下面的钝化层。 但是， 在刻蚀 ITO 层形成像素电极图形的时候， 由于晶态 ITO的刻蚀比较难， 如图 3所示， 经 常出现刻蚀不完全的情况， 从而在区域 7中 ITO薄膜被保留而形成电极， 在 区域 5中 ITO薄膜被去除而露出下面的钝化层， 在区域 7的周边区域 6中由 于晶态 ITO的刻蚀难度大， 仍然会遗留有 ITO晶粒。 区域 7的周边区域 6遗 留的 ITO晶粒如果过多会使相邻像素的像素电极之间电连接， 严重影响阵列 基板的电学性能， 使 列基板整体性能的不可控性增加， 最终将会影响显示 装置的显示效果。 本发明要解决的技术问题是提供一种阵列基板及其制作方法、显示装置。 该阵列基板的制作方法能够保证在刻蚀后的导电图形的周边无残留， 从而减 小了刻蚀残留对显示装置的性能的影响。
为解决上述技术问题， 本发明的实施例提供了如下技术方案： 一方面， 提供了一种阵列基板的制作方法， 包括：
在制作导电图形之前， 利用制作导电图形的掩膜板对所述导电图形之下 的绝缘层进行构图；
沉积导电层， 利用所述制作导电图形的掩膜板对所述导电层进行构图形 成所述导电图形。
进一步地， 所述在制作导电图形之前， 利用制作导电图形的掩膜板对所 述导电图形之下的绝缘层进行构图包括：
形成绝缘层的第一图形；
在形成有所述绝缘层的第一图形的基板上涂覆光刻胶， 利^所述制作导 电图形的掩膜板对所述光刻胶进行曝光， 使光刻胶形成第一光刻胶未保留区 域和第一光刻胶保留区域， 其中， 所述第一光刻胶保留区域对应于所述导电 图形所在区域，所述第一光刻胶未保留区域对应于所述导电图形以外的区域， 进行显影处理， 所述第一光刻胶未保留区域的光刻胶被完全去除， 所述第一 光刻胶保留区域的光刻胶厚度保持不变；
通过刻蚀工艺刻蚀掉所述第一光刻胶未保留区域的部分绝缘层， 剥离剩 余的光刻胶， 形成与所述导电图形对应的绝缘层第二图形， 所述绝缘层第二 图形的边缘处存在有斜坡。
进一步地，所述导电图形下的绝缘层厚度大于其他区域处的绝缘层厚度。 进一步地， 所述沉积导电层， 利用制作导电图形的掩膜板对所述导电层 进行构图形成所述导电图形包括；
在所述绝缘层上沉积导电层；
在所述导电层上涂覆光刻胶， 利用所述制作导电图形的掩膜板对所述光 刻胶进行曝光，使光刻胶形成第二光刻胶未保留区域和第二光刻胶保留区域， 其中， 所述第二光刻胶保留区域对应于所述导电图形所在区域， 所述第二光 刻胶未保留区域对应于所述导电图形以外的区域， 进行显影处理， 所述第二 光刻胶未保留区域的光刻胶被完全去除， 所述第二光刻胶保留区域的光刻胶 厚度保持不变；
通过刻烛工艺完全刻烛掉所述第二光刻胶未保留区域的导电层， 剥离剩 余的光刻胶， 形成所述导电图形。 进一步地， 所述导电图形为源电极、 漏电极、 数据线、 栅电极、 »线或 像素电极。
本发明实施例还提供了一种利^以上述方法制作的阵列基板， 至少一导 电图形之下的绝缘层包括有与所述导电图形对应的绝缘层图形， 所述导电图 形与所述绝缘层图形的边缘对齐。
进一步地， 所述导电图形下的绝缘层厚度大于其他区域处的绝缘层厚度 进一步地， 与所述导电图形对应的绝缘层图形的边缘存在有斜坡。
进一步地， 所述导电图形为源电极、 漏电极、 数据线、 栅电极、 櫥线或 像素电极。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。
本发明的实施例具有以下有益效果：上述方案中，在制作导电图形之前， 利用制作导电图形的掩膜板对导电图形之下的绝缘层进行构图， 使得导电图 形之下的绝缘层具有与导电图形对应的绝缘层图形。 之后在绝缘层上沉积导 电膜层时， 由于在绝缘层图形的边缘存在斜坡， 斜坡处的导电膜层很薄， 使 得刻蚀导电图形的过程变得比较容易， 即使斜坡下方的导电膜层有残留， 也 将被无残留的斜坡所阻挡， 起到良好的隔绝效果， 在导电图形的周边形成无 残留的隔离带， 使得导电图形与刻蚀残留的部分分开， 使得刻蚀的效果得到 体现， 减小了刻蚀残留对显示装置的性能的影响。 图 1是现有阵列基板的截面示意图；
图 2是 ITO刻蚀无残留时的俯视示意图；
图 3是 ITO刻蚀有残留时的俯视示意图；
图 4为本发明实施例阵列基板的制作方法的流程示意图；
图 5是本发明实施例阵列基板沉积透明导电层后的截面示意图； 图 6是本发明实施例 ITO边缘部分的俯视示意图。
附图标记
1 透明导电层 2 钝化层
3 包括栅电极、 欐绝缘层、 有源层、 源漏电极层等在内各膜层
4 衬底基板 5 去除 ITO薄膜的区域 6 区域 7的周边区域 7保留 ITO薄膜的区域
8 隔离带 9 刻蚀残留部分 10像素电极 为使本发明的实施例要解决的技术问题、 技术方案和优点更加清楚， 下 面将结合 i†图及具体实施例进行详细描述。
本发明的实施例针对现有技术中导电图形周边的刻蚀残留会对显示装置 的性能造成影响的问题， 提供一种阵列基板及其制作方法、 显示装置。 该阵 列基板的制作方法能够保证在刻馊后导电图形的周边无残留， 从而减小了刻 蚀残留对显示装置的性能的影响。
本发明实施例提供了一种阵列基板的制作方法， 如图 4所示， 本实施例 包括：
步骤 10h 在制作导电图形之前， 利用制作导电图形的掩膜板对所述导 电图形之下的绝缘层进行构图；
步骤 102; 沉积导电层， 利) ¾所述制作导电图形的掩膜板对所述导电层 进行构图形成所述导电图形。
本发明的阵列基板的制作方法， 在制作导电图形之前， 利 制作导电图 形的掩膜板对导电图形之下的绝缘层进行构图， 使得导电图形之下的绝缘层 具有与导电图形对应的绝缘层图形。 之后在绝缘层上沉积导电膜层时， 由于 在绝缘层图形的边缘存在斜坡， 斜坡处的导电膜层很薄， 使得刻蚀导电图形 的过程变得比较容易， 即使斜坡下方的导电膜层有残留， 也将被无残留的斜 坡所阻挡， 起到良好的隔绝效果， 在导电图形的周边形成无残留的隔离带， 使导电图形与刻蚀残留的部分分开， 使得刻蚀的效果得到体现， 减小了刻蚀 残留对显示装置的性能的影响。
进一步地， 所述在制作导电图形之前， 利用制作导电图形的掩膜板对所 述导电图形之下的绝缘层进行构图包括：
形成绝缘层的第一图形；
在形成有所述绝缘层的第一图形的基板上涂覆光刻胶， 利] ¾制作导电图 形的掩膜板对所述光刻胶进行曝光， 使光刻胶形成光刻胶未保留区域和光刻 胶保留区域， 其中， 光刻胶保留区域对应于所述导电图形所在区域， 光刻胶 未保留区域对应于所述导电图形以外的区域， 进行显影处理， 光刻胶未保留 区域的光刻胶被完全去除， 光刻胶保留区域的光刻胶厚度保持不变；
通过刻蚀工艺刻蚀掉光刻胶未保留区域的部分绝缘层， 剥离剩余的光刻 胶， 形成与所述导电图形对应的所述绝缘层的第二图形， 所述第二图形的边 缘处存在斜坡。
进一步地，所述导电图形下的绝缘层厚度大于其他区域处的绝缘层厚度。 进一步地， 所述沉积导电层， 利用所述制作导电图形的掩膜板对所述导 电层进行构图形成所述导电图形包括：
在所述绝缘层上沉积导电层；
在所述导电层上涂覆光刻胶， 利用制作导电图形的掩膜板对所述光刻胶 进行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻 胶保留区域对应于所述导电图形所在区域， 光刻胶未保留区域对应于所述导 电图形以外的区域，进行显影处理，光刻胶未保留区域的光刻胶被完全去除， 光刻胶保留区域的光刻胶厚度保持不变；
通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的导电层， 剥离剩余的光刻 胶， 形成所述导电图形。
进一步地， 所述导电图形为源电极、 漏电极、 数据线、 栅电极、 »线或 像素电极。
具体地， 所述导电图形可以为源电极、 漏电极、 数据线， 所述阵列基板 包括有位于源电极、 漏电极和数据线之下的绝缘层， 所述绝缘层可以为刻蚀 阻挡层， 所述在制作导电图形之前， 利用制作导电图形的掩膜板对所述导电 图形之下的绝缘层进行构图包括；
在制作源电极、 漏电极和数据线的图形之前， 利用制作源电极、 漏电极 和数据线的掩膜板对所述源电极、 漏电极和数据线之下的刻蚀阻挡层进行构 图， 刻蚀掉部分刻蚀阻挡层， 使得刻蚀阻挡层包括有对应源电极、 漏电极和 所述在制作导电图形之前， 利] ¾制作导电图形的掩膜板对所述导电层进 行构图形成所述导电图形包括：
在刻烛阻挡层上沉积源电极、 漏电极、 数据线金属层； 在所述源电极、漏电极、数据线金属层上涂覆光刻胶，利用制作源电极、 漏电极和数据线的掩膜板对所述光刻胶进行曝光， 使光刻胶形成光刻胶未保 留区域和光刻胶保留区域， 其中， 光刻胶保留区域对应于源电极、 漏电极和 数据线所在区域， 光刻胶未保留区域对应于源电极、 漏电极数据线以外的区 域， 进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶保留区 域的光刻胶厚度保持不变；
通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源电极、 漏电极、 数据线 金属层， 剥离剩余的光刻胶， 形成源电极、 漏电极和数据线的图形。
进一步地， 所述阵列基板包括有位于 »电极和栅线之下的绝缘层， 所述 导电图形可以为栅电极和栅线的图形， 所述导电图形之下的绝缘层可以为栅 电极和 »线之下的缓冲层， 所述在制作导电图形之前， 利用制作导电图形的 掩膜板对所述导电图形之下的绝缘层进行构图包括：
在制作栅电极和栅线的图形之前， 禾 制作 »电极和栅线的掩膜板对所 述栅电极和栅线之下的缓冲层进行构图， 刻蚀掉部分缓冲层， 使得缓冲层包 括有对应栅电极和栅线的图形；
所述在制作导电图形之前， 利 制作导电图形的掩膜板对所述导电层进 行构图形成所述导电图形包括：
在缓冲层上沉积 »金属层；
在所述栅金属层上涂覆光刻胶， 利用制作栅电极和 »线的掩膜板对所述 光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中， 光刻胶保留区域对应于栅电极和栅线所在区域， 光刻胶未保留区域对应于栅 电极和栅线以外的区域， 进行显影处理， 光刻胶未保留区域的光刻胶被完全 去除， 光刻胶保留区域的光刻胶厚度保持不变；
通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属层， 剥离剩余的光 刻胶， 形成栅电极和栅线的图形。
进一步地， 所述阵列基板包括有位于像素电极之下的钝化层， 所述导电 图形可以为像素电极的图形， 所述导电图形之下的绝缘层可以为像素电极之 下的钝化层， 所述在制作导电图形之前， 利用制作导电图形的掩膜板对所述 导电图形之下的绝缘层进行构图包括： 在制作像素电极的图形之前， 利用制作像素电极的掩膜板对所述像素电 极之下的钝化层进行构图， 刻蚀掉部分钝化层， 使得钝化层包括有对应像素 电极的图形；
所述在制作导电图形之前， 利 ffi制作导电图形的掩膜板对所述导电层进 行构图形成所述导电图形包括：
在钝化层上沉积像素电极层；
在所述像素电极层上涂覆光刻胶， 利^制作像素电极的掩膜板对所述光 刻胶进行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留区域对应于像素电极所在区域， 光刻胶未保留区域对应于像素电 极以外的区域， 进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光 刻胶保留区域的光刻胶厚度保持不变；
通过刻馊工艺完全刻馊掉光刻胶未保留区域的像素电极层， 剥离剩余的 光刻胶， 形成像素电极的图形。
上述方案中， 在制作导电图形之前， 利用制作导电图形的掩膜板对导电 图形之下的绝缘层进行构图， 使得导电图形之下的绝缘层具有与导电图形对 应的绝缘层图形。 之后在绝缘层上沉积导电膜层时， 由于在绝缘层图形的边 缘存在斜坡， 斜坡处的导电膜层很薄， 使得刻蚀导电图形的过程变得比较容 易， 即使斜坡下方的导电膜层有残留， 也将被无残留的斜坡所阻挡， 起到良 好的隔绝效果， 在导电图形的周边形成无残留的隔离带， 使得导电图形与刻 蚀残留的部分分开， 使得刻蚀的效果得到体现， 减小了刻蚀残留对显示装置 的性能的影响。
下面以导电图形为像素电极、 导电图形之下的绝缘层为钝化层为例， 对 本发明的阵列基板及其制作方法进行详细介绍：
现有的 列基板的制作方法中， 常规的像素电极常采用氧化铟锡 ατο) 材料。 在利用 ITO形成像素电极时， 首先通过溅射 （Sputter) 制膜过程在基 板上形成 ITO膜层。 在这个过程中， 容易因长期溅射导致的温度升高而形成 ITO结晶。 对于较厚的 ITO膜层， 这种残留更为普遍， 由于晶态 ITO的刻烛 难度大于常态 ITO的刻烛难度， 如图 3所示， 在刻蚀形成像素电极的图形之 后， 在保留 ΓΚ)膜层的区域 7的周边区域 6， ^然会遗留有 ITO晶粒， 导致 相相邻邻的的区区域域 77之之间间存存在在导导电电颗颗粒粒，， 将将会会严严重重影影响响显显示示装装置置的的整整体体性性能能。。
为为了了解解决决上上述述问问题题，， 本本发发明明的的技技术术方方案案在在沉沉积积 ΠΠΌΌ膜膜层层之之前前，， 首首先先利利用用 形形成成像像素素电电极极的的掩掩膜膜板板对对 ΓΓΚΚ))膜膜层层之之下下的的钝钝化化层层进进行行一一次次较较浅浅的的刻刻蚀蚀，， 在在应应 形形成成的的像像素素电电极极的的边边缘缘处处形形成成坡坡度度，， 这这样样在在钝钝化化层层上上沉沉积积 ΠΠΌΌ膜膜层层时时，， 由由于于 在在钝钝化化层层图图形形的的边边缘缘存存在在斜斜坡坡，， 斜斜坡坡处处的的 ΓΓΚΚ))膜膜层层较较其其他他平平坦坦处处的的膜膜层层薄薄，， 使使得得刻刻蚀蚀 ΙΙΤΤΌΌ膜膜层层的的过过程程变变得得比比较较容容易易，， 即即使使斜斜坡坡下下方方的的 ΙΙΊΊ''ΟΟ膜膜层层有有残残留留，， 也也将将被被无无残残留留的的斜斜坡坡所所阻阻挡挡，， 起起到到良良好好的的隔隔绝绝效效果果，， 在在像像素素电电极极的的周周边边形形成成 无无残残留留的的隔隔离离带带，， 使使得得像像素素电电极极与与刻刻蚀蚀残残留留的的部部分分分分开开，， 使使得得刻刻蚀蚀的的效效果果得得 到到体体现现，， 减减小小了了刻刻蚀蚀残残留留对对显显示示装装置置的的性性能能的的影影响响。。
具具体体地地，， 本本实实施施例例的的阵阵列列基基板板的的制制作作方方法法可可以以包包括括以以下下步步骤骤：：
步步骤骤 aa:: 提提供供一一衬衬底底基基板板 44，， 该该衬衬底底基基板板为为透透明明基基板板，， 具具体体地地，， 可可以以为为玻玻 璃璃基基板板或或石石英英基基板板；；
步步骤骤 在在衬衬底底基基板板 44上上形形成成栅栅电电极极和和栅栅线线；；
具具体体地地，， 可可以以采采)) ¾¾溅溅射射或或热热蒸蒸发发的的方方法法在在衬衬底底基基板板 44上上沉沉积积一一层层厚厚度度为为 110000-- 1166000000AA的的栅栅金金属属层层，， 栅栅金金属属层层可可以以是是 CCuu、、 AAUU AAgg、、 MMoo、、 CCrr、、 NNdd、、 NNii、、 MMnn、、 TT 、、 WW等等金金属属以以及及这这些些金金属属的的合合金金，， 栅栅金金属属层层可可以以为为单单层层结结构构或或者者 多多层层结结构构，， 多多层层结结构构比比如如 CCuu\\MMoo、、 TTii\\CCuu\\TTii、、 ΜΜοο\\ΑΑ11\\ΜΜοο等等。。 在在栅栅金金属属层层上上涂涂 覆覆一一层层光光刻刻胶胶，， 采采用用掩掩膜膜板板对对光光刻刻胶胶进进行行曝曝光光，， 使使光光刻刻胶胶形形成成光光刻刻胶胶未未保保留留 区区域域和和光光刻刻胶胶保保留留区区域域，， 其其中中，， 光光刻刻胶胶保保留留区区域域对对应应于于 »»线线和和 »»电电极极的的图图形形 所所在在区区域域，， 光光刻刻胶胶未未保保留留区区域域对对应应于于上上述述图图形形以以外外的的区区域域；； 进进行行显显影影处处理理，， 光光刻刻胶胶未未保保留留区区域域的的光光刻刻胶胶被被完完全全去去除除，， 光光刻刻胶胶保保留留区区域域的的光光刻刻胶胶厚厚度度保保持持 不不变变；； 通通过过刻刻蚀蚀工工艺艺完完全全刻刻蚀蚀掉掉光光刻刻胶胶未未保保留留区区域域的的栅栅金金属属薄薄膜膜，， 剥剥离离剩剩余余 的的光光刻刻胶胶，， 形形成成 **线线和和栅栅电电极极的的图图形形。。
步步骤骤 在在经经过过步步骤骤 bb的的衬衬底底基基板板上上形形成成栅栅绝绝缘缘层层；；
具具体体地地，， 可可以以采采 等等离离子子体体增增强强化化学学气气相相沉沉积积方方法法，， 在在经经过过步步骤骤 bb的的衬衬 底底基基板板上上沉沉积积厚厚度度约约为为 22000000 66000000AA的的栅栅绝绝缘缘层层，， 其其中中，， 栅栅绝绝缘缘层层材材料料可可以以选选 ))¾¾氧氧化化物物、、 氮氮化化物物或或者者氮氮氧氧化化物物，， »»绝绝缘缘层层可可以以为为单单层层、、 双双层层或或多多层层结结构构。。 具具体体地地，， 櫥櫥绝绝缘缘层层可可以以是是 SSiiNNxx、、 SSiiOOxx或或 SSii((OONN))xx。。
Figure imgf000010_0001
具体地， 可以在经过步骤 C的衬底基板上采 ffi磁控溅射、 热蒸发或其它 成膜方法沉积一层厚度约为 20- 000A的透明金属氧化物半导体层，透明金属 氧化物半导体层可以选用非晶 IGZO、 HIZO、 IZO、 InZnO、 ZnO、 Ti02、 SnO、 CdSnO 或其他金属氧化物半导体材料。 在透明金属氧化物半导体层上 涂覆光刻胶， 进行曝光、 显影， 刻蚀透明金属氧化物半导体层， 并剥离光刻 胶， 形成由透明金属氧化物半导体层组成的有源层的图形。
步骤 e: 在经过步骤 d的衬底基板上形成刻蚀 ffi挡层；
具体地， 可以在经过步骤 d的基板上采用等离子体增强化学气相沉积方 法沉积刻蚀阻挡层， 在刻蚀 ffi挡层上涂覆光刻胶， 进行曝光、 显影， 刻蚀刻 蚀阻挡层， 并剥离光刻胶， 形成刻蚀阻挡层的图形。 其中， 刻蚀阻挡层可以 与有源层采用同样的掩膜板进行曝光、 显影、 刻蚀。 刻蚀阻挡层材料可以选 ffi氧化物、氮化物或者氮氧化物，刻馊阻挡层可以为单层、双层或多层结构。 具体地， 刻蚀阻挡层可以是 SiNx、 SiOx或 Si(ON)x。
步骤 f: 在刻蚀阻挡层上形成源电极、 漏电极、 数据线和数据线； 具体地， 可以在经过歩骤 e的衬底基板上采 磁控溅射、 热蒸发或其它 成膜方法沉积一层厚度约为 2000- 6000A 的源漏金属层， 源漏金属层可以是 Cu、 Al、 Ag、 Mo、 Cr、 Nd、 M、 Mn、 Ti、 Ta、 W等金属以及这些金属的合 金。源漏金属层可以是单层结构或者多层结构，多层结构比如 Cu\Mo、Ti\Cu\Ti、 Μο\Α1\Μο等。在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝 光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留 区域对应于源电极、 漏电极、 数据线和数据线的图形所在区域， 光刻胶未保 留区域对应于上述图形以外的区域； 进行显影处理， 光刻胶未保留区域的光 刻胶被完全去除， 光刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀工艺完 全刻蚀掉光刻胶未保留区域的源漏金属薄膜， 剥离剩余的光刻胶， 形成数据 线、 源电极和漏电极的图形。
步骤 g: 在经过步骤 f的衬底基板上形成钝化层 2;
具体地， 在经过步骤 f的衬底基板上采用磁控溅射、 热蒸发、 PECVD或 其它成膜方法沉积厚度为 400- 5000A的钝化层材料， 其中， 钝化层材料可以 选用氧化物、氮化物或氮氧化物。具体地，钝化层可以是 SiNx、SiOx或 Si(ON)x。 钝化层可以是单层结构， 也可以是采 ffi氮化硅和氧化硅构成的两层结构。 在钝化层 料上涂敷一层光刻胶； 采 ffi掩膜板对光刻胶进行曝光， 使光 刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶未保留区域对 应于钝化层的过孔所在区域， 光刻胶保留区域对应于过孔以外的区域； 进行 显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶保留区域的光刻 胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的钝化层材料， 剥离剩余的光刻胶， 形成包括过孔的钝化层 2的图形， 其中该次刻蚀工艺的 刻蚀时间为第一预设时间。
步骤 h: 利用制作像素电极的掩膜板对钝化层进行第二次刻馊； 在经过步骤 g的钝化层上涂敷一层光刻胶； 采用制作像素电极的掩膜板 对光刻胶进行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域， 其 中， 光刻胶保留区域对应于像素电极的图形所在区域， 光刻胶未保留区域对 应于上述图形以外的区域； 进行显影处理， 光刻胶未保留区域的光刻胶被完 全去除， 光刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀工艺刻蚀掉光刻 胶未保留区域的部分钝化层材料， 剥离剩余的光刻胶， 形成对应像素电极图 形的钝化层图形， 其中该次刻蚀工艺的刻蚀时间为第二预设时间， 第二预设 时间小于第一预设时间， 因此并不会将钝化层完全刻透。 钝化层包括有对应 像素电极的钝化层图形， 像素电极下的钝化层厚度大于其他区域的钝化层厚 度， 与像素电极对应的钝化层图形的边缘存在有斜坡。
步骤 在经过步骤 h的衬底基板 4上形成像素电极 10。
具体地， 在经过步骤 h的衬底基板 4上采用磁控溅射、 热蒸发或其它成 膜方法沉积厚度为 300- 1500A的 ITO膜层， 即可形成如图 5所示的结构。 在 ITO膜层上涂敷一层光刻胶； 采用像素电极掩膜板对光刻胶进行曝光， 使光 刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留区域对应 于像素电极的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域； 进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶保留区域的 光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的透明导 电层， 剥离剩余的光刻胶， 形成像素电极的图形， 像素电极通过钝化层的过 与漏电极电性连接。 如图 5所示， 在沉积 ΙΊΌ层时， 正向面对靶材的 ΠΌ层部分厚度为 a， 在钝化层斜坡处，侧向面对靶材的 ΠΌ层部分厚度为 b， b较 a有明显的减小。 显影处理之后， 光刻胶覆盖着斜坡上面的部分即需要保留 ITO层的区域， 在 刻蚀形成像素电极的过程中， 使 ffi用于 a厚度 ΙΤΌ层的刻馊液进行刻蚀， 与 干刻不同， 在刻蚀液中， 各个方向上的刻蚀程度是一致的， 所以斜坡处刻蚀 效果明显优于正向面对靶材的 ΠΌ层部分的刻蚀效果， 能够将斜坡处的 ΠΌ 层完全去除掉， 不再残留 ITO或 ITO结晶， 最终如图 6所示， 在像素电极 10 的周边形成无残留的隔离带 8， 使像素电极 8与刻蚀残留部分 9分开， 使得 刻蚀的效果得到体现， 减小了刻蚀残留对显示装置的性能的影响。 当然像素 电极不限于 ΙΤΌ 料， 氧化铟锌 （IZO) 等 料也可以应^上述阵列基板的 制造方法形成像素电极。
上述实施例以刻蚀 ΙΤΌ层为例说明本发明阵列基板的制作方法，实际上， 不但 ITO层， 各种难以刻蚀的金属层或金属氧化物层， 均可使用此方法进行 处理： 在沉积金属层或金属氧化物层之前， 利用制作金属层或金属氧化物层 的掩膜板对金属层或金属氧化物层之下的绝缘层进行预刻蚀， 使绝缘层具有 与金属层图形或金属氧化物层图形相应的图形， 在应形成的金属层图形或金 属氧化物层图形的边缘存在斜坡， 使得后续沉积金属层或金属氧化物层时， 能够在斜坡处形成较薄的金属层或金属氧化物层， 最终刻蚀形成金属层图形 或金属氧化物层图形后， 在金属层图形或金属氧化物层图形周边形成无残留 的隔离带， 使金属层图形或金属氧化物层图形与刻蚀残留部分分开， 减小了 刻蚀残留对显示装置的性能的影响。
本发明实施例还提供了一种以上述制作方法的阵列基板， 所述阵列基板 的至少一导电图形之下的绝缘层包括有与所述导电图形对应的绝缘层图形， 所述导电图形与所述绝缘层图形的边缘对齐。
进一歩地，所述导电图形下的绝缘层厚度大于其他区域处的绝缘层厚度。 进一步地， 与所述导电图形对应的绝缘层图形的边缘存在有斜坡。 所述 导电图形可以为源电极、 漏电极、 数据线、 栅电极、 栅线或像素电极。
本发明的阵列基板， 导电图形之下的绝缘层具有与导电图形对应的绝缘 层图形。 这样在此种阵列基板的绝缘层上沉积导电膜层制作导电图形时， 由 于在绝缘层图形的边缘存在斜坡， 斜坡处的导电膜层很薄， 使得刻蚀导电图 形的过程变得比较容易， 即使斜坡下方的导电膜层有残留， 也将被无残留的 斜坡所阻挡，起到良好的隔绝效果，在导电图形的周边形成无残留的隔离带， 使得导电图形与刻馊残留的部分分开， 使得刻馊的效果得到体现， 减小了刻 蚀残留对显示装置的性能的影响。
进一步地， 所述阵列基板包括有位于源电极、 漏电极和数据线之下的绝 缘层， 所述绝缘层可以为刻蚀阻挡层， 在所述导电图形之下的绝缘层为刻蚀 阻挡层时， 所述阵列基板的源电极、 漏电极和数据线之下的刻蚀阻挡层具有 与所述源电极、 漏电极、 数据线和数据线对应的刻蚀阻挡层图形， 源电极、 漏电极、 数据线与刻蚀阻挡层的边缘对齐。
进一步地， 所述阵列基板包括有位于 »电极和栅线之下的绝缘层， 所述 导电图形可以为栅电极和栅线的图形， 所述导电图形之下的绝缘层可以为栅 电极和 »线之下的缓冲层， 所述阵列基板的栅电极和栅线之下的缓冲层具有 与所述栅电极和栅线对应的缓冲层图形， 栅电极和栅线与缓冲层图形的边缘 对齐。
进一步地， 所述阵列基板包括有位于像素电极之下的绝缘层， 所述导电 图形可以为像素电极的图形， 所述导电图形之下的绝缘层可以为像素电极之 下的钝化层， 所述阵列基板的像素电极之下的钝化层具有与所述像素电极对 应的钝化层图形， 像素电极与钝化层的边缘对齐。
本发明实施例还提供了一种显示装置，包括如上所述的 列基板。其中， 列基板的结构以及工作原理同上述实施例， 在此不再赘述。 另外， 显示装 置其他部分的结构可以参考现有技术， 对此本文不再详细描述。 该显示装置 可以为： 液晶面板、 电子纸、 OLED (Organic Light Emitting Diode, 有机发 光二极管） 面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等具 有任何显示功能的产品或部件。
以上所述是本发明的优选实施方式， 应当指出， 对于本技术领域的普通 技术人员来说， 在不脱离本发明所述原理的前提下， 还可以作出若干改进和 润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

1 . 一种阵列基板的制作方法， 其中， 包括：
在制作导电图形之前， 利用制作导电图形的掩膜板对所述导电图形之下 的绝缘层进行构图；
沉积导电层， 利用所述制作导电图形的掩膜板对所述导电层进行构图形 成所述导电图形。
2. 根据权利要求 1所述的阵列基板的制作方法， 其中， 所述在制作导电 图形之前， 利^制作导电图形的掩膜板对所述导电图形之下的绝缘层进行构 图包括：
形成绝缘层的第一图形；
在形成有所述绝缘层的第一图形的基板上涂覆光刻胶， 利 ffi所述制作导 电图形的掩膜板对光刻胶进行曝光， 使所述第一光刻胶形成第一光刻胶未保 留区域和第一光刻胶保留区域， 其中， 所述第一光刻胶保留区域对应于所述 导电图形所在区域， 所述第一光刻胶未保留区域对应于所述导电图形以外的 区域， 进行显影处理， 所述第一光刻胶未保留区域的光刻胶被完全去除， 所 述第一光刻胶保留区域的光刻胶厚度保持不变；
通过刻蚀工艺刻蚀掉所述第一光刻胶未保留区域的部分绝缘层， 剥离剩 余的光刻胶， 形成与所述导电图形对应的绝缘层第二图形， 所述绝缘层第二 图形的边缘处存在有斜坡。
3. 根据权利要求 2所述的阵列基板的制作方法， 其中， 所述导电图形下 的绝缘层厚度大于其他区域处的绝缘层厚度。
4. 根据权利要求 1-3中任一项所述的阵列基板的制作方法， 其中， 所述 沉积导电层， 利用所述制作导电图形的掩膜板对所述导电层进行构图形成所 述导电图形包括：
在所述绝缘层上沉积导电层；
在所述导电层上涂覆光刻胶， 利用所述制作导电图形的掩膜板对光刻胶 进行曝光， 使所述第二光刻胶形成第二光刻胶未保留区域和第二光刻胶保留 区域， 其中， 所述第二光刻胶保留区域对应于所述导电图形所在区域， 所述 第二光刻胶未保留区域对应于所述导电图形以外的区域， 进行显影处理， 所 述第二光刻胶未保留区域的光刻胶被完全去除， 所述第二光刻胶保留区域的 光刻胶厚度保持不变；
通过刻馊工艺完全刻馊掉所述第二光刻胶未保留区域的导电层， 剥离剩 余的光刻胶， 形成所述导电图形。
5. 根据权利要求 4所述的阵列基板的制作方法， 其中， 所述导电图形为 源电极、 漏电极、 数据线、 栅电极、 櫥线或像素电极。
6. 根据权利要求 1 5中任一项所述方法制作的阵列基板， 其中， 至少一 导电图形之下的绝缘层包括有与所述导电图形对应的绝缘层图形， 所述导电 图形与所述绝缘层图形的边缘对齐。
7. 根据权利要求 6所述的阵列基板， 其中， 所述导电图形下的绝缘层厚 度大于其他区域处的绝缘层厚度。
8. 根据权利要求 6或 7所述的阵列基板， 其中， 与所述导电图形对应的 绝缘层图形的边缘存在有斜坡。
9. 根据权利要求 8所述的阵列基板， 其中， 所述导电图形为源电极、 漏 电极、 数据线、 栅电极、 栅线或像素电极。
10. 一种显示装置， 其中， 包括如权利要求 6 9 中任一项所述的 列基 板。
PCT/CN2014/078923 2013-12-20 2014-05-30 阵列基板及其制作方法、显示装置 WO2015090008A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114141936A (zh) * 2020-09-03 2022-03-04 京东方科技集团股份有限公司 一种显示基板、其制作方法及显示装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700670B (zh) * 2013-12-20 2016-08-17 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN106086797B (zh) * 2016-07-12 2018-12-11 京东方科技集团股份有限公司 氧化铟锡薄膜及其制备方法、含其的阵列基板、显示装置
CN108987411A (zh) * 2017-06-02 2018-12-11 京东方科技集团股份有限公司 阵列基板及其制备方法和显示装置
CN114924437B (zh) * 2022-05-20 2024-01-12 北京京东方技术开发有限公司 阵列基板及其制备方法、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101034215A (zh) * 2006-03-09 2007-09-12 京东方科技集团股份有限公司 一种液晶显示器阵列基板的像素结构及其制造方法
CN202948924U (zh) * 2012-09-13 2013-05-22 北京京东方光电科技有限公司 一种阵列基板及显示装置
CN103378164A (zh) * 2012-04-23 2013-10-30 乐金显示有限公司 阵列基板及其制造方法
CN103700670A (zh) * 2013-12-20 2014-04-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100617056B1 (ko) * 2004-12-30 2006-08-30 동부일렉트로닉스 주식회사 비어 식각시 어텍을 방지하는 방법
KR100656738B1 (ko) * 2005-12-14 2006-12-14 한국과학기술원 집적형 박막 태양전지 및 그 제조 방법
CN101833204A (zh) * 2009-03-13 2010-09-15 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101034215A (zh) * 2006-03-09 2007-09-12 京东方科技集团股份有限公司 一种液晶显示器阵列基板的像素结构及其制造方法
CN103378164A (zh) * 2012-04-23 2013-10-30 乐金显示有限公司 阵列基板及其制造方法
CN202948924U (zh) * 2012-09-13 2013-05-22 北京京东方光电科技有限公司 一种阵列基板及显示装置
CN103700670A (zh) * 2013-12-20 2014-04-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114141936A (zh) * 2020-09-03 2022-03-04 京东方科技集团股份有限公司 一种显示基板、其制作方法及显示装置

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