WO2018219138A1 - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2018219138A1
WO2018219138A1 PCT/CN2018/086843 CN2018086843W WO2018219138A1 WO 2018219138 A1 WO2018219138 A1 WO 2018219138A1 CN 2018086843 W CN2018086843 W CN 2018086843W WO 2018219138 A1 WO2018219138 A1 WO 2018219138A1
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Prior art keywords
signal line
line
photoresist
array substrate
conductive film
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PCT/CN2018/086843
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English (en)
French (fr)
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黎午升
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京东方科技集团股份有限公司
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Priority to US16/322,420 priority Critical patent/US20190181161A1/en
Publication of WO2018219138A1 publication Critical patent/WO2018219138A1/zh
Priority to US17/337,687 priority patent/US11469258B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, and a display device.
  • the material constituting the source/drain metal layer generally further includes molybdenum crucible (chemical formula: MoNb), and the molybdenum crucible layer is usually formed on the upper and lower surfaces of the copper metal layer to protect the copper.
  • the adhesion of the photoresist to the surface of the molybdenum crucible layer is low.
  • a data line is formed on the surface of the gate line in the array substrate, since the gate line itself has a certain thickness, the data line has a climbing phenomenon at the overlap with the gate line.
  • a photoresist a photoresist is on the surface of the top molybdenum layer
  • the photoresist and the top molybdenum layer are The adhesion is low, so the photoresist is prone to voids at the above-mentioned climbing slope.
  • the etching liquid intrudes into the conductive film layer from the gap, and the formed data line is easily broken.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device for reducing a probability that a signal line at a top layer is broken at a climbing position when a signal line disposed at an intersection is formed in the array substrate.
  • An aspect of the present invention provides a method for fabricating an array substrate, comprising: forming a first conductive film on a substrate, and patterning the first conductive film to form a first conductive layer formed of a conductive pattern,
  • the first conductive layer includes a first signal line;
  • a second conductive film is formed on the first conductive layer, and the second conductive film is patterned to form a second conductive layer composed of a conductive pattern, the second conductive layer includes a second signal line;
  • the first signal line and the second signal line are cross-insulated; wherein a portion of the upper surface of the first signal line that overlaps the second signal line is along the The length of at least one edge of the extending direction of the two signal lines is greater than the linear distance between the two vertices of the edge.
  • a width of the orthogonal intersection of the second signal line and the first signal line on the substrate is greater than the second signal line and the first signal line on the substrate The width of the area on the upper orthographic projection that does not coincide.
  • the preparation method further includes: roughening the second conductive film.
  • the roughening treatment of the second conductive film comprises: coating a photoresist on the surface of the second conductive film, performing pre-baking, exposure, development, and post-baking processes on the photoresist And removing the photoresist.
  • Another aspect of an embodiment of the present invention provides an array substrate including a substrate, a first signal line and a second signal line sequentially disposed on the substrate, the first signal line and the second signal line intersecting An insulating arrangement; a portion of the upper surface of the first signal line overlapping the second signal line, a length of at least one edge along an extending direction of the second signal line being greater than between two vertices of the edge Straight line distance.
  • a portion of the upper surface of the first signal line that overlaps the second signal line has an edge along an extending direction of the second signal line.
  • a width of the orthogonal intersection of the second signal line and the first signal line on the substrate is greater than the second signal line and the first signal line on the substrate The width of the area on the upper orthographic projection that does not coincide.
  • the first signal line is a gate line and/or a common line
  • the second signal line is a data line
  • the first signal line is a data line
  • the second signal line is a gate line And / or public line.
  • the second signal line is composed of a first copper diffusion barrier layer, a copper/copper alloy layer, and a second copper diffusion barrier layer disposed in sequence.
  • a display device comprising any of the array substrates described above.
  • An embodiment of the present invention provides an array substrate, a preparation method thereof, and a display device, and a method for preparing an array substrate, which specifically includes: forming a first conductive film on a substrate, and patterning the first conductive film to form a conductive pattern a conductive layer, the first conductive layer includes a first signal line; a second conductive film is formed on the first conductive layer, the second conductive film is patterned to form a second conductive layer formed of the conductive pattern, and the second conductive layer includes a second The signal line, the first signal line and the second signal line are cross-insulated.
  • the portion of the upper surface of the first signal line that overlaps the second signal line has a length along at least one edge of the extending direction of the second signal line that is greater than a linear distance between the two vertices of the edge.
  • the contact area of the second conductive film with the first conductive layer at the hill climbing is increased with respect to the case where the edge length is equal to the linear distance between the two vertices of the edge.
  • the contact area of the photoresist on the climbing surface and the second conductive film is increased, thereby reducing the probability of the photoresist generating the gap at the climbing edge, so that It is possible to reduce the probability that the etching liquid intrudes into the second conductive film from the gap when the etching process is performed, causing the second signal line to be broken.
  • FIG. 1 is a flowchart of a method for preparing an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of an array substrate prepared according to the preparation method shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is an enlarged view of an area A in the array substrate shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a first signal line and a second signal line in the array substrate shown in FIG. 3;
  • FIG. 6 is another schematic structural diagram of a first signal line and a second signal line in the array substrate shown in FIG. 3;
  • FIG. 7 is another schematic structural diagram of a first signal line and a second signal line in the array substrate shown in FIG. 3;
  • FIGS. 8(a)-8(f) are schematic diagrams showing a process of preparing an array substrate according to an embodiment of the present invention.
  • the embodiment of the invention provides a method for preparing an array substrate, as shown in FIG. 1 , which includes:
  • Step S101 as shown in FIG. 2, forming a first conductive film on the substrate 10, and patterning the first conductive film to form a first conductive layer 11 composed of a conductive pattern.
  • the first conductive layer 11 includes The first signal line 111.
  • the above composition may refer to a process including a photolithography process, or a photolithography process and an etching step to form a predetermined pattern.
  • the lithography process includes a process of forming a film, exposing, developing, etc., and specifically, a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like.
  • Step S102 as shown in FIG. 2, forming a second conductive film on the first conductive layer 11, and patterning the second conductive film to form a second conductive layer 12 composed of a conductive pattern, as shown in FIG. 12 includes a second signal line 121; the first signal line 111 and the second signal line 121 are cross-insulated.
  • a portion of the upper surface of the first signal line 111 overlapping the second signal line 121 has a length along at least one edge E of the extending direction of the second signal line 121 that is greater than two vertices of the edge.
  • the extending direction of the second signal line 121 is the Y direction in FIG.
  • the shape of the mask can be controlled to have a specific pattern identical to the shape of the first signal line 111 to be formed, thereby being formed by exposing the mask and performing a subsequent photolithography process.
  • the first signal line 111 has the above features.
  • an insulating layer may be formed on the surface of the first conductive layer 11, and then the second conductive layer 12 is formed on the surface of the insulating layer, so that the formed first signal line 111 is formed.
  • the second signal line 121 is cross-insulated and disposed, and the second signal line 121 is located above the first signal line 111.
  • the second conductive film is patterned to form a second conductive layer 12 composed of a conductive pattern. Specifically, a photoresist is coated on the surface of the second conductive film, and exposed, developed, and etched. A second conductive layer 12 is formed.
  • the present invention provides a method for preparing an array substrate. Specifically, a first conductive film is formed on the substrate 10, and the first conductive film is patterned to form a first conductive layer 11 composed of a conductive pattern.
  • the first conductive layer 11 includes a first signal line 111; a second conductive film is formed on the first conductive layer 11, and the second conductive film 12 is patterned to form a second conductive layer 12 composed of a conductive pattern, and the second conductive layer 12 includes a second signal line 121.
  • the first signal line 111 and the second signal line 121 are cross-insulated.
  • the portion of the upper surface of the first signal line 111 overlapping the second signal line 121, the length of at least one edge E along the extending direction of the second signal line 121 is greater than the linear distance between the two vertices of the edge E. .
  • the contact area of the second conductive film with the first conductive layer 11 at the climbing slope is relative to the length of the edge E being equal to the linear distance between the two vertices of the edge E.
  • the contact area of the photoresist with the second conductive film at the climbing slope is increased, which reduces the probability of the photoresist at the climbing edge, and thus can be reduced.
  • the etching liquid intrudes into the second conductive film from the gap, causing the probability that the formed second signal line 121 is broken.
  • the present invention does not limit the shape of the above-described edge E as long as the length of the edge E is larger than the straight line distance J between the two vertices of the edge E.
  • the edge E may be as shown in FIG. 4, at least one edge E may be an arc; or the edge E may be a polygonal line.
  • the edge E as an arc as an example, in order to increase the contact area of the photoresist with the second conductive film at the climbing position when forming the second signal line 121 by the patterning process, optionally, the upper surface of the first signal line 111 In the portion overlapping the second signal line 121, the two edges E along the extending direction of the second signal line 121 are all arcs, and as shown in FIG. 5, the arc of the arc of the two edges E may be The direction of the protrusions is the same, and of course, the direction of the arc of the arcs of the two edges E may be different.
  • the width of the portion of the upper surface of the first signal line 111 overlapping the second signal line 121 is larger. Narrow, the first signal line 111 is extremely prone to disconnection. Therefore, in the case where the first signal line 111 is thin, preferably, a portion where the upper surface of the first signal line 111 overlaps with the second signal line 121, and two edges E along the extending direction of the second signal line 121 The circular arcs of the arc are in the same or opposite direction.
  • the gate is served by a portion of the gate line.
  • the first signal line 111 is a gate line
  • the second signal line 121 is a data line.
  • the first signal line 111 includes a convex portion B and a gate line body C
  • the second signal line 121 overlaps the convex portion B
  • the drain electrode 13 overlaps the convex portion B.
  • the first signal line 111 is thick, even if the upper surface of the first signal line 111 overlaps the second signal line 121, the circle of the two edges E along the extending direction of the second signal line 121 The arc bump directions are opposite, and since the width of the portion of the upper surface of the first signal line 111 overlapping the second signal line 121 is wide, the probability of occurrence of the disconnection can be reduced.
  • the second signal line 121 and the first signal line 111 are on the substrate 10.
  • width W of the overlapping area of an orthographic projection a second signal line 121 is greater than the area of the orthogonal projection of the first signal line 111 on the substrate 10 is not overlapped width W 2.
  • the width of the second signal line 121 refers to a linear distance between one end and the other end of the second signal line 121 along the extending direction of the first signal line 111 (the X direction shown in FIG. 3).
  • the second signal formed by controlling the shape of the mask to have the same specific pattern as the shape of the second signal line 121 to be formed, thereby exposing through the mask and performing the subsequent photolithography process.
  • the line 121 has the above shape.
  • the present invention does not limit the type of the array substrate.
  • the signal lines that are arranged in the array substrate when the signal lines located at the bottom of the two signal lines are overlapped, the signal lines located at the bottom layer can be realized. Reduce the probability that the signal line at the top layer will be broken when the signal line is formed.
  • the array substrate is of a bottom gate type, as shown in FIG.
  • the first signal line 111 may be a gate line or a common line (Gate Common) in the same layer as the gate line, and the second signal line 121 is The data line (SD Line); when the array substrate is of a top gate type, the first signal line 111 is a data line, and the second signal line 121 is a gate line or a common line in the same layer as the gate line.
  • first signal line 111 and the second signal line 121 described above are usually formed using a copper/copper alloy. Since the properties of copper are relatively active, in order to prevent the copper/copper alloy from being oxidized or diffused into the active layer or other layers, contamination of other layers may be caused. Alternatively, the upper surface of the copper/copper alloy layer may be formed. The second copper diffusion barrier layer and the lower surface form a first copper diffusion barrier layer. Wherein, the first copper diffusion barrier layer and the second copper diffusion barrier layer can prevent copper from diffusing into other film layers, such as the active layer, and can also prevent the copper/copper alloy from being oxidized in the subsequent fabrication process of the film layer.
  • the material constituting the copper diffusion barrier layer comprises a molybdenum-niobium alloy, a molybdenum-titanium alloy, an indium tin oxide (ITO), an indium zinc oxide (IZO), a molybdenum-niobium alloy, a molybdenum-titanium alloy, an indium tin oxide, an indium zinc oxide.
  • the copper/copper alloy can be well prevented from diffusing and reducing its chance of being oxidized.
  • the manufacturing method provided by the embodiment of the present invention is such that a portion of the upper surface of the first signal line 111 overlapping the second signal line 121 is along at least one edge E of the extending direction of the second signal line 121.
  • the length of the wire is greater than the linear distance J between the two vertices of the edge E to increase the contact area of the second conductive film with the first conductive layer 11 at the climbing slope, thereby effectively reducing the formation of the photoresist on the surface of the second conductive film. The probability of a gap in the photoresist at the climb.
  • the array substrate is used as the bottom gate type
  • the first signal line 111 is the gate line
  • the second signal line 121 is the data line.
  • the preparation process of the array substrate is described. Specifically, the following steps can be implemented.
  • S12 exposing the photoresist by using a mask, and forming a photoresist remaining portion and a photoresist removing portion after development.
  • the length of the opaque portion of the reticle in the extending direction along the second signal line 121, the at least one side of the pre-overlapping of the gate film and the second signal line 121 is greater than the two vertices of the side The straight line distance between them.
  • a portion of the formed photoresist remaining portion corresponding to the second signal line 121 in the upper surface of the first signal line 111 may be formed, along at least one edge of the extending direction of the second signal line 121.
  • the length is greater than the linear distance between the two vertices of the edge.
  • the first conductive layer 11 includes a first signal line 111, and the first signal line 111 is as shown in FIG. 4, and a portion of the upper surface overlapping the second signal line 121 along the extending direction of the second signal line 121
  • the length of at least one edge E is greater than the linear distance J between the two vertices of edge E.
  • the gate insulating layer 20 may be deposited on the substrate 10 on which the first conductive layer 11 is formed by PECVD.
  • an active layer 21 and a second conductive layer 12 are formed on the substrate 10 on which the first conductive layer 11 is formed.
  • Step S21 as shown in FIG. 8(a), an oxide semiconductor film 31, a first copper diffusion barrier film layer 32, and a copper/copper alloy film layer 33 are sequentially formed on the substrate 10 on which the first conductive layer 11 is formed. a second conductive film formed by the second copper diffusion barrier film layer 34, and a photoresist 35 is formed over the second conductive film.
  • Step S22 as shown in FIG. 8(b), the photoresist 35 is exposed by the halftone mask 40, and after the development, the photoresist completely remaining portion 351, the photoresist semi-retained portion 352, and the photoresist are completely removed.
  • the photoresist completely remaining portion 351 corresponds to the source and drain electrodes 13
  • the photoresist half-retaining portion 352 corresponds to the region between the source and the drain 13
  • the photoresist completely removed portion corresponds to other regions.
  • the halftone mask comprises an opaque portion, a translucent portion and a transparent portion.
  • the photoresist 35 After the photoresist 35 is exposed, the photoresist completely retains the portion 351 corresponding to the opaque portion of the halftone mask, the photoresist half-retained portion 352 corresponds to the translucent portion of the halftone mask, and the photoresist is completely removed to correspond to the halftone.
  • the transparent portion of the reticle After the photoresist 35 is exposed, the photoresist completely retains the portion 351 corresponding to the opaque portion of the halftone mask, the photoresist half-retained portion 352 corresponds to the translucent portion of the halftone mask, and the photoresist is completely removed to correspond to the halftone.
  • the transparent portion of the reticle After the photoresist 35 is exposed, the photoresist completely retains the portion 351 corresponding to the opaque portion of the halftone mask, the photoresist half-retained portion 352 corresponds to the translucent portion of the halftone mask, and
  • the photoresist 35 referred to above is a positive glue.
  • the photoresist 35 is a negative glue
  • the photoresist completely remaining portion 351 corresponds to the transparent portion of the halftone mask, and the photoresist is completely removed.
  • the photoresist half-retaining portion 352 still corresponds to the translucent portion of the halftone mask.
  • Step S23 as shown in FIG. 8(c), performing a first copper etching process, the first copper diffusion barrier film layer 32 corresponding to the completely removed portion of the photoresist, the copper/copper alloy film layer 33, and the second The copper diffusion barrier film layer 34 is etched.
  • an overetching time of 10% to 20% is usually used to keep the etching clean.
  • the etching time is shortened as much as possible to reduce the probability of occurrence of photoresist stripping and signal line breakage.
  • step S24 as shown in FIG. 8(d), the oxide semiconductor thin film 31 is etched, and the oxide semiconductor thin film 31 corresponding to the completely removed portion of the photoresist is etched to obtain an oxide active layer 21.
  • Step S25 as shown in FIG. 8(e), the photoresist semi-retained portion 352 is removed by an ashing process.
  • the ashing time is shortened as much as possible to reduce the probability of occurrence of photoresist stripping and signal line disconnection.
  • the photoresist 35 shown in FIG. 8(e) is dried.
  • the drying temperature is 110° to 150°
  • the time is 100s to 200s. In this way, the adhesion of the photoresist 35 on the surface of the second copper diffusion barrier layer 34 can be increased.
  • Step S26 as shown in FIG. 8(f), the exposed first copper diffusion barrier film layer 32, the copper/copper alloy film layer 33, and the second copper diffusion barrier film layer 34 are performed by a second copper etching process. Etching forms the second conductive layer 12 described above.
  • an overetching time of 10% to 20% is usually used to keep the etching clean.
  • the etching time is shortened as much as possible to reduce the probability of occurrence of photoresist 35 peeling and signal line disconnection.
  • the preparation method further includes: roughening the second conductive film.
  • the specific manner of the above roughening treatment is not limited in the present invention, as long as the surface of the second conductive film is roughened after the second conductive film is processed.
  • the adhesion effect of the photoresist 35 on the second conductive film can be increased, thereby reducing the photoresist 35 at The probability of a gap in the above climbing slope.
  • the roughening treatment of the second conductive film may include: coating the surface of the second conductive film with a photoresist 35, pre-baking, exposing, developing, and post-baking the photoresist 35, and illuminating the light.
  • the glue 35 is removed.
  • the surface of the second conductive film can be treated by the high temperature photoresist 35, so that the surface of the second conductive film is rough.
  • the oxide active layer 21 and the second conductive layer 12 are formed by one patterning process, which has the effect of simplifying the process steps, and can reduce the process cost.
  • the oxide active layer 21 may be formed by one patterning process first, and then the second conductive layer 12 is formed by one patterning process.
  • an ordinary adjustment mask is used for the exposure process, and the shape of the mask can be controlled to control the formation.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 3, including a substrate 10, a first signal line 111 and a second signal line 121, a first signal line 111 and a second signal, which are sequentially disposed on the substrate 10.
  • Line 121 is cross-insulated.
  • a portion of the upper surface of the first signal line 111 that overlaps with the second signal line 121 has a length along at least one edge E of the extending direction of the second signal line 121 that is greater than the edge E.
  • first signal line 111 and the second signal line 121 are sequentially disposed on the substrate 10, so the second signal line 121 is located above the first signal line 111, and thus the second signal line 121 and the first signal At the intersection of the lines 111, the second signal line 121 has a climbing phenomenon.
  • the above array substrate provided by the present invention includes a first signal line 111 and a second signal line 121 which are disposed in a cross-insulating manner, wherein a portion of the upper surface of the first signal line 111 overlapping the second signal line 121, The length of at least one edge E along the extending direction of the second signal line 121 is greater than the linear distance J between the two vertices of the edge E.
  • the second signal line 121 is formed by the patterning process on the substrate 10 on which the first signal line 111 is formed, in the case where the thickness of the first signal line 111 is constant, the length with respect to the edge E is equal to the two vertices of the edge E The linear distance between the two conductive layers 12 is formed by the patterning process, the contact area of the second conductive film with the first conductive layer 11 at the climbing slope is increased, thereby forming a photoresist on the surface of the second conductive film.
  • the contact area of the photoresist 35 with the second conductive film at the climbing slope is increased, which reduces the probability of the gap generated by the photoresist 35 at the climbing slope, thereby reducing the etching liquid during the etching process.
  • the voids invade the second conductive film, causing the probability that the formed second signal line 121 is broken.
  • the present invention does not limit the shape of the edge E as long as the length of the edge E is greater than the linear distance J between the two vertices of the edge E.
  • the edge E may be as shown in FIG. 4, and the edge E may be an arc or a broken line.
  • the upper surface of the first signal line 111 and the The portions where the two signal lines 121 overlap, and the two edges E along the extending direction of the second signal line 121 are arcs.
  • the arc convex directions of the arcs of the two edges E are the same, and of course, the arc convex directions of the arcs of the two edges E may be different.
  • the first signal line 111 is disconnected due to the narrow width of the portion of the upper surface of the first signal line 111 overlapping the second signal line 121, preferably, the first signal line 111
  • the portion of the upper surface overlapping the second signal line 121 has the same or opposite direction of the arc of the arc of the two edges E along the extending direction of the second signal line 121.
  • the second signal line 121 and the first signal line 111 are on the substrate 10.
  • the width W of the overlapping area of the orthogonal projection 1, greater than the width W of the second signal lines 121 and 111 in the orthographic projection of the first signal line 10 is not overlapped on the substrate region 2.
  • the width of the second signal line 121 refers to a linear distance between one end and the other end of the second signal line 121 along the extending direction of the first signal line 111 (the X direction shown in FIG. 3).
  • first signal line 111 and the second signal line 121 described above are usually formed using a copper/copper alloy. Since the properties of copper are relatively active, in order to prevent the copper/copper alloy from being oxidized or diffused into the active layer or other layers, contamination of other layers is caused.
  • the first signal line 111 and the second signal line 121 are selected.
  • the first copper diffusion barrier layer, the copper/copper alloy layer, and the second copper diffusion barrier layer are sequentially disposed.
  • the first copper diffusion barrier layer and the second copper diffusion barrier layer can prevent copper from diffusing into other film layers, such as the active layer, and can also prevent the copper/copper alloy from being oxidized in the subsequent fabrication process of the film layer. .
  • the material constituting the copper diffusion barrier layer comprises a molybdenum-niobium alloy, a molybdenum-titanium alloy, an indium tin oxide, an indium zinc oxide, a molybdenum-niobium alloy, a molybdenum-titanium alloy, an indium tin oxide, and an indium zinc oxide, which can prevent copper well. / Copper alloy diffusion and reduce its chance of being oxidized.
  • the present invention does not limit the type of the array substrate, and may be, for example, a bottom gate type array substrate or a top gate type array substrate.
  • a plurality of signal lines are disposed at the intersection.
  • the first signal line 111 may be a gate line or may be the same as the gate line.
  • the common line of the layer, the second signal line 121 is a data line; when the array substrate is of a top gate type, the first signal line 111 is a data line, the second signal line 121 is a gate line, or is common to the same layer as the gate line line.
  • An embodiment of the present invention provides a display device, including any of the array substrates described above, which has the same structure and advantageous effects as the array substrate provided by the foregoing embodiments, since the foregoing embodiments have already been applied to the array substrate.
  • the structure and beneficial effects are described in detail and will not be described here.

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Abstract

一种阵列基板及其制备方法、显示装置，涉及显示技术领域，用于降低在阵列基板中形成交叉设置的信号线时，位于顶层的信号线在爬坡处发生断线的几率。该制备方法包括：在衬底（10）上形成第一导电薄膜，对第一导电薄膜构图形成由导电图案构成的第一导电层（11），第一导电层（11）包括第一信号线（111）；在第一导电层（11）上形成第二导电薄膜，对第二导电薄膜构图形成由导电图案构成的第二导电层（12），第二导电层（12）包括第二信号线（121）；第一信号线（111）和所述第二信号线（121）交叉绝缘设置；其中，第一信号线（111）的上表面中与所述第二信号线（121）交叠的部分，沿第二信号线（121）的延伸方向的至少一边缘（E）的长度大于边缘两个顶点之间的直线距离（J）。

Description

一种阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
阵列基板制备时，通常采用铜作为阵列基板中包括源极、漏极及数据线的源漏金属层的材料。由于铜的性质较为活泼，易扩散至其他膜层中，且在高温或外加电场的作用下，铜易被氧化，影响阵列基板构成的显示器件的显示效果。因此通常构成源漏金属层的材料还包括钼铌(化学式：MoNb)，钼铌层通常形成在铜金属层的上下表面，以对铜进行保护。
然而，光刻胶在钼铌层表面的粘附力较低。当在阵列基板中的栅线表面形成数据线时，由于栅线自身具有一定的厚度，因此数据线在与栅线交叠处存在爬坡现象。在底钼铌层、铜金属层、顶钼铌层构成的导电膜层的表面涂覆光刻胶(光刻胶在顶钼铌层的表面)时，由于光刻胶与顶钼铌层的粘附力较低，因此光刻胶在上述爬坡处易产生空隙，在后续的刻蚀工艺中，刻蚀液从上述空隙处侵入导电膜层中，易使得形成的数据线发生断线。
发明内容
本发明的实施例提供一种阵列基板及其制备方法、显示装置，用于降低在阵列基板中形成交叉设置的信号线时，位于顶层的信号线在爬坡处发生断线的几率。
为达到上述目的，本发明的实施例采用如下技术方案：
本发明实施例的一方面，提供一种阵列基板的制备方法，包括：在衬底上形成第一导电薄膜，对所述第一导电薄膜构图形成由导电图案构成的第一导电层，所述第一导电层包括第一信号线；在所述第一导电层上形成第二导电薄膜，对所述第二导电薄膜构图形成由导电图 案构成的第二导电层，所述第二导电层包括第二信号线；所述第一信号线和所述第二信号线交叉绝缘设置；其中，所述第一信号线的上表面中与所述第二信号线交叠的部分，沿所述第二信号线的延伸方向的至少一边缘的长度大于所述边缘两个顶点之间的直线距离。
可选的，所述第二信号线与所述第一信号线在所述衬底上的正投影重合区域的宽度，大于所述第二信号线与所述第一信号线在所述衬底上的正投影未重合的区域的宽度。
可选的，所述制备方法还包括：对所述第二导电薄膜进行粗糙化处理。
进一步的，所述对所述第二导电薄膜进行粗糙化处理，包括：在所述第二导电薄膜表面涂覆光刻胶，对所述光刻胶进行前烘、曝光、显影、后烘工艺，并将所述光刻胶去除。
本发明实施例的另一方面，提供一种阵列基板，包括衬底，在衬底上依次设置的第一信号线和第二信号线，所述第一信号线和所述第二信号线交叉绝缘设置；所述第一信号线的上表面中与所述第二信号线交叠的部分，沿所述第二信号线的延伸方向的至少一边缘的长度大于所述边缘两个顶点之间的直线距离。
可选的，所述第一信号线的上表面中与所述第二信号线交叠的部分，沿所述第二信号线的延伸方向的两个边缘均为弧线。
可选的，所述第二信号线与所述第一信号线在所述衬底上的正投影重合区域的宽度，大于所述第二信号线与所述第一信号线在所述衬底上的正投影未重合的区域的宽度。
可选的，所述第一信号线为栅线和/或公共线，所述第二信号线为数据线；或者，所述第一信号线为数据线，所述第二信号线为栅线和/或公共线。
可选的，所述第二信号线由依次设置的第一铜扩散阻挡层、铜/铜合金层、第二铜扩散阻挡层构成。
本发明实施例的又一方面，提供一种显示装置，包括上述所述的任一种阵列基板。
本发明实施例提供一种阵列基板及其制备方法、显示装置，阵 列基板的制备方法，具体的包括，在衬底上形成第一导电薄膜，对第一导电薄膜构图形成由导电图案构成的第一导电层，第一导电层包括第一信号线；在第一导电层上形成第二导电薄膜，对第二导电薄膜构图形成由导电图案构成的第二导电层，第二导电层包括第二信号线，第一信号线和第二信号线交叉绝缘设置。
其中，第一信号线的上表面中与第二信号线交叠的部分，沿第二信号线的延伸方向的至少一边缘的长度大于边缘两个顶点之间的直线距离。在第一信号线的厚度不变的情况下，相对于边缘长度等于边缘的两个顶点之间的直线距离的情况，第二导电薄膜在爬坡处与第一导电层的接触面积会增加，从而使得在第二导电薄膜表面形成光刻胶时，光刻胶在爬坡处与第二导电薄膜的接触面积增加，进而降低了爬坡处的光刻胶产生空隙的几率，这样一来，可以降低在执行刻蚀工艺时，刻蚀液从上述空隙处侵入第二导电薄膜中，造成形成的第二信号线发生断线的几率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种阵列基板的制备方法流程图；
图2为根据图1所示的制备方法制备的阵列基板的结构示意图；
图3为本发明实施例提供的一种阵列基板的结构示意图；
图4为图3所示的阵列基板中A区的放大图；
图5为图3所示的阵列基板中第一信号线和第二信号线的一种结构示意图；
图6为图3所示的阵列基板中第一信号线和第二信号线的另一种结构示意图；
图7为图3所示的阵列基板中第一信号线和第二信号线的又一 种结构示意图；
图8(a)-8(f)为本发明实施例提供的一种阵列基板的制备过程示意图。
附图标记：
10-衬底；11-第一导电层；111-第一信号线；121-第二信号线；12-第二导电层；13-漏极；20-栅绝缘层；21-氧化物有源层；31-氧化物半导体薄膜；32-第一铜扩散阻挡薄膜层；33-铜/铜合金薄膜层；34-第二铜扩散阻挡薄膜层；35-光刻胶；351-光刻胶完全保留部分；352-光刻胶半保留部分。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种阵列基板的制备方法，如图1所示，包括：
步骤S101、如图2所示，在衬底10上形成第一导电薄膜，对第一导电薄膜构图形成由导电图案构成的第一导电层11，如图3所示，第一导电层11包括第一信号线111。
需要说明的是，上述构图可指：包括光刻工艺，或，包括光刻工艺以及刻蚀步骤形成预定图形的工艺。光刻工艺，包括成膜、曝光、显影等工艺，具体可以利用光刻胶、掩模板、曝光机等形成图形的工艺。
步骤S102、如图2所示，在第一导电层11上形成第二导电薄膜，对第二导电薄膜构图形成由导电图案构成的第二导电层12，如图3所示，第二导电层12包括第二信号线121；第一信号线111和第二信号线121交叉绝缘设置。
其中，如图4所示，第一信号线111的上表面中与第二信号线 121交叠的部分，沿第二信号线121的延伸方向的至少一边缘E的长度大于边缘两个顶点之间的直线距离J。第二信号线121的延伸方向为图3中的Y方向。
需要说明的是，第一、可以通过控制掩模板的形状，使其具有与需要形成的第一信号线111的形状相同的特定图案，从而通过掩模板曝光并执行后续光刻工艺后，形成的第一信号线111具有上述特征。
第二、在形成第一信号线111后，可以在第一导电层11的表面形成一层绝缘层，然后在绝缘层的表面形成上述第二导电层12，从而使得形成的第一信号线111和第二信号线121交叉绝缘设置，且第二信号线121位于第一信号线111的上方。
第三、上述对第二导电薄膜构图，形成由导电图案构成的第二导电层12，具体的，在第二导电薄膜的表面涂覆一层光刻胶，并通过曝光、显影、刻蚀工艺形成第二导电层12。
基于此，本发明提供一种阵列基板的制备方法，具体的，在衬底10上形成第一导电薄膜，对第一导电薄膜构图形成由导电图案构成的第一导电层11，第一导电层11包括第一信号线111；在第一导电层11上形成第二导电薄膜，对第二导电薄膜构图形成由导电图案构成的第二导电层12，第二导电层12包括第二信号线121，第一信号线111和第二信号线121交叉绝缘设置。
其中，第一信号线111的上表面中与第二信号线121交叠的部分，沿第二信号线121的延伸方向的至少一边缘E的长度大于边缘E两个顶点之间的直线距离J。在第一信号线111的厚度不变的情况下，相对于边缘E长度等于边缘E的两个顶点之间的直线距离，第二导电薄膜在爬坡处与第一导电层11的接触面积会增加，从而使得在第二导电薄膜表面形成光刻胶时，光刻胶在爬坡处与第二导电薄膜的接触面积增加，降低了爬坡处的光刻胶产生空隙的几率，进而可以降低在执行刻蚀工艺时，刻蚀液从上述空隙处侵入第二导电薄膜中，造成形成的第二信号线121发生断线的几率。
此外，本发明对上述边缘E的形状不做限定，只要满足边缘E 的长度大于边缘E的两个顶点之间的直线距离J。示例的，上述边缘E可以如图4所示，至少一边缘E可以为弧线；或者边缘E可以为折线。
以边缘E为弧线为例，为了增加通过构图工艺形成第二信号线121时，光刻胶在爬坡处与第二导电薄膜的接触面积，可选的，第一信号线111的上表面中与第二信号线121交叠的部分，沿第二信号线121的延伸方向的两个边缘E均为弧线，此时可以如图5所示，两个边缘E的弧线的圆弧凸起方向相同，当然两个边缘E的弧线的圆弧凸起方向也可以不同。考虑到通常信号线制作的较细，当两个边缘E的弧线的圆弧凸起方向相对时，第一信号线111的上表面中与第二信号线121交叠处的部分的宽度较窄，第一信号线111极易发生断线。因此在第一信号线111较细的情况下，优选的，第一信号线111的上表面与第二信号线121交叠的部分，沿第二信号线121的延伸方向的两个边缘E的弧线的圆弧凸起方向相同或相背。
在制作阵列基板时，为了简化工艺，有时栅极由栅线的一部分充当。示例的，如图7所示，第一信号线111为栅线，第二信号线121为数据线。其中，第一信号线111包括凸起部B和栅线本体C，第二信号线121与凸起部B交叠，漏极13与凸起部B交叠。此时由于第一信号线111较粗，即使第一信号线111的上表面与第二信号线121交叠的部分，沿第二信号线121的延伸方向的两个边缘E的弧线的圆弧凸起方向相对，由于第一信号线111的上表面中与第二信号线121交叠处的部分的宽度较宽，因此可以降低发生断线的几率。
在此基础上，为了进一步增加光刻胶在爬坡处与第二导电薄膜的接触面积，可选的，如图5所示，第二信号线121与第一信号线111在衬底10上的正投影重合区域的宽度W 1，大于第二信号线121与第一信号线111在衬底10上的正投影未重合的区域的宽度W 2。其中，第二信号线121的宽度是指：沿第一信号线111的延伸方向(如图3所示的X方向)，第二信号线121的一端与另一端之间的直线距离。
需要说明的是，可以通过控制掩模板的形状，使其具有与需要 形成的第二信号线121的形状相同的特定图案，从而通过掩模板曝光并执行后续光刻工艺后，形成的第二信号线121具有上述形状。
在此情况下，当在第二导电薄膜的表面形成光刻胶，在上述爬坡处，相对于第二信号线121中W 1＝W 2的情况，光刻胶与第二导电薄膜的上表面的接触面积进一步增大，这样一来，可以进一步降低爬坡处的光刻胶产生空隙的几率。
在此基础上，本发明对阵列基板的类型不做限定，对于阵列基板中交叉设置的信号线，在两条信号线交叠处，将位于底层的信号线设置为上述结构时，均可以实现降低形成信号线时，位于顶层的信号线发生断线的几率。示例的，当阵列基板为底栅型时，如图3所示，上述第一信号线111可以为栅线，或者为与栅线同层的公共线(Gate Common)，第二信号线121为数据线(SD Line)；当阵列基板为顶栅型时，上述第一信号线111为数据线，第二信号线121为栅线，或者与栅线同层的公共线。
此外，上述第一信号线111和第二信号线121通常采用铜/铜合金形成。由于铜的性质较为活泼，为了防止铜/铜合金被氧化，或扩散至有源层或其他膜层中，对其他膜层造成污染，可选的，在铜/铜合金层的上表面形成第二铜扩散阻挡层、下表面形成第一铜扩散阻挡层。其中，第一铜扩散阻挡层和第二铜扩散阻挡层可以防止铜扩散至其他膜层，例如有源层中，也可以防止在后续膜层的制作工艺中，铜/铜合金被氧化。
可选的，构成上述铜扩散阻挡层的材料包括钼铌合金、钼钛合金、氧化铟锡(ITO)、氧化铟锌(IZO)，钼铌合金、钼钛合金、氧化铟锡、氧化铟锌可以很好的防止铜/铜合金的扩散以及降低其被氧化的几率。
在此基础上，由于光刻胶在采用钼铌合金构成的铜扩散阻挡层表面的附着力较低，因此当形成第二信号线121时，增加了在爬坡处产生空隙，导致形成的第二信号线121发生断线的几率。
在此情况下，根据本发明实施例提供的制作方法，使得第一信号线111的上表面中与第二信号线121交叠的部分，沿第二信号线 121的延伸方向的至少一边缘E的长度大于边缘E两个顶点之间的直线距离J，以增加第二导电薄膜在爬坡处与第一导电层11的接触面积，从而有效的降低在第二导电薄膜表面形成光刻胶时，在爬坡处的光刻胶产生空隙的几率。
以下以阵列基板为底栅型，第一信号线111为栅线，第二信号线121为数据线为例，对阵列基板的制备过程进行说明，具体的可通过如下步骤实现。
S11、在衬底10上形成第一导电薄膜，即栅极薄膜；并在第一导电薄膜101上方形成一层光刻胶。
S12、利用掩模板对光刻胶进行曝光，显影后形成光刻胶保留部分和光刻胶去除部分。
其中，掩模板的不透光部分在沿第二信号线121的延伸方向、栅极薄膜与第二信号线121的预交叠处的至少一个侧边的长度大于该侧边的两个顶点之间的直线距离。
这样一来，可以使得形成的光刻胶保留部分中对应于第一信号线111的上表面中与第二信号线121交叠的部分，沿第二信号线121的延伸方向的至少一边缘的长度大于边缘两个顶点之间的直线距离。
S13、采用刻蚀工艺对栅极薄膜进行刻蚀，形成第一导电层11。
具体的，第一导电层11包括第一信号线111，且第一信号线111如图4所示，上表面中与第二信号线121交叠的部分，沿第二信号线121的延伸方向的至少一边缘E的长度大于边缘E两个顶点之间的直线距离J。
之后，将形成有第一导电层11的衬底10清洗后，还可以采用PECVD在形成有第一导电层11的衬底10上沉积栅绝缘层20。
S14、在形成有第一导电层11的衬底10上形成有源层21、第二导电层12。
具体的，通过以下步骤实现：
步骤S21、如图8(a)所示，在形成有第一导电层11的衬底10上依次形成氧化物半导体薄膜31、由第一铜扩散阻挡薄膜层32、铜/铜合金薄膜层33、第二铜扩散阻挡薄膜层34构成的第二导电薄膜， 并在第二导电薄膜上方形成光刻胶35。
步骤S22、如图8(b)所示，利用半色调掩模板40对光刻胶35进行曝光，显影后形成光刻胶完全保留部分351、光刻胶半保留部分352和光刻胶完全去除部分；光刻胶完全保留部分351与源极和漏极13对应，光刻胶半保留部分352与源极和漏极13之间的区域对应，光刻胶完全去除部分与其他区域对应。
其中，半色调掩模板包括不透明部分、半透明部分和透明部分。光刻胶35经过曝光后，光刻胶完全保留部分351对应半色调掩模板的不透明部分，光刻胶半保留部分352对应半色调掩模板的半透明部分，光刻胶完全去除部分对应半色调掩模板的透明部分。
当然，上述所指的光刻胶35为正性胶，当光刻胶35为负性胶时，光刻胶完全保留部分351则对应半色调掩模板的透明部分，光刻胶完全去除部分则对应半色调掩模板的不透明部分，光刻胶半保留部分352依然对应半色调掩模板的半透明部分。
步骤S23、如图8(c)所示，进行第一次铜刻蚀工艺，对与光刻胶完全去除部分对应的第一铜扩散阻挡薄膜层32、铜/铜合金薄膜层33、第二铜扩散阻挡薄膜层34进行刻蚀。
其中，在铜刻蚀工艺中，通常采用10％～20％的过蚀时间，以保持刻蚀干净。此外，在保证铜刻蚀干净的情况下，尽量缩短过蚀时间，以降低发生光刻胶剥离和信号线断线的几率。
步骤S24、如图8(d)所示，进行氧化物半导体薄膜31刻蚀，对与光刻胶完全去除部分对应的氧化物半导体薄膜31进行刻蚀，得到氧化物有源层21。
步骤S25、如图8(e)所示，采用灰化工艺去除光刻胶半保留部分352。
其中，在保证光刻胶半保留部分352灰化干净的前提下，尽量缩短灰化时间，以降低发生光刻胶剥离和信号线断线的几率。
可选的，对图8(e)所示的光刻胶35进行烘干。其中，烘干温度为110°～150°，时间为100s～200s。这样一来，可以增加光刻胶35在第二铜扩散阻挡层34表面的附着力。
步骤S26、如图8(f)所示，采用第二次铜刻蚀工艺，对露出的第一铜扩散阻挡薄膜层32、铜/铜合金薄膜层33、第二铜扩散阻挡薄膜层34进行刻蚀，形成上述第二导电层12。
其中，在铜刻蚀工艺中，通常采用10％～20％的过蚀时间，以保持刻蚀干净。此外，在保证铜刻蚀干净的情况下，尽量缩短过蚀时间，以降低发生光刻胶35剥离和信号线断线的几率。
最后，剥离上述光刻胶35。
此外，本领域技术人员清楚的知道，可以在形成有第二导电层12的衬底10上继续形成其他膜层，例如公共电极层、像素电极层。本发明对此不再赘述。
此外，可选的，在上述步骤S22之前，上述制备方法还包括：对第二导电薄膜进行粗糙化处理。需要说明的是，本发明对上述粗糙化处理的具体方式不做限定，只要在对第二导电薄膜进行处理后，可以使得第二导电薄膜的表面粗糙即可。
在此情况下，由于第二导电薄膜的表面粗糙，在第二导电薄膜上形成光刻胶35时，可以增加光刻胶35在第二导电薄膜的附着效果，从而降低了光刻胶35在上述爬坡处存在空隙的几率。
示例的，上述对第二导电薄膜进行粗糙化处理，可以包括：在第二导电薄膜表面涂覆光刻胶35，对光刻胶35进行前烘、曝光、显影、后烘工艺，并将光刻胶35去除。这样一来，可以通过高温的光刻胶35对第二导电薄膜的表面进行处理，使得第二导电薄膜的表面粗糙。
本实施中，通过一次构图工艺形成氧化物有源层21、第二导电层12，具有简化工艺步骤的效果，可以降低工艺成本。
当然，也可以先通过一次构图工艺形成氧化物有源层21，再通过一次构图工艺形成第二导电层12，此时采用普通调掩模板进行曝光工艺，通过控制掩模板的形状，可以控制形成的第二导电层12中第二信号线121的上表面的形状。
本发明实施例提供一种阵列基板，如图3所示，包括衬底10，在衬底10上依次设置的第一信号线111和第二信号线121，第一信 号线111和第二信号线121交叉绝缘设置。
其中，如图4所示，第一信号线111的上表面中与第二信号线121交叠的部分，沿第二信号线121的延伸方向的至少一边缘E的长度大于该边缘E两个顶点之间的直线距离J。
需要说明的是，第一信号线111和第二信号线121依次设置在衬底10上，因此第二信号线121位于第一信号线111的上方，因此在第二信号线121与第一信号线111交叠处，第二信号线121存在爬坡现象。
基于此，本发明提供的上述阵列基板，包括交叉绝缘设置的第一信号线111和第二信号线121，其中，第一信号线111的上表面中与第二信号线121交叠的部分，沿第二信号线121的延伸方向的至少一边缘E的长度大于边缘E两个顶点之间的直线距离J。在形成有第一信号线111的衬底10上通过构图工艺形成第二信号线121时，在第一信号线111的厚度不变的情况下，相对于边缘E长度等于边缘E的两个顶点之间的直线距离，在通过构图工艺形成第二导电层12时，第二导电薄膜在爬坡处与第一导电层11的接触面积会增加，从而使得在第二导电薄膜表面形成光刻胶35时，光刻胶35在爬坡处与第二导电薄膜的接触面积增加，降低了爬坡处的光刻胶35产生空隙的几率，进而可以降低在执行刻蚀工艺时，刻蚀液从上述空隙处侵入第二导电薄膜中，造成形成的第二信号线121发生断线的几率。
在此基础上，本发明对对上述边缘E的形状不做限定，只要满足边缘E的长度大于边缘E的两个顶点之间的直线距离J。示例的，上述边缘E可以如图4所示，上述边缘E可以为弧线，或者为折线。
在此基础上，为了增加通过构图工艺形成第二信号线121时，光刻胶35在爬坡处与第二导电薄膜的接触面积，可选的，第一信号线111的上表面中与第二信号线121交叠的部分，沿第二信号线121的延伸方向的两个边缘E均为弧线。此时可以如图5所示，两个边缘E的弧线的圆弧凸起方向相同，当然两个边缘E的弧线的圆弧凸起方向也可以不同。
进一步的，为了降低由于第一信号线111的上表面中与第二信 号线121交叠处的部分的宽度较窄，导致第一信号线111断线的几率，优选的，第一信号线111的上表面与第二信号线121交叠的部分，沿第二信号线121的延伸方向的两个边缘E的弧线的圆弧凸起方向相同或相背。
在此基础上，为了进一步增加光刻胶35在爬坡处与第二导电薄膜的接触面积，可选的，如图5所示，第二信号线121与第一信号线111在衬底10上的正投影重合区域的宽度W 1，大于第二信号线121与第一信号线111在衬底10上的正投影未重合的区域的宽度W 2。其中，第二信号线121的宽度是指：沿第一信号线111的延伸方向(如图3所示的X方向)，第二信号线121的一端与另一端之间的直线距离。
在此情况下，当在第二导电薄膜的表面形成光刻胶35，在上述爬坡处，相对于第二信号线121中W 1＝W 2的情况，光刻胶35与第二导电薄膜的上表面的接触面积进一步增大，这样一来，可以进一步降低爬坡处的光刻胶35产生空隙的几率。
此外，上述第一信号线111和第二信号线121通常采用铜/铜合金形成。由于铜的性质较为活泼，为了防止铜/铜合金被氧化，或扩散至有源层或其他膜层中，对其他膜层造成污染，可选的，第一信号线111和第二信号线121由依次设置的第一铜扩散阻挡层、铜/铜合金层、第二铜扩散阻挡层构成。
这样一来，第一铜扩散阻挡层和第二铜扩散阻挡层可以防止铜扩散至其他膜层，例如有源层中，也可以防止在后续膜层的制作工艺中，铜/铜合金被氧化。
可选的，构成上述铜扩散阻挡层的材料包括钼铌合金、钼钛合金、氧化铟锡、氧化铟锌，钼铌合金、钼钛合金、氧化铟锡、氧化铟锌可以很好的防止铜/铜合金的扩散以及降低其被氧化的几率。
此外，本发明对阵列基板的类型不做限定，例如，可以为底栅型阵列基板或者顶栅型阵列基板。在阵列基板中，形成有交叉设置的多条信号线，当阵列基板为底栅型时，示例的，如图3所示，上述第一信号线111可以为栅线，或者为与栅线同层的公共线，第二信号线 121为数据线；当阵列基板为顶栅型时，上述第一信号线111为数据线，第二信号线121为栅线，或者与栅线同层的公共线。
本发明实施例提供一种显示装置，包括如上所述的任一种阵列基板，上述显示装置具有与前述实施例提供的阵列基板相同的结构和有益效果，由于前述实施例已经对该阵列基板的结构和有益效果进行了详细的描述，此处不再赘述。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种阵列基板的制备方法，其特征在于，包括：在衬底上形成第一导电薄膜，对所述第一导电薄膜构图形成由导电图案构成的第一导电层，所述第一导电层包括第一信号线；
    在所述第一导电层上形成第二导电薄膜，对所述第二导电薄膜构图形成由导电图案构成的第二导电层，所述第二导电层包括第二信号线；所述第一信号线和所述第二信号线交叉绝缘设置；
    其中，所述第一信号线的上表面中与所述第二信号线交叠的部分，沿所述第二信号线的延伸方向的至少一边缘的长度大于所述边缘两个顶点之间的直线距离。
  2. 根据权利要求1所述的制备方法，其特征在于，所述第二信号线与所述第一信号线在所述衬底上的正投影重合区域的宽度，大于所述第二信号线与所述第一信号线在所述衬底上的正投影未重合的区域的宽度。
  3. 根据权利要求1所述的制备方法，其特征在于，所述制备方法还包括：对所述第二导电薄膜进行粗糙化处理。
  4. 根据权利要求3所述的制备方法，其特征在于，所述对所述第二导电薄膜进行粗糙化处理，包括：
    在所述第二导电薄膜表面涂覆光刻胶，对所述光刻胶进行前烘、曝光、显影、后烘工艺，并将所述光刻胶去除。
  5. 一种阵列基板，包括衬底，在衬底上依次设置的第一信号线和第二信号线，所述第一信号线和所述第二信号线交叉绝缘设置；其特征在于，所述第一信号线的上表面中与所述第二信号线交叠的部分，沿所述第二信号线的延伸方向的至少一边缘的长度大于所述边缘两个顶点之间的直线距离。
  6. 根据权利要求5所述的阵列基板，其特征在于，所述第一信号线的上表面中与所述第二信号线交叠的部分，沿所述第二信号线的延伸方向的两个边缘均为弧线。
  7. 根据权利要求5所述的阵列基板，其特征在于，所述第二信号线与所述第一信号线在所述衬底上的正投影重合区域的宽度，大于 所述第二信号线与所述第一信号线在所述衬底上的正投影未重合的区域的宽度。
  8. 根据权利要求5-7任一项所述的阵列基板，其特征在于，所述第一信号线为栅线和/或公共线，所述第二信号线为数据线；
    或者，所述第一信号线为数据线，所述第二信号线为栅线和/或公共线。
  9. 根据权利要求5所述的阵列基板，其特征在于，所述信号线由依次设置的第一铜扩散阻挡层、铜/铜合金层、第二铜扩散阻挡层构成。
  10. 一种显示装置，其特征在于，包括如权利要求5-9任一项所述的阵列基板。
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US11469258B2 (en) 2017-05-31 2022-10-11 Beijing Boe Technology Development Co., Ltd. Display panel and display device
CN109473449A (zh) * 2018-11-07 2019-03-15 惠科股份有限公司 跨线结构及其制作方法、显示面板
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CN112768478B (zh) * 2021-01-19 2023-04-07 Tcl华星光电技术有限公司 一种显示面板以及显示面板的制作方法
CN114980477A (zh) * 2021-02-18 2022-08-30 合肥鑫晟光电科技有限公司 背板、背光源、照明装置及显示装置
CN115472627A (zh) * 2021-05-24 2022-12-13 京东方科技集团股份有限公司 一种显示面板和显示装置
CN117597779A (zh) * 2022-04-26 2024-02-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
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