WO2014153872A1 - 移位寄存器单元、移位寄存器、显示面板以及显示器 - Google Patents

移位寄存器单元、移位寄存器、显示面板以及显示器 Download PDF

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Publication number
WO2014153872A1
WO2014153872A1 PCT/CN2013/077594 CN2013077594W WO2014153872A1 WO 2014153872 A1 WO2014153872 A1 WO 2014153872A1 CN 2013077594 W CN2013077594 W CN 2013077594W WO 2014153872 A1 WO2014153872 A1 WO 2014153872A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
drain
terminal
gate
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Ceased
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PCT/CN2013/077594
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English (en)
French (fr)
Inventor
杨明
陈希
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/356,807 priority Critical patent/US9564244B2/en
Publication of WO2014153872A1 publication Critical patent/WO2014153872A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • Shift register unit shift register, display panel, and display
  • the present invention relates to display driving technology, and more particularly to a shift register unit, a shift register, a display panel, and a display. Background technique
  • the Gate Drive on Array (GOA) technology is a technology for integrating a liquid crystal display gate driver circuit (Array Driver IC) on an array (Array) substrate.
  • Array Driver IC liquid crystal display gate driver circuit
  • COF Chip On Film
  • COG Chip on Glass
  • the GOA technology has the following advantages: (1) The pole drive circuit is integrated on the array substrate, which can effectively reduce the production cost; (2) eliminating the bonding yield process, which can improve the product yield and productivity; (3) eliminating the gate drive circuit bonding
  • the (gate IC bonding) region has a symmetrical structure of the display panel, and can realize a narrow frame of the display panel.
  • GOA technology has many advantages, but GOA technology also has problems such as insufficient gate high-level driving range Vgh Margin, high-temperature horizontal line H-line and Abnormal Display.
  • the main cause of these problems is in the charging phase.
  • the PU (Pull Up) node voltage is not high, and the PD (Pull Down) node voltage is not high during the noise cancellation phase. Summary of the invention
  • the main object of the present invention is to provide a shift register unit, a shift register, a display panel, and a display, which can quickly raise the level of the PU node during the charging phase, and can also ensure the PD node in the noise elimination phase.
  • the noise of the PU node and the signal output terminal OUTPUT is effectively eliminated, and the picture quality is improved.
  • An embodiment of the present invention provides a shift register unit, including: a buffer module, a reset module, a first pull-down module of a signal generating module, and a second pull-down module, wherein the buffer module is connected to a signal input end, and the reset module is connected and reset.
  • the first pull-down module is connected and reset a terminal, a power terminal, and a signal output terminal, and configured to pull the signal output terminal to a level of the power terminal under the control of the reset signal of the reset terminal;
  • the number generating module is connected to the clock end, the signal output end and the output end of the buffer module, and is configured to output the clock signal of the clock end to the signal output end under the control of a signal outputted by the output end of the buffer module
  • the second pull-down module is connected to the pull-down node, the output end of the buffer module, the power terminal, and the signal output terminal, and is configured to use the signal output terminal and the signal under the control of the signal of the pull-down node The output of the buffer module is pulled down to the level of the power terminal; wherein the shift register unit further includes a holding module, the holding module is connected to the output end of
  • the buffer module includes a first thin film transistor, a gate and a drain of the first thin film transistor are connected to a signal input end
  • the reset module includes a second thin film transistor, and the second thin film transistor a gate is connected to the reset end, a source of the second thin film transistor is connected to the power supply end, a drain of the second thin film transistor is connected to a source of the first thin film transistor
  • the signal generating module includes a third thin film transistor And a capacitor connected to the third thin film transistor, one end of the capacitor is connected to the gate of the third thin film transistor, and the other end of the capacitor is respectively connected to the source and the signal output end of the third thin film transistor;
  • the pull-down module includes a fourth thin film transistor, a gate of the fourth thin film transistor is connected to the reset end, a source of the fourth thin film transistor is connected to the power supply end, and a drain and a third film of the fourth thin film transistor a source of the transistor is connected;
  • the second pull-down module includes a tenth thin
  • a gate of the first thin film transistor is connected to a signal input end, and a source of the first thin film transistor is respectively connected to a drain of the second thin film transistor and a gate of the third thin film transistor, a drain of the first thin film transistor is connected to the signal input end; a gate of the second thin film transistor is respectively connected to a reset end and a gate of the fourth thin film transistor, and a source of the second thin film transistor is respectively connected to the fourth thin film a source of the transistor is connected to the power supply terminal, a drain of the second thin film transistor is connected to a gate of the third thin film transistor; a source of the third thin film transistor is respectively connected to a drain and a signal output end of the fourth thin film transistor Connecting, the drain of the third thin film transistor is connected to the clock end; the gate of the fourth thin film transistor is connected to the reset end, and the drain of the fourth thin film transistor is connected to the signal output end.
  • the shift register unit further includes a holding module, the holding module includes a sixth thin film transistor, and a gate of the sixth thin film transistor is connected to a source of the first thin film transistor, the first A source of the six thin film transistor is connected to the power supply terminal, and a drain of the sixth thin film transistor is connected to the pull-down node.
  • the shift register unit further includes a hold module, and the hold module includes a fifth thin film transistor and a sixth thin film transistor.
  • a gate of the fifth thin film transistor is respectively connected to a source of the first thin film transistor, a drain of the second thin film transistor, and a gate of the third thin film transistor; a source of the fifth thin film transistor Connected to a source of the second thin film transistor, a source of the fourth thin film transistor, and a power supply terminal; a drain of the fifth thin film transistor is connected to the clock terminal; and a gate of the sixth thin film transistor and a fifth thin film transistor a gate connection, a source of the sixth thin film transistor is respectively connected to a source of the fifth thin film transistor, a source of the second thin film transistor, a source of the fourth thin film transistor, and a power supply terminal; the sixth thin film transistor The drain is connected to the clock terminal.
  • the shift register unit further includes a seventh thin film transistor, a gate of the seventh thin film transistor is respectively connected to a gate and a signal input end of the first thin film transistor; and a source of the seventh thin film transistor The poles are respectively connected to a source of the second thin film transistor, a source of the fifth thin film transistor, a source of the sixth thin film transistor, a source of the fourth thin film transistor, and a power supply terminal; and a drain and a portion of the seventh thin film transistor The drain connection of the six thin film transistors.
  • the sixth thin film transistor employs a thin film transistor of a double gate structure.
  • the holding module further includes an eighth thin film transistor and a ninth thin film transistor; wherein
  • the drain of the fifth thin film transistor is connected to the clock terminal: the drain of the fifth thin film transistor is respectively connected to the source of the eighth thin film transistor and the gate of the ninth thin film transistor, and the eighth thin film transistor is a gate and a drain are connected to the clock terminal, and a drain of the ninth thin film transistor is connected to the clock terminal;
  • the drain of the sixth thin film transistor is connected to the clock terminal: the drain of the sixth thin film transistor is connected to the source of the ninth thin film transistor, and the drain of the ninth thin film transistor is respectively connected to the eighth thin film
  • the gate of the transistor is connected to the clock terminal.
  • the shift register unit further includes a twelfth thin film transistor, wherein a gate of the fifth thin film transistor passes through the twelfth thin film transistor and a source of the first thin film transistor, The drain of the second thin film transistor, the drain of the eleventh thin film transistor, and the third thin film crystal The gate connection of the body tube.
  • a gate of the fifth thin film transistor is connected to a source of the twelfth thin film transistor, and a gate of the twelfth thin film transistor is respectively connected to a source of the first thin film transistor, a drain of the second thin film transistor, and a tenth A drain of a thin film transistor and a gate of the third thin film transistor are connected; a drain of the twelfth thin film transistor is connected to a gate and a drain of the eighth thin film transistor and a drain of the ninth thin film transistor.
  • the present invention also provides a shift register comprising at least one of the shift register units of any one of the above; wherein, when the shift register unit is plural, the plurality of shift register units are cascaded.
  • the present invention further provides a display panel, wherein the display panel includes the shift register described above, and the shift register serves as a gate driver of the display panel.
  • the invention further provides a display, wherein the display comprises the display panel described above.
  • the shift register unit, the shift register, the display panel and the display provided by the invention have the following advantages and features:
  • the gate of the fifth thin film transistor is connected to the PU node, and the gate of the sixth thin film transistor is connected to the PU node through the gate of the fifth thin film transistor; or the gate of the fifth thin film transistor is passed through the twelfth
  • the thin film transistor is connected to the PU node, the gate of the sixth thin film transistor is connected to the PU node through the gate of the fifth thin film transistor, and the twelfth thin film transistor is connected; when the PU node is at a high level, the shift register unit having the above circuit structure Both can effectively eliminate the noise of the PU node and OUTPUT.
  • the position of the seventh thin film transistor can rapidly lower the voltage of the PD node, thereby facilitating the charging of the PU node and the voltage holding of the PU node.
  • the sixth thin film transistor of the invention adopts a double gate structure thin film transistor, which can effectively reduce the current between the source and the drain, so as to ensure that the PD node is at a higher potential, thereby effectively eliminating the noise of the PU node and the OUTPUT.
  • FIG. 1 is a circuit diagram 1 of a shift register unit of Embodiment 1;
  • Embodiment 2 is a timing chart of the operation of Embodiment 1;
  • FIG. 3 is a circuit diagram 2 of the shift register unit of Embodiment 1;
  • a shift register unit includes: a buffer module, a reset module, a signal generating module, a first pull-down module, and a second pull-down module, wherein the buffer module is connected to a signal input end, and the reset module is connected and reset.
  • the first pull-down module is connected and reset a terminal, a power terminal, and a signal output terminal, and configured to pull the signal output terminal to a level of the power terminal under the control of the reset signal of the reset terminal;
  • the signal generating module is connected to the clock terminal, the signal output terminal, and the An output end of the buffer module, and configured to output a clock signal of the clock end to the signal output end under control of a signal outputted by an output end of the buffer module;
  • the second pull-down module is connected to the pull-down node, An output of the buffer module, a power terminal, and the signal output, and for signals at the pull-down node Depressing a level of the signal output end and an output end of the buffer module to the power supply end,
  • the shift register unit further includes a holding module, wherein the holding module is connected to an output end of the buffer module The pull-
  • the buffer module includes a first thin film transistor, a gate and a drain of the first thin film transistor are connected to a signal input end
  • the reset module includes a second thin film transistor, and a gate of the second thin film transistor a reset terminal is connected, a source of the second thin film transistor is connected to the power supply end, a drain of the second thin film transistor is connected to a source of the first thin film transistor
  • the signal generating module includes a third thin film transistor and a capacitor connected to the three thin film transistors, one end of the capacitor is connected to a gate of the third thin film transistor, and the other end of the capacitor is respectively connected to a source and a signal output end of the third thin film transistor;
  • the first pull-down module The fourth thin film transistor is connected, the gate of the fourth thin film transistor is connected to the reset end, the source of the fourth thin film transistor is connected to the power supply terminal, and the drain of the fourth thin film transistor and the source of the third thin film transistor a second pull-down module comprising a tenth thin film transistor
  • a gate of the first thin film transistor is connected to a signal input end, and a source of the first thin film transistor is respectively connected to a drain of the second thin film transistor and a gate of the third thin film transistor, The drain of the first thin film transistor is connected to the signal input terminal.
  • the gates of the second thin film transistors are respectively connected to the reset terminals and the gates of the fourth thin film transistors, and the sources of the second thin film transistors are respectively connected to the source and the power supply end of the fourth thin film transistor, the second The drain of the thin film transistor is connected to the gate of the third thin film transistor.
  • the source of the third thin film transistor is respectively connected to the drain and the signal output end of the fourth thin film transistor; the drain of the third thin film transistor is connected to the clock end;
  • the gate of the fourth thin film transistor is connected to the reset terminal, and the drain of the fourth thin film transistor is connected to the signal output end.
  • the shift register unit further includes a holding module, the holding module includes a sixth thin film transistor, and a gate of the sixth thin film transistor is connected to a source of the first thin film transistor, the first A source of the six thin film transistor is connected to the power supply terminal, and a drain of the sixth thin film transistor is connected to the pull-down node.
  • the retention module includes a fifth thin film transistor and a sixth thin film transistor.
  • a gate of the fifth thin film transistor is respectively connected to a source of the first thin film transistor, a drain of the second thin film transistor, and a gate of the third thin film transistor;
  • a source of the fifth thin film transistor and a second thin film respectively a source of the transistor, a source of the fourth thin film transistor, and a power supply terminal;
  • a drain of the fifth thin film transistor is connected to the clock terminal;
  • a gate of the sixth thin film transistor is connected to a gate of the fifth thin film transistor, a source of the sixth thin film transistor is respectively connected to a source of the fifth thin film transistor, a source of the second thin film transistor, a source of the fourth thin film transistor, and a power supply terminal;
  • the shift register unit further includes a seventh thin film transistor, a gate of the seventh thin film transistor is respectively connected to a gate and a signal input end of the first thin film transistor; a source of the seventh thin film transistor a pole is respectively connected to a source of the second thin film transistor, a source of the fifth thin film transistor, a source of the sixth thin film transistor, a source of the fourth thin film transistor, and a power supply terminal; and a drain and a portion of the seventh thin film transistor The drain connection of the six thin film transistors.
  • the sixth thin film transistor may be a thin film transistor having a double gate structure.
  • the retention module further includes an eighth thin film transistor and a ninth thin film transistor.
  • the drain of the fifth thin film transistor is connected to the clock terminal: the drain of the fifth thin film transistor is respectively connected to the source of the eighth thin film transistor and the gate of the ninth thin film transistor, a gate and a drain of the eighth thin film transistor are connected to the clock terminal, the ninth thin film transistor
  • the drain of the sixth thin film transistor is connected to the clock terminal: the drain of the sixth thin film transistor is connected to the source of the ninth thin film transistor, and the drain of the ninth thin film transistor is The pole is connected to the clock terminal.
  • the shift register unit further includes a twelfth thin film transistor, and a gate of the fifth thin film transistor passes through the twelfth thin film transistor and a source and a second thin film of the first thin film transistor.
  • the drain of the transistor, the drain of the eleventh thin film transistor, and the gate of the third thin film transistor are connected.
  • the gate of the fifth thin film transistor is connected to the source of the twelfth thin film transistor, and the gate of the twelfth thin film transistor is respectively connected to the source of the first thin film transistor and the second thin film transistor.
  • the shift register unit includes: a first thin film transistor M1 to an eleventh thin film transistor Mil; a signal input terminal INPUT, a signal output terminal OUTPUT, and a clock terminal. CLK, reset terminal RESET, power supply terminal VSS, and a capacitor C1; wherein
  • the gates of the first thin film transistors M1 are respectively connected to the signal input terminals INPUT and the gates of the seventh thin film transistors M7, and the sources of the first thin film transistors M1 and the gates of the third thin film transistors M3 and the fifth respectively.
  • the gate of the second thin film transistor M2 is connected to the gate of the fourth thin film transistor M4, and the source of the second thin film transistor M2 is respectively connected to the source of the eleventh thin film transistor Mil and the source of the seventh thin film transistor M7.
  • the source of the third thin film transistor M3 is respectively connected to the drain of the fourth thin film transistor M4 and the drain of the tenth thin film transistor M10, and the drain of the third thin film transistor M3 and the gate and drain of the eighth thin film transistor M8, respectively. a drain connection of the ninth thin film transistor;
  • the drain of the fifth thin film transistor M5 and the gate of the ninth thin film transistor M9 are respectively thin
  • the source of the membrane transistor M8 is connected;
  • the drain of the sixth thin film transistor M6 is respectively connected to the gate of the tenth thin film transistor M10, the source of the ninth thin film transistor M9, the drain of the seventh thin film transistor M7, and the gate of the eleventh thin film transistor Mil;
  • One end of the capacitor C1 is connected to the gate of the third thin film transistor M3, and the other end of the capacitor C1 is respectively connected to the source of the third thin film transistor M3 and the signal output terminal OUTPUT;
  • the source of the third thin film transistor M3, the drain of the fourth thin film transistor M4, and the drain of the tenth thin film transistor M10 are all connected to the signal output terminal OUTPUT;
  • the drain of the third thin film transistor M3, the drain and the gate of the eighth thin film transistor M8, and the drain of the ninth thin film transistor M9 are all connected to the clock terminal CLK;
  • a source of the second thin film transistor M2 a source of the eleventh thin film transistor Mil, a source of the seventh thin film transistor M7, a source of the fifth thin film transistor M5, a source of the sixth thin film transistor M6, and a fourth
  • the source of the thin film transistor M4 and the source of the tenth thin film transistor M10 are both connected to the power supply terminal VSS;
  • the gate of the second thin film transistor M2 and the gate of the fourth thin film transistor M4 are both connected to the reset terminal RESET.
  • the structure of the sixth thin film transistor may be a double gate structure as shown by M6 in FIG. 1, or a single gate structure as shown by M6 in FIG. 3; when the sixth transistor is a transistor having a double gate structure. Since the double-gate transistor can effectively reduce the current between the source and the drain, the PD node can be kept at a higher potential, thereby effectively eliminating the noise of the PU node and the signal output terminal OUTPUT.
  • Embodiment 2 is an operation timing chart of Embodiment 1. According to the operation timing chart shown in FIG. 2, the working principle of the shift register unit provided in Embodiment 1 can be divided into the following five stages:
  • the first stage When INPUT is high, Ml is turned on, then the PU node is high, and the PU node is charged; RESET is at the level, M2 and M4 are cut off, and since the M2 and M4 are cut off, the PU node can be charged.
  • the second stage INPUT becomes low level, Ml is cut off, RESET is still low level, M2 and M4 are still off, because the charge of C1 remains, the PU node is still high, M3 is on, because of M3 Pass, CLK is high, so OUTPUT output is high, the PU node voltage is further increased due to the bootstrap action of C1; M6 and M5 are turned on because the PU node is kept high; and the source of M6 is The source of M5 is connected to VSS respectively. Therefore, the PD node and the PD_CN node continue to be in a low state, so M10 and Mil continue to be turned off.
  • the third stage INPUT is still low, RESET becomes high, then M2 and M4 are turned on. Since the source of M2 is connected to VSS, the PU node is pulled down to low level at this time; M4 Pass, since the source of M4 is connected to VSS, OUTPUT outputs low level; since PU node is low level, M6 and M5 are turned off, and since CLK is ⁇ level, M8 and M9 are turned off, therefore, PD node and PD_CN The node continues to be in a low state, so M10 and Mil continue to remain off.
  • the fourth stage INPUT is still low, PU node is low, M3 is off, OUTPUT continues to output low level; since PU node is low, M6 and M5 continue to be off; CLK is high Ping, M8 is on, then the PD_CN node is high, M9 is on, PD node is high; since PD node is high, Mil and M10 are on, and since the source of M10 and Mil is connected to VSS Therefore, Mil can eliminate PU node noise, and M10 can eliminate OUTPUT noise.
  • the gate and source of M6 are at the same time low level.
  • the double gate structure can effectively reduce the current between the source and the drain, so Ensure that the PD node is at a higher potential, which can effectively eliminate the noise of the PU node and OUTPUT.
  • the fifth stage INPUT is still low, RESET is still low, PU node is still low, M3 is cut off, OUTPUT continues to output low level; PU node is low, M6 and M5 are cut off, PD_CN node Keep high, M9 turns on; since M9 turns on and CKL is low, the PD node goes low.
  • the duty cycle of the PD node is slightly lower than 50%, which is advantageous for Extending the service life of M11 and M10;
  • the duty ratio is a ratio of the time of the PD node being high level to the total time during a continuous working time.
  • the shift register unit repeats the states of the fourth stage and the fifth stage until the state of the first stage, the second stage, and the third stage as shown in Fig. 2 occurs again, and the one-frame picture refresh is completed.
  • the shift register unit includes: a first thin film transistor M1 to a twelfth thin film transistor M12; a signal input terminal INPUT, a signal output terminal OUTPUT, and a clock terminal.
  • CLK reset terminal RESET, power supply terminal VSS, and a capacitor C1;
  • a gate of the first thin film transistor M1 is connected to a signal input terminal INPUT and a gate of a seventh thin film transistor M7, and a source of the first thin film transistor M1 is respectively a drain of the second thin film transistor and an eleventh thin film.
  • a drain of the transistor, a gate of the twelfth thin film transistor, a gate of the third thin film transistor, a drain of the first thin film transistor M1 is connected to the signal input terminal INPUT; a gate of the second thin film transistor M2 Connected to the gate of the fourth thin film transistor M4, the source of the second thin film transistor M2 and the source of the eleventh thin film transistor Mil, the source of the seventh thin film transistor M7, the source of the fifth thin film transistor M5, and the a source of the sixth thin film transistor M6, a source of the fourth thin film transistor M4, and a source of the tenth thin film transistor M10;
  • the source of the third thin film transistor M3 is respectively connected to the drain of the fourth thin film transistor M4 and the drain of the tenth thin film transistor M10, and the drain of the third thin film transistor M3 and the gate and drain of the eighth thin film transistor M8, respectively. a drain of the ninth thin film transistor and a drain of the twelfth thin film transistor;
  • the gates of the fifth thin film transistor M5 are respectively connected to the source of the twelfth thin film transistor M12 and the gate of the sixth thin film transistor M6, and the drains of the fifth thin film transistor M5 and the gate of the ninth thin film transistor M9, respectively. a source connection of the eighth thin film transistor M8;
  • the drain of the sixth thin film transistor M6 is respectively connected to the gate of the tenth thin film transistor M10, the source of the ninth thin film transistor M9, the drain of the seventh thin film transistor M7, and the gate of the eleventh thin film transistor Mil;
  • One end of the capacitor C1 is connected to the gate of the third thin film transistor M3, and the other end of the capacitor C1 is respectively connected to the source of the third thin film transistor M3 and the signal output terminal OUTPUT;
  • the source of the third thin film transistor M3, the drain of the fourth thin film transistor M4, and the drain of the tenth thin film transistor M10 are all connected to the signal output terminal OUTPUT; a drain of the third thin film transistor M3, a drain and a gate of the eighth thin film transistor M8, a drain of the ninth thin film transistor M9, and a drain of the twelfth thin film transistor M12 are all connected to the clock CLK;
  • a source of the second thin film transistor M2 a source of the eleventh thin film transistor Mil, a source of the seventh thin film transistor M7, a source of the fifth thin film transistor M5, a source of the sixth thin film transistor M6, and a fourth
  • the source of the thin film transistor M4 and the source of the tenth thin film transistor M10 are both connected to the power supply terminal VSS;
  • the gate of the second thin film transistor M2 and the gate of the fourth thin film transistor M4 are both connected to the reset terminal RESET.
  • the sixth thin film transistor may have a double gate structure as shown by M6 in Fig. 4, or may have a single gate structure.
  • VSS is the power supply terminal, and the power supply terminal VSS is directly in a low voltage state; and in this embodiment, the switching end of the thin film transistor is defined as a gate, the direction pointed by the arrow is defined as the source, and the other end is defined as Drain. Further, the thin film transistors in the embodiments of the present invention are all N-type transistors.
  • the gate of the fifth thin film transistor M5 is connected to the PU node, and the gate of the sixth thin film transistor M6 is connected to the PU node through the gate of the fifth thin film transistor M5 (such as the shift register provided in Embodiment 1).
  • the gate of the fifth thin film transistor M5 is connected to the PU node through the twelfth thin film transistor M12, and the gate of the sixth thin film transistor M6 is passed through the gate of the fifth thin film transistor M5, the twelfth thin film.
  • the transistor M12 is connected to the PU node (as shown in the shift register unit provided in Embodiment 2); when the PU node is at a high level, the shift register unit having the above-described circuit structure can effectively cancel the noise of the PU node and the OUTPUT.
  • a shift register comprising at least one of the shift register units of any one of the above; wherein, when the shift register unit is plural, the plurality of shift registers Unit cascade.
  • a display panel wherein the display panel comprises the shift register described above, and the shift register is used as a gate driver of the display panel.
  • the display comprises the display panel described above.

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  • Computer Hardware Design (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Abstract

一种移位寄存器单元、移位寄存器、显示面板以及显示器。所述移位寄存器单元包括保持模块，该保持模块使得当上拉节点 PU为高电平时保持 PU 节点的高电平。采用本发明能在充电阶段使 PU节点的电平迅速拉升，也能在噪声消除阶段保证 PD节点处于更高电位，有效消除 PU节点和 OUTPUT 的噪声，提高画面品质。

Description

移位寄存器单元、 移位寄存器、 显示面板以及显示器 技术领域
本发明涉及显示器驱动技术， 尤其涉及一种移位寄存器单元、 移位寄存 器、 显示面板以及显示器。 背景技术
阵列基板行驱动（Gate Drive on Array, GOA )技术是一种将液晶显示器 栅极驱动电路 ( Gate Driver IC )集成在阵列 （Array )基板上的技术。 相比传 统的覆晶薄膜（ Chip On Flex, or, Chip On Film, COF )技术和芯片被直接绑定 在玻璃上（Chip on Glass, COG )技术， GOA技术有以下优点： （ 1 )将栅极 驱动电路集成在阵列基板上， 能有效降低生产成本； （2 )省去绑定（bonding ) 良率工艺， 能使产品良率和产能得到提升； ( 3 )省去栅极驱动电路绑定（ gate IC bonding )区域， 使显示面板（ panel )具有对称结构， 能实现显示面板的窄 边框化。
GOA技术存在诸多优点， 但 GOA技术也存在栅极高电平驱动范围 Vgh Margin不足、 高温横线不良 H-line及异常显示 （ Abnormal Display )等问题； 而造成这些问题的主要原因是充电阶段中 PU ( Pull Up )节点电压拉升不高、 以及消除噪声阶段中 PD ( Pull Down )节点电压不高。 发明内容
有鉴于此， 本发明的主要目的在于提供一种移位寄存器单元、 移位寄存 器、 显示面板以及显示器， 能在充电阶段使 PU节点的电平迅速拉升， 也能 在噪声消除阶段保证 PD节点处于更高电位，有效消除 PU节点和信号输出端 OUTPUT的噪声， 提高画面品质。
本发明实施例提供了一种移位寄存器单元， 包括： 緩沖模块、 复位模块、 信号生成模块第一下拉模块和第二下拉模块，所述緩沖模块连接信号输入端， 所述复位模块连接复位端、 电源端和所述緩沖模块的输出端， 并且用于在所 述复位端的复位信号的控制下将所述緩沖模块的输出端复位至电源端的电 平； 所述第一下拉模块连接复位端、 电源端和信号输出端， 并且用于在所述 复位端的复位信号的控制下将所述信号输出端下拉至电源端的电平； 所述信 号生成模块连接时钟端、 信号输出端和所述緩沖模块的输出端， 并且用于在 所述緩沖模块的输出端输出的信号的控制下将所述时钟端的时钟信号输出至 所述信号输出端； 所述第二下拉模块连接下拉节点、 所述緩沖模块的输出端、 电源端和所述信号输出端， 并且用于在所述下拉节点的信号的控制下将所述 信号输出端和所述緩沖模块的输出端下拉至所述电源端的电平；其特征在于， 所述移位寄存器单元还包括保持模块， 所述保持模块连接所述緩沖模块的输 出端、 所述下拉节点和所述电源端， 并且用于在所述緩沖模块的输出端为高 电平时将所述下拉节点下拉到所述电源端的电平。
在一个示例中， 所述緩沖模块包括第一薄膜晶体管， 所述第一薄膜晶体 管的栅极和漏极与信号输入端连接； 所述复位模块包括第二薄膜晶体管， 所 述第二薄膜晶体管的栅极与复位端连接， 所述第二薄膜晶体管的源极与电源 端连接， 所述第二薄膜晶体管的漏极与第一薄膜晶体管的源极连接； 所述信 号生成模块包括第三薄膜晶体管以及与第三薄膜晶体管连接的电容， 所述电 容的一端与所述第三薄膜晶体管的栅极连接， 电容的另一端分别与第三薄膜 晶体管的源极和信号输出端连接； 所述第一下拉模块包括第四薄膜晶体管， 所述第四薄膜晶体管的栅极与复位端连接， 所述第四薄膜晶体管的源极与电 源端连接， 所述第四薄膜晶体管的漏极与第三薄膜晶体管的源极连接； 所述 第二下拉模块包括第十薄膜晶体管和第十一薄膜晶体管； 所述第十薄膜晶体 管的栅极和所述第十一薄膜晶体管的栅极与所述下拉节点连接， 所述第十薄 膜晶体管的源极和所述第十一薄膜晶体管的源极与电源端连接， 所述第十薄 膜晶体管的漏极与第四薄膜晶体管的漏极连接， 所述第十一薄膜晶体管的漏 极与第二薄膜晶体管的漏极连接。
在一个示例中， 所述第一薄膜晶体管的栅极与信号输入端连接， 所述第 一薄膜晶体管的源极分别与第二薄膜晶体管的漏极和第三薄膜晶体管的栅极 连接， 所述第一薄膜晶体管的漏极与信号输入端连接； 所述第二薄膜晶体管 的栅极分别与复位端和第四薄膜晶体管的栅极连接， 所述第二薄膜晶体管的 源极分别与第四薄膜晶体管的源极和电源端连接， 所述第二薄膜晶体管的漏 极与第三薄膜晶体管的栅极连接； 所述第三薄膜晶体管的源极分别与第四薄 膜晶体管的漏极和信号输出端连接， 所述第三薄膜晶体管的漏极与时钟端连 接； 所述第四薄膜晶体管的栅极与复位端连接， 所述第四薄膜晶体管的漏极 与信号输出端连接。 在一个示例中， 所述移位寄存器单元还包括保持模块， 所述保持模块包 括第六薄膜晶体管， 所述第六薄膜晶体管的栅极与所述第一薄膜晶体管的源 极连接， 所述第六薄膜晶体管的源极与所述电源端连接， 所述第六薄膜晶体 管的漏极与所述下拉节点连接。
在一个示例中， 所述移位寄存器单元还包括保持模块， 所述保持模块包 括第五薄膜晶体管和第六薄膜晶体管。
在一个示例中， 所述第五薄膜晶体管的栅极分别与第一薄膜晶体管的源 极、 第二薄膜晶体管的漏极、 第三薄膜晶体管的栅极连接； 所述第五薄膜晶 体管的源极分别与第二薄膜晶体管的源极、 第四薄膜晶体管的源极、 电源端 连接； 所述第五薄膜晶体管的漏极与时钟端连接； 所述第六薄膜晶体管的栅 极与第五薄膜晶体管的栅极连接， 所述第六薄膜晶体管的源极分别与第五薄 膜晶体管的源极、 第二薄膜晶体管的源极、 第四薄膜晶体管的源极、 电源端 连接； 所述第六薄膜晶体管的漏极与时钟端连接。
在一个示例中， 所述移位寄存器单元还包括第七薄膜晶体管， 所述第七 薄膜晶体管的栅极分别与第一薄膜晶体管的栅极、 信号输入端连接； 所述第 七薄膜晶体管的源极分别与第二薄膜晶体管的源极、第五薄膜晶体管的源极、 第六薄膜晶体管的源极、 第四薄膜晶体管的源极、 电源端连接； 所述第七薄 膜晶体管的漏极与第六薄膜晶体管的漏极连接。
在一个示例中， 所述第六薄膜晶体管采用双栅结构的薄膜晶体管。
在一个示例中，所述保持模块还包括第八薄膜晶体管和第九薄膜晶体管； 其中，
所述第五薄膜晶体管的漏极与时钟端连接为： 所述第五薄膜晶体管的漏 极分别与第八薄膜晶体管的源极、 第九薄膜晶体管的栅极连接， 所述第八薄 膜晶体管的栅极和漏极与时钟端连接， 所述第九薄膜晶体管的漏极与时钟端 连接；
所述第六薄膜晶体管的漏极与时钟端连接为： 所述第六薄膜晶体管的漏 极与第九薄膜晶体管的源极连接， 所述第九薄膜晶体管的漏极分别与所述第 八薄膜晶体管的栅极和时钟端连接。
在一个示例中， 所述移位寄存器单元还包括第十二薄膜晶体管， 其中， 所述第五薄膜晶体管的栅极通过所述第十二薄膜晶体管与所述第一薄膜晶体 管的源极、 第二薄膜晶体管的漏极、 第十一薄膜晶体管的漏极、 第三薄膜晶 体管的栅极连接。
所述第五薄膜晶体管的栅极与第十二薄膜晶体管的源极连接， 所述第十 二薄膜晶体管的栅极分别与第一薄膜晶体管的源极、第二薄膜晶体管的漏极、 第十一薄膜晶体管的漏极、 第三薄膜晶体管的栅极连接； 所述第十二薄膜晶 体管的漏极与第八薄膜晶体管的栅极和漏极、 第九薄膜晶体管的漏极连接。
本发明还提供了一种移位寄存器， 包括至少一个以上任一所述的移位寄 存器单元； 其中， 当所述移位寄存器单元为多个时， 所述多个移位寄存器单 元级联。
本发明又提供了一种显示面板， 其中， 所述显示面板包括以上所述的移 位寄存器， 所述移位寄存器作为所述显示面板的栅极驱动器。
本发明又提供了一种显示器， 其中， 所述显示器包括以上所述的显示面 板。
本发明所提供的移位寄存器单元、 移位寄存器、 显示面板以及显示器， 具有以下的优点和特点：
本发明将第五薄膜晶体管的栅极与 PU节点连接， 且第六薄膜晶体管的 栅极通过第五薄膜晶体管的栅极与 PU节点连接； 或者， 将第五薄膜晶体管 的栅极通过第十二薄膜晶体管与 PU节点连接， 第六薄膜晶体管的栅极通过 第五薄膜晶体管的栅极、 第十二薄膜晶体管与 PU节点连接； 当 PU节点处于 高电平时， 具有上述电路结构的移位寄存器单元均能有效消除 PU 节点和 OUTPUT的噪声。
此外， 本发明移位寄存器单元的电路中， 第七薄膜晶体管所在的位置能 将 PD节点的电压迅速拉低， 因此有利于 PU节点充电、 PU节点的电压保持。
本发明第六薄膜晶体管采用双栅结构的薄膜晶体管， 能有效减小源极和 漏极间的电流， 以保证 PD节点处于更高电位， 进而能有效消除 PU节点和 OUTPUT的噪声。 附图说明
图 1为实施例 1移位寄存器单元的电路图一；
图 2为实施例 1的工作时序图；
图 3为实施例 1移位寄存器单元的电路图二；
图 4为实施例 2移位寄存器单元的电路图。 具体实施方式
下面将结合具体实施例及附图对本发明的实施方式进行详细描述。
根据本发明实施例的一种移位寄存器单元包括： 緩沖模块、 复位模块、 信号生成模块、 第一下拉模块和第二下拉模块， 所述緩沖模块连接信号输入 端， 所述复位模块连接复位端、 电源端和所述緩沖模块的输出端， 并且用于 在所述复位端的复位信号的控制下将所述緩沖模块的输出端复位至电源端的 电平； 所述第一下拉模块连接复位端、 电源端和信号输出端， 并且用于在所 述复位端的复位信号的控制下将所述信号输出端下拉至电源端的电平； 所述 信号生成模块连接时钟端、 信号输出端和所述緩沖模块的输出端， 并且用于 在所述緩沖模块的输出端输出的信号的控制下将所述时钟端的时钟信号输出 至所述信号输出端； 所述第二下拉模块连接下拉节点、 所述緩沖模块的输出 端、 电源端和所述信号输出端， 并且用于在所述下拉节点的信号的控制下将 所述信号输出端和所述緩沖模块的输出端下拉至所述电源端的电平， 所述移 位寄存器单元还包括保持模块， 所述保持模块连接所述緩沖模块的输出端、 所述下拉节点和所述电源端， 并且用于在所述緩沖模块的输出端为高电平时 将所述下拉节点下拉到所述电源端的电平。
其中， 所述緩沖模块包括第一薄膜晶体管， 所述第一薄膜晶体管的栅极 和漏极与信号输入端连接； 所述复位模块包括第二薄膜晶体管， 所述第二薄 膜晶体管的栅极与复位端连接， 所述第二薄膜晶体管的源极与电源端连接， 所述第二薄膜晶体管的漏极与第一薄膜晶体管的源极连接； 所述信号生成模 块包括第三薄膜晶体管以及与第三薄膜晶体管连接的电容， 所述电容的一端 与所述第三薄膜晶体管的栅极连接， 电容的另一端分别与第三薄膜晶体管的 源极和信号输出端连接； 所述第一下拉模块包括第四薄膜晶体管， 所述第四 薄膜晶体管的栅极与复位端连接，所述第四薄膜晶体管的源极与电源端连接， 所述第四薄膜晶体管的漏极与第三薄膜晶体管的源极连接； 所述第二下拉模 块包括第十薄膜晶体管和第十一薄膜晶体管； 所述第十薄膜晶体管的栅极和 所述第十一薄膜晶体管的栅极与所述下拉节点连接， 所述第十薄膜晶体管的 源极和所述第十一薄膜晶体管的源极与电源端连接， 所述第十薄膜晶体管的 漏极与第四薄膜晶体管的漏极连接， 所述第十一薄膜晶体管的漏极与第二薄 膜晶体管的漏极连接。 在一个示例中， 所述第一薄膜晶体管的栅极与信号输入端连接， 所述第 一薄膜晶体管的源极分别与第二薄膜晶体管的漏极和第三薄膜晶体管的栅极 连接， 所述第一薄膜晶体管的漏极与信号输入端连接。
所述第二薄膜晶体管的栅极分别与复位端和第四薄膜晶体管的栅极连 接，所述第二薄膜晶体管的源极分别与第四薄膜晶体管的源极和电源端连接， 所述第二薄膜晶体管的漏极与第三薄膜晶体管的栅极连接。
所述第三薄膜晶体管的源极分别与第四薄膜晶体管的漏极和信号输出端 连接； 所述第三薄膜晶体管的漏极与时钟端连接；
所述第四薄膜晶体管的栅极与复位端连接， 所述第四薄膜晶体管的漏极 与信号输出端连接。
在一个示例中， 所述移位寄存器单元还包括保持模块， 所述保持模块包 括第六薄膜晶体管， 所述第六薄膜晶体管的栅极与所述第一薄膜晶体管的源 极连接， 所述第六薄膜晶体管的源极与所述电源端连接， 所述第六薄膜晶体 管的漏极与所述下拉节点连接。
在另一个示例中，所述保持模块包括第五薄膜晶体管和第六薄膜晶体管。 所述第五薄膜晶体管的栅极分别与第一薄膜晶体管的源极、 第二薄膜晶 体管的漏极和第三薄膜晶体管的栅极连接； 所述第五薄膜晶体管的源极分别 与第二薄膜晶体管的源极、 第四薄膜晶体管的源极和电源端连接； 所述第五 薄膜晶体管的漏极与时钟端连接； 所述第六薄膜晶体管的栅极与第五薄膜晶 体管的栅极连接，所述第六薄膜晶体管的源极分别与第五薄膜晶体管的源极、 第二薄膜晶体管的源极、 第四薄膜晶体管的源极和电源端连接； 所述第六薄 膜晶体管的漏极与时钟端连接。 在一个示例中， 所述移位寄存器单元还包括 第七薄膜晶体管， 所述第七薄膜晶体管的栅极分别与第一薄膜晶体管的栅极 和信号输入端连接； 所述第七薄膜晶体管的源极分别与第二薄膜晶体管的源 极、 第五薄膜晶体管的源极、 第六薄膜晶体管的源极、 第四薄膜晶体管的源 极和电源端连接；所述第七薄膜晶体管的漏极与第六薄膜晶体管的漏极连接。
所述第六薄膜晶体管可以采用双栅结构的薄膜晶体管。
在一个示例中，所述保持模块还包括第八薄膜晶体管和第九薄膜晶体管。 在此情况下， 所述第五薄膜晶体管的漏极与时钟端连接为： 所述第五薄 膜晶体管的漏极分别与第八薄膜晶体管的源极和第九薄膜晶体管的栅极连 接， 所述第八薄膜晶体管的栅极和漏极与时钟端连接， 所述第九薄膜晶体管 的漏极与时钟端连接； 所述第六薄膜晶体管的漏极与时钟端连接为： 所述第 六薄膜晶体管的漏极与第九薄膜晶体管的源极连接， 所述第九薄膜晶体管的 漏极与时钟端连接。 在一个示例中， 所述移位寄存器单元还包括第十二薄膜晶体管， 所述第 五薄膜晶体管的栅极通过所述第十二薄膜晶体管与所述第一薄膜晶体管的源 极、 第二薄膜晶体管的漏极、 第十一薄膜晶体管的漏极和第三薄膜晶体管的 栅极连接。
在此情况下， 所述第五薄膜晶体管的栅极与第十二薄膜晶体管的源极连 接， 所述第十二薄膜晶体管的栅极分别与第一薄膜晶体管的源极、 第二薄膜 晶体管的漏极、 第十一薄膜晶体管的漏极和第三薄膜晶体管的栅极连接； 所 述第十二薄膜晶体管的漏极与第八薄膜晶体管的漏极、 第九薄膜晶体管的漏 极和时钟端连接。
实施例 1
图 1为实施例 1移位寄存器单元的电路图， 如图 1所示， 移位寄存器单 元包括： 第一薄膜晶体管 Ml至第十一薄膜晶体管 Mil ;信号输入端 INPUT、 信号输出端 OUTPUT, 时钟端 CLK、 复位端 RESET、 电源端 VSS以及一个 电容 C1; 其中，
所述第一薄膜晶体管 Ml的栅极分别与信号输入端 INPUT、 第七薄膜晶 体管 M7的栅极连接， 所述第一薄膜晶体管 Ml的源极分别与第三薄膜晶体 管 M3的栅极、 第五薄膜晶体管 M5的栅极、 第六薄膜晶体管 M6的栅极、 第 二薄膜晶体管 M2的漏极、 第十一薄膜晶体管 Mil的漏极连接， 所述第一薄 膜晶体管 Ml的漏极与信号输入端 INPUT连接；
所述第二薄膜晶体管 M2的栅极与第四薄膜晶体管 M4的栅极连接， 第 二薄膜晶体管 M2的源极分别与第十一薄膜晶体管 Mil的源极、 第七薄膜晶 体管 M7的源极、 第五薄膜晶体管 M5的源极、 第六薄膜晶体管 M6的源极、 第四薄膜晶体管 M4的源极、 第十薄膜晶体管 M10的源极连接；
第三薄膜晶体管 M3的源极分别与第四薄膜晶体管 M4的漏极、 第十薄 膜晶体管 M10的漏极连接， 第三薄膜晶体管 M3的漏极分别与第八薄膜晶体 管 M8的栅极和漏极、 第九薄膜晶体管的漏极连接；
第五薄膜晶体管 M5的漏极分别与第九薄膜晶体管 M9的栅极、 第八薄 膜晶体管 M8的源极连接；
第六薄膜晶体管 M6的漏极分别与第十薄膜晶体管 M10的栅极、第九薄 膜晶体管 M9的源极、 第七薄膜晶体管 M7的漏极、 第十一薄膜晶体管 Mil 的栅极连接；
所述电容 C1的一端与所述第三薄膜晶体管 M3的栅极连接， 电容 C1的 另一端分别与第三薄膜晶体管 M3的源极、 信号输出端 OUTPUT连接；
所述第三薄膜晶体管 M3的源极、 第四薄膜晶体管 M4的漏极、 第十薄 膜晶体管 M10的漏极均与信号输出端 OUTPUT连接；
所述第三薄膜晶体管 M3的漏极、 第八薄膜晶体管 M8的漏极和栅极、 第九薄膜晶体管 M9的漏极均与时钟端 CLK连接；
所述第二薄膜晶体管 M2的源极、 第十一薄膜晶体管 Mil的源极、 第七 薄膜晶体管 M7的源极、 第五薄膜晶体管 M5的源极、 第六薄膜晶体管 M6 的源极、 第四薄膜晶体管 M4的源极、 第十薄膜晶体管 M10的源极均与电源 端 VSS连接；
所述第二薄膜晶体管 M2的栅极、 第四薄膜晶体管 M4的栅极均与复位 端 RESET连接。
这里， 所述第六薄膜晶体管采用的结构可以为图 1中 M6所示的双栅结 构， 也可以为如图 3中 M6所示的单栅结构； 当第六晶体管采用双栅结构的 晶体管时， 由于双栅结构的晶体管能有效减小源极和漏极间的电流， 因此能 保证 PD节点处于更高电位，进而能有效消除 PU节点和信号输出端 OUTPUT 的噪声。
图 2为实施例 1的工作时序图， 根据图 2所示的工作时序图， 实施例 1 所提供的移位寄存器单元的工作原理可以分为如下五个阶段描述：
第一阶段： INPUT为高电平时， Ml导通， 则 PU节点为高电平， 且 PU 节点充电； RESET为氏电平， M2和 M4截止， 由于 M2和 M4截止， 因此能 保证 PU节点充电完全； INPUT为高电平， M7导通， 由于 M7的源极与 VSS 连接， 因此 PD节点被迅速下拉至低电平， 因此 M10和 Mil截止； PU节点 为高电平， M5导通， 由于 M5的源极与 VSS连接， 因此 PD_CN节点为低电 平； PD节点和 PD_CN节点同时为低电平， 有利于 PU节点的电压保持； 此 时， 又由于 PU节点为高电平， M3导通， 由于 CLK为氏电平， 因此 OUTPUT 输出低电平。 此阶段， 利用第七薄膜晶体管 M7将 PD节点的电压迅速拉低， 因此有 利于 PU节点充电、 PU节点的电压保持。
第二阶段： INPUT变为低电平， Ml截止， RESET仍为低电平， M2和 M4仍截止， 由于 C1的电荷保持作用， PU节点仍为高电平， M3导通，； 由 于 M3导通， CLK为高电平， 因此 OUTPUT输出高电平， 由于 C1的自举作 用， 使得 PU节点电压进一步提升； 由于 PU节点保持高电平状态， M6和 M5导通； 又由于 M6的源极、 M5的源极分别与 VSS连接， 因此， PD节点 和 PD_CN节点继续保持低电平状态， 因此 M10和 Mil继续保持截止。
在此阶段中， 由于 M5的栅极与 PU节点连接， 而 M6的栅极通过 M5 的栅极与 PU节点连接， 且此阶段中， PU节点为高电压， 又由于 C1的自举 作用使 PU节点的电压高于 OUTPUT的电压， 因此， 有利用消除 PU节点和 信号输出端 OUTPUT噪声。
第三阶段： INPUT仍为低电平， RESET变为高电平，则 M2和 M4导通， 由于 M2的源极与 VSS连接，所述 PU节点在此时被下拉至低电平； M4导通， 由于 M4的源极与 VSS连接， 所以 OUTPUT输出低电平； 由于 PU节点为低 电平， M6和 M5截止， 又由于 CLK为氐电平， M8和 M9截止， 因此， PD 节点和 PD_CN节点继续保持低电平状态， 因此 M10和 Mil继续保持截止。
第四阶段： INPUT仍为低电平， PU节点为低电平， M3截止， OUTPUT 继续输出低电平；由于 PU节点为低电平，所以 M6和 M5继续保持截止状态； 由于 CLK为高电平， M8导通， 则 PD_CN节点为高电平， M9导通， PD节 点为高电平； 由于 PD节点为高电平， Mil和 M10导通， 并且由于 M10和 Mil的源极与 VSS连接，因此， Mil能消除 PU节点噪声， M10能消除 OUTPUT 噪声。
在此阶段中， M6的栅极和源极同时为低电平， 当 M6采用双栅结构的薄 膜晶体管时， 由于所述双栅结构可有效减小源极和漏极间的电流， 因此能保 证 PD节点处于更高电位， 进而能有效消除 PU节点和 OUTPUT的噪声。
第五阶段： INPUT仍为低电平， RESET仍为低电平， PU节点仍为低电 平， M3截止， OUTPUT继续输出低电平； PU节点为低电平， M6和 M5截 止， PD_CN节点保持高电平， M9导通； 由于 M9导通， 且 CKL为低电平， 因此 PD节点变为低电平。
根据本发明实施例 1 , PD节点占空比（duty cycle )略低于 50%, 有利于 延长 Mll、 M10的使用寿命； 这里， 所述占空比为在一段连续工作时间内 PD 节点为高电平的时间与总时间的比值。
此后， 移位寄存器单元重复第四阶段、 第五阶段的状态， 直至再次出现 如图 2所示第一阶段、 第二阶段、 第三阶段的状态， 则一帧画面刷新完成。
实施例 2
图 4为实施例 2移位寄存器单元的电路图， 如图 4所示， 移位寄存器单 元包括： 第一薄膜晶体管 Ml至第十二薄膜晶体管 M12;信号输入端 INPUT、 信号输出端 OUTPUT, 时钟端 CLK、 复位端 RESET、 电源端 VSS以及一个 电容 C1; 其中，
所述第一薄膜晶体管 Ml的栅极分别与信号输入端 INPUT、 第七薄膜晶 体管 M7的栅极连接， 所述第一薄膜晶体管 Ml的源极分别第二薄膜晶体管 的漏极、 第十一薄膜晶体管的漏极、 第十二薄膜晶体管的栅极、 第三薄膜晶 体管的栅极连接，所述第一薄膜晶体管 Ml的漏极与信号输入端 INPUT连接； 所述第二薄膜晶体管 M2的栅极与第四薄膜晶体管 M4的栅极连接， 第 二薄膜晶体管 M2的源极分别与第十一薄膜晶体管 Mil的源极、 第七薄膜晶 体管 M7的源极、 第五薄膜晶体管 M5的源极、 第六薄膜晶体管 M6的源极、 第四薄膜晶体管 M4的源极、 第十薄膜晶体管 M10的源极连接；
第三薄膜晶体管 M3的源极分别与第四薄膜晶体管 M4的漏极、 第十薄 膜晶体管 M10的漏极连接， 第三薄膜晶体管 M3的漏极分别与第八薄膜晶体 管 M8的栅极和漏极、 第九薄膜晶体管的漏极、 和第十二薄膜晶体管的漏极 连接；
所述第五薄膜晶体管 M5的栅极分别与第十二薄膜晶体管 M12的源极、 第六薄膜晶体管 M6的栅极连接， 第五薄膜晶体管 M5的漏极分别与第九薄 膜晶体管 M9的栅极、 第八薄膜晶体管 M8的源极连接；
第六薄膜晶体管 M6的漏极分别与第十薄膜晶体管 M10的栅极、第九薄 膜晶体管 M9的源极、 第七薄膜晶体管 M7的漏极、 第十一薄膜晶体管 Mil 的栅极连接；
所述电容 C1的一端与所述第三薄膜晶体管 M3的栅极连接， 电容 C1的 另一端分别与第三薄膜晶体管 M3的源极、 信号输出端 OUTPUT连接；
所述第三薄膜晶体管 M3的源极、 第四薄膜晶体管 M4的漏极、 第十薄 膜晶体管 M10的漏极均与信号输出端 OUTPUT连接； 所述第三薄膜晶体管 M3的漏极、 第八薄膜晶体管 M8的漏极和栅极、 第九薄膜晶体管 M9的漏极、 第十二薄膜晶体管 M12的漏极均与时钟 CLK 连接；
所述第二薄膜晶体管 M2的源极、 第十一薄膜晶体管 Mil的源极、 第七 薄膜晶体管 M7的源极、 第五薄膜晶体管 M5 的源极、 第六薄膜晶体管 M6 的源极、 第四薄膜晶体管 M4的源极、 第十薄膜晶体管 M10的源极均与电源 端 VSS连接；
所述第二薄膜晶体管 M2的栅极、 第四薄膜晶体管 M4的栅极均与复位 端 RESET连接。
这里， 所述第六薄膜晶体管可以为图 4中 M6所示的双栅结构， 也可以 为单栅结构。
值得注意的是， VSS为电源端， 该电源端 VSS—直为低电压状态； 且本 实施例将薄膜晶体管的开关端定义为栅极， 箭头所指向的方向定义为源极， 另一端定义为漏极。 另外， 本发明实施例中的薄膜晶体管均为 N型晶体管。
本发明实施例将第五薄膜晶体管 M5的栅极与 PU节点连接， 且第六薄 膜晶体管 M6的栅极通过第五薄膜晶体管 M5的栅极与 PU节点连接（如实施 例 1提供的移位寄存器单元所示 ); 或者， 将第五薄膜晶体管 M5的栅极通过 第十二薄膜晶体管 M12与 PU节点连接， 第六薄膜晶体管 M6的栅极通过第 五薄膜晶体管 M5的栅极、 第十二薄膜晶体管 M12与 PU节点连接 (如实施 例 2提供的移位寄存器单元所示）； 当 PU节点处于高电平时， 具有上述电路 结构的移位寄存器单元均能有效消除 PU节点和 OUTPUT的噪声。
根据本发明实施例， 还提供了一种移位寄存器， 包括至少一个以上任一 所述的移位寄存器单元； 其中， 当所述移位寄存器单元为多个时， 所述多个 移位寄存器单元级联。
根据本发明实施例， 还提供了一种显示面板， 其中， 所述显示面板包括 以上所述的移位寄存器， 所述移位寄存器作为所述显示面板的栅极驱动器。
根据本发明实施例， 还提供了一种显示器， 其中， 所述显示器包括以上 所述的显示面板。
以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保护 范围。

Claims

权 利 要 求 书
1、 一种移位寄存器单元， 包括： 緩沖模块、 复位模块、 信号生成模块、 第一下拉模块和第二下拉模块， 所述緩沖模块连接信号输入端， 所述复位模 块连接复位端、 电源端和所述緩沖模块的输出端， 并且用于在所述复位端的 复位信号的控制下将所述緩沖模块的输出端复位至电源端的电平； 所述第一 下拉模块连接复位端、 电源端和信号输出端， 并且用于在所述复位端的复位 信号的控制下将所述信号输出端下拉至电源端的电平； 所述信号生成模块连 接时钟端、 信号输出端和所述緩沖模块的输出端， 并且用于在所述緩沖模块 的输出端输出的信号的控制下将所述时钟端的时钟信号输出至所述信号输出 端； 所述第二下拉模块连接下拉节点、 所述緩沖模块的输出端、 电源端和所 述信号输出端， 并且用于在所述下拉节点的信号的控制下将所述信号输出端 和所述緩沖模块的输出端下拉至所述电源端的电平；
其特征在于， 所述移位寄存器单元还包括保持模块， 所述保持模块连接 所述緩沖模块的输出端、 所述下拉节点和所述电源端， 并且用于在所述緩沖 模块的输出端为高电平时将所述下拉节点下拉到所述电源端的电平。
2、 根据权利要求 1所述的移位寄存器单元， 其特征在于，
所述緩沖模块包括第一薄膜晶体管， 所述第一薄膜晶体管的栅极和漏极 与信号输入端连接；
所述复位模块包括第二薄膜晶体管， 所述第二薄膜晶体管的栅极与复位 端连接， 所述第二薄膜晶体管的源极与电源端连接， 所述第二薄膜晶体管的 漏极与第一薄膜晶体管的源极连接；
所述信号生成模块包括第三薄膜晶体管以及与第三薄膜晶体管连接的电 容， 所述电容的一端与所述第三薄膜晶体管的栅极连接， 电容的另一端分别 与第三薄膜晶体管的源极和信号输出端连接；
所述第一下拉模块包括第四薄膜晶体管， 所述第四薄膜晶体管的栅极与 复位端连接， 所述第四薄膜晶体管的源极与电源端连接， 所述第四薄膜晶体 管的漏极与第三薄膜晶体管的源极连接；
所述第二下拉模块包括第十薄膜晶体管和第十一薄膜晶体管； 所述第十 薄膜晶体管的栅极和所述第十一薄膜晶体管的栅极与所述下拉节点连接， 所 述第十薄膜晶体管的源极和所述第十一薄膜晶体管的源极与电源端连接， 所 述第十薄膜晶体管的漏极与第四薄膜晶体管的漏极连接， 所述第十一薄膜晶 体管的漏极与第二薄膜晶体管的漏极连接。
3、根据权利要求 2所述的移位寄存器单元， 其特征在于， 所述保持模块 包括第六薄膜晶体管， 所述第六薄膜晶体管的栅极与所述第一薄膜晶体管的 源极连接， 所述第六薄膜晶体管的源极与所述电源端连接， 所述第六薄膜晶 体管的漏极与所述下拉节点连接。
4、根据权利要求 2所述的移位寄存器单元， 其特征在于， 所述保持模块 包括第五薄膜晶体管和第六薄膜晶体管； 所述第五薄膜晶体管的栅极分别与 第一薄膜晶体管的源极、 第二薄膜晶体管的漏极、 第三薄膜晶体管的栅极连 接； 所述第五薄膜晶体管的源极分别与第二薄膜晶体管的源极、 第四薄膜晶 体管的源极、 电源端连接； 所述第五薄膜晶体管的漏极与第三薄膜晶体管的 漏极和时钟端连接； 所述第六薄膜晶体管的栅极与第五薄膜晶体管的栅极连 接， 所述第六薄膜晶体管的源极与电源端连接； 所述第六薄膜晶体管的漏极 与时钟端连接。
5、根据权利要求 4所述的移位寄存器单元， 其特征在于， 所述移位寄存 器单元还包括第七薄膜晶体管， 所述第七薄膜晶体管的栅极分别与第一薄膜 晶体管的栅极、 信号输入端连接； 所述第七薄膜晶体管的源极分别与第二薄 膜晶体管的源极、 第五薄膜晶体管的源极、 第六薄膜晶体管的源极、 第四薄 膜晶体管的源极、 电源端连接； 所述第七薄膜晶体管的漏极与第六薄膜晶体 管的漏极连接。
6、根据权利要求 1所述的移位寄存器单元， 其特征在于， 所述第六薄膜 晶体管采用双栅结构的薄膜晶体管。
7、根据权利要求 4所述的移位寄存器单元， 其特征在于， 所述保持模块 还包括第八薄膜晶体管和第九薄膜晶体管； 其中，
所述第五薄膜晶体管的漏极与时钟端连接为： 所述第五薄膜晶体管的漏 极分别与第八薄膜晶体管的源极、 第九薄膜晶体管的栅极连接， 所述第八薄 膜晶体管的栅极和漏极与时钟连端接， 所述第九薄膜晶体管的漏极与时钟端 连接；
所述第六薄膜晶体管的漏极与时钟连接为： 所述第六薄膜晶体管的漏极 与第九薄膜晶体管的源极连接， 所述第九薄膜晶体管的漏极与时钟端连接。
8、根据权利要求 4所述的移位寄存器单元， 其特征在于， 所述移位寄存 器单元还包括第十二薄膜晶体管，
所述第五薄膜晶体管的栅极与第十二薄膜晶体管的源极连接， 所述第十 二薄膜晶体管的栅极分别与第一薄膜晶体管的源极、第二薄膜晶体管的漏极、 第十一薄膜晶体管的漏极、 第三薄膜晶体管的栅极连接； 所述第十二薄膜晶 体管的漏极分别与第八薄膜晶体管的漏极、 第九薄膜晶体管的漏极和时钟端 连接。
9、 一种移位寄存器， 其特征在于， 所述移位寄存器包括至少一个如权利 要求 1至 8任一项所述的移位寄存器单元；
在所述移位寄存器单元为多个时， 所述多个移位寄存器单元级联。
10、 一种显示面板， 其特征在于， 所述显示面板包括权利要求 9所述的 移位寄存器， 所述移位寄存器作为所述显示面板的栅极驱动器。
PCT/CN2013/077594 2013-03-29 2013-06-20 移位寄存器单元、移位寄存器、显示面板以及显示器 Ceased WO2014153872A1 (zh)

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