WO2014146291A1 - 薄膜晶体管及其像素单元的制造方法 - Google Patents

薄膜晶体管及其像素单元的制造方法 Download PDF

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Publication number
WO2014146291A1
WO2014146291A1 PCT/CN2013/073054 CN2013073054W WO2014146291A1 WO 2014146291 A1 WO2014146291 A1 WO 2014146291A1 CN 2013073054 W CN2013073054 W CN 2013073054W WO 2014146291 A1 WO2014146291 A1 WO 2014146291A1
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gate
metal
layer
source
region
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French (fr)
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余晓军
魏鹏
刘自鸿
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to CN201380000479.2A priority Critical patent/CN104508807A/zh
Priority to US14/778,920 priority patent/US9679995B2/en
Priority to PCT/CN2013/073054 priority patent/WO2014146291A1/zh
Publication of WO2014146291A1 publication Critical patent/WO2014146291A1/zh
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/202—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials for lift-off processes
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Definitions

  • the present invention belongs to the field of electronic technologies, and in particular, to a method for manufacturing a thin film transistor and a pixel unit thereof.
  • TFT Thin film transistor
  • IGZO In-Ga-Zn-O
  • TFT Thin film transistor
  • IGZO In-Ga-Zn-O
  • TFT is a basic circuit component that can be widely used in various electronic systems, and has various advantages such as high electron mobility, low temperature manufacturing process, high stability, transparency, and the like.
  • the overlap of the gate and the source and drain increases, resulting in a large parasitic capacitance of the gate source, which makes the overall performance of the thin film transistor poor.
  • the existing thin film transistor manufacturing process has higher requirements for mask alignment, low yield and high cost.
  • the alignment precision of the mask is high, which also affects the yield and cost.
  • the embodiment of the present invention is implemented by the method for manufacturing a thin film transistor, comprising the following steps:
  • a gate metal layer as a mask, exposing and developing from the back of the substrate to self-align the channel and the gate of the thin film transistor;
  • the channel is a metal oxide layer that is aligned with the gate of the thin film transistor.
  • Another object of the embodiments of the present invention is to provide a method for fabricating a thin film transistor pixel unit, including the following steps:
  • a gate metal layer, a gate lead metal layer and a storage capacitor electrode metal layer as a mask, exposing and developing from the back of the substrate to self-align the channel and the gate of the thin film transistor;
  • the channel is a metal oxide layer that is aligned with the gate of the thin film transistor.
  • the gate metal layer is used as a mask, and the channel and the source and drain of the thin film transistor are positioned by one exposure from the back of the substrate.
  • the gate metal layer is used as a mask, and the back surface of the substrate is exposed and developed to self-align the channel and the gate of the thin film transistor; then the source and drain electrodes are self-aligned with the gate through a metal lift-off process.
  • a passivation layer is deposited, and a source drain contact via lead is formed; wherein the channel is a metal oxide layer aligned with the gate of the thin film transistor.
  • the channel and the gate are self-aligned, the source and drain electrodes are self-aligned and symmetrical, and the resulting thin film transistor has a small parasitic capacitance, and the manufactured circuit has a fast running speed and is shortly susceptible to short circuit and open circuit.
  • the channel and the gate are self-aligned, and the source-drain and gate self-aligned and symmetrical characteristics avoid the need for alignment precision in the production mask, thereby reducing the precision of the lithography apparatus. Need to reduce costs and increase yield.
  • the process is suitable for thin film transistor pixel cell fabrication, which requires only four masks that do not require critical alignment. Compared with other four mask processes using a grayscale mask, the yield can be improved and the cost can be reduced.
  • FIG. 1 is a flow chart showing an implementation of a method for fabricating a thin film transistor according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of forming a gate metal layer on a substrate according to a first embodiment of the present invention
  • FIG. 3 is a schematic structural view showing deposition of a gate insulating layer, a metal oxide layer, and an etch barrier layer on a substrate and a gate metal layer according to a first embodiment of the present invention
  • Figure 4 is a schematic view of the first embodiment of the present invention exposed from the back of the substrate;
  • Figure 5 is a schematic view showing the structure of the first embodiment of the present invention after exposure and development from the back of the substrate;
  • FIG. 6 is a schematic structural view of removing an exposed etch barrier layer according to a first embodiment of the present invention.
  • FIG. 7 is a schematic structural view of a photoresist in a gate region and a metal deposited on both sides thereof according to a first embodiment of the present invention
  • FIG. 8 is a schematic structural view showing a photoresist removed on a gate region and a metal thereon according to a first embodiment of the present invention
  • FIG. 9 is a schematic view showing a structure of a photoresist coated on a substrate side for covering a gate region and a source/drain region on the substrate side after exposure and development;
  • FIG. 10 is a schematic structural view showing etching of an exposed source/drain metal and a metal oxide layer aligned therewith according to a first embodiment of the present invention
  • FIG. 11 is a schematic structural view of a first embodiment of the present invention after removing a photoresist for covering a gate region and a source/drain region;
  • FIG. 12 is a schematic structural view showing deposition of a passivation layer on one side of a substrate according to a first embodiment of the present invention
  • FIG. 13 is a schematic structural view showing a source/drain contact via hole in a passivation layer in a first embodiment of the present invention
  • FIG. 14 is a schematic structural view showing deposition of a conductive material in a source/drain contact via according to a first embodiment of the present invention
  • FIG. 15 is a flowchart showing an implementation of a method for manufacturing a thin film transistor pixel unit according to a second embodiment of the present invention.
  • 16 is a schematic structural view showing formation of a gate metal layer, a gate wiring metal layer, and a storage capacitor electrode metal layer on a substrate according to a second embodiment of the present invention
  • FIG. 17 is a schematic structural view showing deposition of a gate insulating layer, a metal oxide layer, and an etch barrier layer on a substrate, a gate metal layer, a gate wiring metal layer, and a storage capacitor electrode metal layer according to a second embodiment of the present invention
  • FIG. 18 is a schematic view showing a photoresist coated on an etch barrier layer according to a second embodiment of the present invention.
  • Figure 19 is a schematic view showing the structure of the second embodiment of the present invention after exposure and development from the back of the substrate;
  • FIG. 20 is a schematic structural view of a second embodiment of the present invention for removing an exposed etch barrier layer
  • 21 is a schematic structural view of a second embodiment of the present invention after depositing metal on the photoresist and on both sides thereof;
  • Figure 22 is a schematic view showing the structure of a stripping photoresist and a metal thereon according to a second embodiment of the present invention.
  • FIG. 23 is a schematic view showing the structure of a photoresist coated with a gate region and a source/drain region after exposure and development according to a second embodiment of the present invention.
  • FIG. 24 is a schematic structural view of an etch-exposed etch stop layer according to a second embodiment of the present invention.
  • 25 is a schematic structural view showing a second embodiment of the present invention etching an exposed metal and a metal oxide layer aligned with the metal;
  • 26 is a schematic structural view of a second embodiment of the present invention after removing a photoresist for covering a gate region and a source/drain region;
  • Figure 27 is a schematic view showing the structure of depositing a passivation layer on one side of a substrate according to a second embodiment of the present invention.
  • FIG. 28 is a schematic view showing the structure of etching a source drain contact via and a gate contact via in a passivation layer according to a second embodiment of the present invention.
  • 39 is a schematic structural view showing deposition of a conductive material on a source/drain contact via, a gate contact via, and a passivation layer in a second embodiment of the present invention.
  • Figure 30 is a schematic view showing the structure of a portion of the conductive material removed through the fourth mask according to the second embodiment of the present invention.
  • the gate metal layer is used as a mask, and the channel and the source and drain of the thin film transistor are positioned by one exposure from the back of the substrate.
  • the gate metal layer is used as a mask, and the back surface of the substrate is exposed and developed to self-align the channel and the gate of the thin film transistor; then the source and drain electrodes are self-aligned with the gate through a metal lift-off process.
  • a passivation layer is deposited, and a source drain contact via lead is formed; wherein the channel is a metal oxide layer aligned with the gate of the thin film transistor.
  • the channel and the gate are self-aligned, the source and drain electrodes are self-aligned and symmetrical, and the resulting thin film transistor has a small parasitic capacitance, and the manufactured circuit has a fast running speed and is shortly susceptible to short circuit and open circuit.
  • the channel and the gate are self-aligned, and the source-drain and gate self-aligned and symmetrical characteristics avoid the need for alignment precision in the production mask, thereby reducing the precision of the lithography apparatus. Need to reduce costs and increase yield.
  • the process is suitable for thin film transistor pixel cell fabrication, which requires only four masks that do not require critical alignment. Compared with other four mask processes using a grayscale mask, the yield can be improved and the cost can be reduced.
  • FIG. 1 is a flowchart showing an implementation process of a method for manufacturing a thin film transistor according to an embodiment of the present invention, which is described in detail below.
  • step S101 the gate metal layer is used as a mask, and is exposed and developed from the back of the substrate to self-align the channel and the gate of the thin film transistor.
  • a gate metal layer 2 is deposited on the substrate 1, wherein the substrate 1 material may be glass, transparent plastic or the like. If the substrate 1 is large, the metal layer other than the gate region of the thin film transistor needs to be etched away. Here, the first mask can be used to etch away the metal layer outside the gate region of the thin film transistor. Subsequently, a gate insulating layer 3, a metal oxide layer 4, and an etch barrier layer 5 are sequentially deposited on the substrate 1 and the gate metal layer 2, as shown in FIG.
  • the gate insulating layer 3, the metal oxide layer 4 and the etch stop layer 5 are all transparent materials, and the gate metal layer is deposited by an opaque material for the subsequent process. The substrate 1 is exposed at the back.
  • a photoresist 61 is coated on the etch barrier layer 5, and the gate metal layer 2 is used as a mask, and is exposed and developed from the back of the substrate 1 to expose the gate region.
  • the etch barrier layer is shown in Figures 4 and 5. Since the gate metal layer 2 is opaque, the photoresist 62 located in the gate region is retained.
  • the etch stop layer outside the gate region is removed to expose the metal oxide layer aligned with the etch stop layer, and is formed to be self-aligned with the gate 2 (ie, the gate metal layer) of the thin film transistor.
  • the channel 7 of the bit is as shown in FIG.
  • the metal oxide layer aligned with the gate of the thin film transistor is directly used as the channel 7, and the process is simple.
  • the unexposed metal oxide layer ie, the channel
  • the etch barrier layer located in the gate region is aligned with the gate electrode 2 of the thin film transistor
  • the channel 7 and the gate 2 are accurately aligned (that is, the etch stop layer and the gate metal layer are precisely aligned in the gate region), and the edge spacing between the two is 0 ⁇ 1 um, and the self-alignment precision is extremely high.
  • step S102 a source drain that is self-aligned with the gate is formed via a metal lift-off process.
  • an embodiment of the present invention deposits a metal 8 on the side of the substrate 1 (ie, on the photoresist 62 of the gate region and on both sides thereof) on both sides of the photoresist 62 .
  • the metal 8 is a source-drain metal that is self-aligned with the gate 2.
  • the source drain metal is deposited by the side of the photoresist 62 located in the gate region, and the gate metal layer aligned with the photoresist 62 defines an etch barrier layer
  • the source The drain metal edge is precisely aligned with the edge of the etch stop layer (ie, the subsequently formed source drain and gate are self-aligned and symmetrical), the spacing between the two is less than 1 um, and the self-alignment precision is extremely high.
  • the overlapping area of the source drain metal and the gate can be accurately controlled at 1 ⁇ 2um, which is much higher than the accuracy of alignment by other means.
  • the gate metal layer 2 ie, the gate
  • the channel and the source and drain of the thin film transistor are positioned by one exposure from the back of the substrate 1, so that the channel 7 and the gate 2 are self-aligned, source and drain.
  • the pole and the gate 2 are self-aligned and symmetrical, and the thin film transistor thus produced has a small parasitic capacitance, and the circuit produced has a fast running speed and is short in short circuit and open circuit.
  • the self-aligned process in the embodiment of the present invention can minimize the overlap of the gate and the source and drain, and the channel size can be precisely controlled, which can significantly reduce the channel size and improve device performance.
  • the metal 8 deposited on the photoresist and the photoresist 62 in the gate region are stripped to expose an etch barrier layer in the channel region, which is a metal lift-off process, as shown in FIG.
  • the metal stripping process in the embodiment of the present invention refers to pre-retarding a photoresist (mainly by photoresist coating, exposure and development) before depositing metal; after depositing metal, The photoresist and the metal thereon are stripped.
  • a photoresist for covering the gate region and the source and drain regions is coated on one side of the substrate 1 and exposed and developed from the front surface with a second mask to expose part of the source and drain metal. A portion of the photoresist 63 is retained as shown in FIG. The size of the exposed source drain metal depends on the source and drain size to be formed.
  • the exposed source and drain metal and the metal oxide layer aligned with the source drain metal are removed to form the source and drain electrodes 9 of the thin film transistor, and then the gate region and the source and drain regions are removed.
  • Photoresist 63 Specifically, the exposed source and drain metal are etched away to form the source and drain electrodes 9 of the thin film transistor, and then the metal oxide layer aligned with the exposed source and drain metal is etched, as shown in FIG. Photoresist 63 covering the aforementioned gate region and source and drain regions is then removed, as shown in FIG. It should be noted that when the gate side is the source and the other side is the drain.
  • step S103 a passivation layer is deposited, and a source and drain contact via lead is formed.
  • a passivation layer 10 for protecting the gate 2, the source and drain electrodes 9 and the channel 7 formed by the foregoing steps is deposited on the substrate 1 side, and the passivation layer 10 is covered.
  • the channel region and source and drain electrodes 9 of the thin film transistor are used.
  • the embodiment of the present invention etches the passivation layer 10 located in the source and drain regions via a third mask to form a source/drain contact via 11 through the source and drain electrodes 9.
  • the cross section of the source/drain contact via 11 has an inverted trapezoid shape, so that the subsequent process fills the conductive material.
  • the embodiment of the present invention deposits a conductive material 12 in the source-drain contact via 11 that has been formed in the foregoing steps to form a source-drain contact via lead.
  • the conductive material 12 may be a transparent conductive material such as ITO or the like.
  • FIG. 15 is a flowchart showing an implementation process of a method for manufacturing a thin film transistor pixel unit according to an embodiment of the present invention, which is described in detail below.
  • step S201 the gate metal layer, the gate lead metal layer, and the storage capacitor electrode metal layer are used as masks, and are exposed and developed from the back of the substrate to self-align the channel and the gate of the thin film transistor.
  • the embodiment of the present invention first deposits a metal layer on the substrate 21, wherein the substrate 21 material may be glass, transparent plastic, or the like.
  • the metal layer is etched away using the first mask to form the gate metal layer 22, the gate wiring metal layer 23, and the storage capacitor electrode metal layer 24.
  • the gate metal layer 22 serves as a gate of the thin film transistor pixel unit
  • the storage capacitor electrode metal layer 24 serves as one of storage capacitors of the thin film transistor pixel unit.
  • a gate insulating layer 25, a metal oxide layer 26, and an etch barrier layer 27 are sequentially deposited on the substrate 21 side, and the gate insulating layer 25, the metal oxide layer 26, and the etch stop layer 27 are The lower gate metal layer 22, the gate wiring metal layer 23, and the storage capacitor electrode metal layer 24 are covered as shown in FIG.
  • the gate insulating layer 25, the metal oxide layer 26, and the etch stop layer 27 are all transparent materials, and the gate metal layer 22, the gate lead metal layer 23, and the storage capacitor electrode metal layer 24 are all The opaque material is deposited so that the subsequent process is exposed from the back of the substrate 21.
  • a photoresist 64 is coated on the etch barrier layer 27 as shown in FIG.
  • the gate metal layer 22, the gate lead metal layer 23 and the storage capacitor electrode metal layer 24 are used as a mask, exposed and developed from the back of the substrate 21 to expose the gate region, the gate lead region and the storage.
  • the etch stop layer outside the gate region, the gate lead region and the storage capacitor region is removed to expose the metal oxide layer aligned with the etch barrier layer and form a gate 22 with the thin film transistor (ie, the gate metal layer) is self-aligned channel 28, as shown in FIG.
  • the metal oxide layer aligned with the gate 22 of the thin film transistor is directly used as the channel 28, and the process is simple.
  • the etch stop layer located in the gate region is aligned with the gate 22 of the thin film transistor,
  • the channel 28 and the gate electrode 22 are accurately aligned (that is, the etch barrier layer located in the gate region is accurately aligned with the gate metal layer), and the edge spacing between the two is 0 ⁇ 1 um, and the self-alignment precision is extremely high.
  • step S202 a source drain that is self-aligned with the gate is formed via a metal lift-off process.
  • a metal 29 is deposited on both sides of the photoresist 65 and the regions of the gate region, the gate lead region, and the storage capacitor region, and is formed on both sides of the gate region. Source-drain metal that is self-aligned with the gate 22.
  • the source drain metal is deposited by the side of the photoresist 65 located in the gate region, and the etch barrier is defined by the gate metal layer aligned with the photoresist 65, the source drain
  • the edge of the electrode metal is precisely aligned with the edge of the etch barrier layer (that is, the subsequently formed source drain and gate are self-aligned and symmetrical), the spacing between the two is less than 1 um, and the self-alignment precision is extremely high.
  • the overlapping area of the source drain metal and the gate 22 can be accurately controlled at 1 ⁇ 2um, which is much higher than the accuracy of alignment by other means.
  • the gate metal layer 22 ie, the gate
  • the channel 28 and the source and drain of the thin film transistor are positioned from the back of the substrate 21 in one exposure, thereby self-aligning the channel 28 and the gate 22.
  • the drain and the gate 22 are self-aligned and symmetrical, and the resulting thin film transistor pixel unit has a small parasitic capacitance, and the circuit produced has a fast running speed and is less prone to short circuit and open circuit.
  • the self-aligned process in the embodiment of the present invention can minimize the overlap of the gate 22 and the source and drain, and the size of the channel 28 can be precisely controlled, which can significantly reduce the channel size and improve device performance.
  • the metal 29 deposited on the photoresist 65 and the photoresist 65 located in the gate region, the gate lead region and the storage capacitor region are stripped to expose the gate region and the gate lead region.
  • an etch stop layer of the storage capacitor region which is a metal stripping process, as shown in FIG.
  • the photoresist 65 and the metal 29 deposited thereon are simultaneously removed, and the removal efficiency is high.
  • a photoresist 66 for covering the gate region and the source/drain region is coated on the side of the substrate 21, and is exposed and developed from the front surface of the second mask to expose part of the source and drain metal. 23 is shown.
  • the size of the exposed source drain metal depends on the source and drain size to be formed.
  • the exposed source and drain metal, the metal oxide layer aligned with the source and drain metal, and the etch barrier layer, the metal oxide layer, and the deposition layer in the gate lead region and the storage capacitor region are removed.
  • an etch barrier layer located in the gate lead region and the storage capacitor region is first removed to expose a metal oxide layer located in the gate lead region and the storage capacitor region, as shown in FIG.
  • step S203 a passivation layer is deposited, and a source drain contact via lead, a gate contact via lead, and another capacitor of the storage capacitor are fabricated.
  • the embodiment of the present invention deposits a passivation layer 31 for covering the gate region, the source/drain region, the gate lead region, and the storage capacitor region on the side of the substrate 21.
  • the passivation layer 31 covers the source and drain electrodes 30 of the thin film transistor pixel unit, the etch barrier layer in the channel region, and the exposed gate insulating layer.
  • an embodiment of the present invention etches a passivation layer located in a source/drain region and a gate lead region via a third mask, thereby forming a source/drain contact via that is directly through the source and drain 30.
  • 32 and the gate contact via 33 The gate insulating layer is further etched in the gate contact via 33 to bring the conductive material deposited in the subsequent process into contact with the gate lead metal layer 23.
  • the cross-section of the source-drain contact via 32 and the gate contact via 33 has an inverted trapezoid shape so that the subsequent process fills the conductive material.
  • the embodiment of the present invention deposits a conductive material 34 on the source/drain contact via 32, the gate contact via 33, and the passivation layer 31 on the storage capacitor region which have been formed in the foregoing steps.
  • the conductive material 34 may be a transparent conductive material such as ITO or the like.
  • FIG. 30 in order to form a pixel electrode and a storage capacitor, another electrode 35, photolithography is performed here using a fourth mask. In this way, only four masks that do not require critical alignment are used in the fabrication of the thin film transistor pixel unit, thereby improving the yield and reducing the cost.

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Abstract

提供了一种薄膜晶体管及其像素单元的制造方法，制造薄膜晶体管时将栅极金属层作为掩膜，从基板背部一次曝光对薄膜晶体管的沟道和源漏极进行定位。如此使沟道与栅极自对位，源漏极与栅极自对准且对称，由此制成的薄膜晶体管寄生电容小，所制电路运行速度快，且不易发生短路、断路。该制造方法中沟道与栅极自对位，源漏极与栅极自对准且对称的特性避免了生产中掩膜板需要对位的精度，从而降低了对高精度光刻设备的需要，能降低成本，提高成品率。另外，本工艺适于薄膜晶体管像素单元制造，此制造过程仅需四个不需要关键对准的掩膜板。与其它采用了灰阶掩膜的四掩膜工艺相比，可以提高产率，降低成本。

Description

薄膜晶体管及其像素单元的制造方法 技术领域
本发明属于电子技术领域，尤其涉及一种薄膜晶体管及其像素单元的制造方法。
 背景技术
薄膜晶体管（TFT），如In-Ga-Zn-O (IGZO) TFT是一种可广泛用于各种电子系统的基本电路组成器件，具有多种优势，比如高电子迁移率、低温制造工艺、较高稳定性、透明等等。然而现有薄膜晶体管制造过程中因栅极与源漏极的重叠增加，导致栅源寄生电容大，使得薄膜晶体管整体性能差。另外，现有薄膜晶体管制造过程中掩膜板对准要求较高，产率低且成本高。而采用了灰阶掩膜的四掩膜TFT工艺中掩膜板对准精度要求高，同样了影响产率及成本。
 技术问题
本发明实施例的目的在于提供一种薄膜晶体管的制造方法，旨在解决现有方法所制薄膜晶体管性能较差的问题。
 技术解决方案
本发明实施例是这样实现的，一种薄膜晶体管的制造方法，包括以下步骤：
将栅极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位；
经由金属剥离工艺，形成与栅极自对准的源漏极；
沉积钝化层，并制作源漏极接触过孔引线；
其中，所述沟道为与薄膜晶体管的栅极对位的金属氧化物层。
本发明实施例的另一目的在于提供一种薄膜晶体管像素单元的制造方法，包括以下步骤：
将栅极金属层、栅极引线金属层和存储电容电极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位；
经由金属剥离工艺，形成与栅极自对准的源漏极；
沉积钝化层，并制作源漏极接触过孔引线、栅极接触过孔引线和存储电容另一个电极；
其中，所述沟道为与薄膜晶体管的栅极对位的金属氧化物层。
 有益效果
本发明实施例将栅极金属层作为掩模，从基板背部一次曝光对薄膜晶体管的沟道和源漏极进行定位。具体地，先以栅极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位；然后经由金属剥离工艺，形成与栅极自对准的源漏极；最后沉积钝化层，并制作源漏极接触过孔引线；其中，所述沟道为与薄膜晶体管的栅极对位的金属氧化物层。如此使沟道与栅极自对位，源漏极与栅极自对准且对称，由此制成的薄膜晶体管寄生电容小，所制电路运行速度快，且不易发生短路、断路。本发明实施例中沟道与栅极自对位，源漏极与栅极自对准且对称的特性避免了生产中掩膜板需要对位的精度，从而降低了对高精度光刻设备的需要，能降低成本，提高成品率。另外，本工艺适于薄膜晶体管像素单元制造，此制造过程仅需四个不需要关键对准的掩膜板。与其它采用了灰阶掩膜的四掩膜工艺相比，可以提高产率，降低成本。
 附图说明
图1是本发明第一实施例提供的薄膜晶体管的制造方法实现流程图；
图2是本发明第一实施例于基板上形成栅极金属层的结构示意图；
图3是本发明第一实施例于基板和栅极金属层上沉积栅极绝缘层、金属氧化物层和刻蚀阻挡层的结构示意图；
图4是本发明第一实施例从基板背部曝光的示意图；
图5是本发明第一实施例从基板背部曝光、显影后的结构示意图；
图6是本发明第一实施例移除暴露的刻蚀阻挡层的结构示意图；
图7是本发明第一实施例在位于栅极区的光刻胶及其两侧沉积金属后的结构示意图；
图8是本发明第一实施例移除位于栅极区的光刻胶及其上的金属的结构示意图；
图9是本发明第一实施例于基板一侧涂布用以覆盖栅极区及源漏极区的光刻胶，曝光、显影后的结构示意图；
图10是本发明第一实施例刻蚀暴露的源漏极金属及与之对位的金属氧化物层的结构示意图；
图11是本发明第一实施例移除用以覆盖栅极区及源漏极区的光刻胶后的结构示意图；
图12是本发明第一实施例于基板一侧沉积钝化层的结构示意图；
图13是本发明第一实施例于钝化层刻蚀源漏极接触过孔的结构示意图；
图14是本发明第一实施例于源漏极接触过孔内沉积导电材料的结构示意图；
图15是本发明第二实施例提供的薄膜晶体管像素单元的制造方法实现流程图；
图16是本发明第二实施例于基板上形成栅极金属层、栅极引线金属层和存储电容电极金属层的结构示意图；
图17是本发明第二实施例于基板、栅极金属层、栅极引线金属层和存储电容电极金属层上沉积栅极绝缘层、金属氧化物层和刻蚀阻挡层的结构示意图；
图18是本发明第二实施例在刻蚀阻挡层上涂布光刻胶的示意图；
图19是本发明第二实施例从基板背部曝光、显影后的结构示意图；
图20是本发明第二实施例移除暴露的刻蚀阻挡层的结构示意图；
图21是本发明第二实施例在光刻胶上及其两侧沉积金属后的结构示意图；
图22是本发明第二实施例剥离光刻胶及其上的金属的结构示意图；
图23是本发明第二实施例涂布用以覆盖栅极区及源漏极区的光刻胶，曝光、显影后的结构示意图；
图24是本发明第二实施例刻蚀暴露的刻蚀阻挡层的结构示意图；
图25是本发明第二实施例刻蚀暴露的金属及与该金属对位的金属氧化物层的结构示意图；
图26是本发明第二实施例移除用以覆盖栅极区及源漏极区的光刻胶后的结构示意图；
图27是本发明第二实施例于基板一侧沉积钝化层的结构示意图；
图28是本发明第二实施例于钝化层刻蚀源漏极接触过孔及栅极接触过孔的结构示意图；
图39是本发明第二实施例于源漏极接触过孔内、栅极接触过孔及钝化层上沉积导电材料的结构示意图；
图30是本发明第二实施例经由第四个掩膜板移除部分导电材料的结构示意图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明实施例将栅极金属层作为掩模，从基板背部一次曝光对薄膜晶体管的沟道和源漏极进行定位。具体地，先以栅极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位；然后经由金属剥离工艺，形成与栅极自对准的源漏极；最后沉积钝化层，并制作源漏极接触过孔引线；其中，所述沟道为与薄膜晶体管的栅极对位的金属氧化物层。如此使沟道与栅极自对位，源漏极与栅极自对准且对称，由此制成的薄膜晶体管寄生电容小，所制电路运行速度快，且不易发生短路、断路。本发明实施例中沟道与栅极自对位，源漏极与栅极自对准且对称的特性避免了生产中掩膜板需要对位的精度，从而降低了对高精度光刻设备的需要，能降低成本，提高成品率。另外，本工艺适于薄膜晶体管像素单元制造，此制造过程仅需四个不需要关键对准的掩膜板。与其它采用了灰阶掩膜的四掩膜工艺相比，可以提高产率，降低成本。
下面以金属氧化物薄膜晶体管为例对本发明的实现进行详细描述。
实施例一
图1示出了本发明实施例提供的薄膜晶体管的制造方法实现流程，详述如下。
在步骤S101中，将栅极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位。
如图2所示，本发明实施例先在基板1上沉积一栅极金属层2，其中所述基板1材料可以为玻璃、透明塑料等。若所述基板1较大，需刻蚀掉薄膜晶体管栅极区以外的金属层。此处可以采用第一掩膜板刻蚀掉薄膜晶体管栅极区以外的金属层。随后，在所述基板1和栅极金属层2上依序沉积栅极绝缘层3、金属氧化物层4和刻蚀阻挡层5，如图3所示。
应该说明的是，所述栅极绝缘层3、金属氧化物层4和刻蚀阻挡层5均为透明材料，而所述栅极金属层由不透光材料沉积而成，以便后道工序从基板1背部曝光。
接着，于所述刻蚀阻挡层5上涂布光刻胶61，在此将所述栅极金属层2作为掩膜，从所述基板1背部曝光、显影，以暴露栅极区以外的刻蚀阻挡层，如图4、5所示。因所述栅极金属层2不透光，从而保留位于所述栅极区的光刻胶62。
然后，移除所述栅极区以外的刻蚀阻挡层，以暴露与该刻蚀阻挡层对位的金属氧化物层，并形成与薄膜晶体管的栅极2（即栅极金属层）自对位的沟道7，如图6所示。此处直接将与薄膜晶体管的栅极对位的金属氧化物层作为沟道7，工艺简单。因未暴露的金属氧化物层（即沟道）与位于所述栅极区的刻蚀阻挡层对位，位于所述栅极区的刻蚀阻挡层与薄膜晶体管的栅极2对位，故沟道7与栅极2精确对位（亦即位于所述栅极区的蚀阻挡层与栅极金属层精确对位），两者边沿间距为0~1um，自对位精度极高。
在步骤S102中，经由金属剥离工艺，形成与栅极自对准的源漏极。
如图7所示，本发明实施例先在所述基板1一侧（即于所述栅极区的光刻胶62及其两侧上）沉积金属8，位于所述光刻胶62两侧的金属8为与所述栅极2自对准的源漏极金属。因该源漏极金属以位于所述栅极区的光刻胶62侧面为界沉积而成，且由与该光刻胶62对位的栅极金属层定义了刻蚀阻挡层，故该源漏极金属边沿与刻蚀阻挡层边沿精确对准（亦即后续形成的源漏极与栅极自对准且对称），两者间距小于1um，自对准精度极高。这样源漏极金属与栅极的重叠区域能精确控制在1~2um，远高于采用其它方式对准的精度。如此以栅极金属层2（即栅极）作为掩模，从基板1背部一次曝光对薄膜晶体管的沟道和源漏极进行定位，从而使沟道7与栅极2自对位，源漏极与栅极2自对准且对称，由此制成的薄膜晶体管寄生电容小，所制电路运行速度快，且不易发生短路、断路。总之，本发明实施例中自对准工艺可以最小化栅极与源漏极的重叠，且沟道尺寸可以精确控制，如此可以显著减小沟道尺寸，提高器件性能。
接着，剥离沉积于所述光刻胶的金属8以及位于所述栅极区的光刻胶62，以暴露位于沟道区的刻蚀阻挡层，此为金属剥离工艺，如图8所示。由上可知，本发明实施例所述金属剥离工艺是指在沉积金属之前，于不需要沉积金属的地方预留光刻胶（主要通过光刻胶涂敷，曝光显影实现）；沉积金属后，剥离光刻胶以及其上的金属。
然后，于所述基板1一侧涂布用以覆盖所述栅极区和源漏极区的光刻胶，用第二掩膜板从正面曝光、显影，以暴露部分源漏极金属，同时保留部分光刻胶63，如图9所示。其中，所暴露源漏极金属的大小取决于将要形成的源漏极大小。
最后，移除暴露的源漏极金属以及与该源漏极金属对位的金属氧化物层，以形成薄膜晶体管的源漏极9，之后移除覆盖所述栅极区和源漏极区的光刻胶63。具体地，先刻蚀掉暴露的源漏极金属，从而形成薄膜晶体管的源漏极9，接着刻蚀掉与该暴露的源漏极金属对位的金属氧化物层，如图10所示。然后移除覆盖前述栅极区和源漏极区的光刻胶63，如图11所示。应当说明的是，栅极一侧为源极时，另一侧为漏极。
在步骤S103中，沉积钝化层，并制作源漏极接触过孔引线。
如图12所示，本发明实施例于所述基板1一侧沉积用以保护前述步骤所形成的栅极2、源漏极9以及沟道7的钝化层10，该钝化层10覆盖了本薄膜晶体管的沟道区和源漏极9。
如图13所示，本发明实施例经由第三掩膜板刻蚀位于源漏极区的钝化层10，以形成直通所述源漏极9的源漏极接触过孔11。其中，所述源漏极接触过孔11的横截面呈倒梯形状，以便后道工序填充导电材料。
如图14所示，本发明实施例于前述步骤已形成的源漏极接触过孔11内沉积导电材料12，以形成源漏极接触过孔引线。其中，所述导电材料12可为透明导电材料，如ITO等。
实施例二
图15示出了本发明实施例提供的薄膜晶体管像素单元的制造方法实现流程，详述如下。
在步骤S201中，将栅极金属层、栅极引线金属层和存储电容电极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位。
如图16所示，本发明实施例先在基板21上沉积一金属层，其中所述基板21材料可以为玻璃、透明塑料等。此处采用第一个掩膜板刻蚀掉部分金属层，从而形成栅极金属层22、栅极引线金属层23和存储电容电极金属层24。其中，所述栅极金属层22作为本薄膜晶体管像素单元的栅极，所述存储电容电极金属层24作为本薄膜晶体管像素单元的存储电容其中一个电极。
接着，于所述基板21一侧依次沉积栅极绝缘层25、金属氧化物层26和刻蚀阻挡层27，所述栅极绝缘层25、金属氧化物层26和刻蚀阻挡层27自上而下覆盖前述栅极金属层22、栅极引线金属层23和存储电容电极金属层24，如图17所示。其中，所述栅极绝缘层25、金属氧化物层26和刻蚀阻挡层27均为透明材料，而所述栅极金属层22、栅极引线金属层23和存储电容电极金属层24均由不透光材料沉积而成，以便后道工序从所述基板21背部曝光。
然后，于所述刻蚀阻挡层27上涂布光刻胶64，如图18所示。在此将所述栅极金属层22、栅极引线金属层23和存储电容电极金属层24作为掩膜，从所述基板21背部曝光、显影，以暴露栅极区、栅极引线区和存储电容区以外的刻蚀阻挡层，如图19所示。因所述栅极金属层22、栅极引线金属层23和存储电容电极金属层24不透光，从而保留位于所述栅极区、栅极引线区和存储电容区的光刻胶65。
最后，移除所述栅极区、栅极引线区和存储电容区以外的刻蚀阻挡层，以暴露与该刻蚀阻挡层对位的金属氧化物层，并形成与薄膜晶体管的栅极22（即栅极金属层）自对位的沟道28，如图20所示。此处直接将与薄膜晶体管的栅极22对位的金属氧化物层作为沟道28，工艺简单。
因未暴露的金属氧化物层（即沟道）与位于所述栅极区的刻蚀阻挡层对位，位于所述栅极区的刻蚀阻挡层与薄膜晶体管的栅极22对位，故沟道28与栅极22精确对位（亦即位于所述栅极区的蚀阻挡层与栅极金属层精确对位），两者边沿间距为0~1um，自对位精度极高。
在步骤S202中，经由金属剥离工艺，形成与栅极自对准的源漏极。
如图21所示，本发明实施例先在位于所述栅极区、栅极引线区和存储电容区的光刻胶65以及各区两侧沉积金属29，并在所述栅极区两侧形成与栅极22自对准的源漏极金属。因该源漏极金属以位于所述栅极区的光刻胶65侧面为界沉积而成，且由与该光刻胶65对位的栅极金属层定义刻蚀阻挡层，故该源漏极金属边沿与刻蚀阻挡层边沿精确对准（亦即后续形成的源漏极与栅极自对准且对称），两者间距小于1um，自对准精度极高。这样源漏极金属与栅极22的重叠区域能精确控制在1~2um，远高于采用其它方式对准的精度。如此以栅极金属层22（即栅极）作为掩模，从基板21背部一次曝光对薄膜晶体管的沟道28和源漏极进行定位，从而使沟道28与栅极22自对位，源漏极与栅极22自对准且对称，由此制成的薄膜晶体管像素单元寄生电容小，所制电路运行速度快，且不易发生短路、断路。总之，本发明实施例中自对准工艺可以最小化栅极22与源漏极的重叠，且沟道28尺寸可以精确控制，如此可以显著减小沟道尺寸，提高器件性能。
接着，剥离沉积于所述光刻胶65上的金属29及位于所述栅极区、栅极引线区和存储电容区的光刻胶65，以暴露位于所述栅极区、栅极引线区和存储电容区的刻蚀阻挡层，此为金属剥离工艺，如图22所示。此处所述光刻胶65及其上沉积的金属29同时移除，移除效率高。
然后，于所述基板21一侧涂布用以覆盖栅极区和源漏极区的光刻胶66，从第二个掩膜板正面曝光、显影，使部分源漏极金属暴露，如图23所示。其中，所暴露源漏极金属的大小取决于将要形成的源漏极大小。
最后，移除暴露的源漏极金属、与该源漏极金属对位的金属氧化物层以及位于所述栅极引线区和存储电容区的刻蚀阻挡层、金属氧化物层和沉积于该金属氧化物层上的金属，以形成薄膜晶体管的源漏极，之后移除覆盖所述栅极区和源漏极区的光刻胶。具体地，先移除位于所述栅极引线区和存储电容区的刻蚀阻挡层，以暴露位于所述栅极引线区和存储电容区的金属氧化物层，如图24所示；接着移除沉积于所述金属氧化物层上、且暴露的金属，以形成薄膜晶体管的源漏极30，并暴露与该金属对位的金属氧化物层；然后移除暴露的金属氧化物层，如图25所示；最后移除覆盖所述栅极区和源漏极区的光刻胶66，如图26所示。应当说明的是，所述栅极22一侧为源极时，另一侧为漏极。
在步骤S203中，沉积钝化层，并制作源漏极接触过孔引线、栅极接触过孔引线和存储电容另一个电极。
如图27所示，本发明实施例先于所述基板21一侧沉积用以覆盖所述栅极区、源漏极区、栅极引线区和存储电容区的钝化层31。该钝化层31覆盖了本薄膜晶体管像素单元的源漏极30、位于所述沟道区的刻蚀阻挡层和暴露的栅极绝缘层。
如图28所示，本发明实施例经由第三个掩膜板刻蚀位于源漏极区和栅极引线区的钝化层，从而形成直通所述源漏极30的源漏极接触过孔32以及栅极接触过孔33。于所述栅极接触过孔33内进一步刻蚀栅极绝缘层，使后道工序沉积的导电材料与栅极引线金属层23接触。其中，所述源漏极接触过孔32和栅极接触过孔33的横截面呈倒梯形状，以便后道工序填充导电材料。
如图29所示，本发明实施例于前述步骤已形成的源漏极接触过孔32、栅极接触过孔33内以及位于所述存储电容区的钝化层31上沉积导电材料34，该导电材料34可为透明导电材料，如ITO等。如图30所示，为形成像素电极和存储电容另一电极35，此处采用第四掩膜板进行光刻。这样本薄膜晶体管像素单元制造过程中只需采用四个不需要关键对准的掩膜板，从而提高产率，降低成本。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (9)

  1. 一种薄膜晶体管的制造方法，其特征在于，所述方法包括以下步骤：
    将栅极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位；
    经由金属剥离工艺，形成与栅极自对准的源漏极；
    沉积钝化层，并制作源漏极接触过孔引线；
    其中，所述沟道为与薄膜晶体管的栅极对位的金属氧化物层。
  2. 如权利要求1所述的方法，其特征在于，所述将栅极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位的步骤具体为：
    于基板上形成栅极金属层、栅极绝缘层、金属氧化物层和刻蚀阻挡层；
    于所述刻蚀阻挡层上涂布光刻胶，将所述栅极金属层作为掩膜，从所述基板背部曝光、显影，以暴露栅极区以外的刻蚀阻挡层，并保留位于所述栅极区的光刻胶；
    移除所述栅极区以外的刻蚀阻挡层，以暴露与该刻蚀阻挡层对位的金属氧化物层，并形成与薄膜晶体管的栅极自对位的沟道。
  3. 如权利要求2所述的方法，其特征在于，所述经由金属剥离工艺，形成与栅极自对准的源漏极的步骤具体为：
    在位于所述栅极区的光刻胶及其两侧同时沉积金属，并使所述金属覆盖金属氧化物层，以形成与所述栅极自对准的源漏极金属；
    剥离沉积于所述光刻胶的金属以及位于所述栅极区的光刻胶，以暴露位于沟道区的刻蚀阻挡层；
    涂布用以覆盖所述栅极区和源漏极区的光刻胶，用一掩膜板从正面曝光、显影，以使部分源漏极金属暴露；
    移除暴露的源漏极金属以及与该源漏极金属对位的金属氧化物层，以形成薄膜晶体管的源漏极，之后移除覆盖所述栅极区和源漏极区的光刻胶。
  4. 如权利要求3所述的方法，其特征在于，所述沉积钝化层，并制作源漏极接触过孔引线的步骤具体为：
    于所述基板一侧沉积用以覆盖所述栅极和源漏极的钝化层；
    刻蚀所述钝化层，以形成源漏极接触过孔；
    于所述源漏极接触过孔内沉积导电材料，以形成源漏极接触过孔引线。
  5. 一种薄膜晶体管像素单元的制造方法，其特征在于，所述方法包括以下步骤：
    将栅极金属层、栅极引线金属层和存储电容电极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位；
    经由金属剥离工艺，形成与栅极自对准的源漏极；
    沉积钝化层，并制作源漏极接触过孔引线、栅极接触过孔引线和存储电容另一个电极；
    其中，所述沟道为与薄膜晶体管的栅极对位的金属氧化物层。
  6. 如权利要求5所述的方法，其特征在于，所述将栅极金属层、栅极引线金属层和存储电容电极金属层作为掩膜，从基板背部曝光、显影，使薄膜晶体管的沟道与栅极自对位的步骤具体为：
    于基板上制备金属层，通过光刻形成栅极金属层、栅极引线金属层和存储电容电极金属层；
    于所述基板一侧依次沉积用以覆盖所述栅极金属层、栅极引线金属层和存储电容电极金属层的栅极绝缘层、金属氧化物层和刻蚀阻挡层；
    于所述刻蚀阻挡层上涂布光刻胶，将所述栅极金属层、栅极引线金属层和存储电容电极金属层作为掩膜，从所述基板背部曝光、显影，以暴露栅极区、栅极引线区和存储电容区以外的刻蚀阻挡层，并保留位于所述栅极区、栅极引线区和存储电容区的光刻胶；
    移除所述栅极区、栅极引线区和存储电容区以外的刻蚀阻挡层，以暴露与该刻蚀阻挡层对位的金属氧化物层，并形成与薄膜晶体管的栅极自对位的沟道。
  7. 如权利要求6所述的方法，其特征在于，所述经由金属剥离工艺，形成与栅极自对准的源漏极的步骤具体为：
    在位于所述栅极区、栅极引线区和存储电容区的光刻胶以及各区两侧同时沉积金属，并使所述金属覆盖金属氧化物层，以在所述栅极区两侧形成与栅极自对准的源漏极金属；
    同时剥离沉积于所述光刻胶上的金属及位于所述栅极区、栅极引线区和存储电容区的光刻胶，以暴露位于所述栅极区、栅极引线区和存储电容区的刻蚀阻挡层；
    涂布用以覆盖所述栅极区和源漏极区的光刻胶，从一掩膜板正面曝光、显影，使部分源漏极金属暴露；
    移除暴露的源漏极金属、与该源漏极金属对位的金属氧化物层以及位于所述栅极引线区和存储电容区的刻蚀阻挡层、金属氧化物层和沉积于该金属氧化物层上的金属，以形成薄膜晶体管的源漏极，之后移除覆盖所述栅极区和源漏极区的光刻胶。
  8. 如权利要求7所述的方法，其特征在于，所述沉积钝化层，并制作源漏极接触过孔引线、栅极接触过孔引线和存储电容另一个电极的步骤具体为：
    于所述基板一侧沉积用以覆盖所述栅极区、源漏极区、栅极引线区和存储电容区的钝化层；
    刻蚀所述钝化层，以形成源漏极接触过孔和栅极接触过孔；
    于所述源漏极接触过孔、栅极接触过孔内以及位于所述存储电容区的钝化层上沉积导电材料，以形成源漏极接触过孔引线、栅极接触过孔引线和存储电容另一个电极。
  9. 如权利要求7或8所述的方法，其特征在于，所述移除暴露的源漏极金属、与该源漏极金属对位的金属氧化物层以及位于所述栅极引线区和存储电容区的刻蚀阻挡层、金属氧化物层和沉积于该金属氧化物层上的金属，以形成薄膜晶体管的源漏极，之后移除覆盖所述栅极区和源漏极区的光刻胶的步骤具体为：
    移除位于所述栅极引线区和存储电容区的刻蚀阻挡层，以暴露位于所述栅极引线区和存储电容区的金属氧化物层；
    移除沉积于所述金属氧化物层上、且暴露的金属，以形成薄膜晶体管的源漏极，并暴露与该金属对位的金属氧化物层；
    移除暴露的金属氧化物层；
    移除覆盖所述栅极区和源漏极区的光刻胶。
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