WO2014109224A1 - Résistance de puce - Google Patents

Résistance de puce Download PDF

Info

Publication number
WO2014109224A1
WO2014109224A1 PCT/JP2013/084491 JP2013084491W WO2014109224A1 WO 2014109224 A1 WO2014109224 A1 WO 2014109224A1 JP 2013084491 W JP2013084491 W JP 2013084491W WO 2014109224 A1 WO2014109224 A1 WO 2014109224A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
barrier layer
resistor
ceramic substrate
Prior art date
Application number
PCT/JP2013/084491
Other languages
English (en)
Japanese (ja)
Inventor
臣祐 千原
泰 赤羽
Original Assignee
コーア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by コーア株式会社 filed Critical コーア株式会社
Publication of WO2014109224A1 publication Critical patent/WO2014109224A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/144—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being welded or soldered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/142—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being coated on the resistive element

Definitions

  • the present invention relates to a surface mount type chip resistor which is mounted on a circuit board by soldering.
  • FIG. 5 is a cross-sectional view schematically showing a conventional general chip resistor.
  • the chip resistor 21 shown in the figure is made of a rectangular parallelepiped ceramic substrate 22, a pair of surface electrodes 23 made of sintered silver or the like provided at both ends in the longitudinal direction of the upper surface of the ceramic substrate 22, and ruthenium oxide or the like.
  • a resistor 24 provided between the pair of surface electrodes 23, an insulating protective layer 25 covering the resistor 24, and provided at both ends in the longitudinal direction of the lower surface of the ceramic substrate 22 made of sintered silver or the like.
  • a pair of back surface electrodes 26 and a pair of end surface electrodes 27 provided on both end surfaces in the longitudinal direction of the ceramic substrate 22 to bridge the front surface electrode 23 and the back surface electrode 26.
  • a plating layer 28 is attached to the front surface electrode 23, the end surface electrode 27, and the back surface electrode 26 that are continuous in a shape.
  • the ceramic substrate 22 is obtained by dividing a large substrate along a vertical and horizontal dividing groove, and a large number of ceramic substrates 22 are obtained.
  • the back electrode 26, the protective layer 25, and the like are collectively formed.
  • the resistance value of the chip resistor 21 is adjusted by forming a trimming groove (not shown) in the resistor 24.
  • the protective layer 25 generally has a two-layer structure, and an undercoat layer formed before adjusting the resistance value for trimming the resistor 24 and an overcoat layer formed after adjusting the resistance value are laminated. ing.
  • the end surface electrode 27 is formed on a split surface of a strip-shaped substrate obtained by first dividing a large substrate on which a large number of protective layers 25 are formed.
  • the strip-shaped substrate is separated into pieces ( The chip layer is divided into two parts, and the plated layer 28 is deposited on each chip.
  • This plating layer 28 includes an innermost nickel (Ni) plating layer in close contact with the base electrode layer, and an outermost solder (Sn / Pb) plating layer or tin (Sn) plating layer exposed on the outer surface. It has a laminated structure of more than one layer.
  • this type of chip resistor 21 is surface-mounted by mounting a back electrode 26 on a land provided on a circuit board and soldering, but the thermal environment changes to the chip resistor 21 after mounting. Is repeated (hereinafter referred to as heat shock), the solder joints are easily damaged by thermal stress and cracks are likely to occur. When a crack due to heat shock occurs in the solder joint, the solder joint is a place where the back electrode 26 of the chip resistor 21 and the land of the circuit board are electrically and mechanically connected. It may lead to poor conduction.
  • a chip resistor has been proposed in which the back electrode has a two-layer structure of an inner layer made of baked silver and an outer layer made of a conductive resin so that thermal stress acting on the solder joint can be reduced (for example, , See Patent Document 1).
  • the outer layer of the back electrode that contacts the solder joint on the land of the circuit board is made of a conductive resin, it acts on the solder joint compared to the case where the back electrode is made only of sintered silver. The effect of relaxing the thermal stress is expected.
  • the present invention has been made in view of such a state of the art, and an object thereof is to provide a chip resistor that can prevent damage due to heat shock of the entire solder joint including the back electrode and the end electrode. It is in.
  • a chip resistor of the present invention includes a pair of surface electrodes provided at both longitudinal ends of the surface of the ceramic substrate, and the ceramic substrate connected to the pair of surface electrodes.
  • a resistor provided on the front surface, a pair of back electrodes provided on both ends in the longitudinal direction of the back surface of the ceramic substrate, an insulating protective layer covering the resistor, and provided on both end surfaces of the ceramic substrate
  • the end face electrode is formed of a sputtered film containing chromium and the material of the barrier layer, and the barrier layer is a plating made of nickel or copper having a thickness of 8 ⁇ m to 30 ⁇ m. It was configured to be formed of layers.
  • the barrier layer is subjected to thermal stress (heat shock). On the other hand, it becomes a cushion material, and fatigue and cracks due to the thermal stress of the entire solder joint including the back electrode and the end electrode can be prevented.
  • the end face electrode is formed of a sputtered film containing chromium and a barrier layer material (nickel or copper) having good adhesion to the ceramic substrate, the boundary portion between the barrier layer and the end face electrode is strengthened. Also, it can cope with internal stress generated when the barrier layer is formed thick.
  • the end face electrode, the front surface electrode, and the back surface electrode are covered with a thick (8 to 30 ⁇ m) barrier layer, so that the barrier layer becomes a cushioning material against thermal stress (heat shock). Fatigue and cracks due to the thermal stress of the entire solder joint including the back electrode and the end electrode can be prevented.
  • the end face electrode is formed of a sputtered film containing chromium and a barrier layer material (nickel or copper) having good adhesion to the ceramic substrate, the boundary portion between the barrier layer and the end face electrode is strengthened. Further, fatigue and cracks due to internal stress generated when the barrier layer is formed thick can be prevented.
  • this chip resistor does not require a complicated manufacturing process of the back electrode, and therefore it is easy to avoid an increase in cost. Therefore, a chip resistor that is resistant to heat shock and has a long service life can be provided at low cost.
  • a chip resistor 1 according to an embodiment of the present invention is provided at both ends in the longitudinal direction of a rectangular parallelepiped ceramic substrate 2 and the back surface (lower surface in FIG. 1) of the ceramic substrate 2.
  • a pair of backside electrodes 3, a pair of front surface electrodes 4 provided at both ends in the longitudinal direction of the surface of the ceramic substrate 2 (upper surface in FIG. 1), and both ends of the pair of surface electrodes 4 are overlapped with the ceramic substrate 2.
  • a resistor 5 provided on the surface of the ceramic substrate 2, a pair of end face electrodes 6 provided on both end faces in the longitudinal direction of the ceramic substrate 2 to bridge the back electrode 3 and the surface electrode 4, and the resistor 5.
  • Two-layer protective layer undercoat layer 7 and overcoat layer 8
  • barrier layer 9 applied to the front electrode 4, the end face electrode 6 and the back electrode 3, and solder plating applied to the barrier layer 9 Layer 10 and It is.
  • the ceramic substrate 2 is an insulating substrate containing alumina as a main component, and the ceramic substrate 2 is obtained by dividing a large-size substrate, which will be described later, along a vertical and horizontal dividing groove.
  • the back electrode 3 is obtained by screen-printing Ag paste and drying and firing, and the front electrode 4 is also obtained by screen-printing Ag paste and drying and firing.
  • the resistor 5 is obtained by screen-printing a resistor paste such as ruthenium oxide, drying and firing, and the resistance value of the chip resistor 1 is adjusted by forming a trimming groove (not shown) in the resistor 5. Has been.
  • the end face electrode 6 is formed on the end face of the ceramic substrate 2 by sputtering, and is made of a sputtered film containing chromium (Cr) having good adhesion to the ceramic substrate 2 and a material of a barrier layer 9 described later.
  • the barrier layer 9 is a plating layer made of nickel (Ni) or copper (Cu)
  • the solder plating layer 10 is a plating layer made of tin (Sn) -lead (Pb), lead-free Sn, or the like.
  • the chip resistor 1 is mounted on a land 31 provided on a circuit board 30 with the back electrode 3 facing downward, and is the outermost solder plating layer 10 covering the barrier layer 9.
  • the barrier layer 9 is formed to have a thickness of 8 ⁇ m to 30 ⁇ m so as to cover the end face electrode 6, the front surface electrode 4, and the back surface electrode 3, the barrier layer 9 becomes a cushioning material against thermal stress (heat shock), Fatigue and cracks due to the thermal stress of the entire solder joint including the end face electrode 6 and the back face electrode 3 can be prevented.
  • the end face electrode 6 covered with the barrier layer 9 is formed of a sputtered film containing chromium having good adhesion to the ceramic substrate 2 and the material of the barrier layer 9 (nickel or copper), the barrier layer 9 and the end face electrode 6 are strengthened, and fatigue and cracks due to internal stress generated when the barrier layer 9 is formed thick can be prevented.
  • an unbaked back electrode 3 is formed by screen-printing and drying Ag paste on the back surface of a large substrate 40 on which a large number of ceramic substrates 2 are taken.
  • the unfired surface electrode 4 is formed by screen-printing and drying an Ag / Pd paste on the surface of the large substrate 40.
  • the large-sized substrate 40 is provided with a primary division groove and a secondary division groove (both not shown) in advance in a lattice shape, and each square divided by both division grooves is equivalent to one piece. This is the chip area.
  • a resistor paste such as ruthenium oxide is screened on the surface of the large substrate 40 as a fourth step.
  • an unfired resistor 5 is formed in each chip region as shown in FIG. At that time, both ends in the longitudinal direction of the resistor 5 are overlapped with the surface electrodes 4 provided at both ends in the longitudinal direction of each chip region.
  • the resistor 5 is fired at a high temperature of about 850 ° C. Note that the firing of the third step described above may be omitted, and the back electrode 3, the front electrode 4 and the resistor 5 may be fired simultaneously in this fifth step. In this case, the firing step is reduced to reduce the cost. It becomes possible.
  • the glass paste is baked at a high temperature of about 600 ° C. in the seventh step, as shown in FIG. Then, an undercoat layer 7 corresponding to the primary protective coat covering the resistor 5 is formed.
  • the undercoat layer 7 and the resistor 5 are irradiated with laser to form a trimming groove (not shown), thereby adjusting to a desired resistance value.
  • a ninth step after screen printing a glass paste or an epoxy resin paste so as to cover the undercoat layer 7, this is baked in the tenth step (for example, the glass paste is fired at about 600 ° C., The resin paste is heated and cured at about 200 ° C.) to form an overcoat layer 8 corresponding to a secondary protective coat covering the resistor 5 and the undercoat layer 7.
  • This overcoat layer 8 is for protecting the resistor 5 from the external environment.
  • the process up to this point is a batch process for the large-sized substrate 40 for taking a large number of pieces, but in the next eleventh step, the primary break processing is performed in which the large-sized substrate 40 is divided into strips along the primary dividing grooves by a break. I do. Thereby, the strip-shaped substrate 41 provided with a plurality of chip regions is obtained.
  • This end face electrode 6 contains chromium (Cr) having good adhesion to the ceramic substrate 2 (large format substrate 40 or strip substrate 41) and nickel (Ni) which is a material of the barrier layer 9 formed in the next step.
  • Cr chromium
  • Ni nickel
  • the thickness of the sputtered film is set to 500 mm or more in order to prevent erosion of the solder.
  • the barrier layer 9 is a nickel plating layer covering the front electrode 4, the end face electrode 6 and the back electrode 3, and the film thickness is set to 8 ⁇ m to 30 ⁇ m so as to be a cushioning material against heat shock.
  • the thickness of the barrier layer 9 is thinner than 8 ⁇ m, the cushioning effect becomes insufficient and it becomes difficult to prevent cracks.
  • the thickness of the barrier layer 9 exceeds 30 ⁇ m, the barrier layer 9 Since the generated internal stress becomes excessively large, the thickness of the barrier layer 9 is preferably set to 8 ⁇ m to 30 ⁇ m.
  • a solder plating layer 10 is formed by electrolytic plating so as to cover the barrier layer 9, thereby forming a two-layered plating layer (barrier layer 9 as shown in FIG. 4C). And the chip resistor 1 having the solder plating layer 10) are completed.
  • the chip resistor 1 is connected to the pair of surface electrodes 4 provided at both ends in the longitudinal direction of the surface of the ceramic substrate 2 and the pair of surface electrodes 4.
  • a resistor 5 provided on the surface of the ceramic substrate 2, a pair of back electrodes 3 provided at both longitudinal ends of the back surface of the ceramic substrate 2, and an insulating protective layer (undercoat layer) covering the resistor 5 7 and the overcoat layer 8
  • a pair of end face electrodes 6 provided on both end faces of the ceramic substrate 2 to bridge the front face electrode 4 and the back face electrode 3, and the end face electrode 6, the front face electrode 4 and the back face
  • a barrier layer 9 covering the electrode 3 and a solder plating layer 10 covering the barrier layer 9 are provided.
  • the end face electrode 6 is formed of a sputtered film containing chromium and the material of the barrier layer 9, and the barrier Since the layer 9 is formed of a plating layer made of nickel or copper having a thickness of 8 ⁇ m to 30 ⁇ m, the barrier layer 9 serves as a cushioning material against thermal stress (heat shock), and solder bonding including the back electrode 3 and the end surface electrode 6 Fatigue and cracks resulting from the thermal stress of the entire part can be prevented.
  • the end face electrode 6 covered with the barrier layer 9 is formed of a sputtered film containing chromium having good adhesion to the ceramic substrate 2 and the material of the barrier layer 9 (nickel or copper), the barrier layer 9 And the end face electrode 6 are strengthened, and fatigue and cracks due to internal stress generated when the barrier layer 9 is formed thick can be prevented.
  • the barrier layer 9 is formed of a nickel plating layer and the end face electrode 6 is formed of a sputtered film containing chromium and nickel.
  • the barrier layer 9 is made of a nickel plating layer.
  • a copper (Cu) plating layer can also be used.
  • the end face electrode containing chromium and copper is formed by sputtering Cr / Cu on the dividing surface of the strip-shaped substrate 41 in the twelfth step described above. 6 may be formed.
  • the end face electrode 6 may contain titanium (Ti) or the like other than that as long as it contains at least chromium and the material of the barrier layer 9 (nickel or copper).
  • the end face electrode 6 can be formed of a Cr—Ni—Cu sputtered film or a Cr—Ni—Ti sputtered film.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

L'invention concerne une résistance de puce apte à éviter un endommagement dû à un choc thermique sur la totalité d'une partie de joint de soudure contenant une électrode de surface arrière et une électrode de face d'extrémité. La résistance de puce (1) comprend : des électrodes de surface (4) disposées sur la surface d'un substrat céramique (2) ; un corps de résistance (5) qui connecte la paire d'électrodes de surface (4) ; une électrode de surface arrière (3) disposée sur la surface arrière du substrat céramique (2) ; une couche protectrice isolante (une couche de sous-revêtement (7) et une couche de sur-revêtement (8)) pour recouvrir le corps de résistance (5) ; une paire d'électrodes de face d'extrémité (6) qui forment un pont entre les électrodes de surface (4) et l'électrode de surface arrière (3), les électrodes de face d'extrémité (6) étant disposées sur les deux faces d'extrémité du substrat céramique (2) ; une couche barrière (9) qui recouvre les électrodes de face d'extrémité (6), les électrodes de surface (4), et l'électrode de surface arrière (3) ; et une couche de revêtement de soudure (10) qui recouvre la couche barrière (9), les électrodes de face d'extrémité (6) étant formées d'un film projeté contenant du chrome et le matériau de couche barrière (9), et la couche barrière (9) étant formée d'une couche de revêtement comprenant du nickel ou du cuivre ayant une épaisseur de 8 à 30 µm.
PCT/JP2013/084491 2013-01-11 2013-12-24 Résistance de puce WO2014109224A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-003427 2013-01-11
JP2013003427A JP2014135427A (ja) 2013-01-11 2013-01-11 チップ抵抗器

Publications (1)

Publication Number Publication Date
WO2014109224A1 true WO2014109224A1 (fr) 2014-07-17

Family

ID=51166881

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/084491 WO2014109224A1 (fr) 2013-01-11 2013-12-24 Résistance de puce

Country Status (2)

Country Link
JP (1) JP2014135427A (fr)
WO (1) WO2014109224A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107359033A (zh) * 2016-03-15 2017-11-17 罗姆股份有限公司 芯片电阻器及其制造方法
CN107426921A (zh) * 2017-09-07 2017-12-01 上海长园维安电子线路保护有限公司 一种满足过回流焊的自控制型保护器及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10083781B2 (en) 2015-10-30 2018-09-25 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10438729B2 (en) 2017-11-10 2019-10-08 Vishay Dale Electronics, Llc Resistor with upper surface heat dissipation
JP6777104B2 (ja) 2018-01-31 2020-10-28 日亜化学工業株式会社 発光装置及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003045702A (ja) * 2001-07-31 2003-02-14 Koa Corp チップ抵抗器およびその製造方法
JP2009295813A (ja) * 2008-06-05 2009-12-17 Hokuriku Electric Ind Co Ltd チップ状電気部品及びその製造方法
JP2011165752A (ja) * 2010-02-05 2011-08-25 Taiyosha Electric Co Ltd チップ抵抗器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003045702A (ja) * 2001-07-31 2003-02-14 Koa Corp チップ抵抗器およびその製造方法
JP2009295813A (ja) * 2008-06-05 2009-12-17 Hokuriku Electric Ind Co Ltd チップ状電気部品及びその製造方法
JP2011165752A (ja) * 2010-02-05 2011-08-25 Taiyosha Electric Co Ltd チップ抵抗器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107359033A (zh) * 2016-03-15 2017-11-17 罗姆股份有限公司 芯片电阻器及其制造方法
CN107426921A (zh) * 2017-09-07 2017-12-01 上海长园维安电子线路保护有限公司 一种满足过回流焊的自控制型保护器及其制造方法

Also Published As

Publication number Publication date
JP2014135427A (ja) 2014-07-24

Similar Documents

Publication Publication Date Title
JP2024010234A (ja) チップ抵抗器
WO2007034759A1 (fr) Pave resistif
JP5503034B2 (ja) チップ抵抗器
WO2014109224A1 (fr) Résistance de puce
JP6499007B2 (ja) チップ抵抗器
WO2019087725A1 (fr) Résistance pavé
JP2013074044A (ja) チップ抵抗器
WO2006093107A1 (fr) Resistance pave et son procede de fabrication
JP6181500B2 (ja) チップ抵抗器およびその製造方法
JP2011165752A (ja) チップ抵抗器
JP5115968B2 (ja) チップ抵抗器の製造方法およびチップ抵抗器
JP2008311362A (ja) セラミック電子部品
JP5706186B2 (ja) チップ抵抗器およびその製造方法
JP5012432B2 (ja) セラミック電子部品
JP4707890B2 (ja) チップ抵抗器およびその製造方法
JP2022012055A (ja) 抵抗器
JP2007095926A (ja) チップ抵抗器
KR101771836B1 (ko) 칩 저항 소자 및 칩 저항 소자 어셈블리
JP4729398B2 (ja) チップ抵抗器
JP2015061034A (ja) チップ抵抗器
JP6159286B2 (ja) チップ抵抗器及びチップ抵抗器の製造方法
JP3953325B2 (ja) チップ抵抗器およびその製造方法
WO2022190879A1 (fr) Structure de montage pour composant de puce
WO2021261504A1 (fr) Résistance
WO2022180979A1 (fr) Résistance de puce

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13871124

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13871124

Country of ref document: EP

Kind code of ref document: A1