WO2014092089A1 - Dispositif semi-conducteur de puissance, dispositif redresseur, et dispositif de source d'alimentation - Google Patents

Dispositif semi-conducteur de puissance, dispositif redresseur, et dispositif de source d'alimentation Download PDF

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Publication number
WO2014092089A1
WO2014092089A1 PCT/JP2013/083109 JP2013083109W WO2014092089A1 WO 2014092089 A1 WO2014092089 A1 WO 2014092089A1 JP 2013083109 W JP2013083109 W JP 2013083109W WO 2014092089 A1 WO2014092089 A1 WO 2014092089A1
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semiconductor chip
main surface
semiconductor device
layer
type
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PCT/JP2013/083109
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English (en)
Japanese (ja)
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智弘 恩田
耕一 石川
翼 武田
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株式会社 日立パワーデバイス
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Publication of WO2014092089A1 publication Critical patent/WO2014092089A1/fr

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    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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Definitions

  • the present invention relates to a power semiconductor device used in the field of power electronics, and a rectifier and a power supply device using the power semiconductor device.
  • An alternator mounted on a vehicle such as a passenger car uses a rectifier (AC-DC converter) that uses a power semiconductor device (such as a rectifier diode) to convert the alternating current generated by a generator rotated by the power of the engine into direct current. Convert to current.
  • AC-DC converter rectifier
  • a power semiconductor device such as a rectifier diode
  • a power semiconductor device for a vehicle is used for a long time in a harsh temperature environment, and a high-temperature environment and a low-temperature (room temperature) environment are repeated. Impact is a big problem. In particular, improving the thermal fatigue life of a bonding layer (such as a solder bonding layer) between electronic members and the peeling life of an insulating protective film that insulates and protects a semiconductor chip have become practical issues.
  • a bonding layer such as a solder bonding layer
  • a power semiconductor device such as a rectifier diode has a structure in which a semiconductor chip having a rectifying function is sandwiched and held between a base electrode and a lead electrode. Bonded with bonding material.
  • a semiconductor chip and each electrode are bonded with a bonding material via a thermal relaxation body whose linear expansion coefficient has an intermediate value between the linear expansion coefficient of each electrode and that of the semiconductor chip.
  • Patent Document 2 discloses a power semiconductor device having a structure in which a mesa-type semiconductor chip is sandwiched between a base electrode and a lead electrode and bonded to each electrode via a bonding material such as solder.
  • the sealing resin having a value within a specific range in which the linear expansion coefficient includes the linear expansion coefficient of the base electrode in the middle is used as the sealing resin for sealing the heat semiconductor device, the thermal fatigue life of the power semiconductor device is reduced. It has been shown to improve.
  • Patent Document 2 shows that in many cases, peeling or cracking is observed in the sealing resin when the appearance of a test object having a short life in a thermal fatigue life test of a power semiconductor device is inspected.
  • peeling or cracking occurs in the sealing resin, it is considered that moisture or impurity atoms enter from there and peel off the bonding layer such as solder or short-circuit the pn junction in the semiconductor chip.
  • the bonding layer such as solder or short-circuit the pn junction in the semiconductor chip.
  • a mesa type is used as a semiconductor chip, a pn junction is exposed on the side surface of the end of the semiconductor chip, so that moisture or solder metal atoms enter the part. Then, dielectric breakdown occurs at the pn junction.
  • an insulating protective film is further formed between the side surface of the end portion of the semiconductor chip and the sealing resin.
  • the sealing resin is peeled off or cracked, the pn junction portion of the semiconductor chip is protected by the insulating protective film, so that the function as the power semiconductor device is not lost immediately.
  • the insulation protective film is peeled off after that, the dielectric breakdown of the pn junction portion is reached and the function as a power semiconductor device is lost.
  • the relation between the peeling of the insulating protective film and the thermal fatigue life has not been sufficiently considered.
  • an object of the present invention is to provide a power semiconductor device capable of improving the thermal fatigue life, and a rectifier and a DC power supply device using the power semiconductor device. .
  • a power semiconductor device includes a semiconductor chip in which a second conductive type impurity diffusion layer is formed on a first main surface of a semiconductor substrate made of a first conductive type semiconductor layer, and a flat holding surface on the top. And holding the semiconductor chip with the first main surface facing down on the holding surface, and the impurity diffusion layer of the second conductivity type formed on the first main surface is conductive.
  • a base electrode body bonded to the holding surface via a bonding material and a first conductive type semiconductor layer constituting a second main surface that is a main surface opposite to the first main surface are electrically conductive
  • a boundary between the first conductive type semiconductor layer and the second conductive type impurity diffusion layer The pn junction portion to be formed is formed at a position closer to the first main surface than the second main surface, and insulation is provided between the peripheral portion of the semiconductor chip and the sealing resin body.
  • a protective film is formed.
  • the rectifier according to the present invention includes a diode bridge circuit formed by combining a plurality of series connection circuits of upper potential side diode elements and lower potential side diode elements, and the upper potential side diode element is a p substrate.
  • a positive electrode element is used, and an n-substrate negative electrode element is used as the lower potential side diode element.
  • the p-substrate type positive electrode element in the power semiconductor device is such that the first conductivity type semiconductor layer is a p-type semiconductor layer and the second conductivity type impurity diffusion layer is an n-type impurity diffusion layer.
  • the n-substrate type negative electrode element in the power semiconductor device is such that the first conductivity type semiconductor layer is an n-type semiconductor layer and the second conductivity type impurity diffusion layer is a p-type impurity diffusion layer.
  • the power supply device is characterized by including a rotary generator and the rectifier.
  • the present invention it is possible to provide a power semiconductor device having an improved thermal fatigue life, and a rectifier and a DC power supply device using the power semiconductor device.
  • FIG. 1 is a diagram schematically showing an example of the structure of a power semiconductor device 100 according to an embodiment of the present invention.
  • the left half of the center line shown in FIG. 1 is a front view of the appearance of the power semiconductor device 100, and the right half of the figure schematically shows the cross-sectional structure of the power semiconductor device 100.
  • FIG. 1 is a diagram schematically showing an example of the structure of a power semiconductor device 100 according to an embodiment of the present invention.
  • the left half of the center line shown in FIG. 1 is a front view of the appearance of the power semiconductor device 100
  • the right half of the figure schematically shows the cross-sectional structure of the power semiconductor device 100.
  • a semiconductor chip 10 having a rectifying function is sandwiched between a lead electrode body 20 and a base electrode body 30 made of a good conductor such as copper, and solder or the like. Are joined via the joining materials 40 and 41.
  • the semiconductor chip 10 is a mesa rectifier diode.
  • the base electrode body 30 is a basic structure of the power semiconductor device 100, and a pedestal portion 31 on which the semiconductor chip 10 is mounted and a groove portion 32 surrounding the pedestal portion 31 are formed on the upper surface portion thereof.
  • the upper surface of the pedestal portion 31 is a flat surface, and one main surface of the semiconductor chip 10 is bonded to the flat surface via a bonding material 41. Further, the lead electrode body 20 is bonded to the other main surface of the semiconductor chip 10 via a bonding material 40.
  • the sealing resin body 60 is formed of an epoxy resin or the like, seals the semiconductor chip 10 sandwiched between the base electrode body 30 and the lead electrode body 20, and also connects the lead electrode body 20 to the base electrode body 30. It plays the role of fixing. That is, the side wall of the groove portion 32 of the base electrode body 30 on the side of the pedestal portion 31 is formed so that the pedestal portion 31 overhangs, and the epoxy resin is cured after being poured into the groove portion 32.
  • the stop resin body 60 has a structure that does not come off the base electrode body 30.
  • a relatively soft thin film made of a polyimide resin or the like is formed between the peripheral edge of the semiconductor chip 10 and between the bonding materials 40 and 41 and the sealing resin body 60.
  • An insulating protective film 50 is formed. The insulating protective film 50 prevents the pn junction exposed on the side surface of the end portion of the mesa-type semiconductor chip 10 from intrusion of moisture and impurity atoms, and thermal stress generated between the semiconductor chip 10 and the sealing resin body 60. Plays a role in mitigating.
  • FIG. 2A is a diagram showing an example of the structure of the semiconductor chip 10 and its peripheral portion in the power semiconductor device 100 using the p substrate type positive element as the semiconductor chip 10
  • FIG. 2B shows the p substrate type negative element
  • FIG. 2C is a diagram showing an example of the structure of the semiconductor chip 10 and its peripheral portion in the power semiconductor device 100 used as the semiconductor chip 10
  • FIG. 2D is a diagram illustrating an example of the structure of the semiconductor chip 10a and its peripheral portion, and FIG.
  • FIG. 2D is a diagram illustrating an example of the structure of the semiconductor chip 10a and the peripheral portion thereof in the power semiconductor device 100 using the n-substrate negative electrode element as the semiconductor chip 10a. It is. Note that the semiconductor chip 10 and the peripheral edge thereof in the power semiconductor device 100 refer to a portion corresponding to a region A indicated by a broken-line rectangle in FIG. Each of FIGS. 2A to 2D is attached with a diagram showing a vertical structure of the semiconductor chips 10 and 10a, particularly in order to clarify the position of the pn junction portion 13.
  • the positive electrode element is a rectifier diode (power semiconductor device 100) using the lead electrode body 20 of the power semiconductor device 100 as an anode (anode) and the base electrode pair 30 as a cathode (cathode).
  • the negative electrode element refers to a rectifier diode (power semiconductor device 100) that uses the lead electrode body 20 of the power semiconductor device 100 as a cathode (cathode) and the base electrode body 30 as an anode (anode).
  • the names of the p substrate type and the n substrate type are based on the conductivity types of the substrates of the semiconductor chips 10 and 10a used in each rectifier diode (power semiconductor device 100).
  • n-type impurity diffusion layer 12 (n + layer).
  • the p-type semiconductor layer 11 refers to a portion where a high-concentration n-type impurity is not diffused in the p-type semiconductor substrate.
  • the main surface on the p-type semiconductor layer 11 side (the main surface opposite to the main surface on which the n-type impurity diffusion layer 12 is formed) has adhesion between the p-type semiconductor layer 11 and the metal layer.
  • p-type impurities are diffused at a high concentration, and a high-concentration p-type impurity diffusion layer (p + layer) is formed.
  • this high-concentration p-type impurity diffusion layer (p + layer) is also referred to as a p-type semiconductor layer 11.
  • a pn junction 13 is formed at the boundary between the p-type semiconductor layer 11 and the n-type impurity diffusion layer 12 inside the semiconductor chip 10 as described above.
  • the position of the pn junction 13, in other words, the diffusion depth of the n-type impurity diffusion layer 12 is appropriately about 10 to 35% of the entire thickness of the semiconductor chip 10.
  • the position of the pn junction 13 in such a range is a result of considering the reverse breakdown voltage required for the semiconductor chip 10 as a rectifier diode, the impurity concentration of the p-type semiconductor layer 11 and the n-type impurity diffusion layer 12, and the like. It was obtained based on.
  • nickel or nickel is formed on the outside of the high-concentration n-type impurity diffusion layer 12 (n + layer) and the outside of the high-concentration p-type impurity diffusion layer (p + layer) of the semiconductor chip 10, for example.
  • a metal layer made of an alloy or the like is formed (not shown). Therefore, the n-type impurity diffusion layer 12 (n + layer) and the p-type semiconductor layer 11 are electrically connected to the lead electrode body 20 or the base electrode body 30 by bonding the metal layer to the bonding materials 40 and 41. Connected.
  • the lead electrode body 20 is used as an anode (anode)
  • the n type impurity diffusion layer 12 is It arrange
  • the lead electrode body 20 is used as a cathode (cathode). Therefore, when the semiconductor chip 10 is formed of a p-type semiconductor substrate, the n-type impurity diffusion layer 12 is used. Is disposed on the upper surface side and is bonded to the bonding material 40 on the lead electrode body 20 side.
  • the insulating protective film 50 is formed on the side surface of the end portion of the semiconductor chip 10, and the sealing resin body 60 is formed on the outer side thereof. Therefore, the pn junction 13 exposed on the side surface of the end is protected from intrusion of moisture and impurity atoms by the insulating protective film 50, and the dielectric breakdown is prevented.
  • the thermal fatigue life is a period until the function of the power semiconductor device 100 is lost when the power semiconductor device 100 is repeatedly exposed to a high temperature environment and a low temperature environment, and is often estimated based on results of an acceleration test or the like. Is done.
  • the lead electrode body 20 as an anode or a cathode between the p-substrate positive electrode element and the p-substrate negative electrode element, there is no significant difference in the function as a rectifier diode.
  • the n-type impurity diffusion layer 12 is bonded to the base electrode body 30 side or the lead electrode body 20 side, there is a difference in thermal fatigue life between the two.
  • the thermal fatigue life differs is that the position of the pn junction 13 in the semiconductor chip 10 is different between the p-substrate positive electrode element and the p-substrate negative electrode element.
  • the pn junction 13 is formed at a position close to the base electrode body 30 as shown in FIG. 2A.
  • the pn junction 13 is formed at a position close to the lead electrode body 20 as shown in FIG. 2B.
  • the position where the pn junction 13 is formed in the semiconductor chip 10 is closer to the lead electrode body 20 in the case of the p substrate type negative element than in the case of the p substrate type positive element, in other words, in the upper position. Is done.
  • the insulating protective film 50 formed in contact with the side surface of the end portion of the semiconductor chip 10 is thinner in the upper part (on the lead electrode body 20 side) and lower in the lower part (the base electrode body 30). Side) thicker.
  • the environmental temperature fluctuates repeatedly it is known that peeling and cracking are more likely to occur as the insulating protective film 50 is thinner, and peeling and cracking are less likely to occur as the thickness is thicker (for reasons described later, FIG. 4).
  • the thickness of the insulating protective film 50 at the position of the pn junction 13 of the p substrate type positive element is thicker than the thickness of the insulating protective film 50 at the position of the pn junction 13 of the p substrate type negative element.
  • the p-type positive electrode element is less likely to be peeled off or cracked in the insulating protective film 50.
  • the pn junction part 13 breaks down due to moisture or impurity atoms entering the peeling or cracked part, and the function of the rectifier diode Is lost, it is determined that the life of the power semiconductor device 100 has expired.
  • the thickness of the insulating protective film 50 at the position of the pn junction 13 is greater in the p-substrate type positive element as shown in FIGS. 2A and 2B. Since it is thicker than the substrate-type negative electrode element, it can be seen that peeling and cracking are less likely to occur and the thermal fatigue life is prolonged. Therefore, in this embodiment, it is assumed that the p substrate type negative electrode element as shown in FIG. 2B is not used and the p substrate type positive electrode element as shown in FIG. 2A is used.
  • a silicon wafer doped with p-type impurities such as phosphorus
  • p-type impurities such as phosphorus
  • a high-concentration p-type impurity diffusion layer 12a p + layer
  • p-type impurities such as boron
  • the n-type semiconductor layer 11 refers to a portion where a high-concentration p-type impurity is not diffused in the n-type semiconductor substrate.
  • the main surface on the n-type semiconductor layer 11 side (the main surface opposite to the main surface on which the p-type impurity diffusion layer 12a is formed) has adhesion between the n-type semiconductor layer 11a and the metal layer.
  • n-type impurities are diffused at a high concentration, and a high-concentration n-type impurity diffusion layer (n + layer) is formed.
  • the high-concentration n-type impurity diffusion layer (n + layer) is also referred to as an n-type semiconductor layer 11a.
  • the structure of the semiconductor chip 10a as described above is substantially the same as the structure of the semiconductor chip 10 shown in FIGS. 2A and 2B in which p and n are interchanged. Therefore, the description of FIGS. 2A and 2B can be applied to FIGS. 2C and 2D only by replacing p and n, positive and negative, and positive and negative in the explanatory text. Description of FIG. 2D is omitted.
  • the thickness of the insulating protective film 50 at the position of the pn junction 13 is larger in the case of the n-substrate type negative electrode element. It is thicker than in the case of an n-substrate type positive electrode element. Therefore, in the case of the n-substrate type negative electrode element, the insulating protective film 50 is less likely to be peeled off or cracked, so that the thermal fatigue life is longer. Therefore, in this embodiment, the n-substrate type positive electrode element as shown in FIG. 2C is not used, and the n-substrate type negative electrode element as shown in FIG. 2D is used.
  • FIG. 3A is a diagram showing an example of the structure of a p-type positive electrode semiconductor chip 10 used in the power semiconductor device 100 according to the present embodiment and the peripheral portion thereof, and FIG. 3B is used for the power semiconductor device 100 according to the present embodiment. It is the figure which showed the example of the structure of the semiconductor chip 10a of an n board
  • a p-substrate type positive element as shown in FIG. 3A is used, and when the semiconductor chip 10a is configured with an n-type semiconductor substrate.
  • an n-substrate negative electrode element as shown in FIG. 3B.
  • FIGS. 2A and 2D are the same as FIGS. 2A and 2D, respectively, but in both cases, the position of the pn junction 13 is higher than the main surface of the semiconductor chips 10 and 10a on the lead electrode body 20 side. It should be noted that it is close to the main surface on the base electrode pair 30 side.
  • FIG. 4 is a diagram for explaining the relationship between the thickness of the insulating protective film 50 formed on the side surface of the end portion of the semiconductor chip 10 and the shear stress or the thermal fatigue life.
  • peeling and cracking are more likely to occur as the insulating protective film 50 is thinner, and peeling and cracking are less likely to occur as the thickness is thicker. It is shown that the thermal fatigue life becomes longer when is located on the lower side than on the upper side of the semiconductor chip 10.
  • the semiconductor chip 10 and the lead electrode body 20 are It will be in the state mounted on 30 (refer FIG. 1).
  • a liquid polyimide resin is applied to the outer peripheral portions of the bonding materials 40 and 41 and the semiconductor chip 10 and cured to form the insulating protective film 50.
  • the liquid polyimide resin has a considerable viscosity, but when applied, it hangs down due to gravity. Therefore, the thickness of the insulating protective film 50 formed by curing the polyimide resin gradually increases from the top to the bottom.
  • the positions represented by the circled circles 1 to 5 are respectively the position of the upper end portion of the semiconductor chip 10 (circled circle 1) and the pn junction formed on the upper side of the semiconductor chip 10. 13 (circled circle 2), the position of the central portion of the semiconductor chip 10 (circled circle 3), the position of the pn junction 13 formed on the lower side of the semiconductor chip 10 (circled circle 4), the lower end of the semiconductor chip 10
  • the thickness of the insulating protective film 50 is the thinnest at the position of the circle 1 and gradually becomes thicker at the positions of the circle 2, the circle 3, and the circle 4. It is thickest at position 5.
  • the shear stress ⁇ generated in the insulating protective film 50 due to the difference in linear expansion coefficient between the semiconductor chip 10 and the sealing resin body 60 causes the insulating protective film 50 on the sealing resin body 60 side in the high temperature environment and the low temperature environment.
  • the displacement amount is represented by ⁇ 1
  • the displacement amount of the insulating protective film 50 on the semiconductor chip 10 side is represented by ⁇ 2
  • the thickness of the insulating protective film 50 is represented by ⁇ .
  • the shear stress ⁇ increases as the thickness ⁇ of the insulating protective film 50 decreases, the high temperature environment and the low temperature environment are repeated with respect to the power semiconductor device 100, that is, the semiconductor chip 10 and the sealing resin body 60.
  • the insulating protective film 50 is more likely to be peeled off or cracked as it is thinner.
  • peeling or cracking is most likely to occur at the upper end portion (the position of the circle 1) of the semiconductor chip 10, and peeling or Cracks are less likely to occur. That is, peeling and cracking of the insulating protective film 50 first occurs near the upper end (position of the circled circle 1) of the semiconductor chip 10, and the peeling and cracking often take a form that gradually spreads downward.
  • the rectifying function of the semiconductor chip 10 is lost immediately and does not cause a failure.
  • the peeling or cracking of the insulating protective film 50 reaches the position where the pn junction 13 is in contact (the position of the circled circle 2 or the circled circle 4), from which moisture or impurity atoms enter the pn junction 13 and the pn junction is formed.
  • the rectifying function of the semiconductor chip 10 is lost and a failure occurs.
  • the pn junction portion 13 is formed at the position of the circled circle 2, the pn junction is broken down and the rectifying function of the semiconductor chip 10 is lost when it is formed at the position of the circled circle 4. It can be said that the period until failure, that is, the thermal fatigue life becomes longer. That is, when the semiconductor chip 10 is formed of a p-type semiconductor substrate (see FIGS. 2A and 2B), the p-substrate positive element has a longer thermal fatigue life than the p-substrate negative element, and the semiconductor chip When 10a is formed of an n-type semiconductor substrate (see FIGS. 2C and 2D), it can be seen that the n-substrate negative electrode element has a longer thermal fatigue life than the n-substrate positive electrode element.
  • FIG. 5 is a diagram showing the relationship between the position in the thickness direction from the upper end in the semiconductor chip 10 and the shear stress and thermal fatigue life generated in the insulating protective film 50 at the position in the thickness direction.
  • the horizontal axis of the graph on the right represents the relative value of the shear stress generated in the insulating protective film 50
  • the vertical axis represents the position in the thickness direction from the upper end (position of the circled circle 1) of the semiconductor chip 10. This is expressed as a relative ratio to the thickness of the entire semiconductor chip 10.
  • the relative value of the shear stress refers to the shear stress received by the insulating protective film 50 at each position when the shear stress received by the insulating protective film 50 at the upper end of the semiconductor chip 10 (the position of the circled circle 1) is 100. Is the relative value of.
  • the cross-sectional structure diagram of the insulating protective film 50 shown on the left side of FIG. 5 schematically shows the relationship between the thickness of the insulating protective film 50 and the position in the thickness direction in the semiconductor chip 10.
  • the pn junction 13 is formed on the upper side (the position of the circled circle 2), and the formation position is about 10% to 35% of the entire thickness.
  • the relative value of the shear stress is about 32 to 40.
  • the pn junction portion 13 is formed on the lower side (the position of the circled circle 4) and the formation position is about 65% to 90% of the total thickness, the relative value of the shear stress is It is about 27-30.
  • the thermal fatigue life of the power semiconductor device 100 is such that the pn junction 13 is formed on the lower side (the position of the circled circle 4), and the formation position is about 65% to 90% of the total thickness. , About 100 to 90 (relative value).
  • the pn junction portion 13 is formed on the upper side (position of the circled circle 2) and the formation position is a position of about 10% to 35% of the total thickness, the thermal fatigue life is 30 to 50%. (Relative value).
  • the pn junction part 13 is provided on the lower side of the semiconductor chip 10 (position of 65% to 90% of the semiconductor chip thickness), the lower side (position of 10% to 35% of the semiconductor chip thickness).
  • the life until peeling is reached, that is, the thermal fatigue life of the power semiconductor device 100 is improved by 2 to 3 times.
  • FIG. 6 is a graph showing the relationship between the minimum film thickness of the insulating protective film 50 and the shear adhesive strength between the silicon-insulating protective film 50
  • FIG. 7 shows the minimum film thickness of the insulating protective film 50 and the power semiconductor device 100. It is the graph which showed the relationship with a thermal fatigue life.
  • the horizontal axis of the graph in FIG. 6 represents the relative value (logarithmic scale) of the minimum film thickness of the insulating protective film 50
  • the vertical axis of the graph represents the relative value of the shear adhesive strength between the silicon and the insulating protective film 50.
  • the horizontal axis of the graph in FIG. 7 represents the relative value (logarithmic scale) of the minimum film thickness of the insulating protective film 50
  • the vertical axis of the graph represents the thermal fatigue life of the power semiconductor device 100.
  • the minimum film thickness of the insulating protective film 50 means the thickness of the insulating protective film 50 at the upper end (position of the circled circle 1) of the semiconductor chip 10.
  • the minimum film thickness of the insulating protective film 50, the shear adhesive strength between the silicon and the insulating protective film 50 (strength when the insulating protective film 50 is peeled off from the semiconductor chip 10), and the thermal fatigue of the power semiconductor device 100 It can be seen that there is a strong correlation with the lifetime.
  • the relative value of the minimum film thickness of the insulating protective film 50 when the relative value of the minimum film thickness of the insulating protective film 50 is 100%, the relative value of the thermal fatigue life of the power semiconductor device 100 is 100%, but the minimum film thickness is 10%. When it becomes 1 / (relative value is 10), the relative value of thermal fatigue life falls to about 80%. When the minimum film thickness is 1/100 (relative value is 1%), the relative value of the thermal fatigue life is reduced to about 10%.
  • FIG. 8 is a diagram showing an example of the configuration of the power supply device 200 that supplies the alternating current generated by the rotary generator 80 by direct current conversion by the rectifier 70.
  • the power supply device 200 includes a rotary generator 80, a rectifier 70, a regulator 90, a battery 92, and the like.
  • a so-called alternator mounted on a vehicle such as an engine-driven passenger car often has a configuration similar to that of the power supply device 200.
  • the rotary generator 80 includes a stator coil 81 and a rotor coil 82, and the rotor coil 82 is driven and rotated by a vehicle engine or the like.
  • a current flows through the rotor coil 82, for example, a three-phase alternating current is generated by the stator coil 81.
  • the rectifier 70 rectifies the alternating current generated by the stator coil 81, supplies the direct current to the electric load 93 such as in the vehicle, and charges the battery 92 with the surplus current.
  • upper potential side diode elements 72, 73, 74 belonging to the upper potential side diode element group 71 are connected in series to lower potential side diode elements 76, 77, 78 belonging to the lower potential side diode element group 75, respectively. Configured.
  • the sets (72, 76), (73, 77) and (74, 78) of the upper and lower diode elements connected in series constitute a so-called diode bridge circuit via the stator coil 81. To do.
  • a p-substrate type positive electrode element in which the substrate of the semiconductor chip 10 is made of the p-type semiconductor layer 11 is used as the higher-potential-side diode elements 72, 73, and 74.
  • the lower potential side diode elements 76, 77, 78 n substrate type negative electrode elements (see FIG. 3B) in which the substrate of the semiconductor chip 10a is formed of the n type semiconductor layer 11a are used.
  • the series connection circuit of the upper potential side diode element 72 and the lower potential side diode element 76 is obtained by connecting the lead electrode body 20 of the p substrate type positive electrode element and the lead electrode body 20 of the n substrate type negative electrode element. Realized. A series connection circuit of the upper potential side diode element 73 and the lower potential side diode element 77 and a series connection circuit of the upper potential side diode element 74 and the lower potential side diode element 78 are also realized in the same manner.
  • each set of the lead electrode bodies 20 includes three stators. Connected to each of the coils 81. Furthermore, the base electrode bodies 30 of the n-substrate type negative electrode elements are collectively grounded, and the base electrode bodies 30 of the p-substrate type positive electrode elements are collectively connected to the electric load 93.
  • the rectifying device 70 configured as described above uses a p-substrate positive electrode element and an n-substrate negative electrode element having a structure capable of improving the thermal fatigue life.
  • the fatigue life can also be improved.
  • the upper potential side diode elements 72, 73, 74 are aligned with the p substrate type positive element, and the lower potential side diode elements 76, 77, 78 are aligned with the n substrate type negative element. . Therefore, the rectifying device 70 has stabilized rectifying characteristics, improved operational reliability, and can reduce variations in the thermal fatigue life of the rectifying device 70.
  • the power supply device 200 including the rectifying device 70 can also have a long thermal fatigue life and can reduce variations. Furthermore, since the rectification characteristics and reliability of the rectifier 70 are improved, the stability and reliability of the operation of the power supply apparatus 200 can be improved.
  • the stator coil 81 generates a three-phase alternating current, but may generate a two-phase alternating current or a six-phase alternating current.
  • the rectifier 70 is provided with two or six series connection circuits of upper-potential-side diode elements and lower-potential-side diode elements, and these constitute a diode bridge circuit.
  • FIG. 9A is a diagram schematically showing an example of the structure of a power semiconductor device 100b configured using a planar semiconductor chip 10b
  • FIG. 9B shows the structure of the semiconductor chip 10b and its peripheral portion in the power semiconductor device 100b. It is the figure which showed the example. 9A is almost the same as the structure of the semiconductor chip 10 shown in FIG. 1 except that the semiconductor chip 10b is not a mesa type but a planar type as shown in FIG. 9B. The same. Therefore, hereinafter, in the description of FIGS. 9A and 9B, the same components as those in FIG. 1 are denoted by the same reference numerals, overlapping description will be omitted, and only different portions will be described.
  • a region B surrounded by a broken-line rectangle is an enlarged view of the structure of the region B surrounded by the broken line in the power semiconductor device 100b shown in FIG. 9A.
  • the pn junction 13 is not exposed on the side surface of the end of the semiconductor chip 10b, but on the p type or n type semiconductor substrate. On the other hand, it is exposed to the same main surface as the main surface (in FIG. 9B, the lower main surface of the semiconductor chip 10b) subjected to vapor phase diffusion of n-type or p-type impurities.
  • An insulating film 14 such as silicon oxide is formed on the surface of the pn junction 13 exposed on the main surface during the manufacturing process of the semiconductor chip 10b. Accordingly, the pn junction 13 is protected by the insulating film 14.
  • the insulating protective film 50 relieves the thermal stress generated in the semiconductor chip 10b, and the gap between the semiconductor chip 10b and the sealing resin body 60 in which the solder of the bonding materials 40 and 41 is plastically flowed. It is formed for the purpose of suppressing intrusion.
  • p board type positive electrode elements or n board type negative electrode elements as shown in Drawing 3A and Drawing 3B shall be used as semiconductor chip 10b which constitutes power semiconductor device 100b.
  • the pn junction 13 is located at a position close to the main surface facing the base electrode body 30, and the n-type or p-type high-concentration impurity diffusion layer 12b is The semiconductor chip 10b is exposed on the lower main surface.
  • an insulating film 14 is formed on the peripheral portion of the main surface, and the pn junction 13 exposed on the main surface is also covered with the insulating film 14.
  • the n-type or p-type high-concentration impurity diffusion layer 12b of the semiconductor chip 10b is bonded to the base electrode body 30 by a bonding material 41 such as solder. At this time, since the bonding material 41 does not adhere to the portion of the semiconductor chip 10b where the insulating film 14 is formed, a bowl-shaped cavity is formed between the semiconductor chip 10b and the base electrode body 30. . Thereafter, an insulating protective film 50 is formed in the cavity.
  • the insulating protective film 50 even if the insulating protective film 50 is peeled or cracked due to thermal fatigue and the bonding material 40 on the upper part of the semiconductor chip 10b reaches the lower part of the semiconductor chip 10b due to plastic flow or the like, the insulating protective film 50 on that part of the insulating chip 50b. If it does not peel off, it will not reach the lower bonding material 41.
  • the n-type or p-type high-concentration impurity diffusion layer 12b is exposed on the upper main surface of the semiconductor chip 10b (that is, n as shown in FIGS. 2B and 2C).
  • the insulating protective film 50 due to long-term thermal fatigue
  • the upper bonding material 40 reaches the lower bonding material 41 due to plastic flow or the like
  • the bowl-shaped cavity is formed. Since it is not formed, the upper bonding material 40 and the lower bonding material 41 are likely to be short-circuited.
  • the thermal fatigue life can be improved by using the p substrate type positive electrode element or the n substrate type negative electrode element as the semiconductor chip 10b constituting the power semiconductor device 100b.
  • p substrate type positive elements are used as the upper potential side diode elements 72, 73, 74, and n substrate type negative elements are used as the lower potential side diode elements 76, 77, 78.
  • a pn junction diode is formed by forming an n-type or p-type high-concentration impurity diffusion layer on a p-type or n-type semiconductor substrate.
  • a Schottky diode has a Schottky barrier on a p-type or n-type semiconductor substrate. The metal which has is joined. A junction between the semiconductor substrate and the metal having a Schottky barrier is called a Schottky junction and corresponds to the pn junction 13 in the description of the above embodiment.
  • the n-type or p-type high-concentration impurity diffusion layers 12, 12a, 12b are read as a metal having a Schottky barrier, and the pn junction 13 is In other words, the description can be applied to the Schottky diode in almost the same manner.
  • examples of the metal having a Schottky barrier with respect to the n-type semiconductor substrate include Al, Au, W, and Pt.
  • examples of the metal having a Schottky barrier with respect to the p-type semiconductor substrate include In and Zn.
  • the present invention is not limited to the embodiment described above, and includes various modifications.
  • the above embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to the one having all the configurations described.
  • a part of the configuration of an embodiment can be replaced with a part of the configuration of another embodiment, and further, a part or all of the configuration of the other embodiment is added to the configuration of the certain embodiment. Is also possible.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Rectifiers (AREA)
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Abstract

L'invention concerne un dispositif semi-conducteur de puissance qui est configuré à l'aide d'une puce de semi-conducteur (10) d'un élément d'électrode positive de substrat-p ou d'un élément d'électrode négative de substrat-n, mais dans le cas d'une puce de semi-conducteur (10) d'un élément d'électrode positive de substrat-p, la surface primaire de la puce de semi-conducteur (10), sur le côté plus proche d'une jonction p-n (13), est jointe à la surface supérieure d'un corps d'électrode de base (30) avec un matériau de jonction (41) entre celles-ci, et un corps d'électrode principal (20) est joint à la surface de l'autre surface primaire de la puce de semi-conducteur (10) avec un matériau de jonction (40) entre ceux-ci. De plus, un film protecteur isolant (50) est formé sur les surfaces latérales d'extrémité de la puce de semi-conducteur (10), et en outre, un corps en résine de scellement (60) est formé sur l'extérieur de celle-ci.
PCT/JP2013/083109 2012-12-11 2013-12-10 Dispositif semi-conducteur de puissance, dispositif redresseur, et dispositif de source d'alimentation WO2014092089A1 (fr)

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