WO2014092089A1 - Power semiconductor device, rectifier device, and power source device - Google Patents

Power semiconductor device, rectifier device, and power source device Download PDF

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Publication number
WO2014092089A1
WO2014092089A1 PCT/JP2013/083109 JP2013083109W WO2014092089A1 WO 2014092089 A1 WO2014092089 A1 WO 2014092089A1 JP 2013083109 W JP2013083109 W JP 2013083109W WO 2014092089 A1 WO2014092089 A1 WO 2014092089A1
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Prior art keywords
semiconductor chip
main surface
semiconductor device
layer
type
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PCT/JP2013/083109
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French (fr)
Japanese (ja)
Inventor
智弘 恩田
耕一 石川
翼 武田
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株式会社 日立パワーデバイス
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Publication of WO2014092089A1 publication Critical patent/WO2014092089A1/en

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    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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Definitions

  • the present invention relates to a power semiconductor device used in the field of power electronics, and a rectifier and a power supply device using the power semiconductor device.
  • An alternator mounted on a vehicle such as a passenger car uses a rectifier (AC-DC converter) that uses a power semiconductor device (such as a rectifier diode) to convert the alternating current generated by a generator rotated by the power of the engine into direct current. Convert to current.
  • AC-DC converter rectifier
  • a power semiconductor device such as a rectifier diode
  • a power semiconductor device for a vehicle is used for a long time in a harsh temperature environment, and a high-temperature environment and a low-temperature (room temperature) environment are repeated. Impact is a big problem. In particular, improving the thermal fatigue life of a bonding layer (such as a solder bonding layer) between electronic members and the peeling life of an insulating protective film that insulates and protects a semiconductor chip have become practical issues.
  • a bonding layer such as a solder bonding layer
  • a power semiconductor device such as a rectifier diode has a structure in which a semiconductor chip having a rectifying function is sandwiched and held between a base electrode and a lead electrode. Bonded with bonding material.
  • a semiconductor chip and each electrode are bonded with a bonding material via a thermal relaxation body whose linear expansion coefficient has an intermediate value between the linear expansion coefficient of each electrode and that of the semiconductor chip.
  • Patent Document 2 discloses a power semiconductor device having a structure in which a mesa-type semiconductor chip is sandwiched between a base electrode and a lead electrode and bonded to each electrode via a bonding material such as solder.
  • the sealing resin having a value within a specific range in which the linear expansion coefficient includes the linear expansion coefficient of the base electrode in the middle is used as the sealing resin for sealing the heat semiconductor device, the thermal fatigue life of the power semiconductor device is reduced. It has been shown to improve.
  • Patent Document 2 shows that in many cases, peeling or cracking is observed in the sealing resin when the appearance of a test object having a short life in a thermal fatigue life test of a power semiconductor device is inspected.
  • peeling or cracking occurs in the sealing resin, it is considered that moisture or impurity atoms enter from there and peel off the bonding layer such as solder or short-circuit the pn junction in the semiconductor chip.
  • the bonding layer such as solder or short-circuit the pn junction in the semiconductor chip.
  • a mesa type is used as a semiconductor chip, a pn junction is exposed on the side surface of the end of the semiconductor chip, so that moisture or solder metal atoms enter the part. Then, dielectric breakdown occurs at the pn junction.
  • an insulating protective film is further formed between the side surface of the end portion of the semiconductor chip and the sealing resin.
  • the sealing resin is peeled off or cracked, the pn junction portion of the semiconductor chip is protected by the insulating protective film, so that the function as the power semiconductor device is not lost immediately.
  • the insulation protective film is peeled off after that, the dielectric breakdown of the pn junction portion is reached and the function as a power semiconductor device is lost.
  • the relation between the peeling of the insulating protective film and the thermal fatigue life has not been sufficiently considered.
  • an object of the present invention is to provide a power semiconductor device capable of improving the thermal fatigue life, and a rectifier and a DC power supply device using the power semiconductor device. .
  • a power semiconductor device includes a semiconductor chip in which a second conductive type impurity diffusion layer is formed on a first main surface of a semiconductor substrate made of a first conductive type semiconductor layer, and a flat holding surface on the top. And holding the semiconductor chip with the first main surface facing down on the holding surface, and the impurity diffusion layer of the second conductivity type formed on the first main surface is conductive.
  • a base electrode body bonded to the holding surface via a bonding material and a first conductive type semiconductor layer constituting a second main surface that is a main surface opposite to the first main surface are electrically conductive
  • a boundary between the first conductive type semiconductor layer and the second conductive type impurity diffusion layer The pn junction portion to be formed is formed at a position closer to the first main surface than the second main surface, and insulation is provided between the peripheral portion of the semiconductor chip and the sealing resin body.
  • a protective film is formed.
  • the rectifier according to the present invention includes a diode bridge circuit formed by combining a plurality of series connection circuits of upper potential side diode elements and lower potential side diode elements, and the upper potential side diode element is a p substrate.
  • a positive electrode element is used, and an n-substrate negative electrode element is used as the lower potential side diode element.
  • the p-substrate type positive electrode element in the power semiconductor device is such that the first conductivity type semiconductor layer is a p-type semiconductor layer and the second conductivity type impurity diffusion layer is an n-type impurity diffusion layer.
  • the n-substrate type negative electrode element in the power semiconductor device is such that the first conductivity type semiconductor layer is an n-type semiconductor layer and the second conductivity type impurity diffusion layer is a p-type impurity diffusion layer.
  • the power supply device is characterized by including a rotary generator and the rectifier.
  • the present invention it is possible to provide a power semiconductor device having an improved thermal fatigue life, and a rectifier and a DC power supply device using the power semiconductor device.
  • FIG. 1 is a diagram schematically showing an example of the structure of a power semiconductor device 100 according to an embodiment of the present invention.
  • the left half of the center line shown in FIG. 1 is a front view of the appearance of the power semiconductor device 100, and the right half of the figure schematically shows the cross-sectional structure of the power semiconductor device 100.
  • FIG. 1 is a diagram schematically showing an example of the structure of a power semiconductor device 100 according to an embodiment of the present invention.
  • the left half of the center line shown in FIG. 1 is a front view of the appearance of the power semiconductor device 100
  • the right half of the figure schematically shows the cross-sectional structure of the power semiconductor device 100.
  • a semiconductor chip 10 having a rectifying function is sandwiched between a lead electrode body 20 and a base electrode body 30 made of a good conductor such as copper, and solder or the like. Are joined via the joining materials 40 and 41.
  • the semiconductor chip 10 is a mesa rectifier diode.
  • the base electrode body 30 is a basic structure of the power semiconductor device 100, and a pedestal portion 31 on which the semiconductor chip 10 is mounted and a groove portion 32 surrounding the pedestal portion 31 are formed on the upper surface portion thereof.
  • the upper surface of the pedestal portion 31 is a flat surface, and one main surface of the semiconductor chip 10 is bonded to the flat surface via a bonding material 41. Further, the lead electrode body 20 is bonded to the other main surface of the semiconductor chip 10 via a bonding material 40.
  • the sealing resin body 60 is formed of an epoxy resin or the like, seals the semiconductor chip 10 sandwiched between the base electrode body 30 and the lead electrode body 20, and also connects the lead electrode body 20 to the base electrode body 30. It plays the role of fixing. That is, the side wall of the groove portion 32 of the base electrode body 30 on the side of the pedestal portion 31 is formed so that the pedestal portion 31 overhangs, and the epoxy resin is cured after being poured into the groove portion 32.
  • the stop resin body 60 has a structure that does not come off the base electrode body 30.
  • a relatively soft thin film made of a polyimide resin or the like is formed between the peripheral edge of the semiconductor chip 10 and between the bonding materials 40 and 41 and the sealing resin body 60.
  • An insulating protective film 50 is formed. The insulating protective film 50 prevents the pn junction exposed on the side surface of the end portion of the mesa-type semiconductor chip 10 from intrusion of moisture and impurity atoms, and thermal stress generated between the semiconductor chip 10 and the sealing resin body 60. Plays a role in mitigating.
  • FIG. 2A is a diagram showing an example of the structure of the semiconductor chip 10 and its peripheral portion in the power semiconductor device 100 using the p substrate type positive element as the semiconductor chip 10
  • FIG. 2B shows the p substrate type negative element
  • FIG. 2C is a diagram showing an example of the structure of the semiconductor chip 10 and its peripheral portion in the power semiconductor device 100 used as the semiconductor chip 10
  • FIG. 2D is a diagram illustrating an example of the structure of the semiconductor chip 10a and its peripheral portion, and FIG.
  • FIG. 2D is a diagram illustrating an example of the structure of the semiconductor chip 10a and the peripheral portion thereof in the power semiconductor device 100 using the n-substrate negative electrode element as the semiconductor chip 10a. It is. Note that the semiconductor chip 10 and the peripheral edge thereof in the power semiconductor device 100 refer to a portion corresponding to a region A indicated by a broken-line rectangle in FIG. Each of FIGS. 2A to 2D is attached with a diagram showing a vertical structure of the semiconductor chips 10 and 10a, particularly in order to clarify the position of the pn junction portion 13.
  • the positive electrode element is a rectifier diode (power semiconductor device 100) using the lead electrode body 20 of the power semiconductor device 100 as an anode (anode) and the base electrode pair 30 as a cathode (cathode).
  • the negative electrode element refers to a rectifier diode (power semiconductor device 100) that uses the lead electrode body 20 of the power semiconductor device 100 as a cathode (cathode) and the base electrode body 30 as an anode (anode).
  • the names of the p substrate type and the n substrate type are based on the conductivity types of the substrates of the semiconductor chips 10 and 10a used in each rectifier diode (power semiconductor device 100).
  • n-type impurity diffusion layer 12 (n + layer).
  • the p-type semiconductor layer 11 refers to a portion where a high-concentration n-type impurity is not diffused in the p-type semiconductor substrate.
  • the main surface on the p-type semiconductor layer 11 side (the main surface opposite to the main surface on which the n-type impurity diffusion layer 12 is formed) has adhesion between the p-type semiconductor layer 11 and the metal layer.
  • p-type impurities are diffused at a high concentration, and a high-concentration p-type impurity diffusion layer (p + layer) is formed.
  • this high-concentration p-type impurity diffusion layer (p + layer) is also referred to as a p-type semiconductor layer 11.
  • a pn junction 13 is formed at the boundary between the p-type semiconductor layer 11 and the n-type impurity diffusion layer 12 inside the semiconductor chip 10 as described above.
  • the position of the pn junction 13, in other words, the diffusion depth of the n-type impurity diffusion layer 12 is appropriately about 10 to 35% of the entire thickness of the semiconductor chip 10.
  • the position of the pn junction 13 in such a range is a result of considering the reverse breakdown voltage required for the semiconductor chip 10 as a rectifier diode, the impurity concentration of the p-type semiconductor layer 11 and the n-type impurity diffusion layer 12, and the like. It was obtained based on.
  • nickel or nickel is formed on the outside of the high-concentration n-type impurity diffusion layer 12 (n + layer) and the outside of the high-concentration p-type impurity diffusion layer (p + layer) of the semiconductor chip 10, for example.
  • a metal layer made of an alloy or the like is formed (not shown). Therefore, the n-type impurity diffusion layer 12 (n + layer) and the p-type semiconductor layer 11 are electrically connected to the lead electrode body 20 or the base electrode body 30 by bonding the metal layer to the bonding materials 40 and 41. Connected.
  • the lead electrode body 20 is used as an anode (anode)
  • the n type impurity diffusion layer 12 is It arrange
  • the lead electrode body 20 is used as a cathode (cathode). Therefore, when the semiconductor chip 10 is formed of a p-type semiconductor substrate, the n-type impurity diffusion layer 12 is used. Is disposed on the upper surface side and is bonded to the bonding material 40 on the lead electrode body 20 side.
  • the insulating protective film 50 is formed on the side surface of the end portion of the semiconductor chip 10, and the sealing resin body 60 is formed on the outer side thereof. Therefore, the pn junction 13 exposed on the side surface of the end is protected from intrusion of moisture and impurity atoms by the insulating protective film 50, and the dielectric breakdown is prevented.
  • the thermal fatigue life is a period until the function of the power semiconductor device 100 is lost when the power semiconductor device 100 is repeatedly exposed to a high temperature environment and a low temperature environment, and is often estimated based on results of an acceleration test or the like. Is done.
  • the lead electrode body 20 as an anode or a cathode between the p-substrate positive electrode element and the p-substrate negative electrode element, there is no significant difference in the function as a rectifier diode.
  • the n-type impurity diffusion layer 12 is bonded to the base electrode body 30 side or the lead electrode body 20 side, there is a difference in thermal fatigue life between the two.
  • the thermal fatigue life differs is that the position of the pn junction 13 in the semiconductor chip 10 is different between the p-substrate positive electrode element and the p-substrate negative electrode element.
  • the pn junction 13 is formed at a position close to the base electrode body 30 as shown in FIG. 2A.
  • the pn junction 13 is formed at a position close to the lead electrode body 20 as shown in FIG. 2B.
  • the position where the pn junction 13 is formed in the semiconductor chip 10 is closer to the lead electrode body 20 in the case of the p substrate type negative element than in the case of the p substrate type positive element, in other words, in the upper position. Is done.
  • the insulating protective film 50 formed in contact with the side surface of the end portion of the semiconductor chip 10 is thinner in the upper part (on the lead electrode body 20 side) and lower in the lower part (the base electrode body 30). Side) thicker.
  • the environmental temperature fluctuates repeatedly it is known that peeling and cracking are more likely to occur as the insulating protective film 50 is thinner, and peeling and cracking are less likely to occur as the thickness is thicker (for reasons described later, FIG. 4).
  • the thickness of the insulating protective film 50 at the position of the pn junction 13 of the p substrate type positive element is thicker than the thickness of the insulating protective film 50 at the position of the pn junction 13 of the p substrate type negative element.
  • the p-type positive electrode element is less likely to be peeled off or cracked in the insulating protective film 50.
  • the pn junction part 13 breaks down due to moisture or impurity atoms entering the peeling or cracked part, and the function of the rectifier diode Is lost, it is determined that the life of the power semiconductor device 100 has expired.
  • the thickness of the insulating protective film 50 at the position of the pn junction 13 is greater in the p-substrate type positive element as shown in FIGS. 2A and 2B. Since it is thicker than the substrate-type negative electrode element, it can be seen that peeling and cracking are less likely to occur and the thermal fatigue life is prolonged. Therefore, in this embodiment, it is assumed that the p substrate type negative electrode element as shown in FIG. 2B is not used and the p substrate type positive electrode element as shown in FIG. 2A is used.
  • a silicon wafer doped with p-type impurities such as phosphorus
  • p-type impurities such as phosphorus
  • a high-concentration p-type impurity diffusion layer 12a p + layer
  • p-type impurities such as boron
  • the n-type semiconductor layer 11 refers to a portion where a high-concentration p-type impurity is not diffused in the n-type semiconductor substrate.
  • the main surface on the n-type semiconductor layer 11 side (the main surface opposite to the main surface on which the p-type impurity diffusion layer 12a is formed) has adhesion between the n-type semiconductor layer 11a and the metal layer.
  • n-type impurities are diffused at a high concentration, and a high-concentration n-type impurity diffusion layer (n + layer) is formed.
  • the high-concentration n-type impurity diffusion layer (n + layer) is also referred to as an n-type semiconductor layer 11a.
  • the structure of the semiconductor chip 10a as described above is substantially the same as the structure of the semiconductor chip 10 shown in FIGS. 2A and 2B in which p and n are interchanged. Therefore, the description of FIGS. 2A and 2B can be applied to FIGS. 2C and 2D only by replacing p and n, positive and negative, and positive and negative in the explanatory text. Description of FIG. 2D is omitted.
  • the thickness of the insulating protective film 50 at the position of the pn junction 13 is larger in the case of the n-substrate type negative electrode element. It is thicker than in the case of an n-substrate type positive electrode element. Therefore, in the case of the n-substrate type negative electrode element, the insulating protective film 50 is less likely to be peeled off or cracked, so that the thermal fatigue life is longer. Therefore, in this embodiment, the n-substrate type positive electrode element as shown in FIG. 2C is not used, and the n-substrate type negative electrode element as shown in FIG. 2D is used.
  • FIG. 3A is a diagram showing an example of the structure of a p-type positive electrode semiconductor chip 10 used in the power semiconductor device 100 according to the present embodiment and the peripheral portion thereof, and FIG. 3B is used for the power semiconductor device 100 according to the present embodiment. It is the figure which showed the example of the structure of the semiconductor chip 10a of an n board
  • a p-substrate type positive element as shown in FIG. 3A is used, and when the semiconductor chip 10a is configured with an n-type semiconductor substrate.
  • an n-substrate negative electrode element as shown in FIG. 3B.
  • FIGS. 2A and 2D are the same as FIGS. 2A and 2D, respectively, but in both cases, the position of the pn junction 13 is higher than the main surface of the semiconductor chips 10 and 10a on the lead electrode body 20 side. It should be noted that it is close to the main surface on the base electrode pair 30 side.
  • FIG. 4 is a diagram for explaining the relationship between the thickness of the insulating protective film 50 formed on the side surface of the end portion of the semiconductor chip 10 and the shear stress or the thermal fatigue life.
  • peeling and cracking are more likely to occur as the insulating protective film 50 is thinner, and peeling and cracking are less likely to occur as the thickness is thicker. It is shown that the thermal fatigue life becomes longer when is located on the lower side than on the upper side of the semiconductor chip 10.
  • the semiconductor chip 10 and the lead electrode body 20 are It will be in the state mounted on 30 (refer FIG. 1).
  • a liquid polyimide resin is applied to the outer peripheral portions of the bonding materials 40 and 41 and the semiconductor chip 10 and cured to form the insulating protective film 50.
  • the liquid polyimide resin has a considerable viscosity, but when applied, it hangs down due to gravity. Therefore, the thickness of the insulating protective film 50 formed by curing the polyimide resin gradually increases from the top to the bottom.
  • the positions represented by the circled circles 1 to 5 are respectively the position of the upper end portion of the semiconductor chip 10 (circled circle 1) and the pn junction formed on the upper side of the semiconductor chip 10. 13 (circled circle 2), the position of the central portion of the semiconductor chip 10 (circled circle 3), the position of the pn junction 13 formed on the lower side of the semiconductor chip 10 (circled circle 4), the lower end of the semiconductor chip 10
  • the thickness of the insulating protective film 50 is the thinnest at the position of the circle 1 and gradually becomes thicker at the positions of the circle 2, the circle 3, and the circle 4. It is thickest at position 5.
  • the shear stress ⁇ generated in the insulating protective film 50 due to the difference in linear expansion coefficient between the semiconductor chip 10 and the sealing resin body 60 causes the insulating protective film 50 on the sealing resin body 60 side in the high temperature environment and the low temperature environment.
  • the displacement amount is represented by ⁇ 1
  • the displacement amount of the insulating protective film 50 on the semiconductor chip 10 side is represented by ⁇ 2
  • the thickness of the insulating protective film 50 is represented by ⁇ .
  • the shear stress ⁇ increases as the thickness ⁇ of the insulating protective film 50 decreases, the high temperature environment and the low temperature environment are repeated with respect to the power semiconductor device 100, that is, the semiconductor chip 10 and the sealing resin body 60.
  • the insulating protective film 50 is more likely to be peeled off or cracked as it is thinner.
  • peeling or cracking is most likely to occur at the upper end portion (the position of the circle 1) of the semiconductor chip 10, and peeling or Cracks are less likely to occur. That is, peeling and cracking of the insulating protective film 50 first occurs near the upper end (position of the circled circle 1) of the semiconductor chip 10, and the peeling and cracking often take a form that gradually spreads downward.
  • the rectifying function of the semiconductor chip 10 is lost immediately and does not cause a failure.
  • the peeling or cracking of the insulating protective film 50 reaches the position where the pn junction 13 is in contact (the position of the circled circle 2 or the circled circle 4), from which moisture or impurity atoms enter the pn junction 13 and the pn junction is formed.
  • the rectifying function of the semiconductor chip 10 is lost and a failure occurs.
  • the pn junction portion 13 is formed at the position of the circled circle 2, the pn junction is broken down and the rectifying function of the semiconductor chip 10 is lost when it is formed at the position of the circled circle 4. It can be said that the period until failure, that is, the thermal fatigue life becomes longer. That is, when the semiconductor chip 10 is formed of a p-type semiconductor substrate (see FIGS. 2A and 2B), the p-substrate positive element has a longer thermal fatigue life than the p-substrate negative element, and the semiconductor chip When 10a is formed of an n-type semiconductor substrate (see FIGS. 2C and 2D), it can be seen that the n-substrate negative electrode element has a longer thermal fatigue life than the n-substrate positive electrode element.
  • FIG. 5 is a diagram showing the relationship between the position in the thickness direction from the upper end in the semiconductor chip 10 and the shear stress and thermal fatigue life generated in the insulating protective film 50 at the position in the thickness direction.
  • the horizontal axis of the graph on the right represents the relative value of the shear stress generated in the insulating protective film 50
  • the vertical axis represents the position in the thickness direction from the upper end (position of the circled circle 1) of the semiconductor chip 10. This is expressed as a relative ratio to the thickness of the entire semiconductor chip 10.
  • the relative value of the shear stress refers to the shear stress received by the insulating protective film 50 at each position when the shear stress received by the insulating protective film 50 at the upper end of the semiconductor chip 10 (the position of the circled circle 1) is 100. Is the relative value of.
  • the cross-sectional structure diagram of the insulating protective film 50 shown on the left side of FIG. 5 schematically shows the relationship between the thickness of the insulating protective film 50 and the position in the thickness direction in the semiconductor chip 10.
  • the pn junction 13 is formed on the upper side (the position of the circled circle 2), and the formation position is about 10% to 35% of the entire thickness.
  • the relative value of the shear stress is about 32 to 40.
  • the pn junction portion 13 is formed on the lower side (the position of the circled circle 4) and the formation position is about 65% to 90% of the total thickness, the relative value of the shear stress is It is about 27-30.
  • the thermal fatigue life of the power semiconductor device 100 is such that the pn junction 13 is formed on the lower side (the position of the circled circle 4), and the formation position is about 65% to 90% of the total thickness. , About 100 to 90 (relative value).
  • the pn junction portion 13 is formed on the upper side (position of the circled circle 2) and the formation position is a position of about 10% to 35% of the total thickness, the thermal fatigue life is 30 to 50%. (Relative value).
  • the pn junction part 13 is provided on the lower side of the semiconductor chip 10 (position of 65% to 90% of the semiconductor chip thickness), the lower side (position of 10% to 35% of the semiconductor chip thickness).
  • the life until peeling is reached, that is, the thermal fatigue life of the power semiconductor device 100 is improved by 2 to 3 times.
  • FIG. 6 is a graph showing the relationship between the minimum film thickness of the insulating protective film 50 and the shear adhesive strength between the silicon-insulating protective film 50
  • FIG. 7 shows the minimum film thickness of the insulating protective film 50 and the power semiconductor device 100. It is the graph which showed the relationship with a thermal fatigue life.
  • the horizontal axis of the graph in FIG. 6 represents the relative value (logarithmic scale) of the minimum film thickness of the insulating protective film 50
  • the vertical axis of the graph represents the relative value of the shear adhesive strength between the silicon and the insulating protective film 50.
  • the horizontal axis of the graph in FIG. 7 represents the relative value (logarithmic scale) of the minimum film thickness of the insulating protective film 50
  • the vertical axis of the graph represents the thermal fatigue life of the power semiconductor device 100.
  • the minimum film thickness of the insulating protective film 50 means the thickness of the insulating protective film 50 at the upper end (position of the circled circle 1) of the semiconductor chip 10.
  • the minimum film thickness of the insulating protective film 50, the shear adhesive strength between the silicon and the insulating protective film 50 (strength when the insulating protective film 50 is peeled off from the semiconductor chip 10), and the thermal fatigue of the power semiconductor device 100 It can be seen that there is a strong correlation with the lifetime.
  • the relative value of the minimum film thickness of the insulating protective film 50 when the relative value of the minimum film thickness of the insulating protective film 50 is 100%, the relative value of the thermal fatigue life of the power semiconductor device 100 is 100%, but the minimum film thickness is 10%. When it becomes 1 / (relative value is 10), the relative value of thermal fatigue life falls to about 80%. When the minimum film thickness is 1/100 (relative value is 1%), the relative value of the thermal fatigue life is reduced to about 10%.
  • FIG. 8 is a diagram showing an example of the configuration of the power supply device 200 that supplies the alternating current generated by the rotary generator 80 by direct current conversion by the rectifier 70.
  • the power supply device 200 includes a rotary generator 80, a rectifier 70, a regulator 90, a battery 92, and the like.
  • a so-called alternator mounted on a vehicle such as an engine-driven passenger car often has a configuration similar to that of the power supply device 200.
  • the rotary generator 80 includes a stator coil 81 and a rotor coil 82, and the rotor coil 82 is driven and rotated by a vehicle engine or the like.
  • a current flows through the rotor coil 82, for example, a three-phase alternating current is generated by the stator coil 81.
  • the rectifier 70 rectifies the alternating current generated by the stator coil 81, supplies the direct current to the electric load 93 such as in the vehicle, and charges the battery 92 with the surplus current.
  • upper potential side diode elements 72, 73, 74 belonging to the upper potential side diode element group 71 are connected in series to lower potential side diode elements 76, 77, 78 belonging to the lower potential side diode element group 75, respectively. Configured.
  • the sets (72, 76), (73, 77) and (74, 78) of the upper and lower diode elements connected in series constitute a so-called diode bridge circuit via the stator coil 81. To do.
  • a p-substrate type positive electrode element in which the substrate of the semiconductor chip 10 is made of the p-type semiconductor layer 11 is used as the higher-potential-side diode elements 72, 73, and 74.
  • the lower potential side diode elements 76, 77, 78 n substrate type negative electrode elements (see FIG. 3B) in which the substrate of the semiconductor chip 10a is formed of the n type semiconductor layer 11a are used.
  • the series connection circuit of the upper potential side diode element 72 and the lower potential side diode element 76 is obtained by connecting the lead electrode body 20 of the p substrate type positive electrode element and the lead electrode body 20 of the n substrate type negative electrode element. Realized. A series connection circuit of the upper potential side diode element 73 and the lower potential side diode element 77 and a series connection circuit of the upper potential side diode element 74 and the lower potential side diode element 78 are also realized in the same manner.
  • each set of the lead electrode bodies 20 includes three stators. Connected to each of the coils 81. Furthermore, the base electrode bodies 30 of the n-substrate type negative electrode elements are collectively grounded, and the base electrode bodies 30 of the p-substrate type positive electrode elements are collectively connected to the electric load 93.
  • the rectifying device 70 configured as described above uses a p-substrate positive electrode element and an n-substrate negative electrode element having a structure capable of improving the thermal fatigue life.
  • the fatigue life can also be improved.
  • the upper potential side diode elements 72, 73, 74 are aligned with the p substrate type positive element, and the lower potential side diode elements 76, 77, 78 are aligned with the n substrate type negative element. . Therefore, the rectifying device 70 has stabilized rectifying characteristics, improved operational reliability, and can reduce variations in the thermal fatigue life of the rectifying device 70.
  • the power supply device 200 including the rectifying device 70 can also have a long thermal fatigue life and can reduce variations. Furthermore, since the rectification characteristics and reliability of the rectifier 70 are improved, the stability and reliability of the operation of the power supply apparatus 200 can be improved.
  • the stator coil 81 generates a three-phase alternating current, but may generate a two-phase alternating current or a six-phase alternating current.
  • the rectifier 70 is provided with two or six series connection circuits of upper-potential-side diode elements and lower-potential-side diode elements, and these constitute a diode bridge circuit.
  • FIG. 9A is a diagram schematically showing an example of the structure of a power semiconductor device 100b configured using a planar semiconductor chip 10b
  • FIG. 9B shows the structure of the semiconductor chip 10b and its peripheral portion in the power semiconductor device 100b. It is the figure which showed the example. 9A is almost the same as the structure of the semiconductor chip 10 shown in FIG. 1 except that the semiconductor chip 10b is not a mesa type but a planar type as shown in FIG. 9B. The same. Therefore, hereinafter, in the description of FIGS. 9A and 9B, the same components as those in FIG. 1 are denoted by the same reference numerals, overlapping description will be omitted, and only different portions will be described.
  • a region B surrounded by a broken-line rectangle is an enlarged view of the structure of the region B surrounded by the broken line in the power semiconductor device 100b shown in FIG. 9A.
  • the pn junction 13 is not exposed on the side surface of the end of the semiconductor chip 10b, but on the p type or n type semiconductor substrate. On the other hand, it is exposed to the same main surface as the main surface (in FIG. 9B, the lower main surface of the semiconductor chip 10b) subjected to vapor phase diffusion of n-type or p-type impurities.
  • An insulating film 14 such as silicon oxide is formed on the surface of the pn junction 13 exposed on the main surface during the manufacturing process of the semiconductor chip 10b. Accordingly, the pn junction 13 is protected by the insulating film 14.
  • the insulating protective film 50 relieves the thermal stress generated in the semiconductor chip 10b, and the gap between the semiconductor chip 10b and the sealing resin body 60 in which the solder of the bonding materials 40 and 41 is plastically flowed. It is formed for the purpose of suppressing intrusion.
  • p board type positive electrode elements or n board type negative electrode elements as shown in Drawing 3A and Drawing 3B shall be used as semiconductor chip 10b which constitutes power semiconductor device 100b.
  • the pn junction 13 is located at a position close to the main surface facing the base electrode body 30, and the n-type or p-type high-concentration impurity diffusion layer 12b is The semiconductor chip 10b is exposed on the lower main surface.
  • an insulating film 14 is formed on the peripheral portion of the main surface, and the pn junction 13 exposed on the main surface is also covered with the insulating film 14.
  • the n-type or p-type high-concentration impurity diffusion layer 12b of the semiconductor chip 10b is bonded to the base electrode body 30 by a bonding material 41 such as solder. At this time, since the bonding material 41 does not adhere to the portion of the semiconductor chip 10b where the insulating film 14 is formed, a bowl-shaped cavity is formed between the semiconductor chip 10b and the base electrode body 30. . Thereafter, an insulating protective film 50 is formed in the cavity.
  • the insulating protective film 50 even if the insulating protective film 50 is peeled or cracked due to thermal fatigue and the bonding material 40 on the upper part of the semiconductor chip 10b reaches the lower part of the semiconductor chip 10b due to plastic flow or the like, the insulating protective film 50 on that part of the insulating chip 50b. If it does not peel off, it will not reach the lower bonding material 41.
  • the n-type or p-type high-concentration impurity diffusion layer 12b is exposed on the upper main surface of the semiconductor chip 10b (that is, n as shown in FIGS. 2B and 2C).
  • the insulating protective film 50 due to long-term thermal fatigue
  • the upper bonding material 40 reaches the lower bonding material 41 due to plastic flow or the like
  • the bowl-shaped cavity is formed. Since it is not formed, the upper bonding material 40 and the lower bonding material 41 are likely to be short-circuited.
  • the thermal fatigue life can be improved by using the p substrate type positive electrode element or the n substrate type negative electrode element as the semiconductor chip 10b constituting the power semiconductor device 100b.
  • p substrate type positive elements are used as the upper potential side diode elements 72, 73, 74, and n substrate type negative elements are used as the lower potential side diode elements 76, 77, 78.
  • a pn junction diode is formed by forming an n-type or p-type high-concentration impurity diffusion layer on a p-type or n-type semiconductor substrate.
  • a Schottky diode has a Schottky barrier on a p-type or n-type semiconductor substrate. The metal which has is joined. A junction between the semiconductor substrate and the metal having a Schottky barrier is called a Schottky junction and corresponds to the pn junction 13 in the description of the above embodiment.
  • the n-type or p-type high-concentration impurity diffusion layers 12, 12a, 12b are read as a metal having a Schottky barrier, and the pn junction 13 is In other words, the description can be applied to the Schottky diode in almost the same manner.
  • examples of the metal having a Schottky barrier with respect to the n-type semiconductor substrate include Al, Au, W, and Pt.
  • examples of the metal having a Schottky barrier with respect to the p-type semiconductor substrate include In and Zn.
  • the present invention is not limited to the embodiment described above, and includes various modifications.
  • the above embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to the one having all the configurations described.
  • a part of the configuration of an embodiment can be replaced with a part of the configuration of another embodiment, and further, a part or all of the configuration of the other embodiment is added to the configuration of the certain embodiment. Is also possible.

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Abstract

This power semiconductor device is configured using a semiconductor chip (10) of a p-substrate positive electrode element or an n-substrate negative electrode element, but in the case of a semiconductor chip (10) of a p-substrate positive electrode element, the primary surface of the semiconductor chip (10), at the side closer to a p-n junction (13) is joined to the top surface of a base electrode body (30) with a joining material (41) therebetween, and a lead electrode body (20) is joined to the top of the other primary surface of the semiconductor chip (10) with a joining material (40) therebetween. Also, an insulating protective film (50) is formed at the end lateral surfaces of the semiconductor chip (10), and furthermore, a sealing resin body (60) is formed to the outside thereof.

Description

パワー半導体装置、整流装置および電源装置Power semiconductor device, rectifier device and power supply device
　本発明は、パワーエレクトロニクス分野で用いられるパワー半導体装置、ならびに、そのパワー半導体装置を用いた整流装置および電源装置に関する。 The present invention relates to a power semiconductor device used in the field of power electronics, and a rectifier and a power supply device using the power semiconductor device.
　乗用車などの車両に搭載されているオルタネータは、エンジンの力で回転させた発電機で発電した交流電流を、パワー半導体装置（整流ダイオードなど）を用いた整流装置（交流－直流変換装置）により直流電流に変換する。このような車両用のパワー半導体装置に対しては、近年のカーエレクトロニクスの発展やアイドリングストップ車の普及に伴い、大電流化、高耐熱化、高信頼化などの要求が強まってきている。 An alternator mounted on a vehicle such as a passenger car uses a rectifier (AC-DC converter) that uses a power semiconductor device (such as a rectifier diode) to convert the alternating current generated by a generator rotated by the power of the engine into direct current. Convert to current. With respect to such power semiconductor devices for vehicles, demands for higher current, higher heat resistance, higher reliability, and the like have increased with the recent development of car electronics and the spread of idling stop vehicles.
　車両用のパワー半導体装置は、過酷な温度環境下で長時間用いられ、しかも、高温環境と低温（常温）環境が繰り返されることから、その環境下で受ける熱ストレスや熱疲労が素子寿命に及ぼす影響が大きな問題となっている。とくに、電子部材同士の接合層（はんだ接合層など）の熱疲労寿命や半導体チップを絶縁保護する絶縁保護膜の剥離寿命を向上させることが現実の具体的な課題となっている。 A power semiconductor device for a vehicle is used for a long time in a harsh temperature environment, and a high-temperature environment and a low-temperature (room temperature) environment are repeated. Impact is a big problem. In particular, improving the thermal fatigue life of a bonding layer (such as a solder bonding layer) between electronic members and the peeling life of an insulating protective film that insulates and protects a semiconductor chip have become practical issues.
　一般に、整流ダイオードなどのパワー半導体装置は、整流機能を有する半導体チップがベース電極とリード電極との間に挟まれて保持される構造をしており、半導体チップとそれぞれの電極は、ハンダなどの接合材で接合される。特許文献１には、線膨張係数が各電極の線膨張係数と半導体チップの線膨張係数の中間の値を有するような熱緩和体を介して、半導体チップとそれぞれの電極とを接合材で接合することにより、接合層の熱疲労寿命を向上させる技術が開示されている。 In general, a power semiconductor device such as a rectifier diode has a structure in which a semiconductor chip having a rectifying function is sandwiched and held between a base electrode and a lead electrode. Bonded with bonding material. In Patent Document 1, a semiconductor chip and each electrode are bonded with a bonding material via a thermal relaxation body whose linear expansion coefficient has an intermediate value between the linear expansion coefficient of each electrode and that of the semiconductor chip. Thus, a technique for improving the thermal fatigue life of the bonding layer is disclosed.
　また、特許文献２には、メサ型の半導体チップがベース電極とリード電極とに挟まれ、ハンダなどの接合材を介してそれぞれの電極に接合された構造を有するパワー半導体装置において、その半導体チップを封止する封止樹脂として、線膨張係数がベース電極の線膨張係数をその中間に含む特定の範囲の値を有する封止樹脂を使用した場合には、当該パワー半導体装置の熱疲労寿命が向上することが示されている。 Patent Document 2 discloses a power semiconductor device having a structure in which a mesa-type semiconductor chip is sandwiched between a base electrode and a lead electrode and bonded to each electrode via a bonding material such as solder. When the sealing resin having a value within a specific range in which the linear expansion coefficient includes the linear expansion coefficient of the base electrode in the middle is used as the sealing resin for sealing the heat semiconductor device, the thermal fatigue life of the power semiconductor device is reduced. It has been shown to improve.
特開２００８－０４２０８４号公報JP 2008-042084 A 特開２０１０－１９９３６９号公報JP 2010-199369 A
　特許文献２には、パワー半導体装置の熱疲労寿命試験で寿命が短かった被試験体について外観を検査すると、多くの場合、封止樹脂に剥離や亀裂が観察されることが示されている。一般に、封止樹脂に剥離や亀裂が生じた場合、そこから水分や不純物原子が侵入し、ハンダなどの接合層を剥離させたり、半導体チップ内のｐｎ接合部を短絡させたりすることが考えられる。とくに、特許文献２の例の場合、半導体チップとしてメサ型が用いられているため、半導体チップの端部側面にｐｎ接合部が露出しているので、その部分に水分やハンダの金属原子が侵入すると、ｐｎ接合部に絶縁破壊が生じる。 Patent Document 2 shows that in many cases, peeling or cracking is observed in the sealing resin when the appearance of a test object having a short life in a thermal fatigue life test of a power semiconductor device is inspected. In general, when peeling or cracking occurs in the sealing resin, it is considered that moisture or impurity atoms enter from there and peel off the bonding layer such as solder or short-circuit the pn junction in the semiconductor chip. . In particular, in the case of the example of Patent Document 2, since a mesa type is used as a semiconductor chip, a pn junction is exposed on the side surface of the end of the semiconductor chip, so that moisture or solder metal atoms enter the part. Then, dielectric breakdown occurs at the pn junction.
　そこで、一般には、また、特許文献２にも記載されているように、半導体チップの端部側面と封止樹脂との間には、絶縁保護膜がさらに形成されている。その場合には、封止樹脂の剥離や亀裂が生じても、半導体チップのｐｎ接合部は、絶縁保護膜で保護されるので、パワー半導体装置としての機能が直ちに失われることはない。しかしながら、その後、絶縁保護膜にも剥離が生じた場合には、ｐｎ接合部の絶縁破壊に到り、パワー半導体装置としての機能も失われる。従来は、このような絶縁保護膜の剥離と熱疲労寿命との関係については、十分には考慮されていなかった。 Therefore, generally, as described in Patent Document 2, an insulating protective film is further formed between the side surface of the end portion of the semiconductor chip and the sealing resin. In that case, even if the sealing resin is peeled off or cracked, the pn junction portion of the semiconductor chip is protected by the insulating protective film, so that the function as the power semiconductor device is not lost immediately. However, if the insulation protective film is peeled off after that, the dielectric breakdown of the pn junction portion is reached and the function as a power semiconductor device is lost. Conventionally, the relation between the peeling of the insulating protective film and the thermal fatigue life has not been sufficiently considered.
　以上の従来技術の現状に鑑み、本発明の目的は、熱疲労寿命を向上させることが可能なパワー半導体装置、ならびに、そのパワー半導体装置を用いた整流装置および直流電源装置を提供することにある。 In view of the above-described state of the prior art, an object of the present invention is to provide a power semiconductor device capable of improving the thermal fatigue life, and a rectifier and a DC power supply device using the power semiconductor device. .
課題を解決しようとする手段Means to solve the problem
　本発明に係るパワー半導体装置は、第１導電型の半導体層からなる半導体基板の第１の主面に第２導電型の不純物拡散層が形成された半導体チップと、上部に平坦な保持面を有し、前記第１の主面を下に向けた前記半導体チップを前記保持面上に保持するとともに、前記第１の主面に形成された前記第２導電型の不純物拡散層が導電性の接合材を介して前記保持面に接合されるベース電極体と、前記第１の主面の反対側の主面である第２の主面を構成する前記第１導電型の半導体層に、導電性の接合材を介して接合されるリード電極体と、前記ベース電極体と前記リード電極体との間に挟まれた前記半導体チップを封止する封止樹脂体と、を備え、前記半導体チップ内の前記第１導電型の半導体層と前記第２導電型の不純物拡散層との境界に形成されるｐｎ接合部は、前記第２の主面よりも前記第１の主面に近い位置に形成されており、前記半導体チップの周縁部と前記封止樹脂体との間には、絶縁保護膜が形成されていることを特徴とする。 A power semiconductor device according to the present invention includes a semiconductor chip in which a second conductive type impurity diffusion layer is formed on a first main surface of a semiconductor substrate made of a first conductive type semiconductor layer, and a flat holding surface on the top. And holding the semiconductor chip with the first main surface facing down on the holding surface, and the impurity diffusion layer of the second conductivity type formed on the first main surface is conductive. A base electrode body bonded to the holding surface via a bonding material and a first conductive type semiconductor layer constituting a second main surface that is a main surface opposite to the first main surface are electrically conductive A lead electrode body bonded via a conductive bonding material, and a sealing resin body for sealing the semiconductor chip sandwiched between the base electrode body and the lead electrode body, A boundary between the first conductive type semiconductor layer and the second conductive type impurity diffusion layer The pn junction portion to be formed is formed at a position closer to the first main surface than the second main surface, and insulation is provided between the peripheral portion of the semiconductor chip and the sealing resin body. A protective film is formed.
　また、本発明に係る整流装置は、上位電位側ダイオード素子および下位電位側ダイオード素子の直列接続回路が複数個組み合わされてなるダイオードブリッジ回路含んで構成され、前記上位電位側ダイオード素子として、ｐ基板型正極素子を用い、前記下位電位側ダイオード素子として、ｎ基板型負極素子を用いてなることを特徴とする。
　ここで、ｐ基板型正極素子とは、前記パワー半導体装置において、前記第１導電型の半導体層がｐ型半導体層で、前記第２導電型の不純物拡散層がｎ型不純物拡散層であるものをいい、ｎ基板型負極素子とは、前記パワー半導体装置において、前記第１導電型の半導体層がｎ型半導体層で、前記第２導電型の不純物拡散層がｐ型不純物拡散層であるものをいう。 The rectifier according to the present invention includes a diode bridge circuit formed by combining a plurality of series connection circuits of upper potential side diode elements and lower potential side diode elements, and the upper potential side diode element is a p substrate. A positive electrode element is used, and an n-substrate negative electrode element is used as the lower potential side diode element.
Here, the p-substrate type positive electrode element in the power semiconductor device is such that the first conductivity type semiconductor layer is a p-type semiconductor layer and the second conductivity type impurity diffusion layer is an n-type impurity diffusion layer. The n-substrate type negative electrode element in the power semiconductor device is such that the first conductivity type semiconductor layer is an n-type semiconductor layer and the second conductivity type impurity diffusion layer is a p-type impurity diffusion layer. Say.
　また、本発明に係る電源装置は、回転発電機と、前記の整流装置と、を含んでなることを特徴とする。 Moreover, the power supply device according to the present invention is characterized by including a rotary generator and the rectifier.
　本発明によれば、熱疲労寿命が向上したパワー半導体装置、ならびに、そのパワー半導体装置を用いた整流装置および直流電源装置を提供することができる。 According to the present invention, it is possible to provide a power semiconductor device having an improved thermal fatigue life, and a rectifier and a DC power supply device using the power semiconductor device.
本発明の実施形態に係るパワー半導体装置の構造の例を示した図である。It is the figure which showed the example of the structure of the power semiconductor device which concerns on embodiment of this invention. ｐ基板型正極素子を半導体チップとして用いたパワー半導体装置における半導体チップおよびその周縁部の構造の例を示した図である。It is the figure which showed the example of the structure of the semiconductor chip and its peripheral part in the power semiconductor device which used the p board | substrate type | mold positive electrode element as a semiconductor chip. ｐ基板型負極素子を半導体チップとして用いたパワー半導体装置における半導体チップおよびその周縁部の構造の例を示した図である。It is the figure which showed the example of the structure of the semiconductor chip and its peripheral part in the power semiconductor device which used the p board | substrate type negative electrode element as a semiconductor chip. ｎ基板型正極素子を半導体チップとして用いたパワー半導体装置における半導体チップおよびその周縁部の構造の例を示した図である。It is the figure which showed the example of the structure of the semiconductor chip and its peripheral part in the power semiconductor device which used the n board | substrate type positive electrode element as a semiconductor chip. ｎ基板型負極素子を半導体チップとして用いたパワー半導体装置における半導体チップおよびその周縁部の構造の例を示した図である。It is the figure which showed the example of the structure of the semiconductor chip in the power semiconductor device which used the n board | substrate type negative electrode element as a semiconductor chip, and its peripheral part. 本発明の実施形態におけるパワー半導体装置に用いるｐ基板型正極素子の半導体チップおよびその周縁部の構造の例を示した図である。It is the figure which showed the example of the structure of the semiconductor chip of the p board | substrate type | mold positive electrode element used for the power semiconductor device in embodiment of this invention, and its peripheral part. 本発明の実施形態におけるパワー半導体装置に用いるｎ基板型負極素子の半導体チップおよびその周縁部の構造の例を示した図である。It is the figure which showed the example of the structure of the semiconductor chip of the n board | substrate type negative electrode element used for the power semiconductor device in embodiment of this invention, and its peripheral part. 半導体チップ端部側面に形成される絶縁保護膜の厚みと剪断応力または熱疲労寿命との関係を説明するための図である。It is a figure for demonstrating the relationship between the thickness of the insulating protective film formed in a semiconductor chip edge part side surface, and a shear stress or a thermal fatigue life. 半導体チップ内における上端部からの厚み方向位置と、その厚み方向位置における絶縁保護膜に生じる剪断応力および熱疲労寿命の関係を示した図である。It is the figure which showed the relationship of the shear stress and thermal fatigue life which arise in the thickness direction position from the upper end part in a semiconductor chip, and the insulation protective film in the thickness direction position. 絶縁保護膜の最小膜厚とシリコン－絶縁保護膜間の剪断接着強度との関係を示したグラフである。5 is a graph showing the relationship between the minimum thickness of an insulating protective film and the shear adhesive strength between the silicon and the insulating protective film. 絶縁保護膜の最小膜厚とパワー半導体装置の熱疲労寿命との関係を示したグラフである。It is the graph which showed the relationship between the minimum film thickness of an insulating protective film, and the thermal fatigue life of a power semiconductor device. 回転発電機で発電する交流電流を整流装置で直流変換して供給する電源装置の構成の例を示した図である。It is the figure which showed the example of the structure of the power supply device which supplies the alternating current generated with a rotary generator by direct-current-converting with a rectifier. プレーナ型の半導体チップを用いて構成したパワー半導体装置の構造の例を模式的に示した図である。It is the figure which showed typically the example of the structure of the power semiconductor device comprised using the planar type semiconductor chip. 図９Ａに示したパワー半導体装置における半導体チップおよびその周縁部の構造の例を示した図である。It is the figure which showed the example of the structure of the semiconductor chip and its peripheral part in the power semiconductor device shown to FIG. 9A.
　以下、本発明の実施形態について、図面を参照して詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　図１は、本発明の実施形態に係るパワー半導体装置１００の構造の例を模式的に示した図である。ここで、図１に示した中心線より左半分の図は、パワー半導体装置１００の外観の正面図を示した図であり、右半分の図は、パワー半導体装置１００の断面構造を模式的に示した図である。 FIG. 1 is a diagram schematically showing an example of the structure of a power semiconductor device 100 according to an embodiment of the present invention. Here, the left half of the center line shown in FIG. 1 is a front view of the appearance of the power semiconductor device 100, and the right half of the figure schematically shows the cross-sectional structure of the power semiconductor device 100. FIG.
　図１に示すように、本実施形態に係るパワー半導体装置１００は、整流機能を有する半導体チップ１０が、銅などの良導体からなるリード電極体２０およびベース電極体３０のそれぞれに挟まれ、ハンダなどの接合材４０，４１を介して接合されて構成される。ここで、半導体チップ１０は、メサ型の整流ダイオードであるとする。 As shown in FIG. 1, in the power semiconductor device 100 according to the present embodiment, a semiconductor chip 10 having a rectifying function is sandwiched between a lead electrode body 20 and a base electrode body 30 made of a good conductor such as copper, and solder or the like. Are joined via the joining materials 40 and 41. Here, it is assumed that the semiconductor chip 10 is a mesa rectifier diode.
　ベース電極体３０は、パワー半導体装置１００の基礎構造体であり、その上面部には、半導体チップ１０を搭載する台座部３１と、その台座部３１を取り囲む溝部３２が形成されている。台座部３１の上面は平坦面であり、その平坦面には接合材４１を介して半導体チップ１０の一方の主面が接合される。さらに、半導体チップ１０の他方の主面には、接合材４０を介してリード電極体２０が接合される。 The base electrode body 30 is a basic structure of the power semiconductor device 100, and a pedestal portion 31 on which the semiconductor chip 10 is mounted and a groove portion 32 surrounding the pedestal portion 31 are formed on the upper surface portion thereof. The upper surface of the pedestal portion 31 is a flat surface, and one main surface of the semiconductor chip 10 is bonded to the flat surface via a bonding material 41. Further, the lead electrode body 20 is bonded to the other main surface of the semiconductor chip 10 via a bonding material 40.
　また、封止樹脂体６０は、エポキシ系樹脂などによって形成され、ベース電極体３０とリード電極体２０とに挟まれた半導体チップ１０を封止するとともに、リード電極体２０をベース電極体３０に固定する役割を果たす。すなわち、ベース電極体３０の溝部３２の台座部３１側の側壁は、台座部３１がオーバハングするように形成されており、エポキシ系樹脂は、溝部３２にも流し込まれた後に硬化されるので、封止樹脂体６０は、ベース電極体３０から抜けない構造となる。 The sealing resin body 60 is formed of an epoxy resin or the like, seals the semiconductor chip 10 sandwiched between the base electrode body 30 and the lead electrode body 20, and also connects the lead electrode body 20 to the base electrode body 30. It plays the role of fixing. That is, the side wall of the groove portion 32 of the base electrode body 30 on the side of the pedestal portion 31 is formed so that the pedestal portion 31 overhangs, and the epoxy resin is cured after being poured into the groove portion 32. The stop resin body 60 has a structure that does not come off the base electrode body 30.
　また、封止樹脂体６０が形成される前には、半導体チップ１０の周縁端部および接合材４０，４１と封止樹脂体６０との間には、ポリイミド系樹脂などからなる比較的軟らかい薄膜状の絶縁保護膜５０が形成される。絶縁保護膜５０は、メサ型の半導体チップ１０の端部側面に露出するｐｎ接合部を水分や不純物原子の浸入から防止するとともに、半導体チップ１０と封止樹脂体６０との間に生じる熱応力を緩和する役割を果たす。 Further, before the sealing resin body 60 is formed, a relatively soft thin film made of a polyimide resin or the like is formed between the peripheral edge of the semiconductor chip 10 and between the bonding materials 40 and 41 and the sealing resin body 60. An insulating protective film 50 is formed. The insulating protective film 50 prevents the pn junction exposed on the side surface of the end portion of the mesa-type semiconductor chip 10 from intrusion of moisture and impurity atoms, and thermal stress generated between the semiconductor chip 10 and the sealing resin body 60. Plays a role in mitigating.
　次に、図２Ａ～図２Ｄを参照して、半導体チップ１０，１０ａにおける半導体基板の導電型および不純物拡散層の配置の相違に基づくパワー半導体装置１００の分類の例について説明する。
　ここで、図２Ａは、ｐ基板型正極素子を半導体チップ１０として用いたパワー半導体装置１００における半導体チップ１０およびその周縁部の構造の例を示した図、図２Ｂは、ｐ基板型負極素子を半導体チップ１０として用いたパワー半導体装置１００における半導体チップ１０およびその周縁部の構造の例を示した図、図２Ｃは、ｎ基板型正極素子を半導体チップ１０ａとして用いたパワー半導体装置１００における半導体チップ１０ａおよびその周縁部の構造の例を示した図、図２Ｄは、ｎ基板型負極素子を半導体チップ１０ａとして用いたパワー半導体装置１００における半導体チップ１０ａおよびその周縁部の構造の例を示した図である。なお、パワー半導体装置１００における半導体チップ１０およびその周縁部とは、図１の中に破線の長方形で示された領域Ａに対応する部分をいう。また、図２Ａ～図２Ｄのそれぞれには、とくにｐｎ接合部１３の位置を明確化する意味で、半導体チップ１０，１０ａの縦構造を示す図が付されている。 Next, an example of classification of the power semiconductor device 100 based on the difference in the conductivity type of the semiconductor substrate and the arrangement of the impurity diffusion layers in the semiconductor chips 10 and 10a will be described with reference to FIGS. 2A to 2D.
Here, FIG. 2A is a diagram showing an example of the structure of the semiconductor chip 10 and its peripheral portion in the power semiconductor device 100 using the p substrate type positive element as the semiconductor chip 10, and FIG. 2B shows the p substrate type negative element. FIG. 2C is a diagram showing an example of the structure of the semiconductor chip 10 and its peripheral portion in the power semiconductor device 100 used as the semiconductor chip 10, and FIG. FIG. 2D is a diagram illustrating an example of the structure of the semiconductor chip 10a and its peripheral portion, and FIG. 2D is a diagram illustrating an example of the structure of the semiconductor chip 10a and the peripheral portion thereof in the power semiconductor device 100 using the n-substrate negative electrode element as the semiconductor chip 10a. It is. Note that the semiconductor chip 10 and the peripheral edge thereof in the power semiconductor device 100 refer to a portion corresponding to a region A indicated by a broken-line rectangle in FIG. Each of FIGS. 2A to 2D is attached with a diagram showing a vertical structure of the semiconductor chips 10 and 10a, particularly in order to clarify the position of the pn junction portion 13.
　以上の図２Ａ～図２Ｄにおいて、正極素子とは、パワー半導体装置１００のリード電極体２０をアノード（陽極）として用い、ベース電極対３０をカソード（陰極）として用いる整流ダイオード（パワー半導体装置１００）をいう。また、負極素子とは、パワー半導体装置１００のリード電極体２０をカソード（陰極）として用い、ベース電極体３０をアノード（陽極）として用いる整流ダイオード（パワー半導体装置１００）をいう。
　また、ｐ基板型およびｎ基板型の呼称は、それぞれの整流ダイオード（パワー半導体装置１００）の中で用いられる半導体チップ１０，１０ａの基板の導電型に基づく。 2A to 2D, the positive electrode element is a rectifier diode (power semiconductor device 100) using the lead electrode body 20 of the power semiconductor device 100 as an anode (anode) and the base electrode pair 30 as a cathode (cathode). Say. The negative electrode element refers to a rectifier diode (power semiconductor device 100) that uses the lead electrode body 20 of the power semiconductor device 100 as a cathode (cathode) and the base electrode body 30 as an anode (anode).
The names of the p substrate type and the n substrate type are based on the conductivity types of the substrates of the semiconductor chips 10 and 10a used in each rectifier diode (power semiconductor device 100).
　図２Ａ、図２Ｂに示すように、半導体チップ１０をｐ型半導体基板で構成する場合には、そのｐ型半導体基板としてｐ型不純物（ボロンなど）がドープされたシリコンウェハを用いる。そして、その一方の主面にｎ型不純物（リン、ヒ素、アンチモンなど）を高濃度に拡散することにより、高濃度のｎ型の不純物拡散層１２（ｎ＋層）を形成する。 As shown in FIGS. 2A and 2B, when the semiconductor chip 10 is formed of a p-type semiconductor substrate, a silicon wafer doped with p-type impurities (such as boron) is used as the p-type semiconductor substrate. Then, an n-type impurity (phosphorus, arsenic, antimony, etc.) is diffused at a high concentration on one main surface thereof, thereby forming a high-concentration n-type impurity diffusion layer 12 (n + layer).
　ここで、ｐ型の半導体層１１とは、ｐ型半導体基板で高濃度のｎ型不純物が拡散されなかった部分をいう。そして、ｐ型の半導体層１１側の主面（ｎ型の不純物拡散層１２が形成された主面と反対側の主面）には、ｐ型の半導体層１１と金属層との接着性を向上させるために、ｐ型不純物が高濃度に拡散され、高濃度のｐ型の不純物拡散層（ｐ＋層）が形成される。本明細書では、この高濃度のｐ型の不純物拡散層（ｐ＋層）も含めて、ｐ型の半導体層１１という。 Here, the p-type semiconductor layer 11 refers to a portion where a high-concentration n-type impurity is not diffused in the p-type semiconductor substrate. The main surface on the p-type semiconductor layer 11 side (the main surface opposite to the main surface on which the n-type impurity diffusion layer 12 is formed) has adhesion between the p-type semiconductor layer 11 and the metal layer. In order to improve, p-type impurities are diffused at a high concentration, and a high-concentration p-type impurity diffusion layer (p + layer) is formed. In this specification, this high-concentration p-type impurity diffusion layer (p + layer) is also referred to as a p-type semiconductor layer 11.
　以上のような半導体チップ１０の内部のｐ型の半導体層１１とｎ型の不純物拡散層１２との境界にはｐｎ接合部１３が形成される。ｐｎ接合部１３の位置、言い換えれば、ｎ型の不純物拡散層１２の拡散の深さは、半導体チップ１０全体の厚みの１０～３５％になる程度が適切である。このような範囲のｐｎ接合部１３の位置は、整流ダイオードとしての半導体チップ１０に求められる逆耐圧電圧や、ｐ型の半導体層１１やｎ型の不純物拡散層１２の不純物濃度などを考慮した結果に基づき得られたものである。 A pn junction 13 is formed at the boundary between the p-type semiconductor layer 11 and the n-type impurity diffusion layer 12 inside the semiconductor chip 10 as described above. The position of the pn junction 13, in other words, the diffusion depth of the n-type impurity diffusion layer 12 is appropriately about 10 to 35% of the entire thickness of the semiconductor chip 10. The position of the pn junction 13 in such a range is a result of considering the reverse breakdown voltage required for the semiconductor chip 10 as a rectifier diode, the impurity concentration of the p-type semiconductor layer 11 and the n-type impurity diffusion layer 12, and the like. It was obtained based on.
　また、半導体チップ１０の高濃度のｎ型の不純物拡散層１２（ｎ＋層）の外側および高濃度のｐ型の不純物拡散層（ｐ＋層）の外側のそれぞれには、例えば、ニッケルやニッケル合金などからなる金属層が形成される（図示省略）。従って、ｎ型の不純物拡散層１２（ｎ＋層）やｐ型の半導体層１１は、その金属層が接合材４０，４１に接合されることにより、リード電極体２０またはベース電極体３０に電気的に接続される。 In addition, for example, nickel or nickel is formed on the outside of the high-concentration n-type impurity diffusion layer 12 (n + layer) and the outside of the high-concentration p-type impurity diffusion layer (p + layer) of the semiconductor chip 10, for example. A metal layer made of an alloy or the like is formed (not shown). Therefore, the n-type impurity diffusion layer 12 (n + layer) and the p-type semiconductor layer 11 are electrically connected to the lead electrode body 20 or the base electrode body 30 by bonding the metal layer to the bonding materials 40 and 41. Connected.
　図２Ａのｐ基板型正極素子では、リード電極体２０がアノード（陽極）として用いられるので、半導体チップ１０がｐ型の半導体基板で構成される場合には、ｎ型の不純物拡散層１２は、下面側に配置されて、ベース電極体３０側の接合材４１に接合される。また、図２Ｂのｐ基板型負極素子では、リード電極体２０がカソード（陰極）として用いられるので、半導体チップ１０がｐ型の半導体基板で構成される場合には、ｎ型の不純物拡散層１２は、上面側に配置されて、リード電極体２０側の接合材４０に接合される。 In the p substrate type positive electrode element of FIG. 2A, since the lead electrode body 20 is used as an anode (anode), when the semiconductor chip 10 is formed of a p type semiconductor substrate, the n type impurity diffusion layer 12 is It arrange | positions at the lower surface side and is joined to the joining material 41 by the side of the base electrode body 30. FIG. 2B, the lead electrode body 20 is used as a cathode (cathode). Therefore, when the semiconductor chip 10 is formed of a p-type semiconductor substrate, the n-type impurity diffusion layer 12 is used. Is disposed on the upper surface side and is bonded to the bonding material 40 on the lead electrode body 20 side.
　そして、そのいずれの場合にも、半導体チップ１０の端部の側面には、絶縁保護膜５０が形成され、さらに、その外側に封止樹脂体６０が形成されている。従って、その端部の側面に露出するｐｎ接合部１３は、その絶縁保護膜５０により水分や不純物原子の侵入から保護され、その絶縁破壊が防止される。 In either case, the insulating protective film 50 is formed on the side surface of the end portion of the semiconductor chip 10, and the sealing resin body 60 is formed on the outer side thereof. Therefore, the pn junction 13 exposed on the side surface of the end is protected from intrusion of moisture and impurity atoms by the insulating protective film 50, and the dielectric breakdown is prevented.
　ここで、ｐ基板型正極素子（図２Ａ参照）とｐ基板型負極素子（図２Ｂ参照）とにおける熱疲労寿命の相違について検討しておく。熱疲労寿命とは、パワー半導体装置１００が高温環境と低温環境とに繰り返し曝された場合に、パワー半導体装置１００の機能が失われるまでの期間をいい、しばしば、加速試験などの結果に基づき推定される。 Here, the difference in the thermal fatigue life between the p-substrate positive electrode element (see FIG. 2A) and the p-substrate negative electrode element (see FIG. 2B) will be examined. The thermal fatigue life is a period until the function of the power semiconductor device 100 is lost when the power semiconductor device 100 is repeatedly exposed to a high temperature environment and a low temperature environment, and is often estimated based on results of an acceleration test or the like. Is done.
　ところで、ｐ基板型正極素子とｐ基板型負極素子とでは、リード電極体２０をアノードとして用いるか、または、カソードとして用いるかの相違があるものの、整流ダイオードとしての機能には大きな相違はない。しかしながら、ｎ型の不純物拡散層１２がベース電極体３０側に接合されるか、または、リード電極体２０側に接合されるかにより、両者の間では、熱疲労寿命に相違が生じる。 Incidentally, although there is a difference between using the lead electrode body 20 as an anode or a cathode between the p-substrate positive electrode element and the p-substrate negative electrode element, there is no significant difference in the function as a rectifier diode. However, depending on whether the n-type impurity diffusion layer 12 is bonded to the base electrode body 30 side or the lead electrode body 20 side, there is a difference in thermal fatigue life between the two.
　熱疲労寿命に相違が生じる理由は、ｐ基板型正極素子とｐ基板型負極素子とでは、半導体チップ１０におけるｐｎ接合部１３の位置が異なることに由来する。ｐ基板型正極素子の場合、図２Ａに示すように、ｐｎ接合部１３は、ベース電極体３０に近い位置に形成される。一方、ｐ基板型正極素子の場合、図２Ｂに示すように、ｐｎ接合部１３は、リード電極体２０に近い位置に形成される。すなわち、半導体チップ１０においてｐｎ接合部１３が形成される位置は、ｐ基板型負極素子の場合のほうがｐ基板型正極素子の場合よりもリード電極体２０に近い位置、言い換えれば、上部位置に形成される。 The reason why the thermal fatigue life differs is that the position of the pn junction 13 in the semiconductor chip 10 is different between the p-substrate positive electrode element and the p-substrate negative electrode element. In the case of a p-substrate positive electrode element, the pn junction 13 is formed at a position close to the base electrode body 30 as shown in FIG. 2A. On the other hand, in the case of a p-substrate positive electrode element, the pn junction 13 is formed at a position close to the lead electrode body 20 as shown in FIG. 2B. That is, the position where the pn junction 13 is formed in the semiconductor chip 10 is closer to the lead electrode body 20 in the case of the p substrate type negative element than in the case of the p substrate type positive element, in other words, in the upper position. Is done.
　また、図２Ａ、図２Ｂに示すように、半導体チップ１０の端部側面に接して形成される絶縁保護膜５０の厚みは、上部（リード電極体２０側）ほど薄く、下部（ベース電極体３０側）ほど厚い。一般に、環境温度が繰り返し変動する場合、絶縁保護膜５０の厚みが薄いほど剥離や亀裂が生じやすく、厚みが厚いほど剥離や亀裂が生じにくいことが知られている（理由については、後で図４を用いて説明する）。すなわち、ｐ基板型正極素子のｐｎ接合部１３位置における絶縁保護膜５０の厚みは、ｐ基板型負極素子のｐｎ接合部１３位置における絶縁保護膜５０の厚みよりも厚いので、ｐｎ接合部１３位置で比較すると、ｐ基板型正極素子のほうが絶縁保護膜５０に剥離や亀裂が生じにくいことが分かる。 As shown in FIGS. 2A and 2B, the insulating protective film 50 formed in contact with the side surface of the end portion of the semiconductor chip 10 is thinner in the upper part (on the lead electrode body 20 side) and lower in the lower part (the base electrode body 30). Side) thicker. Generally, when the environmental temperature fluctuates repeatedly, it is known that peeling and cracking are more likely to occur as the insulating protective film 50 is thinner, and peeling and cracking are less likely to occur as the thickness is thicker (for reasons described later, FIG. 4). That is, the thickness of the insulating protective film 50 at the position of the pn junction 13 of the p substrate type positive element is thicker than the thickness of the insulating protective film 50 at the position of the pn junction 13 of the p substrate type negative element. In comparison, it can be understood that the p-type positive electrode element is less likely to be peeled off or cracked in the insulating protective film 50.
　ｐｎ接合部１３に接する部分の絶縁保護膜５０に剥離や亀裂が生じた場合、その剥離や亀裂部分に水分や不純物原子が侵入することにより、ｐｎ接合部１３が絶縁破壊し、整流ダイオードの機能が失われると、パワー半導体装置１００の寿命が尽きたと判断される。 When peeling or cracking occurs in the insulating protective film 50 in the part in contact with the pn junction part 13, the pn junction part 13 breaks down due to moisture or impurity atoms entering the peeling or cracked part, and the function of the rectifier diode Is lost, it is determined that the life of the power semiconductor device 100 has expired.
　よって、半導体チップ１０をｐ型半導体基板で構成した場合には、ｐｎ接合部１３の位置における絶縁保護膜５０の厚みは、図２Ａ、図２Ｂに示すように、ｐ基板型正極素子のほうがｐ基板型負極素子よりも厚いので、剥離や亀裂が生じにくく、熱疲労寿命が長くなることが分かる。そこで、本実施形態では、図２Ｂのようなｐ基板型負極素子は使用せず、図２Ａのようなｐ基板型正極素子を使用するものとする。 Therefore, when the semiconductor chip 10 is composed of a p-type semiconductor substrate, the thickness of the insulating protective film 50 at the position of the pn junction 13 is greater in the p-substrate type positive element as shown in FIGS. 2A and 2B. Since it is thicker than the substrate-type negative electrode element, it can be seen that peeling and cracking are less likely to occur and the thermal fatigue life is prolonged. Therefore, in this embodiment, it is assumed that the p substrate type negative electrode element as shown in FIG. 2B is not used and the p substrate type positive electrode element as shown in FIG. 2A is used.
　次に、図２Ｃ、図２Ｄに示すように、半導体チップ１０ａをｎ型半導体基板で構成する場合には、そのｎ型半導体基板としてｐ型不純物（リンなど）がドープされたシリコンウェハを用いる。そして、その一方の主面にｐ型不純物（ボロンなど）を高濃度に拡散することにより、高濃度のｐ型の不純物拡散層１２ａ（ｐ＋層）を形成する。 Next, as shown in FIGS. 2C and 2D, when the semiconductor chip 10a is formed of an n-type semiconductor substrate, a silicon wafer doped with p-type impurities (such as phosphorus) is used as the n-type semiconductor substrate. Then, a high-concentration p-type impurity diffusion layer 12a (p + layer) is formed by diffusing p-type impurities (such as boron) at a high concentration on one main surface.
　ここで、ｎ型の半導体層１１とは、ｎ型半導体基板で高濃度のｐ型不純物が拡散されなかった部分をいう。そして、ｎ型の半導体層１１側の主面（ｐ型の不純物拡散層１２ａが形成された主面と反対側の主面）には、ｎ型の半導体層１１ａと金属層との接着性を向上させるために、ｎ型不純物が高濃度に拡散され、高濃度のｎ型の不純物拡散層（ｎ＋層）が形成される。本明細書では、この高濃度のｎ型の不純物拡散層（ｎ＋層）も含めて、ｎ型の半導体層１１ａという。 Here, the n-type semiconductor layer 11 refers to a portion where a high-concentration p-type impurity is not diffused in the n-type semiconductor substrate. The main surface on the n-type semiconductor layer 11 side (the main surface opposite to the main surface on which the p-type impurity diffusion layer 12a is formed) has adhesion between the n-type semiconductor layer 11a and the metal layer. In order to improve, n-type impurities are diffused at a high concentration, and a high-concentration n-type impurity diffusion layer (n + layer) is formed. In this specification, the high-concentration n-type impurity diffusion layer (n + layer) is also referred to as an n-type semiconductor layer 11a.
　以上のような半導体チップ１０ａの構造は、図２Ａ、図２Ｂに示した半導体チップ１０の構造において、ｐとｎとを入れ替えたものと実質的に同じである。従って、図２Ａ、図２Ｂの説明は、その説明文中で、ｐとｎ、陽と陰および正と負をそれぞれ入れ替えるだけで、図２Ｃ、図２Ｄにも適用することができるので、図２Ｃ、図２Ｄについての説明を省略する。 The structure of the semiconductor chip 10a as described above is substantially the same as the structure of the semiconductor chip 10 shown in FIGS. 2A and 2B in which p and n are interchanged. Therefore, the description of FIGS. 2A and 2B can be applied to FIGS. 2C and 2D only by replacing p and n, positive and negative, and positive and negative in the explanatory text. Description of FIG. 2D is omitted.
　以上、図２Ｃ、図２Ｄに示すように、半導体チップ１０ａをｎ型半導体基板で構成した場合には、ｐｎ接合部１３の位置における絶縁保護膜５０の厚みは、ｎ基板型負極素子の場合ほうがｎ基板型正極素子の場合よりも厚い。従って、ｎ基板型負極素子の場合ほうが、絶縁保護膜５０の剥離や亀裂が生じにくいので、その熱疲労寿命は長くなる。そこで、本実施形態では、図２Ｃのようなｎ基板型正極素子は使用せず、図２Ｄのようなｎ基板型負極素子を使用するものとする。 As described above, as shown in FIGS. 2C and 2D, when the semiconductor chip 10a is formed of an n-type semiconductor substrate, the thickness of the insulating protective film 50 at the position of the pn junction 13 is larger in the case of the n-substrate type negative electrode element. It is thicker than in the case of an n-substrate type positive electrode element. Therefore, in the case of the n-substrate type negative electrode element, the insulating protective film 50 is less likely to be peeled off or cracked, so that the thermal fatigue life is longer. Therefore, in this embodiment, the n-substrate type positive electrode element as shown in FIG. 2C is not used, and the n-substrate type negative electrode element as shown in FIG. 2D is used.
　図３Ａは、本実施形態におけるパワー半導体装置１００に用いるｐ基板型正極素子の半導体チップ１０およびその周縁部の構造の例を示した図、図３Ｂは、本実施形態におけるパワー半導体装置１００に用いるｎ基板型負極素子の半導体チップ１０ａおよびその周縁部の構造の例を示した図である。本実施形態では、半導体チップ１０をｐ型半導体基板で構成した場合には、図３Ａに示すようなｐ基板型正極素子を使用し、また、半導体チップ１０ａをｎ型半導体基板で構成した場合には、図３Ｂに示すようなｎ基板型負極素子を使用する。 FIG. 3A is a diagram showing an example of the structure of a p-type positive electrode semiconductor chip 10 used in the power semiconductor device 100 according to the present embodiment and the peripheral portion thereof, and FIG. 3B is used for the power semiconductor device 100 according to the present embodiment. It is the figure which showed the example of the structure of the semiconductor chip 10a of an n board | substrate type negative electrode element, and its peripheral part. In the present embodiment, when the semiconductor chip 10 is configured with a p-type semiconductor substrate, a p-substrate type positive element as shown in FIG. 3A is used, and when the semiconductor chip 10a is configured with an n-type semiconductor substrate. Uses an n-substrate negative electrode element as shown in FIG. 3B.
　なお、図３Ａおよび図３Ｂは、それぞれ図２Ａおよび図２Ｄと同じものであるが、その両方において、ｐｎ接合部１３の位置が、半導体チップ１０，１０ａのリード電極体２０側の主面よりもベース電極対３０側の主面に近いことに注意すべきである。 3A and 3B are the same as FIGS. 2A and 2D, respectively, but in both cases, the position of the pn junction 13 is higher than the main surface of the semiconductor chips 10 and 10a on the lead electrode body 20 side. It should be noted that it is close to the main surface on the base electrode pair 30 side.
　図４は、半導体チップ１０の端部側面に形成される絶縁保護膜５０の厚みと剪断応力または熱疲労寿命との関係を説明するための図である。ここでは、図４を用いて、まず、絶縁保護膜５０の厚みが薄いほど剥離や亀裂が生じやすく、厚みが厚いほど剥離や亀裂が生じにくいことについて説明し、その結果として、ｐｎ接合部１３が半導体チップ１０の上部側にあるよりも下部側にあるほうが、熱疲労寿命が長くなることを示す。 FIG. 4 is a diagram for explaining the relationship between the thickness of the insulating protective film 50 formed on the side surface of the end portion of the semiconductor chip 10 and the shear stress or the thermal fatigue life. Here, with reference to FIG. 4, first, it will be explained that peeling and cracking are more likely to occur as the insulating protective film 50 is thinner, and peeling and cracking are less likely to occur as the thickness is thicker. It is shown that the thermal fatigue life becomes longer when is located on the lower side than on the upper side of the semiconductor chip 10.
　パワー半導体装置１００の製造過程において、半導体チップ１０がベース電極体３０およびリード電極体２０にそれぞれ接合材４０，４１を介して接合されたとき、半導体チップ１０およびリード電極体２０は、ベース電極体３０の上に搭載された状態になる（図１参照）。この状態で、接合材４０，４１および半導体チップ１０の外周部に液状のポリイミド系樹脂が塗布され、硬化されて絶縁保護膜５０が形成される。液状のポリイミド系樹脂は、かなりの粘性を有するが、塗布されると重力により下方に垂れる。そのため、そのポリイミド系樹脂が硬化されて形成される絶縁保護膜５０の厚みは、上部から下方へ行くほど次第に厚くなる。 In the manufacturing process of the power semiconductor device 100, when the semiconductor chip 10 is bonded to the base electrode body 30 and the lead electrode body 20 via bonding materials 40 and 41, respectively, the semiconductor chip 10 and the lead electrode body 20 are It will be in the state mounted on 30 (refer FIG. 1). In this state, a liquid polyimide resin is applied to the outer peripheral portions of the bonding materials 40 and 41 and the semiconductor chip 10 and cured to form the insulating protective film 50. The liquid polyimide resin has a considerable viscosity, but when applied, it hangs down due to gravity. Therefore, the thickness of the insulating protective film 50 formed by curing the polyimide resin gradually increases from the top to the bottom.
　従って、図４に示すように、丸囲み１～丸囲み５が表す位置を、それぞれ、半導体チップ１０の上端部の位置（丸囲み１）、半導体チップ１０の上部側に形成されるｐｎ接合部１３の位置（丸囲み２）、半導体チップ１０の中央部の位置（丸囲み３）、半導体チップ１０の下部側に形成されるｐｎ接合部１３の位置（丸囲み４）、半導体チップ１０の下端部の位置（丸囲み５）とすれば、絶縁保護膜５０の厚みは、丸囲み１の位置で最も薄く、丸囲み２、丸囲み３、丸囲み４の各位置で次第に厚くなり、丸囲み５の位置で最も厚くなる。 Therefore, as shown in FIG. 4, the positions represented by the circled circles 1 to 5 are respectively the position of the upper end portion of the semiconductor chip 10 (circled circle 1) and the pn junction formed on the upper side of the semiconductor chip 10. 13 (circled circle 2), the position of the central portion of the semiconductor chip 10 (circled circle 3), the position of the pn junction 13 formed on the lower side of the semiconductor chip 10 (circled circle 4), the lower end of the semiconductor chip 10 In this case, the thickness of the insulating protective film 50 is the thinnest at the position of the circle 1 and gradually becomes thicker at the positions of the circle 2, the circle 3, and the circle 4. It is thickest at position 5.
　一方、半導体チップ１０と封止樹脂体６０との線膨張係数の差によって絶縁保護膜５０に生じる剪断応力γは、高温環境時と低温環境時における封止樹脂体６０側の絶縁保護膜５０の変位量をδ１、半導体チップ１０側の絶縁保護膜５０の変位量をδ２、絶縁保護膜５０の厚みをτで表すと、
　γ＝ｋ・（δ１－δ２）／τ　　（ｋ：比例定数）
なる関係式を用いて求めることができる。 On the other hand, the shear stress γ generated in the insulating protective film 50 due to the difference in linear expansion coefficient between the semiconductor chip 10 and the sealing resin body 60 causes the insulating protective film 50 on the sealing resin body 60 side in the high temperature environment and the low temperature environment. When the displacement amount is represented by δ1, the displacement amount of the insulating protective film 50 on the semiconductor chip 10 side is represented by δ2, and the thickness of the insulating protective film 50 is represented by τ.
γ = k · (δ1-δ2) / τ (k: proportional constant)
Can be obtained using the following relational expression.
　すなわち、剪断応力γは、絶縁保護膜５０の厚みτが薄くなるほど増大するので、パワー半導体装置１００、すなわち、半導体チップ１０および封止樹脂体６０に対し、高温環境と低温環境が繰り返されるような温度環境ストレスが加えられると、絶縁保護膜５０は、薄いほど剥離や亀裂が生じやすくなる。 That is, since the shear stress γ increases as the thickness τ of the insulating protective film 50 decreases, the high temperature environment and the low temperature environment are repeated with respect to the power semiconductor device 100, that is, the semiconductor chip 10 and the sealing resin body 60. When temperature environmental stress is applied, the insulating protective film 50 is more likely to be peeled off or cracked as it is thinner.
　従って、半導体チップ１０の端部の側面に形成された絶縁保護膜５０においては、その半導体チップ１０の上端部（丸囲み１の位置）で剥離や亀裂が最も生じやすく、下方に行くほど剥離や亀裂が生じにくい。つまり、絶縁保護膜５０の剥離や亀裂は、まず、半導体チップ１０の上端部（丸囲み１の位置）近傍で生じ、その剥離や亀裂が次第に下方に広がっていく形態をとることが多い。 Therefore, in the insulating protective film 50 formed on the side surface of the end portion of the semiconductor chip 10, peeling or cracking is most likely to occur at the upper end portion (the position of the circle 1) of the semiconductor chip 10, and peeling or Cracks are less likely to occur. That is, peeling and cracking of the insulating protective film 50 first occurs near the upper end (position of the circled circle 1) of the semiconductor chip 10, and the peeling and cracking often take a form that gradually spreads downward.
　なお、半導体チップ１０の上端部（丸囲み１の位置）近傍などに絶縁保護膜５０の剥離や亀裂が生じても、直ちに半導体チップ１０の整流機能が失われ、故障に到るわけではない。絶縁保護膜５０の剥離や亀裂がｐｎ接合部１３に接する位置（丸囲み２または丸囲み４の位置）に到達し、そこから水分や不純物原子がｐｎ接合部１３に侵入して、ｐｎ接合が絶縁破壊されたとき、半導体チップ１０の整流機能が失われ、故障に到る。 It should be noted that even if the insulating protective film 50 is peeled off or cracked in the vicinity of the upper end portion (the position of the circled circle 1) of the semiconductor chip 10, the rectifying function of the semiconductor chip 10 is lost immediately and does not cause a failure. The peeling or cracking of the insulating protective film 50 reaches the position where the pn junction 13 is in contact (the position of the circled circle 2 or the circled circle 4), from which moisture or impurity atoms enter the pn junction 13 and the pn junction is formed. When the dielectric breakdown occurs, the rectifying function of the semiconductor chip 10 is lost and a failure occurs.
　従って、ｐｎ接合部１３が丸囲み２の位置に形成される場合よりも、丸囲み４の位置に形成される場合のほうが、ｐｎ接合が絶縁破壊され、半導体チップ１０の整流機能が失われ、故障に到るまでの期間、すなわち、熱疲労寿命は長くなるといえる。つまり、半導体チップ１０をｐ型半導体基板で構成した場合には（図２Ａ、図２Ｂ参照）、ｐ基板型正極素子のほうがｐ基板型負極素子よりも熱疲労寿命が長くなり、また、半導体チップ１０ａをｎ型半導体基板で構成した場合には（図２Ｃ、図２Ｄ参照）、ｎ基板型負極素子のほうがｎ基板型正極素子よりも熱疲労寿命が長くなることが分かる。 Accordingly, when the pn junction portion 13 is formed at the position of the circled circle 2, the pn junction is broken down and the rectifying function of the semiconductor chip 10 is lost when it is formed at the position of the circled circle 4. It can be said that the period until failure, that is, the thermal fatigue life becomes longer. That is, when the semiconductor chip 10 is formed of a p-type semiconductor substrate (see FIGS. 2A and 2B), the p-substrate positive element has a longer thermal fatigue life than the p-substrate negative element, and the semiconductor chip When 10a is formed of an n-type semiconductor substrate (see FIGS. 2C and 2D), it can be seen that the n-substrate negative electrode element has a longer thermal fatigue life than the n-substrate positive electrode element.
　図５は、半導体チップ１０内における上端部からの厚み方向位置と、その厚み方向位置における絶縁保護膜５０に生じる剪断応力および熱疲労寿命の関係を示した図である。図５において、右側のグラフの横軸は、絶縁保護膜５０に生じる剪断応力の相対値を表し、縦軸は、半導体チップ１０の上端部（丸囲み１の位置）からの厚み方向位置を、半導体チップ１０全体の厚みに対する相対比率で表したものである。 FIG. 5 is a diagram showing the relationship between the position in the thickness direction from the upper end in the semiconductor chip 10 and the shear stress and thermal fatigue life generated in the insulating protective film 50 at the position in the thickness direction. In FIG. 5, the horizontal axis of the graph on the right represents the relative value of the shear stress generated in the insulating protective film 50, and the vertical axis represents the position in the thickness direction from the upper end (position of the circled circle 1) of the semiconductor chip 10. This is expressed as a relative ratio to the thickness of the entire semiconductor chip 10.
　ここで、剪断応力の相対値とは、半導体チップ１０の上端部（丸囲み１の位置）における絶縁保護膜５０が受ける剪断応力を１００とした場合、各位置における絶縁保護膜５０が受ける剪断応力の相対値である。また、図５の左側に示されている絶縁保護膜５０の断面構造図は、絶縁保護膜５０の厚みと半導体チップ１０内の厚み方向の位置との関係を概略的に図示したものである。 Here, the relative value of the shear stress refers to the shear stress received by the insulating protective film 50 at each position when the shear stress received by the insulating protective film 50 at the upper end of the semiconductor chip 10 (the position of the circled circle 1) is 100. Is the relative value of. Further, the cross-sectional structure diagram of the insulating protective film 50 shown on the left side of FIG. 5 schematically shows the relationship between the thickness of the insulating protective film 50 and the position in the thickness direction in the semiconductor chip 10.
　図５に示した剪断応力カーブによれば、ｐｎ接合部１３が上部側（丸囲み２の位置）に形成され、その形成位置が、全体の厚みの１０％～３５％程度の位置である場合には、剪断応力の相対値は、３２～４０程度である。また、ｐｎ接合部１３が下部側（丸囲み４の位置）に形成され、その形成位置が、全体の厚みの６５％～９０％程度の位置である場合には、剪断応力の相対値は、２７～３０程度である。 According to the shear stress curve shown in FIG. 5, the pn junction 13 is formed on the upper side (the position of the circled circle 2), and the formation position is about 10% to 35% of the entire thickness. The relative value of the shear stress is about 32 to 40. Further, when the pn junction portion 13 is formed on the lower side (the position of the circled circle 4) and the formation position is about 65% to 90% of the total thickness, the relative value of the shear stress is It is about 27-30.
　このとき、パワー半導体装置１００の熱疲労寿命は、ｐｎ接合部１３が下部側（丸囲み４の位置）に形成され、その形成位置が全体の厚みの６５％～９０％程度の位置である場合、１００～９０（相対値）程度となる。それに対し、ｐｎ接合部１３が上部側（丸囲み２の位置）に形成され、その形成位置が全体の厚みの１０％～３５％程度の位置である場合、その熱疲労寿命は、３０～５０（相対値）程度となる。なお、これらは、加速試験などにより実験的、経験的に得られた結果である。 At this time, the thermal fatigue life of the power semiconductor device 100 is such that the pn junction 13 is formed on the lower side (the position of the circled circle 4), and the formation position is about 65% to 90% of the total thickness. , About 100 to 90 (relative value). On the other hand, when the pn junction portion 13 is formed on the upper side (position of the circled circle 2) and the formation position is a position of about 10% to 35% of the total thickness, the thermal fatigue life is 30 to 50%. (Relative value). These are results obtained experimentally and empirically by an accelerated test or the like.
　以上の結果によれば、ｐｎ接合部１３を半導体チップ１０の下部側（半導体チップ厚みの６５％～９０％の位置）に設けると、下部側（半導体チップ厚みの１０％～３５％の位置）に設けるよりも、剥離に到るまでの寿命、つまり、パワー半導体装置１００の熱疲労寿命が２～３倍向上することになる。 According to the above results, when the pn junction part 13 is provided on the lower side of the semiconductor chip 10 (position of 65% to 90% of the semiconductor chip thickness), the lower side (position of 10% to 35% of the semiconductor chip thickness). The life until peeling is reached, that is, the thermal fatigue life of the power semiconductor device 100 is improved by 2 to 3 times.
　図６は、絶縁保護膜５０の最小膜厚とシリコン－絶縁保護膜５０間の剪断接着強度との関係を示したグラフ、図７は、絶縁保護膜５０の最小膜厚とパワー半導体装置１００の熱疲労寿命との関係を示したグラフである。 FIG. 6 is a graph showing the relationship between the minimum film thickness of the insulating protective film 50 and the shear adhesive strength between the silicon-insulating protective film 50, and FIG. 7 shows the minimum film thickness of the insulating protective film 50 and the power semiconductor device 100. It is the graph which showed the relationship with a thermal fatigue life.
　ここで、図６におけるグラフの横軸は、絶縁保護膜５０の最小膜厚の相対値（対数目盛）を表し、グラフの縦軸は、シリコン－絶縁保護膜５０間の剪断接着強度の相対値を表している。また、図７におけるグラフの横軸は、絶縁保護膜５０の最小膜厚の相対値（対数目盛）を表し、グラフの縦軸は、パワー半導体装置１００の熱疲労寿命を表している。
　なお、絶縁保護膜５０の最小膜厚とは、半導体チップ１０の上端部（丸囲み１の位置）における絶縁保護膜５０の厚みを意味する。 Here, the horizontal axis of the graph in FIG. 6 represents the relative value (logarithmic scale) of the minimum film thickness of the insulating protective film 50, and the vertical axis of the graph represents the relative value of the shear adhesive strength between the silicon and the insulating protective film 50. Represents. Further, the horizontal axis of the graph in FIG. 7 represents the relative value (logarithmic scale) of the minimum film thickness of the insulating protective film 50, and the vertical axis of the graph represents the thermal fatigue life of the power semiconductor device 100.
The minimum film thickness of the insulating protective film 50 means the thickness of the insulating protective film 50 at the upper end (position of the circled circle 1) of the semiconductor chip 10.
　図６および図７に示したグラフは、いずれも、加速試験などにより実験的、経験的に得られたものである。ここで、図６および図７のグラフを比較すると、シリコン－絶縁保護膜５０間の剪断接着強度およびパワー半導体装置１００の熱疲労寿命は、絶縁保護膜５０の最小膜厚に対して、極めて類似した依存特性を有していることが分かる。 6 and 7 are both experimentally and empirically obtained by an acceleration test or the like. Here, comparing the graphs of FIG. 6 and FIG. 7, the shear adhesive strength between the silicon-insulating protective film 50 and the thermal fatigue life of the power semiconductor device 100 are very similar to the minimum film thickness of the insulating protective film 50. It can be seen that it has the dependency characteristic.
　すなわち、絶縁保護膜５０の最小膜厚と、シリコン－絶縁保護膜５０間の剪断接着強度（絶縁保護膜５０が半導体チップ１０からの剥離されるときの強度）と、パワー半導体装置１００の熱疲労寿命との間には、強い相関があることがわかる。 That is, the minimum film thickness of the insulating protective film 50, the shear adhesive strength between the silicon and the insulating protective film 50 (strength when the insulating protective film 50 is peeled off from the semiconductor chip 10), and the thermal fatigue of the power semiconductor device 100 It can be seen that there is a strong correlation with the lifetime.
　ちなみに、図７によれば、絶縁保護膜５０の最小膜厚の相対値が１００％であるときには、パワー半導体装置１００の熱疲労寿命の相対値は、１００％であるが、最小膜厚が１０分の１（相対値が１０）になると、熱疲労寿命の相対値は、８０％程度まで低下する。また、最小膜厚が１００分の１（相対値が１％）になると、熱疲労寿命の相対値は、１０％程度まで低下する。 Incidentally, according to FIG. 7, when the relative value of the minimum film thickness of the insulating protective film 50 is 100%, the relative value of the thermal fatigue life of the power semiconductor device 100 is 100%, but the minimum film thickness is 10%. When it becomes 1 / (relative value is 10), the relative value of thermal fatigue life falls to about 80%. When the minimum film thickness is 1/100 (relative value is 1%), the relative value of the thermal fatigue life is reduced to about 10%.
　図８は、回転発電機８０で発電する交流電流を整流装置７０で直流変換して供給する電源装置２００の構成の例を示した図である。図８に示すように、電源装置２００は、回転発電機８０、整流装置７０、レギュレータ９０、バッテリ９２などを含んで構成される。なお、エンジン駆動の乗用車などの車両に搭載されている、いわゆるオルタネータは、この電源装置２００と同様の構成を有していることが多い。 FIG. 8 is a diagram showing an example of the configuration of the power supply device 200 that supplies the alternating current generated by the rotary generator 80 by direct current conversion by the rectifier 70. As shown in FIG. 8, the power supply device 200 includes a rotary generator 80, a rectifier 70, a regulator 90, a battery 92, and the like. A so-called alternator mounted on a vehicle such as an engine-driven passenger car often has a configuration similar to that of the power supply device 200.
　回転発電機８０は、ステータコイル８１とロータコイル８２を含んで構成され、ロータコイル８２は、車両のエンジンなどによって駆動され、回転する。そして、キーＳＷ９１がオンされてロータコイル８２に電流が流されると、ステータコイル８１により、例えば３相の交流電流が発電される。 The rotary generator 80 includes a stator coil 81 and a rotor coil 82, and the rotor coil 82 is driven and rotated by a vehicle engine or the like. When the key SW 91 is turned on and a current flows through the rotor coil 82, for example, a three-phase alternating current is generated by the stator coil 81.
　整流装置７０は、ステータコイル８１により発電される交流電流を整流し、車両内などの電気負荷９３に直流電流を供給するとともに、余剰の電流によりバッテリ９２を充電する。整流装置７０は、上位電位側ダイオード素子群７１に属する上位電位側ダイオード素子７２，７３，７４が、それぞれ、下位電位側ダイオード素子群７５に属する下位電位側ダイオード素子７６，７７，７８に直列接続されて構成される。 The rectifier 70 rectifies the alternating current generated by the stator coil 81, supplies the direct current to the electric load 93 such as in the vehicle, and charges the battery 92 with the surplus current. In the rectifier 70, upper potential side diode elements 72, 73, 74 belonging to the upper potential side diode element group 71 are connected in series to lower potential side diode elements 76, 77, 78 belonging to the lower potential side diode element group 75, respectively. Configured.
　このとき、それぞれ直列接続された上位側および下位側のダイオード素子の組（７２，７６）、（７３，７７）、（７４，７８）は、ステータコイル８１を介して、いわゆるダイオードブリッジ回路を構成する。 At this time, the sets (72, 76), (73, 77) and (74, 78) of the upper and lower diode elements connected in series constitute a so-called diode bridge circuit via the stator coil 81. To do.
　本実施形態の場合、上位電位側ダイオード素子７２，７３，７４として、半導体チップ１０の基板がｐ型半導体層１１からなるｐ基板型正極素子（図３Ａ参照）を用いる。また、下位電位側ダイオード素子７６，７７，７８として、半導体チップ１０ａの基板がｎ型半導体層１１ａからなるｎ基板型負極素子（図３Ｂ参照）を用いる。 In the case of the present embodiment, a p-substrate type positive electrode element (see FIG. 3A) in which the substrate of the semiconductor chip 10 is made of the p-type semiconductor layer 11 is used as the higher-potential- side diode elements 72, 73, and 74. Further, as the lower potential side diode elements 76, 77, 78, n substrate type negative electrode elements (see FIG. 3B) in which the substrate of the semiconductor chip 10a is formed of the n type semiconductor layer 11a are used.
　ここで、上位電位側ダイオード素子７２と下位電位側ダイオード素子７６との直列接続回路は、ｐ基板型正極素子のリード電極体２０とｎ基板型負極素子のリード電極体２０とを接続することにより実現される。また、上位電位側ダイオード素子７３と下位電位側ダイオード素子７７との直列接続回路および上位電位側ダイオード素子７４と下位電位側ダイオード素子７８との直列接続回路も、それぞれ同様にして実現される。 Here, the series connection circuit of the upper potential side diode element 72 and the lower potential side diode element 76 is obtained by connecting the lead electrode body 20 of the p substrate type positive electrode element and the lead electrode body 20 of the n substrate type negative electrode element. Realized. A series connection circuit of the upper potential side diode element 73 and the lower potential side diode element 77 and a series connection circuit of the upper potential side diode element 74 and the lower potential side diode element 78 are also realized in the same manner.
　以上のようにして、リード電極体２０同士が互いに接続されたｐ基板型正極素子およびｎ基板型負極素子の組が３組構成されるが、それぞれの組のリード電極体２０は、３つのステータコイル８１のそれぞれに接続される。さらに、各ｎ基板型負極素子のベース電極体３０は、まとめて接地され、また、各ｐ基板型正極素子のベース電極体３０は、まとめて電気負荷９３に接続される。 As described above, three sets of the p substrate type positive electrode element and the n substrate type negative electrode element in which the lead electrode bodies 20 are connected to each other are configured, and each set of the lead electrode bodies 20 includes three stators. Connected to each of the coils 81. Furthermore, the base electrode bodies 30 of the n-substrate type negative electrode elements are collectively grounded, and the base electrode bodies 30 of the p-substrate type positive electrode elements are collectively connected to the electric load 93.
　以上のように構成された整流装置７０には、熱疲労寿命の向上させることが可能な構造を有するｐ基板型正極素子およびｎ基板型負極素子が用いられているので、整流装置７０自体の熱疲労寿命も向上させることができる。また、整流装置７０では、上位電位側ダイオード素子７２，７３，７４は、ｐ基板型正極素子に揃えられ、下位電位側ダイオード素子７６，７７，７８は、ｎ基板型負極素子に揃えられている。従って、整流装置７０は、その整流特性が安定化され、動作の信頼性が向上し、さらには、整流装置７０の熱疲労寿命のばらつきも低減することができる。 The rectifying device 70 configured as described above uses a p-substrate positive electrode element and an n-substrate negative electrode element having a structure capable of improving the thermal fatigue life. The fatigue life can also be improved. In the rectifier 70, the upper potential side diode elements 72, 73, 74 are aligned with the p substrate type positive element, and the lower potential side diode elements 76, 77, 78 are aligned with the n substrate type negative element. . Therefore, the rectifying device 70 has stabilized rectifying characteristics, improved operational reliability, and can reduce variations in the thermal fatigue life of the rectifying device 70.
　その結果として、整流装置７０を含んで構成される電源装置２００についても、熱疲労寿命を長くすることができるとともに、そのばらつきを低減することができる。さらには、整流装置７０の整流特性や信頼性が向上することから、電源装置２００の動作の安定性や信頼性を向上させることができる。 As a result, the power supply device 200 including the rectifying device 70 can also have a long thermal fatigue life and can reduce variations. Furthermore, since the rectification characteristics and reliability of the rectifier 70 are improved, the stability and reliability of the operation of the power supply apparatus 200 can be improved.
　なお、図８の説明では、ステータコイル８１は、３相の交流電流を発生するとしたが、２相の交流電流や６相の交流電流を発生するとしてもよい。その場合には、整流装置７０は、上位電位側ダイオード素子と下位電位側ダイオード素子との直列接続回路が、２組または６組設けられ、それらにより、ダイオードブリッジ回路が構成される。 In the description of FIG. 8, the stator coil 81 generates a three-phase alternating current, but may generate a two-phase alternating current or a six-phase alternating current. In that case, the rectifier 70 is provided with two or six series connection circuits of upper-potential-side diode elements and lower-potential-side diode elements, and these constitute a diode bridge circuit.
（実施形態の変形例）
　図９Ａは、プレーナ型の半導体チップ１０ｂを用いて構成したパワー半導体装置１００ｂの構造の例を模式的に示した図、図９Ｂは、パワー半導体装置１００ｂにおける半導体チップ１０ｂおよびその周縁部の構造の例を示した図である。
　なお、図９Ａに示したパワー半導体装置１００ｂの構造は、半導体チップ１０ｂがメサ型ではなく図９Ｂに示すようなプレーナ型であることを除き、ほとんどが図１に示した半導体チップ１０の構造と同じである。従って、以下、図９Ａおよび図９Ｂの説明では、図１と同じ構成要素には同じ符号を付し、重複する説明を省略し、相違する部分についてのみ説明する。 (Modification of the embodiment)
FIG. 9A is a diagram schematically showing an example of the structure of a power semiconductor device 100b configured using a planar semiconductor chip 10b, and FIG. 9B shows the structure of the semiconductor chip 10b and its peripheral portion in the power semiconductor device 100b. It is the figure which showed the example.
9A is almost the same as the structure of the semiconductor chip 10 shown in FIG. 1 except that the semiconductor chip 10b is not a mesa type but a planar type as shown in FIG. 9B. The same. Therefore, hereinafter, in the description of FIGS. 9A and 9B, the same components as those in FIG. 1 are denoted by the same reference numerals, overlapping description will be omitted, and only different portions will be described.
　図９Ｂにおいて、破線の四角形で囲まれた領域Ｂは、図９Ａに示したパワー半導体装置１００ｂのうち破線で囲った領域Ｂの部分の構造を拡大して示したものである。図９Ｂの領域Ｂの中に示すように、プレーナ型の半導体チップ１０ｂの場合、ｐｎ接合部１３は、半導体チップ１０ｂの端部側面に露出するのではなく、ｐ型またはｎ型の半導体基板に対し、ｎ型またはｐ型の不純物の気相拡散を施した主面（図９Ｂでは、半導体チップ１０ｂの下側の主面）と同じ主面に露出する。そして、その主面に露出したｐｎ接合部１３の表面には、半導体チップ１０ｂの製造工程の中で酸化シリコンなどの絶縁膜１４が形成される。従って、ｐｎ接合部１３は、絶縁膜１４によって保護される。 9B, a region B surrounded by a broken-line rectangle is an enlarged view of the structure of the region B surrounded by the broken line in the power semiconductor device 100b shown in FIG. 9A. As shown in the region B of FIG. 9B, in the case of the planar type semiconductor chip 10b, the pn junction 13 is not exposed on the side surface of the end of the semiconductor chip 10b, but on the p type or n type semiconductor substrate. On the other hand, it is exposed to the same main surface as the main surface (in FIG. 9B, the lower main surface of the semiconductor chip 10b) subjected to vapor phase diffusion of n-type or p-type impurities. An insulating film 14 such as silicon oxide is formed on the surface of the pn junction 13 exposed on the main surface during the manufacturing process of the semiconductor chip 10b. Accordingly, the pn junction 13 is protected by the insulating film 14.
　このような絶縁膜１４は、半導体チップ１０ｂ表面に直接に形成された良好な絶縁膜であるため、その剥離防止を目的にｐｎ接合部１３をさらに絶縁保護膜５０で覆う必要はない。そこで、本変形例では、絶縁保護膜５０は、半導体チップ１０ｂに発生する熱応力を緩和するとともに、接合材４０，４１のハンダなどが塑性流動した半導体チップ１０ｂと封止樹脂体６０の隙間などに侵入するのを抑制することを目的に形成されるものとする。 Since such an insulating film 14 is a good insulating film formed directly on the surface of the semiconductor chip 10b, it is not necessary to further cover the pn junction 13 with the insulating protective film 50 for the purpose of preventing the peeling. Therefore, in this modification, the insulating protective film 50 relieves the thermal stress generated in the semiconductor chip 10b, and the gap between the semiconductor chip 10b and the sealing resin body 60 in which the solder of the bonding materials 40 and 41 is plastically flowed. It is formed for the purpose of suppressing intrusion.
　そして、本変形例でも、パワー半導体装置１００ｂを構成する半導体チップ１０ｂとして、図３Ａおよび図３Ｂに示したようなｐ基板型正極素子またはｎ基板型負極素子を使用するものとする。この場合、図９Ｂの領域Ｂに示すように、ｐｎ接合部１３は、ベース電極体３０に対向する主面側に近い位置に位置し、ｎ型またはｐ型の高濃度の不純物拡散層１２ｂは、半導体チップ１０ｂの下側の主面に露出する。このとき、その主面の周縁部には絶縁膜１４が形成されており、当該主面に露出するｐｎ接合部１３も絶縁膜１４で覆われている。 And also in this modification, p board type positive electrode elements or n board type negative electrode elements as shown in Drawing 3A and Drawing 3B shall be used as semiconductor chip 10b which constitutes power semiconductor device 100b. In this case, as shown in region B of FIG. 9B, the pn junction 13 is located at a position close to the main surface facing the base electrode body 30, and the n-type or p-type high-concentration impurity diffusion layer 12b is The semiconductor chip 10b is exposed on the lower main surface. At this time, an insulating film 14 is formed on the peripheral portion of the main surface, and the pn junction 13 exposed on the main surface is also covered with the insulating film 14.
　そして、半導体チップ１０ｂのｎ型またはｐ型の高濃度の不純物拡散層１２ｂは、ハンダなどの接合材４１によりベース電極体３０に接合される。このとき、半導体チップ１０ｂの周縁部の絶縁膜１４が形成された部分には、接合材４１が付着しないので、半導体チップ１０ｂとベース電極体３０との間に庇状の空洞部が形成される。その後、その空洞部には、絶縁保護膜５０が形成される。 The n-type or p-type high-concentration impurity diffusion layer 12b of the semiconductor chip 10b is bonded to the base electrode body 30 by a bonding material 41 such as solder. At this time, since the bonding material 41 does not adhere to the portion of the semiconductor chip 10b where the insulating film 14 is formed, a bowl-shaped cavity is formed between the semiconductor chip 10b and the base electrode body 30. . Thereafter, an insulating protective film 50 is formed in the cavity.
　従って、熱疲労により絶縁保護膜５０に剥離や亀裂が生じ、半導体チップ１０ｂの上部の接合材４０が塑性流動などによって半導体チップ１０ｂの下部まで到達したとしても、その庇の部分の絶縁保護膜５０が剥離しなければ、下部の接合材４１に到達することはない。 Therefore, even if the insulating protective film 50 is peeled or cracked due to thermal fatigue and the bonding material 40 on the upper part of the semiconductor chip 10b reaches the lower part of the semiconductor chip 10b due to plastic flow or the like, the insulating protective film 50 on that part of the insulating chip 50b. If it does not peel off, it will not reach the lower bonding material 41.
　一方、ここでは図示を省略するが、ｎ型またはｐ型の高濃度の不純物拡散層１２ｂが半導体チップ１０ｂの上側の主面に露出する場合（すなわち、図２Ｂおよび図２Ｃに示したようなｎ基板型正極素子およびｐ基板型負極素子の場合）には、半導体チップ１０ｂとベース電極体３０との間には、庇状の空洞部は形成されない。従って、長期間の熱疲労により、絶縁保護膜５０に剥離が生じた場合には、上部の接合材４０が塑性流動などにより下部の接合材４１に到達した場合には、庇状の空洞部が形成されない分、上部の接合材４０と下部の接合材４１とが短絡する可能性が大きいことになる。 On the other hand, although not shown here, the n-type or p-type high-concentration impurity diffusion layer 12b is exposed on the upper main surface of the semiconductor chip 10b (that is, n as shown in FIGS. 2B and 2C). In the case of a substrate-type positive electrode element and a p-substrate type negative electrode element), no bowl-shaped cavity is formed between the semiconductor chip 10b and the base electrode body 30. Therefore, when peeling occurs in the insulating protective film 50 due to long-term thermal fatigue, when the upper bonding material 40 reaches the lower bonding material 41 due to plastic flow or the like, the bowl-shaped cavity is formed. Since it is not formed, the upper bonding material 40 and the lower bonding material 41 are likely to be short-circuited.
　よって、本変形例でも、パワー半導体装置１００ｂを構成する半導体チップ１０ｂとしてｐ基板型正極素子またはｎ基板型負極素子を使用することにより、その熱疲労寿命を向上させることができる。 Therefore, also in this modification, the thermal fatigue life can be improved by using the p substrate type positive electrode element or the n substrate type negative electrode element as the semiconductor chip 10b constituting the power semiconductor device 100b.
　さらに、図８に示した整流装置７０において、上位電位側ダイオード素子７２，７３，７４としてｐ基板型正極素子を用い、下位電位側ダイオード素子７６，７７，７８としてｎ基板型負極素子を用いることにより、整流装置７０や電源装置２００の熱疲労寿命を向上させることができ、さらには、その動作の安定性や信頼性を向上させることができる。 Further, in the rectifier 70 shown in FIG. 8, p substrate type positive elements are used as the upper potential side diode elements 72, 73, 74, and n substrate type negative elements are used as the lower potential side diode elements 76, 77, 78. As a result, the thermal fatigue life of the rectifying device 70 and the power supply device 200 can be improved, and further, the stability and reliability of the operation can be improved.
（その他の実施形態）
　以上に説明した実施形態およびその変形例は、ｐｎ接合を有する通常のダイオードだけでなく、ショットキダイオードに対しても、ほとんど同様に適用することができる。ｐｎ接合ダイオードは、ｐ型またはｎ型の半導体基板にｎ型またはｐ型の高濃度の不純物拡散層を形成したものであるが、ショットキダイオードは、ｐ型またはｎ型の半導体基板にショットキ障壁を有する金属を接合したものである。半導体基板とショットキ障壁を有する金属との接合部は、ショットキ接合部と呼ばれ、前記実施形態の説明におけるｐｎ接合部１３に相当する。 (Other embodiments)
The above-described embodiment and its modifications can be applied almost equally to not only a normal diode having a pn junction but also a Schottky diode. A pn junction diode is formed by forming an n-type or p-type high-concentration impurity diffusion layer on a p-type or n-type semiconductor substrate. A Schottky diode has a Schottky barrier on a p-type or n-type semiconductor substrate. The metal which has is joined. A junction between the semiconductor substrate and the metal having a Schottky barrier is called a Schottky junction and corresponds to the pn junction 13 in the description of the above embodiment.
　従って、以上に説明した実施形態およびその変形例の説明において、ｎ型またはｐ型の高濃度の不純物拡散層１２，１２ａ，１２ｂを、ショットキ障壁を有する金属として読み替え、さらに、ｐｎ接合部１３を、ショットキ接合部と読み替えれば、その説明は、ショットキダイオードに対してもほとんど同様に適用することができる。 Therefore, in the above-described embodiment and the modifications thereof, the n-type or p-type high-concentration impurity diffusion layers 12, 12a, 12b are read as a metal having a Schottky barrier, and the pn junction 13 is In other words, the description can be applied to the Schottky diode in almost the same manner.
　ここで、ｎ型の半導体基板に対しショットキ障壁を有する金属としては、Ａｌ，Ａｕ，Ｗ，Ｐｔなどがある。また、ｐ型の半導体基板に対しショットキ障壁を有する金属としては、Ｉｎ，Ｚｎなどがある。 Here, examples of the metal having a Schottky barrier with respect to the n-type semiconductor substrate include Al, Au, W, and Pt. Examples of the metal having a Schottky barrier with respect to the p-type semiconductor substrate include In and Zn.
　よって、整流機能を有する半導体チップとして、ｐｎ接合ダイオードの代わりにショットキダイオードを用いたとしても、ここまでに説明した実施形態の効果と同様の効果を得ることができる。 Therefore, even if a Schottky diode is used instead of the pn junction diode as the semiconductor chip having a rectifying function, the same effects as those of the embodiments described so far can be obtained.
　なお、本発明は、以上に説明した実施形態に限定されるものでなく、さらに様々な変形例が含まれる。例えば、前記の実施形態は、本発明を分かりやすく説明するために、詳細に説明したものであり、必ずしも説明したすべての構成を備えるものに限定されるものではない。また、ある実施形態の構成の一部を他の実施形態の構成の一部で置き換えることが可能であり、さらに、ある実施形態の構成に他の実施形態の構成の一部または全部を加えることも可能である。 Note that the present invention is not limited to the embodiment described above, and includes various modifications. For example, the above embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to the one having all the configurations described. Further, a part of the configuration of an embodiment can be replaced with a part of the configuration of another embodiment, and further, a part or all of the configuration of the other embodiment is added to the configuration of the certain embodiment. Is also possible.
　　１０，１０ｂ　　　　　半導体チップ
　　１１，１１ａ　　　　　半導体層
　　１２，１２ａ，１２ｂ　不純物拡散層
　　１３　　ｐｎ接合部
　　２０　　リード電極体
　　３０　　ベース電極体
　　３１　　台座部
　　３２　　溝部
　　４０，４１　　接合材
　　５０　　絶縁保護膜
　　６０　　封止樹脂体
　　７０　　整流装置
　　７１　　上位電位側ダイオード素子群
　　７２，７３，７４　上位電位側ダイオード素子
　　７５　　下位電位側ダイオード素子群
　　７６，７７，７８　下位電位側ダイオード素子
　　８０　　回転発電機
　　８１　　ステータコイル
　　８２　　ロータコイル
　　９０　　レギュレータ
　　９１　　キーＳＷ
　　９２　　バッテリ
　　９３　　電気負荷
　　１００　パワー半導体装置（整流ダイオード）
　　２００　電源装置 DESCRIPTION OF SYMBOLS 10, 10b Semiconductor chip 11, 11a Semiconductor layer 12, 12a, 12b Impurity diffusion layer 13 pn junction part 20 Lead electrode body 30 Base electrode body 31 Base part 32 Groove part 40, 41 Joining material 50 Insulating protective film 60 Sealing resin body 70 Rectifier 71 Upper potential side diode element group 72, 73, 74 Upper potential side diode element 75 Lower potential side diode element group 76, 77, 78 Lower potential side diode element 80 Rotary generator 81 Stator coil 82 Rotor coil 90 Regulator 91 Key SW
92 Battery 93 Electric load 100 Power semiconductor device (rectifier diode)
200 Power supply

Claims (12)

  1. 　第１導電型の半導体層からなる半導体基板の第１の主面に第２導電型の不純物拡散層が形成された半導体チップと、
    　上部に平坦な保持面を有し、前記第１の主面を下に向けた前記半導体チップを前記保持面上に保持するとともに、前記第１の主面に形成された前記第２導電型の不純物拡散層が導電性の接合材を介して前記保持面に接合されるベース電極体と、
    　前記第１の主面の反対側の主面である第２の主面を構成する前記第１導電型の半導体層に、導電性の接合材を介して接合されるリード電極体と、
    　前記ベース電極体と前記リード電極体との間に挟まれた前記半導体チップを封止する封止樹脂体と
    を備え、
    　前記半導体チップ内の前記第１導電型の半導体層と前記第２導電型の不純物拡散層との境界に形成されるｐｎ接合部は、前記第２の主面よりも前記第１の主面に近い位置に形成されており、
    　前記半導体チップの周縁部と前記封止樹脂体との間には、絶縁保護膜が形成されている
    ことを特徴とするパワー半導体装置。     A semiconductor chip in which a second conductivity type impurity diffusion layer is formed on a first main surface of a semiconductor substrate made of a first conductivity type semiconductor layer;
    The semiconductor chip having a flat holding surface at the top and holding the first main surface facing downward is held on the holding surface, and the second conductivity type formed on the first main surface A base electrode body in which the impurity diffusion layer is bonded to the holding surface via a conductive bonding material;
    A lead electrode body bonded to the first conductive type semiconductor layer constituting the second main surface, which is the main surface opposite to the first main surface, via a conductive bonding material;
    A sealing resin body for sealing the semiconductor chip sandwiched between the base electrode body and the lead electrode body;
    A pn junction formed at a boundary between the first conductive type semiconductor layer and the second conductive type impurity diffusion layer in the semiconductor chip is located on the first main surface rather than the second main surface. It is formed in a close position,
    An insulating protective film is formed between a peripheral edge of the semiconductor chip and the sealing resin body.
  2. 　前記半導体チップの周縁部側面に形成される前記絶縁保護膜の厚みは、前記第２の主面側で薄く、前記第１の主面側に近付くほど厚くなる
    ことを特徴とする請求項１に記載のパワー半導体装置。     The thickness of the insulating protective film formed on the side surface of the peripheral portion of the semiconductor chip is thin on the second main surface side, and becomes thicker as it approaches the first main surface side. The power semiconductor device described.
  3. 　前記第１導電型の半導体層は、ｐ型半導体層であり、前記第２導電型の不純物拡散層は、ｎ型不純物拡散層である
    ことを特徴とする請求項１に記載のパワー半導体装置。     2. The power semiconductor device according to claim 1, wherein the first conductivity type semiconductor layer is a p-type semiconductor layer, and the second conductivity type impurity diffusion layer is an n-type impurity diffusion layer.
  4. 　前記第１導電型の半導体層は、ｎ型半導体層であり、前記第２導電型の不純物拡散層は、ｐ型不純物拡散層である
    ことを特徴とする請求項１に記載のパワー半導体装置。     2. The power semiconductor device according to claim 1, wherein the first conductivity type semiconductor layer is an n-type semiconductor layer, and the second conductivity type impurity diffusion layer is a p-type impurity diffusion layer.
  5. 　上位電位側ダイオード素子および下位電位側ダイオード素子の直列接続回路が複数個組み合わされてなるダイオードブリッジ回路含んで構成され、
    　前記上位電位側ダイオード素子として、請求項３に記載のパワー半導体装置を用い、前記下位電位側ダイオード素子として、請求項４に記載のパワー半導体装置を用いてなる
    ことを特徴とする整流装置。     A diode bridge circuit comprising a combination of a plurality of series connection circuits of upper potential side diode elements and lower potential side diode elements,
    A rectifier using the power semiconductor device according to claim 3 as the upper potential side diode element and using the power semiconductor device according to claim 4 as the lower potential side diode element.
  6. 　回転発電機と、請求項５に記載の整流装置とを含んでなる
    ことを特徴とする電源装置。     A power supply device comprising: a rotary generator; and the rectifier according to claim 5.
  7. 　導電性を有する半導体層からなる半導体基板の第１の主面側に、前記半導体層に対しショットキ障壁を有する金属層が形成された半導体チップと、
    　上部に平坦な保持面を有し、前記第１の主面を下に向けた前記半導体チップを前記保持面上に保持するとともに、前記第１の主面に形成された前記金属層が導電性の接合材を介して前記保持面に接合されるベース電極体と、
    　前記第１の主面の反対側の主面である第２の主面を構成する前記半導体層に、導電性の接合材を介して接合されるリード電極体と、
    　前記ベース電極体と前記リード電極体との間に挟まれた前記半導体チップを封止する封止樹脂体と
    を備え、
    　前記半導体チップ内の前記半導体層と前記金属層との境界に形成されるショットキ接合部は、前記第２の主面よりも前記第１の主面に近い位置に形成されており、
    　前記半導体チップの周縁部と前記封止樹脂体との間には、絶縁保護膜が形成されている
    ことを特徴とするパワー半導体装置。     A semiconductor chip in which a metal layer having a Schottky barrier with respect to the semiconductor layer is formed on a first main surface side of a semiconductor substrate made of a conductive semiconductor layer;
    The semiconductor chip having a flat holding surface at the top, holding the semiconductor chip with the first main surface facing down on the holding surface, and the metal layer formed on the first main surface being conductive A base electrode body bonded to the holding surface via the bonding material of
    A lead electrode body bonded to the semiconductor layer constituting the second main surface, which is the main surface opposite to the first main surface, via a conductive bonding material;
    A sealing resin body for sealing the semiconductor chip sandwiched between the base electrode body and the lead electrode body;
    The Schottky junction formed at the boundary between the semiconductor layer and the metal layer in the semiconductor chip is formed at a position closer to the first main surface than the second main surface,
    An insulating protective film is formed between a peripheral edge of the semiconductor chip and the sealing resin body.
  8. 　前記半導体チップの周縁部側面に形成される前記絶縁保護膜の厚みは、前記第２の主面側で薄く、前記第１の主面側に近付くほど厚くなる
    ことを特徴とする請求項７に記載のパワー半導体装置。     The thickness of the insulating protective film formed on the side surface of the peripheral portion of the semiconductor chip is thin on the second main surface side, and becomes thicker as it approaches the first main surface side. The power semiconductor device described.
  9. 　前記半導体層は、ｐ型半導体層である
    ことを特徴とする請求項７に記載のパワー半導体装置。     The power semiconductor device according to claim 7, wherein the semiconductor layer is a p-type semiconductor layer.
  10. 　前記半導体層は、ｎ型半導体層である
    ことを特徴とする請求項７に記載のパワー半導体装置。     The power semiconductor device according to claim 7, wherein the semiconductor layer is an n-type semiconductor layer.
  11. 　上位電位側ダイオード素子および下位電位側ダイオード素子の直列接続回路が複数個組み合わされてなるダイオードブリッジ回路含んで構成され、
    　前記上位電位側ダイオード素子として、請求項９に記載のパワー半導体装置を用い、前記下位電位側ダイオード素子として、請求項１０に記載のパワー半導体装置を用いてなる
    ことを特徴とする整流装置。     A diode bridge circuit comprising a combination of a plurality of series connection circuits of upper potential side diode elements and lower potential side diode elements,
    A rectifier using the power semiconductor device according to claim 9 as the upper potential side diode element and using the power semiconductor device according to claim 10 as the lower potential side diode element.
  12. 　回転発電機と、請求項１１に記載の整流装置とを含んでなる
    ことを特徴とする電源装置。     A power supply device comprising: a rotary generator; and the rectifier according to claim 11.
PCT/JP2013/083109 2012-12-11 2013-12-10 Power semiconductor device, rectifier device, and power source device WO2014092089A1 (en)

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