JPS63150954A - Bridge type semiconductor device - Google Patents

Bridge type semiconductor device

Info

Publication number
JPS63150954A
JPS63150954A JP61297514A JP29751486A JPS63150954A JP S63150954 A JPS63150954 A JP S63150954A JP 61297514 A JP61297514 A JP 61297514A JP 29751486 A JP29751486 A JP 29751486A JP S63150954 A JPS63150954 A JP S63150954A
Authority
JP
Japan
Prior art keywords
type
semiconductor substrate
planar
semiconductor device
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61297514A
Other languages
Japanese (ja)
Inventor
Yoshimasa Kudo
工藤　好正
Toshiyuki Miyata
敏幸 宮田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61297514A priority Critical patent/JPS63150954A/en
Publication of JPS63150954A publication Critical patent/JPS63150954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the yield of a bridge type semiconductor device by forming 2 planar type elements of the same polarity separated by a separating region in a semiconductor substrate, forming planar type elements of different polarity in other semiconductor substrate, connecting electrodes disposed substantially along a horizontal direction by metal fine wirings, and integrating them by a sealing resin layer. CONSTITUTION:When P is diffused after a separating region forming opening is formed so as to form a P-type diode and then an N<+> type separating region 3 is formed, the P is also diffused from the other whole surface of an N<-> type silicon semiconductor substrate. After two openings for forming P<+> type regions are then formed by a photolithography method on a silicon oxide layer 2, B is diffused to form P<+> type regions 4, 4. After the diffusing steps are finished, the regions 4, 4, N<+> type regions 5, 5 and the other surface of the N<-> type silicon semiconductor substrate are covered with a conductive metal, such as V-Ni-Au to form electrodes 7, 8. After a planar type element is secured to die stages 10, 10 formed at lead frames 9, 9, the diodes are connected by metal fine wirings 11, 11 therebetween, positive and negative poles and an AC terminal are provided, and sealed by resin 12.

Description

【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は電源整流用半導体装置に関し、特に小型のブリ
ッジ型半導体装置に好適する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device for power rectification, and is particularly suitable for a small bridge type semiconductor device.

（従来の技術） 電源整流に適用する半導体素子既ちダイオードはいわゆ
るメサ構造を持ちそのベベル面には鉛もしくは亜鉛ガラ
スを被着し、これをリードフレームにマウント後封止樹
脂層によって一体とする手法が一般的である。(Prior art) Semiconductor elements used for power rectification, such as diodes, have a so-called mesa structure, and their beveled surfaces are coated with lead or zinc glass, which is mounted on a lead frame and then integrated with a sealing resin layer. The method is common.

第８図に示す断面図により説明すると、１０１０１４ａ
ｔｏ／ｃｃ程度のＮ−型シリコン半導体基板３０を準備
し、その両面からＰ型不純物ならびにＮ型不純物を導入
して１ｏ２０′″”ａｔｏｍｓ／ｃｃのＰ十導電型領域
３２及び１０”ａｔｏｍｓ／ｃｃオーダのＮ÷導電型領
域３１を形成し、各領域の境界に形成されるＰＮ接合端
を半導体基板３０の側面に露出する。更にこの側面には
傾斜をつけて正ベベル面（機種によっては逆ベベル面を
設置する）を設け、前述のようにこゝに鉛ガラスもしく
は亜鉛ガラス３３を被着してパッシベーション（Ｐａｓ
ｓｉｖａｔｉｏｎ）層として機能させる。又半導体即ち
ダイオードとしての動作を発揮するために導電性金属も
しくは合金によってガラス層形成後電極３４．３５をこ
−のパッシベーション層と重ならないように半導体基板
表面に形成する。To explain with the cross-sectional view shown in FIG. 8, 101014a
Prepare an N-type silicon semiconductor substrate 30 of approximately 1.0 to/cc, and introduce P-type impurities and N-type impurities from both sides of the substrate to form a P conductivity type region 32 of 1020'''''atoms/cc and a P10 conductivity type region 32 of 10''atoms/cc. A conductivity type region 31 of the order of N divided by conductivity type is formed, and the PN junction end formed at the boundary of each region is exposed on the side surface of the semiconductor substrate 30. Further, this side surface is sloped to have a positive bevel surface (depending on the model, a reverse bevel surface). A beveled surface is provided, and lead glass or zinc glass 33 is coated on this as described above to provide passivation.
sivation) layer. Further, in order to exhibit the operation as a semiconductor, that is, a diode, after forming a glass layer of a conductive metal or alloy, electrodes 34 and 35 are formed on the surface of the semiconductor substrate so as not to overlap with this passivation layer.

このようにして製造されるダイオードは約１ｍｍ角と極
めて小型であるが、その組立にはリードフレームならび
にコネクターを利用して、ブリッジ回路形成に必要な４
個のダイオードを縦方向にマウントする方法が一般的で
ある。第５図に示すように２個のリードフレーム３６．
３７を用意し、その一方のり−ド３８・・・はコネクタ
ー３９ならびに４０と導電的に接続し、リードフレーム
３６のり−ド４１の先端に設けるダイステージ４２を境
としてダイオード４３・・・を設置する。The diodes manufactured in this way are extremely small, measuring approximately 1 mm square, but their assembly requires the use of lead frames and connectors to form the 4 diodes required to form a bridge circuit.
A common method is to mount several diodes vertically. As shown in FIG. 5, two lead frames 36.
37 is prepared, one of the leads 38... is conductively connected to the connectors 39 and 40, and diodes 43... are installed with the die stage 42 provided at the tip of the lead frame 36 lead 41 as the boundary. do.

このダイオード４３・・・の固着に当っては第７図に示
すように、半田タブレット４４．４４をコネクタ３９゜
３９に設置後ダイオード４３．４３を重ね更に半田タブ
レット４４．４４をこ＼に乗せ、次にリードフレーム３
６に形成するリード４１．４１端部に位置するダイステ
ージ４２．４２、更に又半田タブレットならびにコネク
ター４０を配置してから炉内で半田を溶融冷却して一体
化する。To fix the diodes 43, as shown in Fig. 7, after installing the solder tablets 44 and 44 on the connector 39°39, stack the diodes 43 and 43, and then place the solder tablets 44 and 44 on top of each other. , then lead frame 3
A die stage 42, 42 located at the end of the lead 41, 41 formed at 6, a solder tablet and a connector 40 are placed, and then the solder is melted and cooled in a furnace to be integrated.

この組立におけるダイオードの配置はダイステージ４２
の表面（上方）にはＰ型ダイオード２個の底部電極を半
田タブレットを介して更にコネクター３９表面にｎ型ダ
イオード２個を半田タブレットを介して設けるので、ダ
イステージ４２の裏面はｎ型ダイオードの上部電極と半
田を介して接続することになる。The arrangement of the diodes in this assembly is the die stage 42.
The bottom electrodes of two P-type diodes are provided on the surface (upper side) of the connector 39 via a solder tablet, and the bottom electrodes of two N-type diodes are provided on the surface of the connector 39 via a solder tablet. It will be connected to the upper electrode via solder.

従ってＰ型ダイオード４３．４３、コネクタ４０、に接
続するリードフレーム３７のリード３８が■端子、Ｎ型
ダイオード４３．４３、コネクタ３９に接続するリード
フレーム３７のリード３８がｅ端子そしてリードフレー
ム３６のダイステージ４２．４２に接続するリード４１
．４１が交流端子を構成することになる。Therefore, the lead 38 of the lead frame 37 connected to the P-type diode 43.43 and the connector 40 is the ■ terminal, and the lead 38 of the lead frame 37 connected to the N-type diode 43.43 and the connector 39 is the e terminal. Lead 41 connected to die stage 42.42
．． 41 constitutes an AC terminal.

このような配置をもつ単位体を封止樹脂層４４で被覆し
てからリードフレームを切断しリードを成形してブリッ
ジ型半導体装置Ｕを完成する。After covering the unit body having such an arrangement with a sealing resin layer 44, the lead frame is cut and leads are formed to complete the bridge type semiconductor device U.

（発明が解決しようとする問題点） 前述のように１■角と極めて小型のダイオードを縦方向
に積重ねしかもコネクター、ダイステージならびに半田
タブレットを間に挿入しなければならないので、組立の
位置出しは極めて蓮かしく、従って治具゛を利用せざる
を得ない。このためセットに要する時間が長くてコスト
アップの基になるほかに、この治具内に各部品を収納す
るためにどうしても精度が悪く、半田がズした場合には
短絡事故につながって歩留り低下を起す難点がある。(Problems to be Solved by the Invention) As mentioned above, extremely small square diodes must be stacked vertically, and the connector, die stage, and solder tablet must be inserted between them, so positioning for assembly is difficult. It is extremely complicated, so a jig must be used. For this reason, not only does it take a long time to set up, which increases costs, but the accuracy is poor because each part is housed in this jig, and if the solder slips, it can lead to short circuits and lower yields. There are some difficulties that arise.

本発明は上記難点を除去する新規なブリッジ型半導体装
置を提供することを目的とする。An object of the present invention is to provide a novel bridge type semiconductor device that eliminates the above-mentioned difficulties.

〔発明の構成〕[Structure of the invention]

（問題点を解決するための手段） この目的を達成するのに本発明に係るブリッジ型半導体
装置では半導体基板内に分離領域で隔たてられた極性が
同一のプレーナ型素子２個を形成し、他の半導体基板に
も同様な手法で前記極性と異なる極性をもつプレーナ型
素子を設けてから。(Means for Solving the Problem) In order to achieve this object, in the bridge type semiconductor device according to the present invention, two planar type elements having the same polarity and separated by a separation region are formed in the semiconductor substrate. , After providing planar type elements having a polarity different from the above polarity on other semiconductor substrates using the same method.

水平方向にほぼ沿って配置する雨プレーナ型素子の電極
間を金属製細線で接続し、更にこれらを封止樹脂層によ
って一体化する手法を採用した。A method was adopted in which the electrodes of the rain planar type elements, which are arranged almost horizontally, are connected with thin metal wires, and then these are integrated with a sealing resin layer.

（作　用） 従来は約ＩＩ角の同極性のダイオード２個からなる１対
の単位体をフレームもしくはコネクターに固着して縦方
向に組立る方式から、本発明では水平方向にほぼ沿って
配置するプレーナ型素子の電極間を金属細線により接続
し、樹脂によって封止して一体化する手法を採用したの
で、組立工程でのマウント精度が向上しひいては歩留り
を改善することが可能になる。(Function) Conventionally, a pair of units consisting of two diodes of the same polarity each having a diameter of about 2 mm are fixed to a frame or a connector and assembled in the vertical direction, but in the present invention, they are arranged substantially along the horizontal direction. Since we adopted a method of connecting the electrodes of the planar element with thin metal wires and sealing them with resin to integrate them, it is possible to improve mounting accuracy during the assembly process and, in turn, improve yield.

（実施例） 第１図乃至第４図により本発明の実施例を詳述する。(Example) Embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4.

前述のように本発明に係るブリッジ型半導体装置では分
離領域を形成したプレーナ型素子を適用しており、その
断面図を第３図ならびに第４図に示す。既ち１０１０１
４ａｔｏ／ｃｃ程度の表面濃度を持っＮ−シリコン半導
体基板１を出発材料とし、その−表面付近には通常の熱
酸化法によりシリコン酸化物層２を厚さ１００００人程
度被覆する。As described above, the bridge type semiconductor device according to the present invention uses a planar type element in which an isolation region is formed, and cross-sectional views thereof are shown in FIGS. 3 and 4. Already 10101
An N-silicon semiconductor substrate 1 having a surface concentration of about 4ato/cc is used as a starting material, and the vicinity of its surface is coated with a silicon oxide layer 2 to a thickness of about 10,000 by a conventional thermal oxidation method.

この後の工程は第３図及び第４図のプレーナ型半導体素
子によって相違する。The subsequent steps differ depending on the planar semiconductor device shown in FIGS. 3 and 4.

第３図のようにＰ型ダイオードを形成するに当っては分
離領域形成用開孔を設けてからＰを拡散して表面濃度が
１１０１９ａｔｏ／ｃｃ程度のＮ十分前領域３を形成す
るが、この時Ｎ−シリコン半導体基板の地表面全面から
もＰを拡散する。As shown in Fig. 3, when forming a P-type diode, an opening for forming an isolation region is provided, and then P is diffused to form a region 3 sufficiently in front of N with a surface concentration of about 11019ato/cc. At the same time, P is also diffused from the entire ground surface of the N-silicon semiconductor substrate.

次にシリコン酸化物層２にはＰ中領域形成用開孔２個を
フォトリングラフィ法によって設けてからＢを拡散して
表面濃度１０２０〜”　’　ａｔｏｍｓ／ｃｃのＰ中領
域４．４を設置するが、Ｎ−シリコン半導体基板１との
間に得られるＰＮ接合端はこのＮ′″シリコン半湛体基
板表面に露出し、シリコン酸化物層２で保護される。こ
の結果Ｐ中領域４．４は分離領域３で完全に分離した構
造となる。Next, in the silicon oxide layer 2, two openings for forming a P medium region are formed by photolithography, and then B is diffused to form a P medium region 4.4 with a surface concentration of 1020~'' atoms/cc. However, the PN junction end obtained with the N-silicon semiconductor substrate 1 is exposed on the surface of this N''' silicon semi-containing substrate and protected by the silicon oxide layer 2. As a result, the P middle region 4.4 has a structure completely separated by the separation region 3.

一方、第４図に示すプレーナ型半導体素子にはＮ中領域
５を設置するのでＰ十型分離領域６が必要となり、従っ
てこれより不純物濃度の低いＮ中領域５を先ず形成する
。そのためにはシリコン酸化物層２にＮ中領域用開口を
２個設けてから、Ｐを拡散して表面濃度１０１ｇａｔｏ
ｍｓ／ｃｃ程度のＮ中領域５を形成し、この結果発生す
るＰＮ接合端をシリコン酸化物層２により保護する。次
に不純物濃度の大きいＰ十型分離領域６の形成に移行す
る。On the other hand, in the planar semiconductor device shown in FIG. 4, since the N medium region 5 is provided, the P 10-type isolation region 6 is required, and therefore the N medium region 5 having a lower impurity concentration is formed first. To do this, two openings for the N middle region are provided in the silicon oxide layer 2, and then P is diffused to achieve a surface concentration of 101gato.
A N medium region 5 of approximately ms/cc is formed, and the resulting PN junction end is protected by a silicon oxide layer 2. Next, the process moves on to forming a P-type isolation region 6 having a high impurity concentration.

この場合には第３図と同様にＮ−型半導体基板１の表面
を被覆するシリコン酸化物層２の所定位置を通常のフォ
トリソグラフィ工程によって開孔してからＢを拡散して
表面濃度がｔｏ”’″”　’　ａｔｏｍｓ／ｃｃのピ分
離領域６を形成する。この拡散工程はＮ−シリコン半導
体基板の両表面から実施し、特に地表面は全面からＢを
導入するがこの拡散工程ではＮ÷領域５．５にその拡散
工程的に形成する酸化膜を拡散マスクに利用する。In this case, similarly to FIG. 3, holes are opened at predetermined positions in the silicon oxide layer 2 covering the surface of the N-type semiconductor substrate 1 by a normal photolithography process, and then B is diffused to bring the surface concentration to ``'''''' Form the isolation region 6 of atoms/cc. This diffusion process is carried out from both surfaces of the N-silicon semiconductor substrate, and in particular, B is introduced from the entire surface of the ground surface. The oxide film formed in the region 5.5 during the diffusion process is used as a diffusion mask.

これらの拡散工程終了後Ｐ中領域４．４、Ｎ÷領域５．
５ならびにＮ−シリコン半導体基板の地表面には導電性
金属例えばＶ−Ｎｉ−Ａｕを被着して電極７．８を設け
てプレーナ型ダイオード即ちプレーナ型素子を完成する
。After completing these diffusion steps, P middle area 4.4, N÷ area 5.
A conductive metal such as V--Ni--Au is deposited on the ground surface of the silicon semiconductor substrates 5 and 7 to form electrodes 7 and 8, thereby completing a planar diode or element.

このように１対のＰ型ダイオードならびにＮ＋ダイオー
ドを分離領域によって隔だてたプレーナ型素子は第１図
及第２図に示すようにリードフレーム９．９に設けるダ
イステージ１０．１０に固着後この金属細線１１．１１
によって両ダイオード間を連結して■極、○極及び交流
端子〜を設けてブリッジ回路を構成し、このような組立
体を樹脂１２により封止してハイブリッド型半導体装置
を完成する。The planar type device in which a pair of P-type diodes and N+ diodes are separated by a separation region is fixed to a die stage 10.10 provided on a lead frame 9.9, as shown in FIGS. 1 and 2. This thin metal wire 11.11
A bridge circuit is constructed by connecting both diodes and providing poles 1, 2, and AC terminals, and this assembly is sealed with resin 12 to complete a hybrid semiconductor device.

尚第１図ではリードフレーム９に設けるダイステージ１
０はいわゆるデプレス構造のものを示した。In addition, in FIG. 1, the die stage 1 provided on the lead frame 9 is
0 indicates a so-called depressed structure.

〔発明の効果〕〔Effect of the invention〕

本発明によるブリッジ型半導体装置はリードフレームに
プレーナ型半導体素子をマウンタ、ならびにボンダーを
利用して組立る手法が採用可能となって作業時間の大幅
な短縮をもたらし、更に約ｌｎｏ角と小型なプレーナ型
素子を確実にマウントしてその精度向上を図ることによ
って、半田ズレなどを完全に解消されて歩留りを大幅に
改善するものである。The bridge type semiconductor device according to the present invention can be assembled using a mounter and a bonder for planar semiconductor elements on a lead frame, resulting in a significant reduction in working time. By reliably mounting the mold element and improving its precision, solder misalignment and the like can be completely eliminated and yields can be significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に係るブリッジ型半導体装置の要部を示
す上面図第２図は第１図に示す半導体装置の断面図第３
図ならびに第４図はプレーナ型素子の断面構造を示す同
第５図は従来のブリッジ型半導体装置の組立工程を示す
斜視図第６図は従来のブリッジ型半導体装置の一部切欠
斜視図第７図は半導体素子の組立方法を示す同第８図は
従来のブリッジ型半導体装置に適用するメサ型ダイオー
ドの断面図である。FIG. 1 is a top view showing essential parts of a bridge type semiconductor device according to the present invention. FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1.
5 and 4 show a cross-sectional structure of a planar type element.FIG. 5 is a perspective view showing the assembly process of a conventional bridge type semiconductor device.FIG. 6 is a partially cutaway perspective view of a conventional bridge type semiconductor device. The figure shows a method of assembling a semiconductor element. FIG. 8 is a sectional view of a mesa diode applied to a conventional bridge type semiconductor device.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板と、こゝに形成する同極性をもつ１対のプレ
ーナ型素子と、他の半導体基板と、この他の半導体基板
に設け前記極性と異なるそれをもつ１対のプレーナ型素
子と、異極性の前記プレーナ型素子を接続する金属細線
と、水平方向に沿って配置する両半導体装置を一体にす
る樹脂封止層とを具備することを特徴とするブリッジ型
半導体装置。A semiconductor substrate, a pair of planar elements having the same polarity formed thereon, another semiconductor substrate, a pair of planar elements formed on the other semiconductor substrate and having a polarity different from the above-mentioned polarity; A bridge type semiconductor device comprising: a thin metal wire connecting the polar planar type elements; and a resin sealing layer disposed along the horizontal direction and integrating both semiconductor devices.
JP61297514A 1986-12-16 1986-12-16 Bridge type semiconductor device Pending JPS63150954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61297514A JPS63150954A (en) 1986-12-16 1986-12-16 Bridge type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61297514A JPS63150954A (en) 1986-12-16 1986-12-16 Bridge type semiconductor device

Publications (1)

Publication Number Publication Date
JPS63150954A true JPS63150954A (en) 1988-06-23

Family

ID=17847500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61297514A Pending JPS63150954A (en) 1986-12-16 1986-12-16 Bridge type semiconductor device

Country Status (1)

Country Link
JP (1) JPS63150954A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218231A (en) * 1989-08-30 1993-06-08 Kabushiki Kaisha Toshiba Mold-type semiconductor device
US5541683A (en) * 1993-12-02 1996-07-30 Fuji Photo Film Co., Ltd. Instant film pack and instant camera
JP2004506326A (en) * 2000-08-04 2004-02-26 ローベルト　ボツシユ　ゲゼルシヤフト　ミツト　ベシユレンクテル　ハフツング Method for electrically connecting a semiconductor component to an electrical component group
CN102157471A (en) * 2010-12-29 2011-08-17 常州星海电子有限公司 Dual-layer laminated patch rectifying full bridge
WO2014092089A1 (en) * 2012-12-11 2014-06-19 株式会社 日立パワーデバイス Power semiconductor device, rectifier device, and power source device
CN106684065A (en) * 2016-09-07 2017-05-17 四川上特科技有限公司 Novel integrated Mini rectifier bridge structure and fabrication process thereof
CN111261626A (en) * 2019-12-13 2020-06-09 上海晶丰明源半导体股份有限公司 Chip packaging structure adopting multi-base-island lead frame

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218231A (en) * 1989-08-30 1993-06-08 Kabushiki Kaisha Toshiba Mold-type semiconductor device
US5541683A (en) * 1993-12-02 1996-07-30 Fuji Photo Film Co., Ltd. Instant film pack and instant camera
JP2004506326A (en) * 2000-08-04 2004-02-26 ローベルト　ボツシユ　ゲゼルシヤフト　ミツト　ベシユレンクテル　ハフツング Method for electrically connecting a semiconductor component to an electrical component group
JP4800556B2 (en) * 2000-08-04 2011-10-26 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Method for electrically connecting a semiconductor component with an electrical component group
CN102157471A (en) * 2010-12-29 2011-08-17 常州星海电子有限公司 Dual-layer laminated patch rectifying full bridge
WO2014092089A1 (en) * 2012-12-11 2014-06-19 株式会社 日立パワーデバイス Power semiconductor device, rectifier device, and power source device
CN106684065A (en) * 2016-09-07 2017-05-17 四川上特科技有限公司 Novel integrated Mini rectifier bridge structure and fabrication process thereof
CN111261626A (en) * 2019-12-13 2020-06-09 上海晶丰明源半导体股份有限公司 Chip packaging structure adopting multi-base-island lead frame

Similar Documents

Publication Publication Date Title
US20060223199A1 (en) Semiconductor device and manufacturing method thereof
TWI395277B (en) Wafer level chip scale packaging
US20060220214A1 (en) Semiconductor device and manufacturing method thereof
KR100272686B1 (en) Semiconductor device and method for manufacturing the same
JPH0671062B2 (en) Resin-sealed semiconductor device
KR20070083857A (en) Solderable top metal for sic device
US5034345A (en) Method of fabricating a bump electrode for an integrated circuit device
EP1906452A1 (en) Semiconductor device and method for manufacturing same
JPH0832060A (en) Semiconductor integrated circuit device and manufacture thereof
JPS63150954A (en) Bridge type semiconductor device
US7368380B2 (en) Method of manufacturing semiconductor device
JP3895884B2 (en) Semiconductor device
JP3432708B2 (en) Semiconductor devices and semiconductor modules
JPH01194439A (en) Manufacture of semiconductor device
JPH06177242A (en) Semiconductor integrated circuit device
US3581166A (en) Gold-aluminum leadout structure of a semiconductor device
TW497232B (en) Semiconductor device and method of manufacturing the same
JP4017625B2 (en) Manufacturing method of semiconductor device
JP2007073987A (en) Semiconductor module
JPS6269564A (en) Semiconductor device
JPH09307103A (en) Composite type semiconductor device and its manufacture
JPS6158248A (en) Thin type semiconductor device
JP2754969B2 (en) Semiconductor device having bump formation region
JPH05326844A (en) Semiconductor integrated circuit
JP2526534Y2 (en) Shot barrier diode device