WO2015104808A1 - Dispositif à semi-conducteurs de puissance et dispositif de conversion de puissance - Google Patents

Dispositif à semi-conducteurs de puissance et dispositif de conversion de puissance Download PDF

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Publication number
WO2015104808A1
WO2015104808A1 PCT/JP2014/050182 JP2014050182W WO2015104808A1 WO 2015104808 A1 WO2015104808 A1 WO 2015104808A1 JP 2014050182 W JP2014050182 W JP 2014050182W WO 2015104808 A1 WO2015104808 A1 WO 2015104808A1
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Prior art keywords
power semiconductor
insulating resin
ceramic
resin
insulating
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PCT/JP2014/050182
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English (en)
Japanese (ja)
Inventor
順平 楠川
英一 井出
円丈 露野
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株式会社日立製作所
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Priority to PCT/JP2014/050182 priority Critical patent/WO2015104808A1/fr
Publication of WO2015104808A1 publication Critical patent/WO2015104808A1/fr

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a power semiconductor device used for a power conversion device such as an inverter device.
  • the needs for these power conversion devices include a reduction in cost, a reduction in installation area, and high reliability.
  • the power conversion device is composed of a power semiconductor device (power module) incorporating a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), as well as a number of components such as a control circuit, a bus bar, a coil, and a capacitor. Yes.
  • a technology for reducing the size and reliability of the power semiconductor device that is the main component of the power conversion device is important.
  • Al 2 O 3 aluminum oxide
  • AlN aluminum nitride
  • SiN silicon nitride
  • a conductive plate such as a copper foil is pasted on both sides via a brazing material. Then, the conductive plate is etched to form a circuit electrode and a back electrode, and a ceramic substrate with a circuit electrode is obtained.
  • solder (solder) paste is apply
  • a power semiconductor element is an element that switches a current of several amperes to several hundred amperes, and the element generates heat.
  • the quality of the heat generated by the element heat greatly affects the downsizing and reliability of the device.
  • heat generated by the power semiconductor element is dissipated from one surface of the element. Therefore, the heat dissipation performance is low, and there is a limit to the miniaturization and reliability of the power semiconductor device. For this reason, in recent years, power semiconductor devices having a double-sided cooling structure in which electrodes, insulating plates, and heat sinks are attached to both surfaces of the power semiconductor element to dissipate heat generated in the power semiconductor element from both surfaces of the element have been developed.
  • Patent Document 1 discloses a semiconductor device cooling structure in which a semiconductor device having a pair of heat sinks on both surfaces of a power semiconductor element and molded with resin almost entirely is in contact with a cooler via an insulating material.
  • Patent Document 2 includes two high thermal conductive insulating substrates which are provided so as to sandwich a semiconductor chip, and are provided with electrode patterns for bonding to the electrodes of the semiconductor chip on each sandwiching surface. The technology of the semiconductor device is disclosed.
  • Patent Document 3 discloses a power semiconductor element, a first heat radiating plate provided on one side of the power semiconductor element, a second heat radiating plate provided on a surface side opposite to the one surface, A technology of a power semiconductor module provided with a flow path through which a refrigerant flows so as to be in contact with the first and second heat radiating plates, respectively, is disclosed.
  • the present invention solves such a problem, and the object is to prevent peeling at the interface between the ceramic substrate (ceramic insulating substrate) and the insulating resin and to have high reliability.
  • a semiconductor device and a power conversion device are provided.
  • the present invention is configured as follows. That is, the power semiconductor device of the present invention includes a power semiconductor element, at least one ceramic insulating circuit board having a circuit electrode formed on a ceramic substrate, at least one electrode surface of the power semiconductor element, and the ceramic insulating circuit.
  • a second insulating resin having an adhesive strength higher than that of the first insulating resin.
  • the second insulating resin has an adhesive strength higher than that of the first insulating resin.
  • the present invention it is possible to provide a semiconductor device and a power conversion device that can prevent peeling at the interface between the ceramic substrate and the insulating resin and have high reliability.
  • FIG. 1 is a schematic plan view of a vicinity of main components of a power semiconductor device according to a first embodiment of the present invention as viewed from above. It is a figure which shows the cross-section of the power semiconductor device of a comparative example.
  • FIG. 1 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the first embodiment of the present invention.
  • a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A are provided to constitute a first ceramic insulating circuit substrate 23A.
  • the second ceramic insulating circuit board 23B is configured by including the ceramic substrate 2B, the circuit electrode 3B, and the back electrode 4B.
  • the heat generated by the first ceramic insulated circuit board 23A is radiated by the heat radiating base plate 19A and the heat conducting member 18A.
  • the heat radiating base plate 19B and the heat conducting member 18B are configured to radiate heat generated in the second ceramic insulated circuit board 23B.
  • the power semiconductor device 10 has a structure having a double-sided cooling structure. As shown in FIG. 1, the first ceramic insulated circuit board 23A and the second ceramic insulated circuit board 23B are arranged to face each other with the circuit electrodes 3A and the circuit electrodes 3B facing inward.
  • the power semiconductor element 11 made of IGBT or the like is connected to the first and second ceramic insulated circuit boards (23A and 23B) via a base 141 and solders 51A and 51B.
  • the power semiconductor element 12 is connected to the first and second ceramic insulated circuit boards (23A, 23B) via a pedestal 142, solders 52A, 52B, and the like.
  • the bus bars 8A, 8B, and 8G are connected to the power semiconductor element 11 and the first and second ceramic insulating circuit boards (23A and 23B) via solders 53A and 53B and wires 6G. .
  • the power semiconductor element 11 and the power semiconductor element 12 are separate chips as semiconductor chips.
  • the second insulating resin 17A is in contact with the circuit electrode 3A and the ceramic substrate 2A (ceramic insulating circuit substrate 23A) for insulation.
  • the second insulating resin 17B is in contact with the circuit electrode 3A and the ceramic substrate 2B (ceramic insulating circuit substrate 23A) for insulation.
  • the first insulating resin 16 includes second insulating resins 17A and 17B, ceramic insulating circuit boards 23A and 23B, power semiconductor elements 11 and 12, pedestals 141 and 142, and solders 51A, 51B, 52A, 52B, 53A, and 53B. Is covered and insulated.
  • the first insulating resin 16 covers and insulates part of the bus bars 8A, 8B, 8G.
  • circuit electrodes 3A and 3B have a notation that looks like a single metal body.
  • the circuit electrodes 3A and 3B are a plurality of circuit electrodes separated from each other to form an electric circuit. May be configured. Even when a plurality of circuit electrodes 3A and 3B are respectively formed, the plurality of circuit electrodes are formed on the same plane of the ceramic insulating circuit boards (23A and 23B). It is written in.
  • a ceramic insulated circuit board 23A is prepared in which a circuit electrode 3A is formed on one surface of a ceramic substrate 2A made of silicon nitride (SiN), and a back electrode 4A for heat dissipation is formed on the opposite surface.
  • a ceramic insulated circuit board 23B is prepared in which a circuit electrode 3B is formed on one surface of a ceramic substrate 2B made of silicon nitride (SiN), and a back electrode 4B for heat dissipation is formed on the opposite surface.
  • two ceramic insulating circuit boards (23A, 23B) on which the circuit electrodes (3A, 3B) and the back electrodes (4A, 4B) are formed are prepared.
  • a resin mainly composed of polyamideimide is applied to the whole. Then, the resin is cured at a predetermined temperature and time to form the second insulating resin (17A, 17B) on the ceramic insulating circuit boards (23A, 23B).
  • solders 51A, 52A, and 53A are formed at predetermined positions of the circuit electrode 3A of the ceramic insulating circuit board 23A located on the lower side of the first sheet. Then, on the solder (51A, 52A, 53A, etc.), the collector bus bar 8A, the control terminal bus bar 8G, and the power semiconductor element 11 are superimposed on the corresponding positions of the circuit electrode 3A, respectively. . (The actual configuration related to the notation of the control terminal bus bar 8G will be described later.) Then, by a reflow process through a reflow furnace (not shown), the first ceramic insulating circuit board 23A, the power semiconductor element 11, the collector bus bar 8A, and the control terminal bus bar 8G are joined. The gate terminal (not shown) and the control terminal bus bar 8G are connected by an aluminum thin wire 6G.
  • solder (51B, 52B, 53B, etc.) is formed at a predetermined position of the other ceramic insulated circuit board 23B, the emitter bus bar 8B and the base 141 are placed, and they are joined by a reflow process through a reflow furnace. . Then, solders 51B, 52B, 51C, and 52C are formed on the bases 141 and 142, and the emitter electrode (not shown) of the power semiconductor element 11 and the base 141 are formed so that the circuit electrodes 3B of the ceramic insulating circuit board 23B face each other. Align to match and join through reflow oven.
  • these joined circuit components are placed in a transfer mold (not shown), a molding material made of epoxy mold resin is injected, and a predetermined temperature and pressure are applied for a predetermined time.
  • the epoxy mold resin is thermally cured to form the first insulating resin 16 of the epoxy mold resin in which the entire power semiconductor element between the two ceramic insulated circuit boards 23A and 23B is insulated and sealed.
  • the back electrodes 4A, 4B of the two ceramic insulated circuit boards 23A, 23B and the heat radiating base plates 19A, 19B are joined via the heat conducting members 18A, 18B, thereby completing the power semiconductor device 10.
  • the first dielectric resin 16 had a relative dielectric constant of 4.0
  • the second dielectric resins 17A and 17B had a dielectric constant of 4.0.
  • the influence and effect of the difference between the relative dielectric constant of the first insulating resin 16 and the relative dielectric constant of the second insulating resins 17A and 17B will be described later.
  • FIG. 5 shows main components of the power semiconductor device 10 according to the first embodiment of the present invention (power semiconductor element 11, ceramic insulating circuit board 23A, heat radiation base plate 19A, circuit electrode 3A, control terminal bus bar 8G, collector. It is the schematic top view which looked at the neighborhood where bus bar 8A etc. are arranged from the upper surface. (FIG. 4 will be described later.) 5 is a diagram showing the relationship between the arrangement of the control terminal bus bar (control terminal) 8G and the collector bus bar 8A, and therefore, the illustration of the components other than those described above and the exact arrangement corresponding to FIG. 1 is omitted. ing.
  • the collector bus bar 8A and the control terminal bus bar 8G in FIG. 5 are located at the same height when viewed from the plane of the ceramic insulated circuit board 23A.
  • the control terminal bus bar 8G is hidden by the collector bus bar 8A and I can't show it. Therefore, in FIG. 1, in order to show that the control terminal bus bar 8G exists, for convenience, the control terminal bus bar 8G is shown at a position higher than the collector bus bar 8A. However, as described above, the control terminal bus bar 8G is the same height as the collector bus bar 8A, and a joining process or the like by solder (51A, 52A, 53A, etc.) is performed.
  • FIG. 2 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the second embodiment of the present invention.
  • the difference in the cross-sectional structure of the power semiconductor device 10 in FIG. 1 is the volume of the second insulating resins 17A and 17B and the contact area with the ceramic insulating circuit boards 23A and 23B.
  • the volume of the second insulating resins 17A and 17B in FIG. 2 and the contact area with the ceramic insulating circuit boards 23A and 23B are both smaller than those of the second insulating resins 17A and 17B in FIG.
  • the power semiconductor device 10 of FIG. 2 differs from FIG. ⁇ 1> Predetermined temperature, pressure, and time based on a resin in which the second insulating resins 17A and 17B are mainly composed of a polyamideimide resin and an alumina filler having an average particle size of 5 ⁇ m is mixed in the polyamideimide resin at a weight ratio of 30 wt%. It is formed by curing with.
  • the ceramic substrates 2A and 2B are made of aluminum nitride (AlN).
  • the ceramic substrates 2A and 2B of the first embodiment are made of silicon nitride (SiN) as described above.
  • the power semiconductor device 10 of FIGS. Description is omitted.
  • the relative dielectric constant of the first insulating resin 16 of the completed power semiconductor device 10 is 4.0
  • the relative dielectric constant of the second insulating resins 17A and 17B is 6.2. .
  • the characteristics and features of the second embodiment of FIG. 2 different from those of the first embodiment of FIG. 1 will be described later.
  • FIG. 3 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the third embodiment of the present invention.
  • the arrangement of the second insulating resins 17A and 17B is the arrangement of the second insulating resins 17A and 17B. That is, the ceramic substrates 2A and 2B applied to the end portions of the ceramic substrates 2A and 2B (ceramic insulating circuit substrates 23A and 23B) from a portion about 1 mm away from the peripheral ends of the circuit electrodes 3A and 3B of the ceramic insulating circuit substrates 23A and 23B. Second insulating resins 17A and 17B are respectively formed on the surfaces of
  • the power semiconductor device 10 of FIG. 1 differs from the power semiconductor device 10 of FIG. 1 in terms of material in that the second insulating resins 17A and 17B have a predetermined temperature and pressure based on a resin mainly composed of silicone. It is formed by curing with time. Except for the shapes and materials of the second insulating resins 17A and 17B, the power semiconductor device 10 of FIGS. 1 and 3 has the same shape, material, and manufacturing process, and therefore redundant description is omitted.
  • the first dielectric resin 16 of the completed power semiconductor device 10 has a relative dielectric constant of 4.0, and the second dielectric resins 17A and 17B have a dielectric constant of 2.8. .
  • the characteristics and features of the third embodiment of FIG. 3 different from those of the first and second embodiments of FIGS. 1 and 2 will be described later.
  • FIG. 6 is a diagram showing a cross-sectional structure of a power semiconductor device 20 of a comparative example. 6 differs from the power semiconductor device 10 according to the first embodiment of the present application shown in FIG. 1 in that the second insulating resins 17A and 17B in FIG. 1 are present in the comparative example shown in FIG. Is not to. Other components, materials, and manufacturing processes are the same. Therefore, the overlapping description is omitted.
  • the relative dielectric constant of the insulating resin (first insulating resin) of the completed power semiconductor device 20 of the comparative example was 4.0.
  • FIG. 7 is an enlarged view of the area S indicated by a broken line in FIG. Note that the shapes of the circuit electrode 3A and the back electrode 4A are described in a state closer to the actual state than FIG. 6, as will be described later.
  • the ceramic insulated circuit board (23A) includes a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A.
  • the heat conducting member 18A and the heat radiating base plate 19A are joined to the back electrode 4A of the ceramic insulated circuit board (23A).
  • the power semiconductor element 12 is joined to the circuit electrode 3A of the ceramic insulated circuit board (23A) and the pedestal 142 via the solder 52A and the solder 52C, respectively.
  • the first insulating resin 16 made of epoxy mold resin insulates and seals the ceramic insulated circuit board (23A) and the power semiconductor element 12.
  • the circuit electrode 3 ⁇ / b> A and the back electrode 4 ⁇ / b> A have acute angles at the ends as indicated by the hatched lines. This acute angle shape is due to the nature of the chemical reaction when the circuit electrode 3A and the back electrode 4A are formed by chemical etching.
  • the power semiconductor element (11, 12: FIG. 6) is provided with a pair of high thermal conductivity ceramic substrates (2A, 2B: FIG. 6) on both sides, and almost the entire apparatus is resin molded (first insulating resin 16: FIG. 6)
  • first insulating resin 16 FIG. 6
  • tensile stress acts between the two ceramic substrates (2A, 2B: FIG. 6) due to curing shrinkage of the mold resin. This is the reason why 7) is likely to occur.
  • the ceramic substrate 2A is formed by sintering an inorganic powder material of silicon nitride. Even if aluminum oxide or aluminum nitride is used instead of silicon nitride, the interfacial peeling is performed in the same manner. 99 may occur.
  • FIG. 8A is a diagram showing the equipotential lines of the electric field in the ceramic substrate 2A and the first insulating resin 16 in the region S (FIGS. 6 and 7) of the comparative example.
  • an equipotential line of an electric field is shown by a plurality of curve groups of thin lines.
  • the electric field is most concentrated (the interval between equipotential lines is narrow). Become.
  • dielectric breakdown and partial discharge are most likely to occur in the vicinity of the maximum electric field strength.
  • the electric field characteristics of the comparative example shown in FIG. 8A are characteristics when an SiN substrate is used for the ceramic substrate 2A and an epoxy mold resin having a relative dielectric constant of 4.0 is used for the first insulating resin 16. Based on this comparative example, the maximum electric field strength in the comparative example is used as a reference in order to compare with the characteristics of Examples 1, 2, and 3 described below. In FIG. 8A, since the comparative example is used as a reference for comparison, “maximum electric field strength ratio 1” is described. In addition, about the other part and structure in FIG. 8A, since description overlaps, it abbreviate
  • FIG. 8B is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 1 according to the first embodiment of the present invention. Since the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, FIG. The structure shown in FIG. 8B is different from the structure shown in FIG. 8A in that the second insulating resin 17A is provided. The second insulating resin 17A is provided at a location where the surface of the ceramic substrate 2A is not covered with the circuit electrode 3A. FIG. 8B corresponds to FIG. 1 describing the first embodiment.
  • the second insulating resin 17A is made of a material having higher adhesive strength to the ceramic substrate 2A than the first insulating resin 16 is. However, the relative dielectric constant of the second insulating resin 17A is 4.0, and the same dielectric constant as that of the first insulating resin 16 is used.
  • the form and characteristics of the equipotential lines of the electric field in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in FIG. 8B are almost the same as those in FIG. 8A as the comparative example.
  • the electric field is most concentrated (the equipotential lines are narrow), and the maximum electric field strength is obtained. A ratio of 1 is obtained.
  • Other overlapping explanations are omitted.
  • FIG. 8C is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 2 according to the second embodiment of the present invention. Note that the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, and therefore FIG.
  • the structure shown in FIG. 8C differs from the structure shown in FIG. 8B in that the length of the second insulating resin 17A in the direction in contact with the ceramic substrate 2A is shortened. 8C corresponds to FIG. 2 describing the second embodiment.
  • an AlN substrate is used as the ceramic substrate 2A.
  • the second insulating resin 17A is mainly composed of a polyamideimide resin, and is cured at a predetermined temperature, pressure, and time based on a resin in which an alumina filler having an average particle diameter of 5 ⁇ m is mixed in a polyamideimide resin at a weight ratio of 30 wt%. Is formed.
  • the relative dielectric constant of the first insulating resin 16 was 4.0
  • the relative dielectric constant of the second insulating resin 17A was 6.2.
  • FIG. 8D is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 3 according to the third embodiment of the present invention. Note that the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, so FIG.
  • the structure shown in FIG. 8D is different from the structure shown in FIG. 8B in that the second insulating resin 17A is in contact only with the ceramic substrate 2A and away from the end of the circuit electrode 3A.
  • FIG. 8D corresponds to FIG. 3 describing the third embodiment.
  • a SiN substrate is used for the ceramic substrate 2A.
  • the second insulating resin 17A is formed by curing at a predetermined temperature, pressure, and time based on a resin mainly composed of silicone. At this time, the relative dielectric constant of the first insulating resin 16 was 4.0, whereas the relative dielectric constant of the second insulating resin 17A was 2.8.
  • the first, second, and third embodiments of the present application are provided with the second insulating resins 17A and 17B, and are intended to increase the adhesive strength between the ceramic substrate 2A and the ceramic surface.
  • FIG. 9 shows the shear between the ceramic substrate (2A, 2B) and the mold resin (first insulating resin 16) for Examples 1, 2, 3 and Comparative Examples according to the first, second, and third embodiments of the present invention. It is a figure which shows an intensity
  • the comparative example, Examples 1, 2, and 3 are shown in order from the left in the horizontal axis direction, and the vertical axis indicates the shear strength ratio (pu: unit method) with the comparative example being the reference value 1. Have taken.
  • the shear strength of Examples 1, 2, and 3 is higher than that of the comparative example, and the adhesive strength with the ceramic insulating plate is increased by forming the second insulating resin.
  • a solid silicon nitride (SiN) ceramic substrate is prepared, and a resin (second insulating resin) mainly composed of polyamideimide is provided on one surface thereof. It was applied and cured under predetermined conditions. After that, the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm. A trapezoidal cylindrical specimen was prepared.
  • a solid aluminum nitride (AlN) ceramic substrate was prepared, and one surface thereof was mainly composed of a polyamideimide resin.
  • a resin in which an alumina filler having an average particle diameter of 5 ⁇ m and a weight ratio of 30 wt% was mixed was applied and cured at a predetermined temperature and time to form a second insulating resin on the ceramic insulating plate.
  • the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm.
  • a trapezoidal cylindrical specimen was prepared.
  • a solid silicon nitride (SiN) ceramic insulating plate is prepared, and a resin mainly composed of silicone is applied to one surface thereof,
  • the second insulating resin was formed on the ceramic insulating plate by curing at a predetermined temperature and time. After that, the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm.
  • a trapezoidal cylindrical specimen was prepared.
  • a solid silicon nitride (SiN) ceramic insulating plate is prepared as a configuration corresponding to the comparative example, a mold is placed on the ceramic insulating plate, and an epoxy mold resin (first insulating resin) is used.
  • a trapezoidal cylindrical specimen having a bottom surface diameter of 5 mm, a top surface diameter of 4 mm, and a height of 3 mm was prepared at a predetermined temperature, pressure, and time.
  • FIG. 9 shows the result of the test described above.
  • the first, second, and third embodiments (Examples 1, 2, and 3) having the second insulating resin have higher shear strength than the comparative examples having no second insulating resin.
  • the height of the shear strength varies depending on the materials of the second insulating resin and the ceramic substrate.
  • Example 1 in which the ceramic substrate is made of SiN and the second insulating resin is made of polyamideimide resin has the highest shear strength.
  • Example 3 in which the ceramic substrate is made of SiN and the second insulating resin is made of a resin mainly composed of silicone, the shear strength is next high.
  • the ceramic substrate is AlN
  • the second insulating resin is mainly composed of a polyamideimide resin
  • the polyamideimide resin is composed of a resin in which an alumina filler having an average particle diameter of 5 ⁇ m is mixed in a weight ratio of 30 wt%.
  • (2nd Embodiment) is a result lower than Example 1 and Example 3 about shear strength.
  • Example 1-3 has the second insulating resin that has a stronger adhesion to the ceramic substrate than the first insulating resin. This is considered to be the reason why the shear strength is increased. Moreover, it is thought that the difference in shear strength ratio is mainly caused by the difference in the material of the second insulating resin.
  • the collector lead (collector bus bar 8A, FIG. 1), emitter lead (emitter bus bar 8B, FIG. 1), and control terminal (control terminal bus bar) of the power semiconductor device (10, FIG. 1) are used. 8G, FIG. 1) was set to the same potential.
  • FIG. 10 is a diagram illustrating a result of performing a temperature cycle test on Examples 1, 2, 3 and the comparative example, and measuring a partial discharge voltage of the power semiconductor device every predetermined cycle.
  • the horizontal axis represents the cumulative number (cycle) of temperature cycle tests
  • the vertical axis represents the partial discharge start voltage at each temperature cycle.
  • the characteristic line 1000 represents a comparative example
  • the characteristic line 1001 represents Example 1
  • the characteristic line 1002 represents Example 2
  • the characteristic line 1003 represents Example 3.
  • ⁇ Temperature cycle test result of comparative example> As shown by the characteristic line 1000 in FIG. 10, in the comparative example, it was about 6 kVrms before the temperature cycle test, and no partial discharge occurred at less than 6 kVrms. However, after 200 cycles (cumulative number) of the temperature cycle test, the partial discharge start voltage was about 5.3 kVrms, and thereafter the partial discharge start voltage decreased with the progress of the test cycle. The reason why the partial discharge start voltage is lowered is that the adhesion between the ceramic substrates 2A and 2B and the epoxy mold resin which is the first insulating resin is peeled off to cause interface peeling, and partial discharge is generated at the peeling portion.
  • Example 1 ⁇ Results of temperature cycle test of Example 1> As shown by the characteristic line 1001 in FIG. 10, in Example 1, partial discharge did not occur at less than 6 kVrms before the temperature cycle test. And even after 1000 cycles (cumulative number) of the temperature cycle test, the occurrence of partial discharge was not seen at less than 6 kVrms. Note that the maximum electric field strength ratio of the electric field concentration portion in the comparative example of FIG. 8A is 1, and the maximum electric field strength ratio of the electric field concentration portion in the embodiment 1 of FIG. Thus, from the viewpoint of the maximum electric field strength, the partial discharge start voltage decreases in the comparative example (characteristic line 1000) in the temperature cycle test shown in FIG. In Example 1 (characteristic line 1001), the partial discharge start voltage is maintained.
  • Example 1 The reason why the comparative example deteriorates faster than Example 1 is that the second insulating resin is not present in the comparative example, so the first insulating resin 16 (FIGS. 7 and 8A) and the ceramic substrate 2A (FIGS. 7 and 8A) Peeling (interfacial peeling 99, FIG. 7) occurred, and as the cumulative number of temperature cycles increased, the peeling increased and the partial discharge start voltage decreased.
  • Example 1 since the second insulating resin 17A (FIG. 8B) is more firmly bonded to the ceramic substrate 2A than the first insulating resin 16 (FIG. 8B), peeling does not occur and partial discharge is caused. The starting voltage does not decrease.
  • Example 2 ⁇ Results of temperature cycle test of Example 2> As shown by the characteristic line 1002 in FIG. 10, in Example 2, the partial discharge start voltage was about 7.2 kVrms from the time before the temperature cycle test until the cumulative number of temperature cycles was about 400 times.
  • the second insulating resin 17A As described above, as the second insulating resin 17A (FIG. 8C), a polyamideimide resin is mainly used, and an alumina filler having an average particle diameter of 5 ⁇ m is added to the polyamideimide resin at a weight ratio of 30 wt%. A mixed resin is used.
  • Example 3 ⁇ Results of temperature cycle test of Example 3> As shown by the characteristic line 1003 in FIG. 10, in Example 3, the partial discharge start voltage was about 6.4 kVrms from before the temperature cycle test until the cumulative number of temperature cycles was about 800 times. This temperature cycle partial discharge start voltage (about 6.4 kVrms) is between the partial discharge start voltage of the comparative example and Example 1 (about 6 kVrms) and the partial discharge start voltage of Example 2 (about 7.2 kVrms). The value is shown. In the structure of Example 3, the maximum electric field strength ratio of the electric field concentration portion in FIG. 8D is 0.99, and the maximum electric field strength ratio of the comparative example of FIG. 8A and FIG. This corresponds to the value of the maximum electric field strength ratio of Example 2 in FIG. 8C being between 0.88.
  • Example 1-3 ⁇ Results of Temperature Cycle Test and Shear Strength Test of Example 1-3>
  • the second insulating resin 17A having an adhesive strength stronger than that of the first insulating resin 16 and having an appropriate relative dielectric constant is provided. It can be seen that the reliability is improved in the reliability test by the temperature cycle test. This improvement in reliability is achieved by the second insulating resin 17A (polyamideimide resin, silicone resin, etc.) having excellent adhesion to the ceramic between the ceramic substrate 2A and the first insulating resin 16 (epoxy mold resin). This is because interfacial peeling is prevented.
  • Example 2 had the highest partial discharge start voltage from 0 to 1000 times, followed by Example 3 and then Example 1. Met.
  • Example 1 had the strongest shear strength, followed by Example 3 and then Example 2.
  • the order of these desirable properties does not necessarily match between the shear strength test of FIG. 9 and the partial cycle start voltage temperature cycle test of FIG. That is, the selection of the optimal structure and material of the second insulating resin 17A differs depending on whether priority is given to the strength characteristic of the shear strength or the reliability by the temperature cycle test. Furthermore, various characteristics are exhibited not only by the second insulating resin 17A but also by the material and structure of the first insulating resin 16 and the ceramic substrate 2A.
  • FIG. 4 is a diagram showing a cross-sectional structure of a power semiconductor device 40 according to the fourth embodiment of the present invention.
  • a ceramic insulated circuit board 23S is configured by including a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A.
  • the heat generating base plate 19A and the heat conducting member 18A are configured to radiate heat generated in the ceramic insulated circuit board 23S.
  • the power semiconductor device 40 has a structure having a single-sided cooling structure.
  • the power semiconductor element 11 made of IGBT or the like is connected to the ceramic insulating circuit board 23S through the solder 5A.
  • the external terminal 113 is connected to the power semiconductor element 11 and the ceramic insulating circuit board 23S via leads (bus bars) 8L, solder 57, circuit electrodes 3A, and wires 6W.
  • a second insulating resin 17A made of polyamideimide resin is provided in contact with the ceramic substrate 2A and the circuit electrode 3A.
  • the power semiconductor element 11 and the ceramic insulated circuit board 23S are insulated and sealed with the first insulating resin 16 made of epoxy mold resin.
  • the power semiconductor element 11 and the ceramic insulating circuit board 23S which are insulated and sealed are accommodated.
  • the second insulating resin 17A made of the polyamideimide resin is provided, so that the first and second embodiments are provided. Similar to the embodiment (Examples 1 and 2), there is an effect of improving reliability in a shear strength test, a temperature cycle test, and the like.
  • the second insulating resin has been described as a resin mainly composed of polyamideimide, a resin in which an alumina filler having an average particle size of 5 ⁇ m is mixed in a polyamideimide resin with a weight ratio of 30 wt%, and a resin mainly composed of silicone. A resin may be applied.
  • the first insulating resin has been described as an epoxy mold resin, but the effect of including the second insulating resin in the power semiconductor device in any case of a transfer mold resin or a potting resin mainly composed of an epoxy resin. There is.
  • the material of the ceramic substrate the case where the inorganic powder material such as aluminum nitride and silicon nitride is produced by sintering has been described, but the case where the ceramic substrate is produced using aluminum oxide also includes the above-mentioned second insulation in the power semiconductor device. There is an effect when a resin is provided.
  • the power semiconductor device includes the second insulating resin.
  • the power semiconductor device to a wide gap device, SiC (Silicon Carbide, Silicon Carbide) or GaN (gallium Nitride, GaN) semiconductor devices using such and Ga 2 O 3 (gallium oxide, gallium oxide) But it has the same effect.
  • a power conversion device including the power semiconductor device of the present invention described above can be configured. At this time, high reliability can be secured in the factor resulting from the power semiconductor device as the power conversion device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs de puissance qui comprend : un élément à semi-conducteurs de puissance (11) ; au moins une carte de circuit imprimé isolante en céramique (23A), où une électrode de circuit (3A) est formée sur un substrat céramique (2A) ; une première résine isolante (16) qui tient de façon étanche l'élément à semi-conducteurs de puissance (11) et l'électrode de circuit (3A) du substrat céramique (2A) dans un état dans lequel au moins une surface d'électrode de l'élément à semi-conducteurs de puissance (11) et l'électrode de circuit (3A) de la carte de circuit imprimé isolante en céramique (23A) sont raccordées électriquement l'une à l'autre ; et une seconde résine isolante (17A) qui est agencée au moins sur une partie entre la carte de substrat céramique (2A) et la première résine isolante (16) et qui présente une force de liaison à une céramique du substrat céramique (2A) supérieure à celle de la première résine isolante (16).
PCT/JP2014/050182 2014-01-09 2014-01-09 Dispositif à semi-conducteurs de puissance et dispositif de conversion de puissance WO2015104808A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3300463A1 (fr) * 2016-09-26 2018-03-28 Hitachi Power Semiconductor Device, Ltd. Dispositif à semi-conducteurs
WO2020136459A1 (fr) * 2018-12-28 2020-07-02 федеральное государственное бюджетное научное учреждение "Научно-производственный комплекс "Технологический центр" Procédé de fabrication de modules électroniques en 3d et modules électroniques en 3d
CN116798882A (zh) * 2023-08-22 2023-09-22 哈尔滨工业大学（威海） 一种双面散热结构功率模块的制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091472A (ja) * 1998-09-10 2000-03-31 Toshiba Corp 半導体装置
JP2005116602A (ja) * 2003-10-03 2005-04-28 Denki Kagaku Kogyo Kk 回路基板及びその製造方法
JP2006032617A (ja) * 2004-07-15 2006-02-02 Hitachi Ltd 半導体パワーモジュール
JP2009070863A (ja) * 2007-09-11 2009-04-02 Hitachi Ltd 半導体パワーモジュール
JP2010123914A (ja) * 2008-10-20 2010-06-03 Denso Corp 電子制御装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091472A (ja) * 1998-09-10 2000-03-31 Toshiba Corp 半導体装置
JP2005116602A (ja) * 2003-10-03 2005-04-28 Denki Kagaku Kogyo Kk 回路基板及びその製造方法
JP2006032617A (ja) * 2004-07-15 2006-02-02 Hitachi Ltd 半導体パワーモジュール
JP2009070863A (ja) * 2007-09-11 2009-04-02 Hitachi Ltd 半導体パワーモジュール
JP2010123914A (ja) * 2008-10-20 2010-06-03 Denso Corp 電子制御装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3300463A1 (fr) * 2016-09-26 2018-03-28 Hitachi Power Semiconductor Device, Ltd. Dispositif à semi-conducteurs
WO2020136459A1 (fr) * 2018-12-28 2020-07-02 федеральное государственное бюджетное научное учреждение "Научно-производственный комплекс "Технологический центр" Procédé de fabrication de modules électroniques en 3d et modules électroniques en 3d
CN116798882A (zh) * 2023-08-22 2023-09-22 哈尔滨工业大学（威海） 一种双面散热结构功率模块的制造方法
CN116798882B (zh) * 2023-08-22 2024-01-30 哈尔滨工业大学（威海） 一种双面散热结构功率模块的制造方法

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