WO2014086054A1 - 一种后栅工艺假栅的制造方法和后栅工艺假栅 - Google Patents

一种后栅工艺假栅的制造方法和后栅工艺假栅 Download PDF

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WO2014086054A1
WO2014086054A1 PCT/CN2012/086401 CN2012086401W WO2014086054A1 WO 2014086054 A1 WO2014086054 A1 WO 2014086054A1 CN 2012086401 W CN2012086401 W CN 2012086401W WO 2014086054 A1 WO2014086054 A1 WO 2014086054A1
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Prior art keywords
layer
amorphous silicon
hard mask
gate
ono structure
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PCT/CN2012/086401
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English (en)
French (fr)
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李春龙
李俊峰
闫江
赵超
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中国科学院微电子研究所
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Priority to US14/119,869 priority Critical patent/US9111863B2/en
Publication of WO2014086054A1 publication Critical patent/WO2014086054A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

Definitions

  • the present invention relates to the field of semiconductor technology, and more particularly to a method for fabricating a back gate process dummy gate and a back gate process dummy gate.
  • the feature size of MOS transistors is getting smaller and smaller.
  • the gate stack structure of high-k gate dielectric layer and metal gate is introduced into MOS.
  • the gate stack structure of the metal gate and the high-k gate dielectric house is usually fabricated by a "gate last" process.
  • back gate process refers to: providing a semiconductor substrate on which a dummy gate structure is formed and an etch barrier layer covering the gate structure on the semiconductor substrate, in which the etch barrier is formed Forming an interlayer dielectric layer on the surface of the layer; performing chemical mechanical polishing on the interlayer dielectric layer and the etch barrier layer with the surface of the dummy gate structure as a stop layer; forming a trench after removing the dummy gate structure; A method of depositing or refracting a metal target fills the trench with a genus to form a metal*
  • the fabrication of dummy gates is critical, but currently, due to limitations in physical mechanisms, process techniques, and processing methods, the critical dimensions of dummy gates and dummy gates in the 22 nm and below technology bands
  • the profile of the profile is not precisely controlled, which affects the roughness of the gate line and does not guarantee the performance and stability of the device.
  • an embodiment of the present disclosure provides a method for fabricating a back gate process dummy gate, the method comprising: providing a semiconductor substrate;
  • ONO oxide film-nitride film-oxide film
  • a photoresist line is formed on the hard mask layer, the hard mask is etched by using the photoresist line as a mask 5 , and the light line is removed.
  • the T-layer amorphous silicon, the ONO structural hard mask, and the bottom-house amorphous silicon are etched by using the reduced hard mask layer as a standard, and the hard mask layer and the top are removed.
  • Amorphous silicon comprising: using the micro-hardened mask layer as a mask of the top-layer amorphous silicon, engraving the top-layer amorphous silicon;
  • the hard mask layer and the topped amorphous silicon are used as a mask of the ONO structure hard mask, and the ONO structure hard mask is etched to remove the hard mask layer;
  • top layer amorphous silicon and the ONO structure hard mask as a mask of the underlying amorphous silicon, etching the underlying amorphous silicon to remove the top layer amorphous silicon
  • depositing the underlying amorphous silicon on the gate gasification layer comprises:
  • a bottom amorphous silicon is deposited on the gate oxide layer using a low pressure chemical vapor deposition process.
  • the thickness of the underlying amorphous silicon is ⁇ ) ⁇ 1200 ⁇ ⁇
  • depositing the germanium structure hard mask on the underlying amorphous silicon comprises: depositing a bottom oxide film on the underlying amorphous silicon by a plasma enhanced chemical vapor deposition process; by a low pressure chemical vapor deposition process Depositing a nitrogen film on the bottom oxide film;
  • An oxide film of a portion is deposited on the nitride film by an atmospheric pressure chemical vapor deposition process.
  • the bottom gasification film has a thickness of 80 ⁇ to 120 ⁇
  • the nitride film has a thickness of 160 ⁇ to 240 ⁇
  • the top oxide film has a thickness of 500 ⁇ to 800 ⁇ .
  • the top layer of amorphous silicon and the hard mask layer are deposited on the tantalum structure hard mask, and the top layer of amorphous silicon is deposited on the tantalum structure hard mask by a low pressure chemical vapor deposition process.
  • layer amorphous silicon by a plasma enhanced chemical vapor deposition process Preferably, the top layer of amorphous silicon has a thickness of 300A to 400A, and the thickness of the hard mask layer is
  • An embodiment of the present disclosure further provides a back gate process dummy gate, including: a semiconductor substrate, a gate oxide layer on a surface of the semiconductor substrate, an amorphous silicon layer on a surface of the gate oxide layer, and An ONO structure hard mask on the amorphous silicon layer, the degree of the amorphous silicon layer and the ONO structure hard mask is less than or equal to 22 ⁇ ⁇ »
  • the ONO structure hard mask comprises: a bottom oxide film, a nitride film and a top oxide film.
  • the post-process dummy gate manufacturing method provided by the embodiment of the present disclosure firstly deposits an ONO structure hard mask on amorphous silicon, and then, in the etching stage, the hard mask layer is shrunk to make the width smaller than Equal to 22iim, and etch the OO structure hard mask with this width as the standard.
  • the critical dimension of the pole, the cross-sectional shape of the gate can be precisely controlled, and the bucking line The roughness can also be effectively improved, thereby ensuring the performance and stability of the device.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a back gate process dummy gate according to an embodiment of the present disclosure
  • Figure 2-] to Figure 2-10 shows the structure of the back gate process using the method shown in Figure 1 for the embodiment of the present disclosure: a schematic diagram of the structure of each stage of the gate ⁇ ,
  • Embodiments of the present disclosure provide a method of fabricating a germanium process dummy gate, including: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing underlying amorphous silicon on the gate oxide layer Depositing an oxide film-nitride film-oxide film (ONO) structure hard mask ⁇ on the underlying amorphous silicon; depositing a top layer of amorphous silicon on the ONO structure hard mask; a hard mask layer is deposited on the crystalline silicon, and the hard mask chamber is miniaturized so that the width of the hard mask layer after the shrinkage is less than or equal to 22 ⁇ m; and the hard mask layer after the shrinkage is used as a standard
  • the top layer of amorphous silicon, the germanium structure hard mask and the underlying amorphous silicon are etched, and the hard mask layer and the top layer of amorphous silicon are removed
  • the gate-gate dummy gate firstly, a hard mask of germanium structure is deposited on amorphous silicon, and then the hard mask layer is miniaturized in an etching stage to have a width of 22 nm or less, and This width is a standard etching of the ONO structure hard mask.
  • the critical dimension of the gate, the cross-sectional shape of the gate can be accurately controlled, and the roughness of the gate line is also Can be effectively improved to ensure the performance and stability of the device
  • a method for producing a solid jerk present embodiment the hood false Bu process flowchart of FIG. 7 to FIG. 2-1 embodiment 240 of the present embodiment employs the disclosed method of manufacturing the structure shown in FIG. 1 in various stages of the dummy gate schematic gate process, such as As shown in FIG. 1, the manufacturing method of the dummy gate in the back gate process includes:
  • Step S1 providing a semiconductor substrate 20;
  • the substrate 20 can be any semiconductor material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide.
  • the material of the substrate may also be a stacked semiconductor structure, such as Si/SiGe, silicon-on-insulator (SO! or silicon-on-insulator (SOOi ⁇ ).
  • the substrate can also be a fin device, a normal planar CMOS device, or a nanowire channel device.
  • the substrate 20 is exemplified by only using Si.
  • the present disclosure is not limited to this step S2: the gate oxide layer 22 is grown on the semiconductor substrate, and the gate electrode is grown. Depositing underlying amorphous silicon 24 on the layer;
  • the gate oxide layer 22 may be grown on the semiconductor substrate 20 by a thermal oxidation process, wherein the thermal oxidation process may be a conventional thermal oxidation process furnace tube (Funia ⁇ e) steam in situ generation (in situ Stream-generated, 1SSG ) or Rapid ihermal oxidation 5 ⁇ process.
  • the material of the gate oxide layer 22 may be silicon oxide or silicon oxynitride.
  • the material of the gate oxide layer 22 may be other materials known to those skilled in the art, and may have a thickness of 8 ⁇ .
  • underlying amorphous silicon 24 is deposited on the generated gate oxide 22.
  • the chemical vapor deposition (CVD) process can be used to complete the step, for example, low pressure chemical vapor deposition (L:P CVD), atmospheric pressure chemical vapor deposition (AP CVD), plasma
  • L:P CVD low pressure chemical vapor deposition
  • AP CVD atmospheric pressure chemical vapor deposition
  • plasma The thickness of the underlying amorphous silicon 24 deposited by processes such as bulk enhanced chemical vapor deposition (PE CVD) and tantalum density plasma chemical vapor deposition (HOP CVD) may range from 600 ⁇ to 00 ⁇ .
  • Step S3 depositing an oxide film-nitride film-oxide film ( ⁇ ) structure hard mask 26 on the deposited underlying amorphous silicon 24;
  • the deposition process of the ⁇ structure hard mask 26 may specifically be: sequentially depositing a bottom oxide film 261, a nitride film 262, and a germanium oxide film 263 on the underlying amorphous silicon 24, wherein
  • the bottom gasification film 261 may be deposited by a plasma enhanced chemical vapor deposition process
  • the vaporization film 262 may be deposited by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process
  • the oxide film 263 can be deposited by an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.
  • the material of the bottom oxide film 261 and the top oxide film 263 may be silicon oxide, and the thickness is 80A-120A.
  • the material of the 500 ⁇ .800 A nitride film 262 may be silicon nitride, and the thickness may be ⁇ 60 ⁇ 240 ⁇ Step S4: depositing a top layer of amorphous silicon 28 and a hard mask layer 30 on the tantalum structure hard mask 26;
  • the top layer amorphous silicon 28 can be deposited by processes such as chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and high density plasma chemical vapor deposition.
  • the thickness of the top layer of amorphous silicon 28 deposited in this step may be 300 ⁇ to 4 ⁇ ) 0 ⁇ respect, after depositing a hard mask layer 30 on the top layer of amorphous silicon 28, in this embodiment, hard masking
  • the material of the film layer 30 may be an oxide film and may be deposited by a plasma enhanced chemical vapor deposition process, and may have a thickness of 300 ⁇ to 400 ⁇ .
  • Step S5 forming a photoresist line 32 on the hard mask layer 30;
  • the photoresist line 32 can be formed by immersion lithography or electron beam direct writing, which is not limited in this embodiment.
  • this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the width of the photoresist line 32 formed, this embodiment No restrictions, for the
  • Step S6 etching the hard mask layer 30;
  • the hard mask layer 30 can be etched by a thousand etching process, for example, by reactive ion etching (RIE).
  • RIE reactive ion etching
  • Step S7 removing the photoresist line 32;
  • the hard mask layer 30 is to be shrunk in a subsequent step, in order to effectively remove the photoresist and the polymer generated during the etching of the hard mask layer 30, the micro-shrink quality of the hard mask layer 30 is ensured.
  • the photoresist line 32 can be removed by using a thousand method first, and then the wet cleaning method can be used. First, the photoresist can be removed by oxygen plasma filled in the plasma 3 ⁇ 4 etching cavity.
  • the SPM solution in this embodiment can be S04, 3 ⁇ 40 2 It is prepared by mixing with 3 ⁇ 40; and the APM solution can be prepared by mixing NH 4 OH, 3 ⁇ 40 2 and 3 ⁇ 40,
  • Step S8 miniaturizing the hard mask layer 30;
  • the hard mask layer 30 in order to realize a false twist having a width of 22 nm and a smaller size, it is necessary to reduce the hard mask layer 30 to have a width of 22 nm or less.
  • HF 00:] or 200:1 may be used.
  • the solution is tapered toward the hard mask layer 30.
  • Step S9 etching the top layer of amorphous silicon 28;
  • the top-wall amorphous silicon 28 is etched by using the mini-hardened mask layer 30 as a mask of the top-layer amorphous silicon 28, and the width of the top-off amorphous silicon is etched to 22 mii or less. Size; among them, In this embodiment, the top-layer amorphous silicon 28 may be etched by reactive ion etching or the like, and the specific method is not described herein.
  • Step S10 etching (0 ⁇ structural hard mask 26, and removing the hard mask layer 30;
  • the hard mask layer 30 and the germanium layer amorphous silicon 28 are used as a mask, and the tantalum structure hard mask 26 is etched.
  • reactive ion etching may be used.
  • the ⁇ structure hard mask 26 is etched; at the same time, the hard mask 30 can be removed after etching the ⁇ structure hard mask 26 to simplify the subsequent process
  • Step S11 etching the underlying amorphous silicon 24 and removing the top amorphous silicon 28;
  • the bottom amorphous silicon 24 is etched by using the top-wall amorphous silicon 28 and the germanium structure hard mask 26 as a mask.
  • the reactive ion etching method may be used to The crystalline silicon 24 is etched; at the same time, the top amorphous silicon 28 can be directly removed after etching the underlying amorphous silicon 24.
  • the method for manufacturing a back gate process dummy gate provided by the embodiment of the present disclosure firstly deposits an ONO structure hard mask on amorphous silicon, and then, in an etch phase, the hard mask layer is shrunk to have a width less than or equal to 22iim, and etch the ONO structure hard mask with this width as the standard.
  • the critical dimension of the gate and the cross-sectional shape of the gate can be accurately controlled.
  • the roughness of the pole lines can also be effectively improved to ensure the performance and stability of the device.
  • the real family of the present disclosure also provides a dummy gate structure formed by the above method, please refer to the figure.
  • a schematic cross-sectional structural diagram of a dummy gate provided by the present embodiment, specifically including: a semiconductor substrate 20, a gate oxide layer 22 on a surface of the semiconductor substrate, located at the gate oxide layer
  • the surface of the amorphous silicon layer 24, and the ONO structure hard mask 26 on the amorphous silicon layer 24, the amorphous silicon layer 24 and the ONO structure hard mask 26 have a width of 22 tim or less.
  • the O 3 structure hard mask 26 includes: a bottom oxide film 261, a nitride film 262 and a partial germanium film 263; the bottom oxide film 261 and the top oxide film 263 may be made of silicon oxide, and the thickness may be 80A ⁇ 120A, and 500A ⁇ 800A, the material of the gasification film 262 may be silicon nitride, and the thickness may be 160A-240A. It will be apparent to those skilled in the art that ⁇ RTIgt; ⁇ /RTI> ⁇ RTIgt; ⁇ /RTI> ⁇ RTIgt; ⁇ /RTI> ⁇ RTIgt; ⁇ /RTI> ⁇ RTIgt; The principles may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not limited to the embodiments shown herein, but rather conforms to the principles disclosed herein. The widest range consistent with novel features.

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Abstract

提供了一种后栅工艺假栅的制造方法和一种后栅工艺假栅，该方法包括：提供半导体衬底（20）；在所述半导体衬底（20）上生长栅极氧化层（22）；在所述栅极氧化层（22）上淀积底层非晶硅（24）；在所述底层非晶硅（24）上淀积ONO结构硬掩膜（26）；在所述ONO结构硬掩膜（26）上淀积顶层非晶硅（28）；在所述顶层非晶硅（28）上淀积硬掩膜层（30）；对所述硬掩膜层（30）进行微缩，使微缩后的硬掩膜层（30）宽度小于等于22nm；以所述微缩后的硬掩膜层（30）为标准，对所述顶层非晶硅（28）、ONO结构硬掩膜（26）和底层非晶硅（24）进行刻蚀，并去除所述硬掩膜层（30）和顶层非晶硅（28）。

Description

—种后栅工艺艮栅的制造方法和后栅工艺叚栅 技术领域 本发明涉及半导体技术领域，尤其涉及一种后栅工艺假柵的制造方法和后 栅工艺假栅 背景技术 随着集成电路制造技术的不断发展， MOS晶体管的特征尺寸也越来越小， 为了降低 MOS 晶体管柵极的寄生电容， 提高器件速度， 高 K栅介电层与金 属栅极的栅极叠层结构被引入到 MOS晶体管中 为了避免金属栅极的金属材 料对晶体管其他结构的影响， 所述金属柵极与高 K柵介电屋的栅极叠层结构 通常采用 "后槲（ gate last )'， 工艺制作。
所谓后栅工艺是指： 提供半导体衬底， 所迷半导体衬底上形成有假柵结构 和位于所述半导体衬底上覆盖所述^ _柵结构的刻蚀阻挡层，在所述刻蚀阻挡层 表面形成层间介质层； 以所述假柵结构表面作为停止层，对所迷层间介质层和 刻蚀阻挡层进行化学机械研磨； 除去所述假栅结构后形成沟槽； 通过物理气相 沉积或金属靶減射的方法向所述沟槽内填充^ r属， 以形成金属 *|电 *层； 用化 学机械研磨法研磨金属栅电极层直至露出层间介质层， 形成金属柵。
因此， 在后栅工艺中， 假.栅的制造至关重要 但目前， 由于受到物理机 制、 工艺技术以及加工手段等方面的限制， 22nm及以下技术带中， 假柵的关 键尺寸、以及假栅的剖面形貌还无法精准控制，从而影响了柵极线条的粗糙度， 无法保证器件的性能及其稳定性 发明内容
有鉴于此，本公开实施例提供一种后柵工艺假柵的制造方法，该方法包括： 提供半导体衬底；
在所述半导体衬底上生长.栅极氧化层；
在所述柵极氧化层上淀积底层非晶硅；
在所迷底层非晶硅上淀积氧化膜-氮化膜-氧化膜（ONO )结构硬掩膜； 在所述 ONO结构硬掩膜上淀积頂层非晶硅；
在所述项层非晶硅上淀积硬掩膜层； 将所述硬掩膜层进行微缩，使微縮后 的硬掩膜层宽度小于等于 22mn;
以所述微缩后的硬掩膜层为标准， 对所述顶层非晶硅、 ONO結构硬掩膜 和底展非晶.硅进行刻蚀， 并去除所述硬掩膜层和'琐层非晶硅。
优选的， 在所述硬掩膜层上形成光刻胶线条， 以所述光刻胶线条为掩膜 5 对所述硬掩膜进行刻蚀， 并去除所述光 ¾胶线条„
优选的， 以所迷微缩后的硬掩膜层为标准， 对所迷 T 层非晶硅、 ONO 结 构硬掩膜和底屋非晶硅进行刻蚀， 并去除所述硬掩膜层和顶 非晶硅， 包括： 将所述微缩后的硬掩膜层作为所述頂层非晶硅的掩膜，对所述顶层非晶硅 进行刻 '烛；
将所述硬掩膜层和所述顶居非晶硅作为 ONO结构硬掩膜的掩膜， 对所述 ONO结构硬掩膜进行釗蚀， 去除所述硬掩膜层；
将所述顶层非晶硅和所述 ONO结构硬掩膜作为所述底层非晶硅的掩膜， 对所述底层非晶硅进行刻蚀， 去除所述顶层非晶硅
优选的 所述在所迷栅极氣化层上淀积底层非晶硅， 包括：
采用低压化学气相淀积工艺在所述栅极氧化层上淀积底层非晶硅。
优选的， 所述底层非晶硅厚度为 Κ)Α〜1200Αβ
优选的 所述在所述底层非晶硅上淀积 ΟΝΟ结构硬掩膜， 包括： 通过等离子体增强化学气相淀积工艺在底层非晶硅上淀积底部氧化膜； 通过低压化学气相淀积工艺在所述底部氧化膜上淀积氮^膜；
通过常压化学气相淀积工艺在所述氮化膜上淀积项部氧化膜。
优选的， 所述底部氣化膜的厚度为 80Α~120Α， 所述氮化膜的厚度为 160Α--240Α, 所述顶部氧化膜的厚度为 500Α〜800Α。
优选的， 所述在所述 ΟΝΟ结构硬掩膜上淀积頂层非晶硅和硬掩膜层， 包 通过低压化学气相淀积工艺在所述 ΟΝΟ結构硬掩膜上淀积顶层非晶硅； 通过等离子体增强化学气相淀积工艺在所述 τ|层非晶硅上淀积硬掩膜层 优选的， 所述顶层非晶硅厚度为 300A〜400A , 所述硬掩膜层厚度为
Figure imgf000005_0001
本公开实施例还提供了一种后栅工艺假柵， 包括： 半导体衬底， 位于所述 半导体衬底表面的柵极氧化层，位于所述柵极氧化层表面的非晶硅层，和位于 所述非晶硅层上的 ONO结构硬掩膜， 所述非晶硅层和所述 ONO结构硬掩膜的 度小于等于 22誦■»
优选的， 所述 ONO結构硬掩膜包括： 底部氧化膜 氮化膜和顶部氧化膜。 本公开实施例所提供的后 *工艺假栅制造方法，首先釆用在非晶硅上淀积 ONO结构硬掩膜， 之后在刻蚀阶段， 对硬.掩膜层进行微缩， 使之宽度小于等 于 22iim, 并以此宽度为标准对 O O结构硬掩膜进行刻蚀， 通过此方法， 在 22nm及以下技术带中， 极的关键尺寸， 栅极的剖面形貌能得到精确控制， 槺极线条的粗糙度也能得到有效改善， 从而保证了器件的性能及稳定性 附图说明 为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述 中的附图仅仅是本公开中记载的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性的前提下 , 还可以根椐这些附图获得其他的附图。
图 1. 为本公开实施例所提供的一种后栅工艺假柵的制造方法的流程示意 ^¾，
图 2-】 至图 2-10 为本公开实旎例采用图 1所示的方法制造后柵工艺假：柵 的各个阶段的结构示意图 <,
附图标记：
20-半导体衬底， 22-栅极氧化物， 24-底层非晶硅， 26-0: ()結构硬掩膜， 28顶层非晶硅， 30-硬掩膜层， 32-光刻胶线条； 261 -底部氧化膜， 262-氮化膜， 263-顶部氧化膜 具体实施方式 为了使本技术领域的人员更好地理解本申请中的技术方案 下面将结合本 公开实施例中的附图， 对本公开实施例中的技术方案进行清楚， 完整 .地描述， 显然， 所描述的实施例仅仅是本公开一部分实施例， 而不是全部的实施例 基 于本公开中的实旄例，本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都应当属于本公开保护的范围。
本公开实施例提供一种后槲工艺假柵的制造方法，包括：提供半导体衬底； 在所述半导体衬底上生长栅极氧化层； 在所迷柵极氧化层上淀积底层非晶硅； 在所述底层非晶硅上淀积氧化膜-氮化膜-氧化膜（ONO )结构硬掩膜餍； 在所 述 ONO結构硬掩膜上淀积顶层非晶硅; 在所述顶层非晶硅上淀积硬掩膜层， 将所述硬掩膜屋进行微縮, 使徵缩后的硬掩膜层宽度小于等于 22iim; 以所述 微缩后的硬掩膜层为标准, 对所述顶层非晶硅、 ΟΝΌ结构硬掩膜和底层非晶 硅进行刻蚀， 并去除所述硬掩膜层和顶层非晶硅
上述的后栅工艺假栅的制造方法中， 首先采用在非晶硅上淀积 ΟΝΟ结构 硬掩膜， 之后在刻蚀阶段， 对硬掩膜层进行微縮， 使之宽度小于等于 22mn, 并以此宽度为标准对 ONO结构硬掩膜进行刻蚀， 通过此方法， 在 22nm及以 下技术带中， 栅极的关键尺寸， 柵极的剖面形貌能得到精确控制， 柵极线条的 粗糙度也能得到有效改善， 从而保证了器件的性能及稳定性
为使本公开的上述目的 特征和有点能够更加明显易懂， 下面结合附图对 本公开的具体实施方式做详细的说明„ 在详述本公开实施例时， 为便于说明， 表示器件结构的剖面图会不依一般比例作局部放大， ¾且所述示意图只是示 例， 其在此不应「艮制本公开的保护范围。 此外， 在实际制作中应包舍长度， 宽 度以及深度的三维空间尺寸,，
图 1 为本实旄例后捬工艺假櫥的制造方法流程图 7 图 2-1至图 240为本 公开实施例采用图 1所示的方法制造后柵工艺假柵的各个阶段的结构示意图 如图 1所示， 所述后栅工艺中假栅的制造方法包括:
步骤 S1 : 提供半导体衬底 20;
在本步骤中， 该衬底 20可以采用任何的半导体材料， 例如单晶硅、 多晶 硅、 非晶硅、 锗、 硅锗、 碳化硅、 锑化铟、 碲化铅、 砷化铟、 磷化铟 砷化镓 或锑化镓、合金半导体或其他化合物半导体材料， 衬底的材质还可以为叠层半 导体结构， 例如 Si/SiGe、 绝缘体上硅（ SO! )或绝缘体上硅锗（ SOOi λ 另外, 衬底还可以为鳍型器件、 正常平面型 CMOS 器件或者纳米线沟道器件等。 本 公开实施例中衬底 20仅以采用 Si为例， 此处仅为示例， 本公开并不限于此 步骤 S2: 在半导体衬底上生长柵极氧化层 22, 并在所生长的栅极氧化层 上淀积底层非晶硅 24;
在本步骤中，可以采用热氧化工艺在半导体衬底 20上生长柵极氧化层 22， 其中， 所述热氧化工艺可以为传统的热氧化工艺炉管 （Funia^e ) 蒸汽原位生 成 ( situ stream-generated, 1SSG )或者是快速热氧 4匕 ( Rapid ihermal oxidation 5 ΚΊΌ ) 工艺。 栅极氧化层 22的材料可以为氧化硅或氮氧化硅等， 除此之外， 栅极氧化层 22的材料也可以为本领域技术人员公知的其他材料， 其厚度可以 为 8Α.、40Α。
之后， 在所生成的柵极氧化 22上淀积底层非晶硅 24。 其中， 此处可采 用化学气相淀积（Chemical Vapor Deposition , CVD )工艺来完成该步骤， 例 如可采用低压化学气相淀积（L:P CVD )、 常压化学气相淀积（AP CVD )、 等离 子体增强化学气相淀积（ PE CVD )、 以及髙密度等离子体化学气相淀积（ HOP CVD ) 等工艺 所淀积的底层非晶硅 24厚度可以为 600Α~ 00Α。
步骤 S3:在所淀积的底层非晶硅 24上淀积氧化膜-氮化膜-氧化膜（ ΟΝΟ ) 结构硬掩膜 26;
在本步骤中， ΟΝΟ 结构硬掩膜 26 的淀积过程可具体为： 在底层非晶硅 24上依次淀积底部氧化膜 261、 氮化膜 262和 Τ|部氧化膜 263 其中， 在本实 施例中， 底部氣化膜 261可以采用等离子体增强化学气相淀积工艺进行淀积， 氣化膜 262 可以采用低压化学气相淀积工艺或等离子体增强化学气相淀积工 艺等进行淀积； 项部氧化膜 263可以采用常压化学气相淀积工艺、低压化学气 相淀积工艺或等离子体增强化学气相淀积工艺等进行淀积。并且， 底部氧化膜 261 和顶部氧化膜 263 的材料可以为氧化硅， 厚度分別为 80A-120A., 和 500Α .800 A 氮化膜 262的材料可以为氮化硅 , 厚度可以为 ί 60 Α·、240Α„ 步艨 S4: 在 ΟΝΟ结构硬掩膜 26上进行顶层非晶硅 28和硬掩膜层 30的 淀积；
在本步骤中， 顶层非晶硅 28可以采用化学气相淀积、常压化学气相淀积、 等离子体增强化学气相淀积、以及高密度等离子体化学气相淀积等工艺进行淀 积 其中， 该步骤中所淀积的顶层非晶硅 28厚度可以为 300Α〜4{)0Α„ 之后， 在顶层非晶硅 28上淀积硬掩膜层 30， 在本实施例中， 硬掩膜层 30 材料可以为氧化膜， 并可以通过等离子体增强化学气相淀积工艺进行淀积，其 厚度可以为 300Α〜400Α。
步骤. S5: 在硬掩膜层 30上形成光刻胶线条 32;
在本步驟中， 光刻胶线条 32可以采用浸润式光刻或者电子束直写的方式 形成, 本实施例不做限制； 另外， 对于所 ^成的光刻胶线条 32的宽度， 本实 施例不做限制,。
步骤 S6: 对硬.掩膜层 30进行刻蚀；
在本步骤中， 以所形成的光刻胶线条 32为掩膜， 可以采用千法刻蚀工艺 对硬掩膜层 30进行刻蚀， 例如采用反应离子刻蚀（ Reaciive km Etching, RIE ) 方式对硬掩膜层 30进行刻蚀。
步骤 S7: 去除光刻胶线条 32;
由于在后续步骤中要对硬掩膜层 30进行微缩， 为了能够有效去除光刻胶. 和硬掩膜层 30刻蚀过程中所产生的聚合物 ,保障硬掩膜层 30的微縮质量，在 本步骤中， 光刻胶线条 32的去除可以先采用千法去胶， 之后再采用湿法清洗 的方式进行 具体可以为， 首先通过填充在等离子¾蚀腔^ ^内的氧气等离子去 除光刻胶线条 32;之后通过 SPM溶液和 APM溶液对残留的光刻胶线条 32和 硬掩膜层 30刻蚀过程中产生的聚合物进行湿法去除， 其中， 本实施例中 SPM 溶液可由 S04、 ¾02和 ¾0混合配制而成；而 APM溶液可由 NH4OH、 ¾02 和¾0混合配制而成,，
步骤 S8: 对硬掩膜层 30进行微缩；
在本步骤中， 为实现宽度为 22nm以及更小尺寸的假槲， 需要对硬掩膜层 30进行微缩， 使其宽度为 22nm或更小 例如， 可以采用 〗00:】或 200:1的 HF 溶液对硬掩膜层 30进-行微缩。 除此之外， 除此之外， 也可以为采用本领域技 术^ V员公知的方式进行微缩， 本实施例不做限制。
步骤 S9: 对顶层非晶硅 28进.行刻蚀；
在本步骤中， 以微縮后的硬掩膜层 30作为顶层非晶硅 28的掩膜，对顶屋 非晶硅 28进行刻蚀， 将頂罢非晶硅的宽度刻蚀为 22mii或更小尺寸； 其中， 本实施例中可采用反应离子刻蚀等方式对顶层非晶硅 28进行剖蚀， 具体方法 在此不做赘述
步骤 S10: 对（0ΝΟ结构硬掩膜 26进行刻蚀， 并去除硬掩膜层 30;
在本步艨中， 以硬掩膜层 30和顸层非晶硅 28为掩膜， 对 ΟΝΟ结构硬掩 膜 26进.行刻蚀，在本实施例中，可以采用反应离子刻蚀方法对 ΟΝΟ结构硬掩 膜 26进行刻蚀; 同时, 可以在对 ΟΝΟ结构硬掩膜 26进行刻蚀之后， 去除硬 掩膜展 30， 以简化后续流程
步骤 S11 : 对底层非晶硅 24进行刻蚀， 并去除顶层非晶硅 28;
在本步骤中， 以顶屋非晶硅 28和 ΟΝΟ结构硬掩膜 26为掩膜， 对底屡非 晶硅 24进行刻蚀， 在本实施例中， 可以采用反应离子刻蚀方法对底层非晶硅 24进行刻蚀； 同时， 可以在对底层非晶硅 24进行刻蚀之后， 直接去除顶层非 晶硅 28。
至此， 线宽为 22nm或更小尺寸的后栅工艺假柵制造完成。
本公开实施例所提供的后栅工艺假柵制造方法，首先采用在非晶硅上淀积 ONO结构硬掩膜， 之后在 1蚀阶段， 对硬.掩膜层进行微缩， 使之宽度小于等 于 22iim, 并以此宽度为标准对 ONO結构硬掩膜进行刻蚀， 通过此方法， 在 22:nm及以下技术带中， 柵极的关键尺寸， 栅极的剖面形貌能得到精确控制， 柵极线条的粗糙度也能得到有效改善， 从而保证了器件的性能及穩定性。 本公开实族例还提供了一种利用上迷方法形成的假柵结构， 请参考图
2-10, 为本^ H 实旄例所提供的假栅的剖面结构示意图， 具体包括： 半导体衬 底 20， 位于所述半导体衬底表面的栅极氧化层 22， 位于所述栅极氧化层 22 表面的非晶硅层 24， 和位于所述非晶硅层 24上的 ONO结构硬掩膜 26 所迷 非晶硅层 24和所述 ONO结构硬掩膜 26的宽度小于等于 22tim。
其中， 所述 O 3结构硬掩膜 26包括： 底部氧化膜 261 , 氮化膜 262和 部氡化膜 263; 所述底部氧化膜 261和顶部氧化膜 263的材料可以为氧化硅， 厚度可以为 80A〜120A， 和 500A〜800A， 氣化膜 262的材料可以为氮化硅， 厚 度可以为 160A-240A , 对所公开的实施例的上迷说明，使本领域专业技术人员能够实现或使用本 发明 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见 的， 本文中所定义的一般原理可以在不脱离本发明的精神或范 1¾的情况下，在 其它实施例中实现 因此, 本发明将不会被限制于本文所示的这些实施例， 而 是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims

权 利 要 求
1、 一种后柵工艺 #_柵的制造方法， 其特征在于， 包括：
提供半导体衬底；
在所述半导体衬底上生长柵极氣^ i层；
在所述栅极氧化层上淀积底层非晶硅；
在所述底层非晶硅上淀积氧化膜-氮化膜-氧化膜（ONO )结构硬掩膜； 在所述 ONO结构硬掩膜上淀积頂层非晶硅;
在所述项屋非晶硅上淀积硬掩膜层，将所述硬掩膜层进行微缩，使微缩后 的硬 膜层宽度小于等于 22¾n;
以所述微缩后的硬掩膜层为标准， 对所迷顶层非晶硅、 ONO结构硬掩膜. 和底 非晶硅进行刻蚀， 并去除所述硬掩膜层和顶层非晶硅„
2、 根据权利要求〗所述的方法， 其特征在于， 还包括： 在所述硬掩膜屋 上形成光刻胶线条， 以所迷光刻胶线条为掩膜， 对所述^ _掩膜进行朝蚀， 并去 除所述光刻胶线条 ¾
3、 根据权利要求 1或 2所迷的方法， 其特征在于， 以所述微缩后的硬掩 膜层为标准 对所述I层非晶硅， ONO结构硬掩膜和底层非晶硅进行刻蚀， 并去除所述硬掩膜层和顶层非晶硅， 包括：
将所述徽縮后的硬 4¾1层作为所述頂层非晶硅的掩膜，对所述顶层非晶硅 进行剖蚀；
将所述硬藉膜层和所述顶层非晶硅作为 ONO结构硬掩膜的掩膜， 对所述
ΟΝΌ结构硬掩膜进行刻：蚀，， 去除所述硬掩膜层；
将所述顶房非晶硅和所述 ONO結构硬掩膜作为所述底层非晶硅的掩膜， 对所述底层非晶硅进行刻蚀， 去除所述项层非晶硅
4、 根椐权利要求 1或 2所述的方法 其特征在于， 所述在所述栅极氧化 层上淀积底层非晶硅， 包括：
采用低压化学气相淀积工艺在所述栂极氧化层上淀积底层非晶硅
5、 根据权利要求 1或 2所述的方法， 其特^ E在于， 所述底层非晶硅厚度 为 600A- 1200A,
6、 根据权利要求 5所述的方法， 其特征在于， 所迷^所迷底层 晶鞋上 淀积 ONO结构硬掩膜， 包括：
通过等离子体增强化学气相淀积工艺在底层非晶硅上淀积底部氣化膜； 通过低压化学气相淀积工艺在所述底部氧化膜上淀积氮化膜；
通过常压化学气相淀积工艺在所述氮化膜上淀积项部氧化膜
7、 根据权利要求 6所述的方法， 其特征在于， 所述底部氧化膜的厚度为
80A^120A， 所述氮化膜的厚度为 160A〜240A， 所迷顶部氧化膜的厚度为
500A-800A.
8、 根据权利要求〗或 2所迷的方法， 其特征在于， 所述在所述 ONO结 构硬掩膜上淀积頂层非晶硅和硬掩膜层， 包括：
通过低压化学气相淀积工艺在所述 ONO结构硬掩膜上淀积顶层非晶硅； 通过等离子体增强化学气相淀积工艺在所述顶,层非晶硅上淀积硬掩膜层 ¾
9、 根椐权利要求 8 所述的方法， 其特征在于， 所述顸层非晶硅厚度为 300A-400A, 所述硬掩膜层厚度为 300A〜400A,:
10、 一种后栅工艺假栅， 其特征在于， 包括： 半导体衬底， 位于所述半导 体衬底表面的栅极氧化层，位于所述柵极氣化层表面的非晶硅层， 和位于所迷 非晶硅层上的 ONO结构硬掩膜， 所述非晶硅层和所述 ONO结构硬掩膜的宽 度小于等于 22nm,
11、 根据权利要求 .0所述的后柵工艺假栅， 其特征在于， 所述 ONO结 构硬掩膜包括： 底部氧化膜、 氮化膜和頂部氧化膜 :：
PCT/CN2012/086401 2012-12-03 2012-12-12 一种后栅工艺假栅的制造方法和后栅工艺假栅 WO2014086054A1 (zh)

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