WO2014086053A1 - 一种后栅工艺假栅的制造方法和后栅工艺假栅 - Google Patents

一种后栅工艺假栅的制造方法和后栅工艺假栅 Download PDF

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WO2014086053A1
WO2014086053A1 PCT/CN2012/086398 CN2012086398W WO2014086053A1 WO 2014086053 A1 WO2014086053 A1 WO 2014086053A1 CN 2012086398 W CN2012086398 W CN 2012086398W WO 2014086053 A1 WO2014086053 A1 WO 2014086053A1
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layer
amorphous silicon
hard mask
gate
ono structure
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PCT/CN2012/086398
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English (en)
French (fr)
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李春龙
李俊峰
闫江
赵超
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中国科学院微电子研究所
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Priority to US14/119,862 priority Critical patent/US9202890B2/en
Publication of WO2014086053A1 publication Critical patent/WO2014086053A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a method for fabricating a back gate process dummy gate and a back gate process dummy gate.
  • BACKGROUND OF THE INVENTION With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is also getting smaller and smaller.
  • the gate of the high-k gate dielectric layer and the metal gate is improved.
  • the stacked structure is introduced into the MOS transistor.
  • the gate stack structure of the metal gate and the high-k gate dielectric layer is usually fabricated by a "gate last" process.
  • the back gate process refers to: providing a semiconductor substrate, wherein the semiconductor substrate is formed with a dummy gate structure and an etch barrier layer covering the dummy gate structure on the semiconductor substrate, in the etch barrier layer Forming an interlayer dielectric layer on the surface; performing chemical mechanical polishing on the interlayer dielectric layer and the etch barrier layer with the surface of the dummy gate structure as a stop layer; forming a trench after removing the dummy gate structure; by physical vapor deposition Or a method of sputtering a metal target, filling the trench with a metal to form a metal gate electrode layer; polishing the metal gate electrode layer by chemical mechanical polishing until the interlayer dielectric layer is exposed to form a metal gate.
  • an embodiment of the present disclosure provides a method for fabricating a back gate process dummy gate, the method comprising: providing a semiconductor substrate;
  • ONO oxide film-nitride film-oxide film
  • the hard mask layer, the top layer amorphous silicon, the ONO structure hard mask, and the underlying amorphous silicon are etched by using a photoresist line as a standard, and the photoresist line and the hard line are removed.
  • the mask layer and the top layer of amorphous silicon including:
  • the hard mask layer and the top layer amorphous silicon are used as a mask of the ONO structure hard mask, and the ONO structure hard mask is etched to remove the hard mask layer;
  • the top layer amorphous silicon and the ONO structure hard mask are used as a mask of the underlying amorphous silicon, and the underlying amorphous silicon is etched to remove the top layer amorphous silicon.
  • depositing the underlying amorphous silicon on the gate oxide layer comprises:
  • a bottom amorphous silicon is deposited on the gate oxide layer using a low pressure chemical vapor deposition process.
  • the underlying amorphous silicon has a thickness of 600A to 1200A.
  • depositing an ONO structure hard mask on the underlying amorphous silicon comprises: depositing a bottom oxide film on the underlying amorphous silicon by a plasma enhanced chemical vapor deposition process; and performing low pressure chemical vapor deposition a process depositing a nitride film on the bottom oxide film;
  • a top oxide film is deposited on the nitride film by an atmospheric pressure chemical vapor deposition process.
  • the thickness of the bottom oxide film is 80A to 120A, and the thickness of the nitride film is
  • the top oxide film has a thickness of 500 A to 800 A.
  • the top layer of amorphous silicon and the hard mask layer are deposited on the ONO structure hard mask,
  • a hard mask layer is deposited on the top layer of amorphous silicon by a thermal oxidation process.
  • the top layer of amorphous silicon has a thickness of 300A to 400A
  • the hard mask layer has a thickness of 300A to 400A.
  • An embodiment of the present disclosure further provides a back gate process dummy gate, including: a semiconductor substrate, a gate oxide layer on a surface of the semiconductor substrate, an amorphous silicon layer on a surface of the gate oxide layer, and The ONO structure hard mask on the amorphous silicon layer, the amorphous silicon layer and the ONO structure hard mask have a width of 32 nm to 45 nm.
  • the ONO structure hard mask comprises: a bottom oxide film, a nitride film and a top oxide film.
  • the method for manufacturing a back gate process dummy gate provided by an embodiment of the present disclosure can accurately control the critical size of the gate by depositing an ONO structure hard mask on amorphous silicon and etching the ONO structure hard mask.
  • the cross-sectional shape of the gate electrode can effectively improve the roughness of the gate line, ensuring the performance and stability of the device.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a back gate process dummy gate according to an embodiment of the present disclosure
  • FIG. 2-1 to FIG. 2-9 are schematic structural views of various stages of manufacturing a back gate process dummy gate by using the method shown in FIG. 1 according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a method for fabricating a back gate process dummy gate, including: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing underlying amorphous silicon on the gate oxide layer Depositing an ONO structure hard mask on the underlying amorphous silicon; depositing a top layer of amorphous silicon on the ONO structure hard mask; depositing a hard mask layer on the top layer of amorphous silicon; Forming a photoresist line having a width of 32 nm to 45 nm on the hard mask layer; using the photoresist line as a standard, the hard mask layer, the top layer amorphous silicon, the ONO structure hard mask, and the underlying amorphous layer Silicon is etched and the photoresist lines, hard mask layers, and top layer amorphous silicon are removed.
  • the critical dimension of the gate can be precisely controlled, and the gate is The profile is shaped and can effectively improve the roughness of the gate lines to ensure the performance and stability of the device.
  • FIG. 1 is a flow chart of a method for manufacturing a back gate process dummy gate according to an embodiment of the present invention
  • FIGS. 2-1 to 2-9 are schematic structural views showing stages of manufacturing a back gate process dummy gate by using the method shown in FIG. 1 according to an embodiment of the present disclosure; .
  • the manufacturing method of the dummy gate in the back gate process includes:
  • Step S1 providing a semiconductor substrate 20;
  • the substrate 20 can be made of any semiconductor material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide. , gallium arsenide or gallium antimonide, alloy semiconductor or other compound semiconductor materials, the material of the village bottom can also be a stacked semiconductor structure, such as Si / SiGe, silicon-on-insulator (SOI) or silicon-on-insulator (SGOI). In addition, the bottom of the village can also be a fin device, a normal planar CMOS device, or a nanowire channel device.
  • semiconductor material such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide.
  • the material of the village bottom
  • Step S2 growing a gate oxide layer 22 on the semiconductor substrate, and depositing underlying amorphous silicon 24 on the grown gate oxide layer;
  • the thermal oxidation process may be a conventional thermal oxidation process furnace tube (Furnace), a steam stream generation (ISSG) or a rapid thermal oxidation (RTO) process.
  • the material of the gate oxide layer 22 may be silicon oxide or silicon oxynitride.
  • the material of the gate oxide layer 22 may be other materials known to those skilled in the art, and may have a thickness of 8A to 40A.
  • underlying amorphous silicon 24 is deposited on the generated gate oxide layer 22.
  • the chemical vapor deposition (CVD) process can be used to complete the step, for example, low pressure chemical vapor deposition (LP CVD), atmospheric pressure chemical vapor deposition (AP CVD), plasma enhancement. Processes such as chemical vapor deposition (PE CVD) and high density plasma chemical vapor deposition (HDP CVD).
  • the deposited underlying amorphous silicon 24 may have a thickness of 600A to 1200A.
  • Step S3 depositing an oxide film-nitride film-oxide film (ONO) structure hard mask 26 on the deposited underlying amorphous silicon 24;
  • ONT oxide film-nitride film-oxide film
  • the deposition process of the ONO structure hard mask 26 can be specifically as follows:
  • a bottom oxide film 261, a nitride film 262, and a top oxide film 263 are sequentially deposited.
  • the bottom oxide film 261 may be deposited by a plasma enhanced chemical vapor deposition process
  • the nitride film 262 may be deposited by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
  • the top oxide film 263 may be deposited by an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.
  • the material of the bottom oxide film 261 and the top oxide film 263 may be silicon oxide having a thickness of 80A to 120A and 500A to 800A, respectively.
  • the material of the nitride film 262 may be silicon nitride and may have a thickness of 160A to 240A.
  • Step S4 performing deposition of the top amorphous silicon 28 and the hard mask layer 30 on the ONO structure hard mask 26;
  • the top layer amorphous silicon 28 can be deposited by processes such as chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and high density plasma chemical vapor deposition.
  • the top layer of amorphous silicon 28 deposited in this step may have a thickness of 300A to 400A.
  • a hard mask layer 30 is deposited on the top layer of amorphous silicon 28.
  • the hard mask layer 30 material may be an oxide film and may be subjected to a thermal oxidation process or a plasma enhanced chemical vapor deposition process. The deposition may be carried out to a thickness of 300A to 400A.
  • Step S5 forming a photoresist line 32 on the hard mask layer 30;
  • the photoresist line 32 can be formed by immersion lithography or electron beam direct writing, which is not limited in this embodiment; in addition, in order to realize the formation of 32 nm to 45 nm ⁇ Jt, the formed photoresist The width of the line 32 is 32 nm to 45 nm.
  • Step S6 etching the hard mask layer 30;
  • the hard masking layer 30 can be etched by a dry etching process, such as Reactive Ion Etching (RIE).
  • RIE Reactive Ion Etching
  • Step S7 removing the photoresist line 32;
  • a dry stripping process can be employed, for example, using an oxygen plasma to remove the photoresist lines 32, specifically: etching the photoresist lines 32 by oxygen plasma filled in the plasma etching chamber.
  • Step S8 etching the top layer of amorphous silicon 28;
  • the hard mask layer 30 is used as a mask for the top layer of amorphous silicon 28, and the top layer of amorphous silicon is used.
  • the etch is performed on the top layer of the amorphous silicon 28 by using reactive ion etching or the like in the embodiment. The specific method is not described herein.
  • Step S9 etching the ONO structure hard mask 26;
  • the ONO structure hard mask 26 is etched by using the hard mask layer 30 and the top layer amorphous silicon 28 as a mask.
  • the reactive ion etching method can be used to hard mask the ONO structure.
  • the film 26 is etched; at the same time, the hard mask layer 30 may be removed after the ONO structure hard mask 26 is etched to cool the subsequent process.
  • Step S10 etching the underlying amorphous silicon 24;
  • the underlying amorphous silicon 24 is etched by using the top amorphous silicon 28 and the ONO structural hard mask 26 as a mask.
  • the reactive amorphous etching method can be used for the underlying amorphous silicon. 24 etching is performed; at the same time, the top amorphous silicon 28 can be directly removed after etching the underlying amorphous silicon 24.
  • the ONO structure hard mask and the ONO structure hard mask are etched, which can precisely control the critical dimension of the gate, the cross-sectional shape of the gate, and can effectively improve the roughness of the gate line, ensuring the performance of the device and stability.
  • the embodiment of the present disclosure further provides a dummy gate structure formed by the above method. Referring to FIG.
  • a schematic diagram of a cross-sectional structure of a 4-gate includes: A gate oxide layer 22 on the surface of the semiconductor substrate, an amorphous silicon layer 24 on the surface of the gate oxide layer 22, and an ONO structure hard mask 26 on the amorphous silicon layer 24.
  • the amorphous silicon layer 24 and the ONO structure hard mask 26 have a width of 32 nm to 45 nm.
  • the ONO structure hard mask 26 includes: a bottom oxide film 261, a nitride film 262 and a top oxide film 263; the bottom oxide film 261 and the top oxide film 263 may be made of silicon oxide, and the thickness may be 80A. 120A, and 500A ⁇ 800A, the material of the nitride film 262 may be silicon nitride, and the thickness may be 160A ⁇ 240A.

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  • Power Engineering (AREA)
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Abstract

本公开实施例提供了一种后栅工艺假栅的制造方法，该方法包括：提供半导体村底；在所述半导体村底上生长栅极氧化层；在所述栅极氧化层上淀积底层非晶硅；在所述底层非晶硅上淀积ONO结构硬掩膜；在所述ONO结构硬掩膜上淀积顶层非晶硅；在所述顶层非晶硅上淀积硬掩膜层；在所述硬掩膜层上形成宽度为32nm~45nm的光刻胶线条；以所述光刻胶线条为标准，对所述硬掩膜层、顶层非晶硅、ONO结构硬掩膜和底层非晶硅进行刻蚀，并去除所述光刻胶线条、硬掩膜层和顶层非晶硅。相应地，本公开实施例还提供了一种后栅工艺假栅。采用本公开所提供的技术方案，能精确控制栅极的关键尺寸，栅极的剖面形貌，并能有效改善栅极线条的粗糙度，保证了器件的性能及稳定性。

Description

一种后栅工艺假栅的制造方法和后栅工艺假栅 技术领域 本发明涉及半导体技术领域，尤其涉及一种后栅工艺假栅的制造方法和后 栅工艺假栅。 背景技术 随着集成电路制造技术的不断发展， MOS晶体管的特征尺寸也越来越小， 为了降低 MOS 晶体管栅极的寄生电容， 提高器件速度， 高 K栅介电层与金 属栅极的栅极叠层结构被引入到 MOS晶体管中。 为了避免金属栅极的金属材 料对晶体管其他结构的影响， 所述金属栅极与高 K栅介电层的栅极叠层结构 通常采用 "后栅（gate last )" 工艺制作。
所谓后栅工艺是指： 提供半导体村底， 所述半导体村底上形成有假栅结构 和位于所述半导体村底上覆盖所述假栅结构的刻蚀阻挡层，在所述刻蚀阻挡层 表面形成层间介质层； 以所述假栅结构表面作为停止层，对所述层间介质层和 刻蚀阻挡层进行化学机械研磨； 除去所述假栅结构后形成沟槽； 通过物理气相 沉积或金属靶溅射的方法向所述沟槽内填充金属， 以形成金属栅电极层； 用化 学机械研磨法研磨金属栅电极层直至露出层间介质层， 形成金属栅。
因此， 在后栅工艺中， 假栅的制造至关重要。 但目前， 由于受到物理机 制、 工艺技术以及加工手段等方面的限制， 45nm~32nm技术带中， 假栅的关 键尺寸、以及假栅的剖面形貌还无法精准控制，从而影响了栅极线条的粗糙度， 无法保证器件的性能及其稳定性。 发明内容 有鉴于此，本公开实施例提供一种后栅工艺假栅的制造方法，该方法包括： 提供半导体村底；
在所述半导体村底上生长栅极氧化层；
在所述栅极氧化层上淀积底层非晶硅； 在所述底层非晶硅上淀积氧化膜-氮化膜-氧化膜（ONO ) 结构硬掩膜； 在所述 ONO结构硬掩膜上淀积顶层非晶硅；
在所述顶层非晶硅上淀积硬掩膜层；
在所述硬掩膜层上形成宽度为 32nm~45nm的光刻胶线条；
以所述光刻胶线条为标准， 对所述硬掩膜层、 顶层非晶硅、 ONO结构硬 掩膜和底层非晶硅进行刻蚀， 并去除所述硬掩膜层和顶层非晶硅。
优选的， 所述以光刻胶线条为标准， 对所述硬掩膜层、 顶层非晶硅、 ONO 结构硬掩膜和底层非晶硅进行刻蚀， 并去除所述光刻胶线条、硬掩膜层和顶层 非晶硅， 包括：
将所述光刻胶线条作为所述硬掩膜层的掩膜， 对所述硬掩膜层进行刻蚀， 去除所述光刻胶线条；
将所述硬掩膜层作为所述顶层非晶硅的掩膜， 对所述顶层非晶硅进行刻 蚀；
将所述硬掩膜层和所述顶层非晶硅作为 ONO结构硬掩膜的掩膜， 对所述 ONO结构硬掩膜进行刻蚀， 去除所述硬掩膜层；
将所述顶层非晶硅和所述 ONO结构硬掩膜作为所述底层非晶硅的掩膜， 对所述底层非晶硅进行刻蚀， 去除所述顶层非晶硅。
优选的， 所述在所述栅极氧化层上淀积底层非晶硅， 包括：
采用低压化学气相淀积工艺在所述栅极氧化层上淀积底层非晶硅。
优选的， 所述底层非晶硅厚度为 600A~1200A。
优选的， 所述在所述底层非晶硅上淀积 ONO结构硬掩膜， 包括： 通过等离子体增强化学气相淀积工艺在底层非晶硅上淀积底部氧化膜； 通过低压化学气相淀积工艺在所述底部氧化膜上淀积氮化膜；
通过常压化学气相淀积工艺在所述氮化膜上淀积顶部氧化膜。
优选的， 所述底部氧化膜的厚度为 80A~120A , 所述氮化膜的厚度为
160A-240A , 所述顶部氧化膜的厚度为 500 A~800 A。
优选的， 所述在所述 ONO结构硬掩膜上淀积顶层非晶硅和硬掩膜层， 包 通过热氧化工艺在所述顶层非晶硅上淀积硬掩膜层。
优选的， 所述顶层非晶硅厚度为 300A~400A , 所述硬掩膜层厚度为 300A~400A。
本公开实施例还提供了一种后栅工艺假栅， 包括： 半导体村底， 位于所述 半导体村底表面的栅极氧化层，位于所述栅极氧化层表面的非晶硅层， 和位于 所述非晶硅层上的 ONO结构硬掩膜， 所述非晶硅层和所述 ONO结构硬掩膜的 宽度为 32nm~45nm。
优选的， 所述 ONO结构硬掩膜包括： 底部氧化膜、 氮化膜和顶部氧化膜。 本公开实施例所提供的后栅工艺假栅制造方法，通过采用在非晶硅上淀积 ONO结构硬掩膜，并对 ONO结构硬掩膜进行刻蚀， 能精确控制栅极的关键尺 寸， 栅极的剖面形貌， 并能有效改善栅极线条的粗糙度， 保证了器件的性能及 稳定性。 附图说明 为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作筒单地介绍，显而易见地， 下面描述 中的附图仅仅是本公开中记载的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。
图 1 为本公开实施例所提供的一种后栅工艺假栅的制造方法的流程示意 图；
图 2-1至图 2-9 为本公开实施例采用图 1所示的方法制造后栅工艺假栅的 各个阶段的结构示意图。
附图标记：
20-半导体村底， 22-栅极氧化物， 24-底层非晶硅， 26-ONO结构硬掩膜， 28-顶层非晶硅， 30-硬掩膜层， 32-光刻胶线条； 261-底部氧化膜， 262-氮化膜， 263-顶部氧化膜。 具体实施方式 为了使本技术领域的人员更好地理解本申请中的技术方案，下面将结合本 公开实施例中的附图， 对本公开实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本公开一部分实施例， 而不是全部的实施例。 基 于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都应当属于本公开保护的范围。
本公开实施例提供一种后栅工艺假栅的制造方法，包括：提供半导体村底； 在所述半导体村底上生长栅极氧化层； 在所述栅极氧化层上淀积底层非晶硅； 在所述底层非晶硅上淀积 ONO结构硬掩膜； 在所述 ONO结构硬掩膜上淀积 顶层非晶硅； 在所述顶层非晶硅上淀积硬掩膜层； 在所述硬掩膜层上形成宽度 为 32nm~45nm的光刻胶线条； 以所述光刻胶线条为标准， 对所述硬掩膜层、 顶层非晶硅、 ONO结构硬掩膜和底层非晶硅进行刻蚀， 并去除所述光刻胶线 条、 硬掩膜层和顶层非晶硅。
上述的后栅工艺假栅的制造方法中， 通过采用在非晶硅上淀积 ONO结构 硬掩膜， 并对 ONO结构硬掩膜进行刻蚀， 能精确控制栅极的关键尺寸， 栅极 的剖面形貌， 并能有效改善栅极线条的粗糙度， 保证了器件的性能及稳定性。
为使本公开的上述目的、特征和有点能够更加明显易懂， 下面结合附图对 本公开的具体实时方式做详细的说明。 在详述本公开实施例时， 为便于说明， 表示器件结构的剖面图会不依一般比例作局部放大， 而且所述示意图只是示 例， 其在此不应限制本公开的保护范围。 此外， 在实际制作中应包含长度、 宽 度以及深度的三维空间尺寸。
图 1为本实施例后栅工艺假栅的制造方法流程图， 图 2-1至图 2-9为本公 开实施例采用图 1所示的方法制造后栅工艺假栅的各个阶段的结构示意图。
如图 1所示， 所述后栅工艺中假栅的制造方法包括：
步骤 S1: 提供半导体村底 20;
在本步骤中， 该村底 20可以采用任何的半导体材料， 例如单晶硅、 多晶 硅、 非晶硅、 锗、 硅错、 碳化硅、 锑化铟、 碲化铅、 砷化铟、 磷化铟、 砷化镓 或锑化镓、合金半导体或其他化合物半导体材料，村底的材质还可以为叠层半 导体结构， 例如 Si/SiGe、 绝缘体上硅（SOI )或绝缘体上硅锗（SGOI )。 另夕卜， 村底还可以为鳍型器件、 正常平面型 CMOS器件或者纳米线沟道器件等。 本 公开实施例中村底 20仅以采用 Si为例， 此处仅为示例， 本公开并不限于此。 步骤 S2: 在半导体村底上生长栅极氧化层 22, 并在所生长的栅极氧化层 上淀积底层非晶硅 24;
其中， 所述热氧化工艺可以为传统的热氧化工艺炉管（Furnace ), 蒸汽原 位生成 （ situ stream-generated, ISSG ) 或者是快速热氧化 ( Rapid thermal oxidation, RTO ) 工艺。 栅极氧化层 22 的材料可以为氧化硅或氮氧化硅等， 除此之外， 栅极氧化层 22的材料也可以为本领域技术人员公知的其他材料， 其厚度可以为 8A~40A。
之后， 在所生成的栅极氧化层 22上淀积底层非晶硅 24。 其中， 此处可采 用化学气相淀积（Chemical Vapor Deposition, CVD )工艺来完成该步骤， 例 如可采用低压化学气相淀积（LP CVD )、 常压化学气相淀积（AP CVD )、 等离 子体增强化学气相淀积（PE CVD )、 以及高密度等离子体化学气相淀积（HDP CVD )等工艺。 所淀积的底层非晶硅 24厚度可以为 600A~1200A。
步骤 S3:在所淀积的底层非晶硅 24上淀积氧化膜-氮化膜-氧化膜（ ONO ) 结构硬掩膜 26;
在本步骤中， ONO 结构硬掩膜 26 的淀积过程可具体为： 在底层非晶硅
24上依次淀积底部氧化膜 261、 氮化膜 262和顶部氧化膜 263。 其中， 在本实 施例中， 底部氧化膜 261可以采用等离子体增强化学气相淀积工艺进行淀积， 氮化膜 262 可以采用低压化学气相淀积工艺或等离子体增强化学气相淀积工 艺等进行淀积； 顶部氧化膜 263可以采用常压化学气相淀积工艺、低压化学气 相淀积工艺或等离子体增强化学气相淀积工艺等进行淀积。 并且，底部氧化膜 261 和顶部氧化膜 263 的材料可以为氧化硅， 厚度分别为 80A~120A, 和 500A-800A, 氮化膜 262的材料可以为氮化硅， 厚度可以为 160A~240A。
步骤 S4: 在 ONO结构硬掩膜 26上进行顶层非晶硅 28和硬掩膜层 30的 淀积；
在本步骤中，顶层非晶硅 28可以采用化学气相淀积、常压化学气相淀积、 等离子体增强化学气相淀积、以及高密度等离子体化学气相淀积等工艺进行淀 积。 其中， 该步骤中所淀积的顶层非晶硅 28厚度可以为 300A~400A。
之后， 在顶层非晶硅 28上淀积硬掩膜层 30, 在本实施例中， 硬掩膜层 30 材料可以为氧化膜，并可以通过热氧化工艺或等离子体增强化学气相淀积工艺 进行淀积， 其厚度可以为 300A~400A。
步骤 S5: 在硬掩膜层 30上形成光刻胶线条 32;
在本步骤中， 光刻胶线条 32可以采用浸润式光刻或者电子束直写的方式 形成， 本实施例不做限制； 另外， 为实现 32nm~45nm ^Jt的形成， 所形成的 光刻胶线条 32的宽度为 32nm~45nm。
步骤 S6: 对硬掩膜层 30进行刻蚀；
在本步骤中， 以所形成的光刻胶线条 32为掩膜， 可以采用干法刻蚀工艺 对硬掩月莫层 30进行刻蚀， 例如反应离子刻蚀（ Reactive Ion Etching, RIE ) 方 式对硬掩膜层 30进行刻蚀。
步骤 S7: 去除光刻胶线条 32;
在本步骤中， 可以采用干法去胶工艺， 例如， 使用氧气等离子体去除光刻 胶线条 32, 具体为： 通过填充在等离子刻蚀腔体内的氧气等离子体去刻蚀光 刻胶线条 32。
步骤 S8: 对顶层非晶硅 28进行刻蚀；
在本步骤中， 以硬掩膜层 30作为顶层非晶硅 28的掩膜， 对顶层非晶硅
28进行刻蚀， 其中， 本实施例中可采用反应离子刻蚀等方法对顶层非晶硅 28 进行刻蚀， 具体方法在此不做赘述。
步骤 S9: 对 ONO结构硬掩膜 26进行刻蚀；
在本步骤中， 以硬掩膜层 30和顶层非晶硅 28为掩膜， 对 ONO结构硬掩 膜 26进行刻蚀， 在本实施例中，可以采用反应离子刻蚀方法对 ONO结构硬掩 膜 26进行刻蚀； 同时， 可以在对 ONO结构硬掩膜 26进行刻蚀之后， 去除硬 掩膜层 30, 以筒化后续流程。
步骤 S10: 对底层非晶硅 24进行刻蚀；
在本步骤中， 以顶层非晶硅 28和 ONO结构硬掩膜 26为掩膜， 对底层非 晶硅 24进行刻蚀， 在本实施例中， 可以采用反应离子刻蚀方法对底层非晶硅 24进行刻蚀； 同时， 可以在对底层非晶硅 24进行刻蚀之后， 直接去除顶层非 晶硅 28。
至此， 线宽为 32nm~45nm的后栅工艺假栅制造完成。
本公开实施例所提供的后栅工艺假栅制造方法，通过采用在非晶硅上淀积 ONO结构硬掩膜，并对 ONO结构硬掩膜进行刻蚀， 能精确控制栅极的关键尺 寸， 栅极的剖面形貌， 并能有效改善栅极线条的粗糙度， 保证了器件的性能及 稳定性。 本公开实施例还提供了一种利用上述方法形成的假栅结构，请参考图 2-9, 为本公开实施例所提供的 4 栅的剖面结构示意图， 具体包括： 半导体村底 20, 位于所述半导体村底表面的栅极氧化层 22, 位于所述栅极氧化层 22表面的非 晶硅层 24, 和位于所述非晶硅层 24上的 ONO结构硬掩膜 26。 所述非晶硅层 24和所述 ONO结构硬掩膜 26的宽度为 32nm~45nm。
其中， 所述 ONO结构硬掩膜 26包括： 底部氧化膜 261 , 氮化膜 262和顶 部氧化膜 263; 所述底部氧化膜 261和顶部氧化膜 263的材料可以为氧化硅， 厚度可以为 80A~120A, 和 500A~800A, 氮化膜 262的材料可以为氮化硅， 厚 度可以为 160A~240A。 对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本 发明。 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见 的， 本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下， 在 其它实施例中实现。 因此， 本发明将不会被限制于本文所示的这些实施例， 而 是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims

权 利 要 求
1、 一种后栅工艺假栅的制造方法， 其特征在于， 包括：
提供半导体村底；
在所述半导体村底上生长栅极氧化层；
在所述栅极氧化层上淀积底层非晶硅；
在所述底层非晶硅上淀积氧化膜-氮化膜-氧化膜（ONO ) 结构硬掩膜； 在所述 ONO结构硬掩膜上淀积顶层非晶硅；
在所述顶层非晶硅上淀积硬掩膜层；
在所述硬掩膜层上形成宽度为 32nm~45nm的光刻胶线条；
以所述光刻胶线条为标准， 对所述硬掩膜层、 顶层非晶硅、 ONO结构硬 掩膜和底层非晶硅进行刻蚀，并去除所述光刻胶线条、硬掩膜层和顶层非晶硅。
2、 根据权利要求 1所述的方法， 其特征在于， 所述以光刻胶线条为标准， 对所述硬掩膜层、 顶层非晶硅、 ONO结构硬掩膜和底层非晶硅进行刻蚀， 并 去除所述光刻胶线条、 硬掩膜层和顶层非晶硅， 包括：
将所述光刻胶线条作为所述硬掩膜层的掩膜， 对所述硬掩膜层进行刻蚀， 去除所述光刻胶线条；
将所述硬掩膜层作为所述顶层非晶硅的掩膜， 对所述顶层非晶硅进行刻 蚀；
将所述硬掩膜层和所述顶层非晶硅作为 ONO结构硬掩膜的掩膜， 对所述 ONO结构硬掩膜进行刻蚀， 去除所述硬掩膜层；
将所述顶层非晶硅和所述 ONO结构硬掩膜作为所述底层非晶硅的掩膜， 对所述底层非晶硅进行刻蚀， 去除所述顶层非晶硅。
3、 根据权利要求 1或 2所述的方法， 其特征在于， 所述在所述栅极氧化 层上淀积底层非晶硅， 包括：
采用低压化学气相淀积工艺在所述栅极氧化层上淀积底层非晶硅。
4、 根据权利要求 3 所述的方法， 其特征在于， 所述底层非晶硅厚度为 600A~1200A。
5、 根据权利要求 4所述的方法， 其特征在于， 所述在所述底层非晶硅上 淀积 ONO结构硬掩膜， 包括： 通过等离子体增强化学气相淀积工艺在底层非晶硅上淀积底部氧化膜； 通过低压化学气相淀积工艺在所述底部氧化膜上淀积氮化膜；
通过常压化学气相淀积工艺在所述氮化膜上淀积顶部氧化膜。
6、 根据权利要求 5所述的方法， 其特征在于， 所述底部氧化膜的厚度为 80A-120A , 所述氮化膜的厚度为 160A~240A , 所述顶部氧化膜的厚度为
500A~800A。
7、 根据权利要求 1或 2所述的方法， 其特征在于， 所述在所述 ONO结 构硬掩膜上淀积顶层非晶硅和硬掩膜层， 包括： 通过热氧化工艺在所述顶层非晶硅上淀积硬掩膜层。
8、 根据权利要求 7 所述的方法， 其特征在于， 所述顶层非晶硅厚度为 300A-400A, 所述硬掩膜层厚度为 300A~400A。
9、 一种后栅工艺假栅， 其特征在于， 包括： 半导体村底， 位于所述半导 体村底表面的栅极氧化层，位于所述栅极氧化层表面的非晶硅层， 和位于所述 非晶硅层上的 ONO结构硬掩膜， 所述非晶硅层和所述 ONO结构硬掩膜的宽 度为 32匪〜 45匪。
10、 根据权利要求 9所述的后栅工艺假栅， 其特征在于， 所述 ONO结构 硬掩膜包括： 底部氧化膜、 氮化膜和顶部氧化膜。
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