WO2014086013A1 - Igbt及其元胞结构、以及igbt的形成方法 - Google Patents
Igbt及其元胞结构、以及igbt的形成方法 Download PDFInfo
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- WO2014086013A1 WO2014086013A1 PCT/CN2012/085999 CN2012085999W WO2014086013A1 WO 2014086013 A1 WO2014086013 A1 WO 2014086013A1 CN 2012085999 W CN2012085999 W CN 2012085999W WO 2014086013 A1 WO2014086013 A1 WO 2014086013A1
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- doping
- semiconductor substrate
- drift region
- igbt
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims description 87
- 239000004065 semiconductor Substances 0.000 claims description 84
- 238000005468 ion implantation Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 10
- -1 arsenic ions Chemical class 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 238000002207 thermal evaporation Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 210000004027 cell Anatomy 0.000 claims 9
- 229910001439 antimony ion Inorganic materials 0.000 claims 1
- 210000003850 cellular structure Anatomy 0.000 claims 1
- 239000010410 layer Substances 0.000 description 41
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000002161 passivation Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 229910052684 Cerium Inorganic materials 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Definitions
- IGBT and its cell structure, and method of forming IGBT
- the present invention relates to the field of semiconductor device manufacturing technologies, and in particular, to an IGBT and a cell structure thereof, and a method of forming an IGBT. Background technique
- Insulated Gate Bipolar Transistor is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), which has both MOSFETs.
- BJT bipolar transistor
- MOSFET insulated gate field effect transistor
- the high input impedance of the device and the low on-voltage drop of the power transistor ie, giant transistor, GTR for short.
- GTR giant transistor
- the vertical structure of the IGBT mainly includes a non-punch-through IGBT (referred to as NPT-IGBT) and a punch-through IGBT (referred to as PT-IGBT).
- NPT-IGBT non-punch-through IGBT
- PT-IGBT punch-through IGBT
- the non-punch-through IGBT has the advantages of simple fabrication process, low production cost, good safety voltage characteristics, on-voltage with positive temperature coefficient and low switching loss. However, its conduction loss is large.
- punch-through IGBTs have lower conduction losses, but their switching losses are larger.
- an embodiment of the present invention provides an IGBT and a cell structure thereof, and
- the method of forming the IGBT has a good compromise between switching loss and conduction loss, and improves the overall performance of the IGBT.
- the embodiment of the present invention provides the following technical solutions:
- An IGBT cell structure includes: a first drift region and a second drift region on a lower surface of the first drift region, wherein the first drift region and the second drift region have the same doping type and concentration At least one doped region between the first drift region and the second drift region, the doping type of the doping region is the same as the doping type of the second drift region, and the doping region a doping concentration greater than a doping concentration of the second drift region; a collector region located on a side of the second drift region facing away from the doped region, a doping type of the collector region and the second The doping type of the drift region is reversed.
- the number of the doped regions is at least two, adjacent doped regions are spaced apart.
- the doping ions of the doping region are arsenic ions or cerium ions.
- the doping region doping concentration ranges from 5*10 15 cn 3 -9*10 17 cn 3 , including the endpoint value.
- the number of the doped regions ranges from 2-4, including the endpoint value.
- the doped regions are evenly distributed.
- the spacing between adjacent doped regions is 1-3 times the width of the doped region.
- the doped region has a depth ranging from 3 ⁇ ⁇ -8 ⁇ ⁇ , including an endpoint value.
- the distance between the doped region and the collector region ranges from 4 ⁇ ⁇ to 9 ⁇ ⁇ , including the endpoint value.
- An IGBT comprising at least one of the cell structures described in any of the above.
- a method of forming an IGBT comprising: providing a first semiconductor substrate, the first semiconductor substrate including a first drift region; forming at least one doped region in a lower surface of the first semiconductor substrate, The doping type of the doping region is the same as the doping type of the first drift region, and the doping concentration of the doping region is greater than the doping concentration of the first drift region; under the first semiconductor substrate Surface formation a semiconductor substrate, the doping type and concentration of the second semiconductor substrate and the first semiconductor substrate are the same, and the second semiconductor substrate includes a second drift region, the second drift region is completely Covering the first drift region and the doped region; forming a collector region in a lower surface of the second semiconductor substrate.
- forming at least one doped region in the lower surface of the first semiconductor substrate comprises: forming an oxide layer in the lower surface of the first semiconductor; forming an etching window in the oxide layer, the engraving The etch window corresponds to a position in the first semiconductor substrate where a doping region is to be formed; and at least one doped region is formed in the first semiconductor substrate by using an oxide layer having an etched window as a mask.
- the forming process of the doping region is ion implantation or thermal deposition.
- the implantation energy of the doping ions is less than 40 keV.
- the forming process of the second semiconductor substrate is epitaxy.
- the second semiconductor substrate has a thickness ranging from 5 ⁇ m to 10 ⁇ m, including an endpoint value.
- the technical solution provided by the embodiment of the present invention includes at least one doped region between the first drift region and the second drift region, the doping The doping type of the region is the same as the doping type of the drift region, and the doping concentration of the doping region is greater than the doping concentration of the drift region, such that when subjected to the same breakdown voltage, the present technology
- the IGBT provided in the scheme reduces the conduction loss compared with the conventional non-punch-through IGBT.
- the turn-off loss is reduced, thereby optimizing the compromise between the conduction loss and the switching loss of the IGBT. relationship.
- the IGBT provided in the technical solution of the present invention reduces the turn-off loss compared with the conventional non-punch-through IGBT, and reduces the conduction loss compared with the conventional punch-through IGBT. Thereby optimizing the trade-off relationship between the conduction loss of the IGBT and the switching loss. Therefore, the IGBT provided by the present invention has a good compromise between the conduction loss and the switching loss, and the overall performance is relatively high.
- FIG. 1 is a schematic structural view of a non-punch-through IGBT in the prior art
- FIG. 2 is a schematic structural view of a through-type IGBT in the prior art
- FIG. 3 is a schematic structural diagram of an IGBT according to an embodiment of the present invention. detailed description
- the prior art through-type IGBTs and non-punch-through IGBTs each include a plurality of cell structures.
- the cell structure of the non-punch-through IGBT mainly includes: an N-type lightly doped (N-) substrate, and a front surface structure of the front surface of the N-type lightly doped (N-) substrate, And a backside structure on the back side of the N-type lightly doped (N-) substrate.
- the front structure comprises: a gate structure 104 on an upper surface of the N-type lightly doped (N-) substrate; a P-type well region 102 (generally a P-type) located in an upper surface of the N-substrate Lightly doped), an N-type source region 103 located in the surface of the P-type well region 102; a source electrode 105 on the surface of the P-type well region 102 and the N-type source region 103.
- the backside structure includes a P-type heavily doped collector region 106 on the back side of the N-substrate and a collector 107 on the surface of the collector region 106.
- the region of the N-type lightly doped (N-) substrate from which the front surface structure and the back surface structure are removed is the drift region 101.
- the cell structure of the punch-through IGBT includes: an N-type buffer layer 108 formed between the drift region 101 and the collector region 106 as compared with the non-punch-through IGBT.
- the inventors have found that the implantation efficiency of the non-punch-through IGBT collector region 106 is high under the same device thickness, so that the conduction loss of the non-punch-through IGBT is small, but in the switching state, the The non-punch-through IGBT has a large turn-off tail current, which causes a large turn-off loss and a small safe voltage range, resulting in certain defects in its application as a switch, and overall performance is poor.
- the non-punch-through IGBT When the same breakdown voltage is applied, the non-punch-through IGBT has a relatively small switching loss, but its overall thickness is relatively large, so that its conduction voltage drop is relatively large, and the conduction loss is relatively large.
- the through-type IGBT Compared with the non-punch-through IGBT, the through-type IGBT has a relatively thin drift region and a small conduction loss, but the turn-off loss is relatively large.
- a very thick drift region is required, thereby greatly increasing the fabrication cost of the feedthrough IGBT.
- the present invention provides an IGBT and its cell structure, and a method for forming an IGBT, so that the IGBT provided by the present invention has a good compromise between switching loss and conduction loss. Improve the overall performance of the IGBT.
- the above described objects, features and advantages of the present invention will become more apparent from the aspects of the appended claims.
- the embodiment of the present invention is described by taking the IGBT as a planar gate structure IGBT as an example, but is also applicable to a trench gate structure IGBT, which is not limited by the present invention.
- Embodiment 1 is therefore not limited by the specific embodiments disclosed below.
- Embodiments of the present invention provide an IGBT cell structure, and an IGBT including at least one of the cell structures.
- the IGBT cell structure provided by the embodiment of the present invention includes: a drift region, the drift region includes a first drift region 301 and a second drift region 302 located at a lower surface of the first drift region 301, and a doping type of the first drift region 301 and the second drift region 302 And the same concentration;
- the collector region 304 is located on the side of the second drift region 302 away from the doped region 303, and the doping type of the collector region 304 is opposite to the doping type of the second drift region.
- the embodiment of the present invention further includes: a front structure located on a front surface of the drift region, the front structure including a gate structure 305 on an upper surface of the drift region; and a drift region on both sides of the gate structure 305 A well region 306 of the surface; a source region 307 located in the upper surface of the well region 306; a source electrode 308 located on the upper surface of the source region 307 and electrically connected to the source region 307.
- a passivation layer is further formed between the source electrode 308 and the gate structure 305.
- the doping ions of the doped region 303 are preferably arsenic ions or cerium ions. Since the arsenic ion or the cerium ion has a small diffusion coefficient, the phenomenon that the doping region 303 diffuses toward the first drift region 301 during the fabrication of the cell structure is avoided, so that the Doping concentration and implantation depth of doped region 303.
- the cell structure provided in the embodiment of the present invention includes at least one doped region 303 between the first drift region 301 and the second drift region 302, the doping type and the doping region of the doping region 303
- the doping type of the drift region is the same, and the doping concentration of the doping region 303 is greater than the doping concentration of the drift region, so that the IGBT provided in the technical solution of the present invention is subjected to the same breakdown voltage.
- the IGBT provided in the technical solution of the present invention is subjected to the same breakdown voltage.
- the IGBT provided in the technical solution of the present invention is subjected to the same breakdown voltage.
- the IGBT provided in the technical solution of the present invention is subjected to the same breakdown voltage.
- it Compared with the traditional non-punch-through IGBT, it has a thin drift region and a small overall thickness.
- the ion implantation efficiency of the collector region is relatively low, and the turn-off loss is relatively small, compared with the conventional one.
- the ion implantation efficiency of the collector region is relatively high, and the conduction loss is relatively small.
- the IGBT provided by the present invention has a good trade-off relationship between conduction loss and switching loss, and the overall performance is relatively high.
- the cell structure provided by the embodiment of the present invention includes at least two doped regions 303 between the first drift region 301 and the second drift region 302, adjacent doping The areas 303 are spaced apart.
- the doping concentration of the doping region 303 ranges from 5*10 15 cm" 3 -9*10 17 cm" 3 , including the endpoint value, and the doping region 303 is along the
- the depth hi of the collector region 304 to the drift region is in the range of 3 ⁇ ⁇ -8 ⁇ ⁇ , including the endpoint value; in order to form the good quality collector region 304, and the injection of the collector region 304 can be adjusted
- the efficiency of the IGBT is further optimized.
- the distance between the doping region 303 and the collector region 304 along the collector region 304 to the drift region is 4 ⁇ ⁇ - 9 ⁇ . ⁇ , including the endpoint value, is not limited in the present invention, depending on the specific situation.
- the number of the doping regions 303 ranges from 2 to 4, including the endpoint value; 303 is evenly distributed on the interface between the first drift region 301 and the second drift region 302; the spacing b between the adjacent doping regions 303 is 1-3 times the width a of the doped region 303,
- the present invention is not limited thereto, and may be determined depending on the specific circumstances.
- the IGBT cell structure provided by the present invention, and the IGBT including the cell structure have a good compromise between switching loss and conduction loss, thereby improving the overall performance of the IGBT.
- Embodiment 2 is a diagrammatic representation of Embodiment 1:
- the embodiment of the invention provides a method for forming an IGBT according to the first embodiment.
- the IGBT forming method provided by the present invention includes:
- Step 201 providing a first semiconductor substrate, the first semiconductor substrate including a first drift region 301.
- the first semiconductor substrate may be N-type doped or P-type doped, as the case may be.
- the method of forming the IGBT provided by the present invention will be described in detail by taking the semiconductor substrate as an N-type light doping as an example.
- Step 202 forming at least one doping region 303 in a lower surface of the first semiconductor substrate, the doping type of the doping region 303 is the same as the doping type of the first drift region 301, and the The doping concentration of the doping region 303 is greater than the doping concentration of the first drift region 301.
- step 202 includes:
- Step 20201 forming an oxide layer on a lower surface of the first semiconductor substrate, the oxide layer completely covering the first semiconductor substrate;
- Step 20202 forming a photoresist layer on the surface of the oxide layer, and placing a mask on the surface of the photoresist layer, the mask plate having a doped region to be formed in the first semiconductor substrate An etched window corresponding to the position of 303;
- Step 20203 exposing and developing the photoresist layer by using the mask as a mask, forming an etching window in the photoresist layer, wherein the etching window penetrates the photoresist layer. And corresponding to a position of the first semiconductor substrate where the doping region 303 is to be formed;
- Step 20204 etching the oxide layer by using a photoresist layer having an etched window as a mask. Forming an etch window in the oxide layer, the etch window penetrating the oxide layer and corresponding to a position of the first semiconductor substrate where the doping region 303 is to be formed;
- Step 20205 forming at least one doping region 303 in the first semiconductor substrate by using an oxide layer having an etch window as a mask, the first doping region 303 being located under the first drift region 301 surface.
- the formation process of the doping region 303 may be ion implantation or thermal deposition, which is not limited in the present invention.
- the formation process of the doping region 303 is ion implantation, the implantation energy of the doping ions is less than 40 keV.
- Step 203 removing an oxide layer on a lower surface of the first semiconductor substrate, forming a second semiconductor substrate on a lower surface of the first semiconductor substrate, and doping the second semiconductor substrate and the first semiconductor substrate
- the type and concentration are the same, and it is also an N-type lightly doped semiconductor substrate.
- the second semiconductor substrate includes a second drift region 302, and the second drift region 302 is located on a lower surface of the first drift region 301 and completely covers the first drift region and the doped region;
- the forming process of the second semiconductor substrate is preferably epitaxial, so that the doping type and the doping concentration of the second drift region 302 and the first drift region 301 can be ensured. the same.
- the thickness of the second semiconductor substrate in the direction from the second semiconductor substrate to the first semiconductor substrate ranges from 5 ⁇ m to 10 ⁇ m, including an end point. value.
- the IGBT forming method provided by the embodiment of the present invention does not require a very thick drift region, but only requires a second semiconductor substrate having a small epitaxial thickness. The manufacturing cost of the IGBT is greatly reduced.
- Step 204 Form a gate structure on an upper surface of the first semiconductor substrate.
- step 204 includes:
- Step 20401 forming a gate dielectric layer on an upper surface of the first semiconductor substrate, wherein the gate dielectric layer is preferably a gate oxide layer;
- Step 20402 forming a gate electrode layer on the surface of the gate dielectric layer, etching the gate dielectric layer and the gate electrode layer, and forming a gate structure 305 on the upper surface of the first semiconductor substrate.
- Step 20403 forming a passivation layer on a surface of the gate structure 305, and the passivation layer is formed on an upper surface and a sidewall of the gate structure 305.
- Step 205 Form a source structure in the first semiconductor substrate on both sides of the gate structure 305.
- step 205 includes:
- Step 20501 performing ion implantation on the first semiconductor substrate by using the passivation layer as a mask, forming a well region 306 in an upper surface of the first semiconductor substrate, and at 1000 ° C - 1200 ° C Under the condition, the first semiconductor substrate is subjected to high temperature annealing to bring the well region 306 to a desired depth.
- the well region 306 is a P-type well region, and the doping ions thereof are preferably boron ions.
- Step 20502 performing ion implantation on the well region 306 to form a heavily doped N-type doped region in the well region 306;
- Step 20503 forming an oxide layer on the surface of the well region 306 and the source region 307, and annealing the N-type doped region at 800 ° C - 1000 ° C to form a source region 307, which is doped
- the ion is preferably an arsenic ion.
- Step 20504 Forming a source electrode 308 electrically connected to the well region 306 and the source region 307 on the surface of the well region 306 and the source region 307.
- the source electrode 308 is preferably an aluminum electrode, the formation process of which is preferably deposition.
- Step 206 forming a protective layer on the surface of the gate structure and the source structure to prevent the gate structure and the source structure from being contaminated by the external environment.
- Step 207 performing ion implantation on a lower surface of the second semiconductor substrate, and performing annealing at 450 ° C to form a collector region 304, a doping type of the collector region 304 and the drift region.
- the doping type is different and is a P-type collector region.
- Step 208 forming a collector electrically connected to the collector region 306 on the lower surface of the collector region 304, the collector electrode is preferably an aluminum electrode, and the forming process is preferably deposition.
- the IGBT fabricated by the IGBT forming method provided by the embodiment of the invention has a good compromise between switching loss and conduction loss, improves the overall performance of the IGBT, and has low manufacturing cost.
- Embodiment 3 is a diagrammatic representation of Embodiment 3
- the embodiment of the invention provides a method for forming the IGBT according to another embodiment 1.
- the IGBT forming method provided by the present invention includes:
- Step 301 providing a first semiconductor substrate, where the first semiconductor substrate includes a first drift region
- Step 302 forming at least one doping region 303 in a lower surface of the first semiconductor substrate, a doping type of the doping region 303 is the same as a doping type of the first drift region 301, and the The doping concentration of the doping region 303 is greater than the doping concentration of the first drift region 301.
- Step 303 forming a second semiconductor substrate on a lower surface of the first semiconductor substrate, the doping type and concentration of the second semiconductor substrate and the first semiconductor substrate are the same, and is also N-type lightly doped Semiconductor substrate.
- the second semiconductor substrate includes a second drift region 302, the second drift region 302 is located on a lower surface of the first drift region 301, and completely covers the first drift region and the doped region;
- the forming process of the second semiconductor substrate is preferably epitaxial; in another embodiment of the present invention, the second semiconductor substrate is along the second semiconductor substrate
- the thickness in the direction of the first semiconductor substrate ranges from 5 ⁇ m to 10 ⁇ m, including the endpoint value, but the invention is not limited thereto.
- Step 304 performing ion implantation on the first semiconductor substrate, forming a well region 306 in an upper surface of the first semiconductor substrate, and performing the first semiconductor on a condition of 1000 ° C to 1200 ° C
- the substrate is annealed at a high temperature to bring the well region 306 to the desired depth.
- the well region 306 is a P-type well region, and the doping ions thereof are preferably boron ions.
- Step 305 forming a gate structure in the first semiconductor substrate, wherein the gate structure penetrates through The well region 306 is described.
- step 305 includes:
- Step 30501 forming a groove in the first semiconductor substrate, the groove penetrating the well region;
- Step 30502 forming a gate dielectric layer on a surface of the first semiconductor substrate having the groove;
- Step 30502 Form a gate electrode layer on the surface of the gate dielectric layer, and etch the excess gate dielectric layer and the gate electrode layer to form a gate structure 305.
- the forming process of the gate electrode layer is preferably deposition.
- Step 306 Form a source structure in the first semiconductor substrate.
- step 306 includes:
- Step 30601 forming a passivation layer on the surface of the gate structure 305 and the well region 306, and forming an etch window in the passivation layer, and the etch window and the source region 307 to be formed in the well region 306 Corresponding to the location;
- Step 30602 performing ion implantation on the well region 306 to form a heavily doped N-type doped region in the well region 306;
- Step 30603 forming a passivation layer on the surface of the N-type doped region, and annealing the N-type doped region under conditions of 800 ° C to 1000 ° C to form a source region 307, which is doped ion It is preferably an arsenic ion.
- Step 30604 removing the passivation layer on the surface of the well region 306 and the source region 307, and forming a source electrode 308 electrically connected to the well region 306 and the source region 307 on the surface of the well region 306 and the source region 307.
- the source electrode 308 is preferably an aluminum electrode, the formation process of which is preferably deposition.
- Step 307 forming a protective layer on the surface of the gate structure and the source structure to prevent the gate structure and the source structure from being contaminated by the external environment.
- Step 308 performing ion implantation on a lower surface of the second semiconductor substrate, and performing annealing at 450 ° C to form a collector region 304, a doping type of the collector region 304 and the drift region.
- the doping type is different and is a P-type collector region.
- the IGBT fabricated by the IGBT forming method provided by the embodiment of the present invention has a good compromise between the switching loss and the conduction loss, improves the overall performance of the IGBT, and has low manufacturing cost.
- the various parts of this manual are described in a progressive manner. Each part focuses on the differences between the other parts. The same similar parts between the parts can be referred to each other.
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Abstract
公开了一种绝缘栅双极型晶体管(IGBT)及其元胞结构,和IGBT形成方法,其中所述IGBT元胞结构包括:第一漂移区(301)和位于第一漂移区(301)下表面的第二漂移区(302),第一漂移区(301)与第二漂移区(302)的掺杂类型和浓度均相同;至少一个位于第一漂移区(301)和第二漂移区(302)之间的掺杂区(303),掺杂区(303)的掺杂类型与第二漂移区(302)的掺杂类型相同,且掺杂区(303)的掺杂浓度大于第二漂移区(302)的掺杂浓度;位于第二漂移区(302)背离掺杂区(303)一侧的集电区(304),集电区(304)的掺杂类型与所述第二漂移区(302)的掺杂类型相反。所述IGBT结构具有良好的导通损耗与开关损耗之间的折中关系,整体性能比较高。
Description
IGBT及其元胞结构、 以及 IGBT的形成方法
技术领域
本发明涉及半导体器件制造技术领域,尤其涉及一种 IGBT及其元胞结构、 以及 IGBT的形成方法。 背景技术
绝缘栅双极型晶体管 ( Insulated Gate Bipolar Transistor, 简称 IGBT )是由 双极型三极管 (BJT )和绝缘栅型场效应管 (MOSFET )组成的复合全控型电 压驱动式功率半导体器件, 兼有 MOSFET器件的高输入阻抗和电力晶体管 (即 巨型晶体管, 简称 GTR ) 的低导通压降两方面的优点, 由于 IGBT具有驱动功 率小而饱和压降低的优点, 目前 IGBT作为一种新型的电力电子器件被广泛应 用到各个领域。
IGBT在纵向结构上主要包括非穿通型 IGBT (简称 NPT-IGBT ) 和穿通型 IGBT (简称 PT-IGBT )。其中, 非穿通型 IGBT具有制作工艺简单, 生产成本低, 较好的安全电压特性、具有正温度系数的导通电压和开关损耗低等优点。但是, 其导通损耗较大。而相较于非穿通型 IGBT,穿通型 IGBT具有较低的导通损耗, 但是其开关损耗较大。
由于所述 IGBT在具体应用时存在开关和导通两种状态, 而开关损耗与导 通损耗之间存在着此消彼长的关系, 导致现有技术中的 IGBT或者开关损耗较 小, 导通损耗较大, 或者导通损耗较小, 开关损耗较大, 即现有技术中 IGBT 的开关损耗与导通损耗之间的折中关系较差。
发明内容
为解决上述技术问题, 本发明实施例提供了一种 IGBT及其元胞结构, 和
IGBT 的形成方法。 本发明所提供的 IGBT, 具有良好的开关损耗与导通损耗 之间的折中关系, 提高了 IGBT的整体性能。 为解决上述问题, 本发明实施例提供了如下技术方案:
一种 IGBT元胞结构, 包括: 第一漂移区和位于所述第一漂移区下表面的 第二漂移区, 所述第一漂移区与所述第二漂移区的掺杂类型和浓度均相同; 至 少一个位于所述第一漂移区和第二漂移区之间的掺杂区,所述掺杂区的掺杂类 型与所述第二漂移区的掺杂类型相同,且所述掺杂区的掺杂浓度大于所述第二 漂移区的掺杂浓度; 位于所述第二漂移区背离所述掺杂区一侧的集电区, 所述 集电区的掺杂类型与所述第二漂移区的掺杂类型相反。
优选的, 所述掺杂区的个数至少为两个时, 相邻的掺杂区间隔分布。
优选的, 所述掺杂区的掺杂离子为砷离子或锑离子。
优选的, 所述掺杂区掺杂浓度范围为 5*1015cn 3-9*1017cn 3, 包括端点值。 优选的, 所述掺杂区的个数范围为 2-4, 包括端点值。
优选的, 所述掺杂区均匀分布。
优选的, 相邻掺杂区之间的间距为所述掺杂区宽度的 1-3倍。
优选的, 所述掺杂区的深度范围为 3 μ ηι-8 μ ηι, 包括端点值。
优选的, 所述掺杂区与所述集电区的间距范围为 4 μ ηι-9 μ ηι, 包括端点 值。
一种 IGBT, 包括至少一个上述任一项中所述的元胞结构。
一种 IGBT的形成方法, 包括: 提供第一半导体衬底, 所述第一半导体衬 底包括第一漂移区; 在所述第一半导体衬底的下表面内形成至少一个掺杂区, 所述掺杂区的掺杂类型与所述第一漂移区的掺杂类型相同,且所述掺杂区的掺 杂浓度大于所述第一漂移区的掺杂浓度;在所述第一半导体衬底下表面形成第
二半导体衬底,所述第二半导体衬底与所述第一半导体衬底的掺杂类型和浓度 均相同,且所述第二半导体衬底包括第二漂移区, 所述第二漂移区完全覆盖所 述第一漂移区和所述掺杂区; 在所述第二半导体衬底下表面内形成集电区。
优选的,在所述第一半导体衬底的下表面内形成至少一个掺杂区包括: 在 所述第一半导体下表面内形成氧化层; 在所述氧化层内形成刻蚀窗口, 所述刻 蚀窗口与所述第一半导体衬底内待形成掺杂区的位置相对应;以具有刻蚀窗口 的氧化层为掩膜, 在所述第一半导体衬底内形成至少一个掺杂区。
优选的, 所述掺杂区的形成工艺为离子注入或热淀积。
优选的, 所述掺杂区的形成工艺为离子注入时,掺杂离子的注入能量小于 40keV。
优选的, 所述第二半导体衬底的形成工艺为外延。
优选的, 所述第二半导体衬底的厚度范围为 5 μ ηι-10 μ ηι, 包括端点值。 与现有技术相比, 上述技术方案具有以下优点: 本发明实施例所提供的技术方案,包括至少一个位于所述第一漂移区和第 二漂移区之间的掺杂区, 所述掺杂区的掺杂类型与所述漂移区的掺杂类型相 同,且所述掺杂区的掺杂浓度大于所述漂移区的掺杂浓度,从而使得在承受相 同的击穿电压时, 本发明技术方案中所提供的 IGBT, 相较于传统的非穿通型 IGBT, 降低了导通损耗; 相较于穿通型 IGBT, 降低了关断损耗, 从而优化了 IGBT的导通损耗与开关损耗的折中关系。 在具有相同的器件厚度时, 本发明技术方案中所提供的 IGBT, 相较于传 统的非穿通型 IGBT, 降低了关断损耗, 而相较于传统的穿通型 IGBT, 降低 了导通损耗, 从而优化了 IGBT的导通损耗与开关损耗的折中关系。 因此,本发明所提供的 IGBT具有良好的导通损耗与开关损耗之间的折中 关系, 整体性能比较高。
附图说明
图 1为现有技术中非穿通型 IGBT的结构示意图;
图 2为现有技术中穿通型 IGBT的结构示意图;
图 3为本发明实施例所提供的 IGBT的结构示意图。 具体实施方式
现有技术中穿通型 IGBT和非穿通型 IGBT均包括多个元胞结构。 如图 1所 示, 非穿通型 IGBT的元胞结构主要包括: N型轻掺杂 (N- ) 的衬底、 位于所 述 N型轻掺杂 (N- ) 的衬底正面的正面结构, 以及位于所述 N型轻掺杂 (N- ) 的衬底背面的背面结构。其中,所述正面结构包括:位于所述 N型轻掺杂(N- ) 的衬底上表面的栅极结构 104; 位于 N-衬底上表面内的 P型阱区 102 (一般为 P 型轻掺杂), 位于 P型阱区 102表面内的 N型源区 103; 位于 P型阱区 102和 N型源 区 103表面上的源极电极 105。
所述背面结构包括:位于 N-衬底背面的 P型重掺杂集电区 106,位于集电区 106表面的集电极 107。 所述 N型轻掺杂(N- )的衬底内除去正面结构和背面结 构的区域为漂移区 101。
如图 2所示, 相较于非穿通型 IGBT, 穿通型 IGBT的元胞结构还包括: 形 成于所述漂移区 101与集电区 106之间的 N型緩冲层 108。
发明人研究发现, 在相同的器件厚度的条件下, 所述非穿通型 IGBT集电 区 106的注入效率高, 使得所述非穿通型 IGBT的导通损耗小, 但是在开关状态 下, 所述非穿通型 IGBT的关断尾电流较大, 使其关断损耗较大和安全电压范 围较小, 导致其作为开关应用时存在一定的缺陷, 整体性能较差。
相较于非穿通型 IGBT, 在相同的器件厚度的条件下, 由于所述緩冲层 108
的存在, 所述穿通型 IGBT集电区 106的注入效率低, 具有更高的击穿电压, 虽 然降低了所述穿通型 IGBT的关断损耗, 但导致所述穿通型 IGBT的导通损耗比 较大。
在承受相同的击穿电压时, 所述非穿通型 IGBT的开关损耗比较小, 但其 整体厚度比较大, 从而使得其导通压降比较大, 导通损耗比较大。 相较于非穿 通型 IGBT, 所述穿通型 IGBT的漂移区比较薄, 导通损耗比较小, 但是其关断 损耗比较大。 而且, 现有技术中所述穿通型 IGBT的制作工艺中, 需要外延很 厚的漂移区, 从而大大增加了所述穿通型 IGBT制作成本。
基于上述研究的基础上, 本发明提供了一种 IGBT及其元胞结构, 和 IGBT 的形成方法, 使得本发明所提供的 IGBT, 具有良好的开关损耗与导通损耗之 间的折中关系, 提高了 IGBT的整体性能。
为使本发明的上述目的、特征和优点能够更为明显易懂, 下面结合附图对 本发明的具体实施方式做详细的说明。本发明实施例以所述 IGBT为平面栅结 构 IGBT为例进行说明, 但同样适用于沟槽栅结构 IGBT, 本发明对此并不做 限定。
在以下描述中阐述了具体细节以便于充分理解本发明。但是本发明能够以 多种不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明 内涵的情况下做类似推广。 因此本发明不受下面公开的具体实施的限制。 实施例一:
本发明实施例提供了一种 IGBT元胞结构,以及包括至少一个该元胞结构 的 IGBT。 如图 3所示, 本发明实施例所提供的 IGBT元胞结构包括:
漂移区,所述漂移区包括第一漂移区 301和位于所述第一漂移区 301下表 面的第二漂移区 302, 所述第一漂移区 301与所述第二漂移区 302的掺杂类型 和浓度均相同;
至少一个位于所述第一漂移区 301和第二漂移区 302之间的掺杂区 303 , 所述掺杂区 303的掺杂类型与所述第二漂移区的掺杂类型相同,且所述掺杂区 303的掺杂浓度大于所述第二漂移区的掺杂浓度;
位于所述第二漂移区 302背离所述掺杂区 303—侧的集电区 304, 所述集 电区 304的掺杂类型与所述第二漂移区的掺杂类型相反。
此外, 本发明实施例还包括: 位于所述漂移区正面的正面结构, 所述正面 结构包括位于所述漂移区上表面的栅极结构 305; 位于所述栅极结构 305两侧 的漂移区上表面的阱区 306; 位于所述阱区 306上表面内的源区 307; 位于所 述源区 307上表面, 且与所述源区 307电连接的源极电极 308。 其中, 所述源 极电极 308与所述栅极结构 305之间还形成有钝化层。
在本发明的一个实施例中,所述掺杂区 303的掺杂离子优选为砷离子或锑 离子。 由于砷离子或锑离子具有较小的扩散系数,从而避免了所述元胞结构制 作过程中, 所述掺杂区 303向所述第一漂移区 301方向扩散的现象,从而可以 严格控制所述掺杂区 303的掺杂浓度和注入深度。
由于本发明实施例中所提供的元胞结构,包括至少一个位于所述第一漂移 区 301和第二漂移区 302之间的掺杂区 303 , 所述掺杂区 303的掺杂类型与所 述漂移区的掺杂类型相同,且所述掺杂区 303的掺杂浓度大于所述漂移区的掺 杂浓度, 从而使得在承受相同的击穿电压时, 本发明技术方案中所提供的 IGBT, 相较于传统的非穿通型 IGBT, 具有较薄的漂移区, 整体厚度比较小,
从而降低了导通损耗, 改善了器件的导通损耗与开关损耗之间的折中关系,提 高了器件的整体性能; 而相较于传统的穿通型 IGBT, 降低了关断损耗, 改善 了器件的导通损耗与开关损耗之间的折中关系, 提高了器件的整体性能。
在具有相同的器件厚度, 本发明技术方案中所提供的 IGBT结构, 相较于 传统的非穿通型 IGBT, 集电区的离子注入效率比较低, 关断损耗比较小, 而 相较于传统的穿通型 IGBT, 集电区的离子注入效率比较高,导通损耗比较小。
因此,本发明所提供的 IGBT具有良好的导通损耗与开关损耗之间的折中 关系, 整体性能比较高。
需要说明的是, 当本发明实施例所提供的元胞结构中, 包括至少两个位于 所述第一漂移区 301和第二漂移区 302之间的掺杂区 303时, 相邻的掺杂区 303间隔分布。
在本发明的一个实施例中, 所述掺杂区 303 的掺杂浓度范围为 5*1015cm"3-9*1017cm"3, 包括端点值, 所述掺杂区 303沿所述集电区 304至所 述漂移区方向上的深度 hi的范围为 3 μ ηι-8 μ ηι, 包括端点值; 为了形成质量 良好的集电区 304, 并能够 调所述集电区 304的注入效率, 进一步优化所述 IGBT的整体性能, 所述掺杂区 303与所述集电区 304沿所述集电区 304至所 述漂移区方向上的间距 h2的范围为 4 μ ηι-9 μ ηι, 包括端点值, 但本发明对此 并不做限定, 视具体的情况而定。 最靠近原点的最优点, 以提高所述 IGBT的整体性能, 在本发明的另一个实施 例中, 所述掺杂区 303的个数范围为 2-4, 包括端点值; 所述掺杂区 303在所 述第一漂移区 301 与所述第二漂移区 302的交界面上均匀分布; 相邻掺杂区 303之间的间距 b为所述掺杂区 303宽度 a的 1-3倍, 但本发明对此并不做限 定, 视具体的情况而定。
综上所述,本发明所提供的 IGBT元胞结构,以及包括该元胞结构的 IGBT, 具有良好的开关损耗与导通损耗之间的折中关系,从而提高了所述 IGBT的整 体性能。
实施例二:
本发明实施例提供了一种实施例一中所述 IGBT的形成方法。 以平面栅结 构 IGBT 为例, 本发明所提供的 IGBT形成方法包括:
步骤 201 : 提供第一半导体衬底, 所述第一半导体衬底包括第一漂移区 301。 在本发明实施例中, 所述第一半导体衬底可以为 N型掺杂, 也可以为 P 型掺杂, 视具体情况而定。 在本实施例中, 以所述半导体衬底为 N型轻掺杂 为例, 对本发明所提供的 IGBT的形成方法进行详细说明。
步骤 202: 在所述第一半导体衬底的下表面内形成至少一个掺杂区 303 , 所述掺杂区 303的掺杂类型与所述第一漂移区 301的掺杂类型相同,且所述掺 杂区 303的掺杂浓度大于所述第一漂移区 301的掺杂浓度。
在本发明的一个实施例中, 步骤 202包括:
步骤 20201 : 在所述第一半导体衬底的下表面形成氧化层, 所述氧化层完 全覆盖所述第一半导体衬底;
步骤 20202: 在所述氧化层表面形成光刻胶层, 并在所述光刻胶层表面放 置掩膜版,所述掩膜版上具有与所述第一半导体衬底内待形成掺杂区 303的位 置相对应的刻蚀窗口;
步骤 20203: 以所述掩膜版为掩膜对所述光刻胶层进行曝光、 显影, 在所 述光刻胶层内形成刻蚀窗口, 所述刻蚀窗口贯穿所述光刻胶层,且与所述第一 半导体衬底内待形成掺杂区 303的位置相对应;
步骤 20204:以具有刻蚀窗口的光刻胶层为掩膜,对所述氧化层进行刻蚀,
在所述氧化层内形成刻蚀窗口, 所述刻蚀窗口贯穿所述氧化层,且与所述第一 半导体衬底内待形成掺杂区 303的位置相对应;
步骤 20205: 以具有刻蚀窗口的氧化层为掩膜, 在所述第一半导体衬底内 形成至少一个掺杂区 303 , 所述第一掺杂区 303位于所述第一漂移区 301的下 表面。
在本发明的一个实施例中, 所述掺杂区 303的形成工艺可以为离子注入, 也可以为热淀积, 本发明对此并不做限定。 当所述掺杂区 303的形成工艺为离 子注入时, 掺杂离子的注入能量小于 40keV。
步骤 203: 去除所述第一半导体衬底下表面的氧化层, 在所述第一半导体 衬底下表面形成第二半导体衬底,所述第二半导体衬底与所述第一半导体衬底 的掺杂类型和浓度均相同, 也为 N型轻掺杂半导体衬底。 所述第二半导体衬 底包括第二漂移区 302, 所述第二漂移区 302位于所述第一漂移区 301的下表 面, 且完全覆盖所述第一漂移区和所述掺杂区;
在本发明的一个实施例中, 所述第二半导体衬底的形成工艺优选为外延, 从而可以保证所述第二漂移区 302与所述第一漂移区 301的掺杂类型和掺杂浓 度均相同。
在本发明的另一个实施例中,所述第二半导体衬底沿所述第二半导体衬底 到所述第一半导体衬底的方向上的厚度范围为 5 μ ηι-10 μ ηι, 包括端点值。 相 较于现有技术中的穿通型 IGBT形成方法, 本发明实施例所提供的 IGBT形成 方法,不需要外延很厚的漂移区,而是只需要外延厚度很小的第二半导体衬底, 从而大大降低了所述 IGBT的制作成本。
步骤 204: 在所述第一半导体衬底的上表面形成栅极结构。
在本发明的一个实施例中, 步骤 204包括:
步骤 20401 : 在所述第一半导体衬底上表面形成栅介质层, 所述栅介质层 优选为栅氧化层;
步骤 20402: 在所述栅介质层表面形成栅电极层, 并对所述栅介质层和所 述栅电极层进行刻蚀, 在所述第一半导体衬底上表面形成栅极结构 305。
步骤 20403: 在所述栅极结构 305表面形成钝化层, 所述钝化层形成于所 述栅极结构 305的上表面和侧壁。
步骤 205: 在所述栅极结构 305两侧的第一半导体衬底内形成源极结构。 在本发明的一个实施例中, 步骤 205包括:
步骤 20501 : 以所述钝化层为掩膜,对所述第一半导体衬底进行离子注入, 在所述第一半导体衬底上表面内形成阱区 306, 并在 1000°C-1200°C的条件下, 对所述第一半导体衬底进行高温退火,使所述阱区 306达到所需的深度。在本 实施例中, 所述阱区 306为 P型阱区, 其掺杂离子优选为硼离子。
步骤 20502: 对所述阱区 306进行离子注入, 在所述阱区 306内形成重掺 杂的 N型掺杂区域;
步骤 20503:在所述阱区 306和源区 307表面形成氧化层,并在 800°C -1000 °C的条件下, 对所述 N型掺杂区域进行退火, 形成源区 307, 其掺杂离子优选 为砷离子。
步骤 20504: 在所述阱区 306与源区 307的表面形成与所述阱区 306与源 区 307电连接的源极电极 308。 在本发明的一个实施例中, 所述源极电极 308 优选为铝电极, 其形成工艺优选为淀积。
步骤 206: 在所述栅极结构和源极结构表面形成保护层, 以避免所述栅极 结构和源极结构受到外界环境的污染。
步骤 207: 对所述第二半导体衬底的下表面进行离子注入, 并在 450°C的 条件下进行退火, 形成集电区 304, 所述集电区 304的掺杂类型与所述漂移区 的掺杂类型不同, 为 P型集电区。
步骤 208: 在所述集电区 304的下表面形成与所述集电区 306电连接的集 电极, 所述集电极优选为铝电极, 其形成工艺优选为淀积。
利用本发明实施例所提供的 IGBT形成方法制作的 IGBT, 具有良好的开 关损耗与导通损耗之间的折中关系 ,提高了 IGBT的整体性能,且制作成本低。
实施例三:
本发明实施例提供了另一种实施例一中所述 IGBT的形成方法。 以沟槽栅 结构 IGBT 为例, 本发明所提供的 IGBT形成方法包括:
步骤 301 : 提供第一半导体衬底, 所述第一半导体衬底包括第一漂移区
301。
步骤 302: 在所述第一半导体衬底的下表面内形成至少一个掺杂区 303 , 所述掺杂区 303的掺杂类型与所述第一漂移区 301的掺杂类型相同,且所述掺 杂区 303的掺杂浓度大于所述第一漂移区 301的掺杂浓度。
步骤 303: 在所述第一半导体衬底下表面形成第二半导体衬底, 所述第二 半导体衬底与所述第一半导体衬底的掺杂类型和浓度均相同, 也为 N型轻掺 杂半导体衬底。所述第二半导体衬底包括第二漂移区 302,所述第二漂移区 302 位于所述第一漂移区 301 的下表面, 且完全覆盖所述第一漂移区和所述掺杂 区;
在本发明的一个实施例中, 所述第二半导体衬底的形成工艺优选为外延; 在本发明的另一个实施例中,所述第二半导体衬底沿所述第二半导体衬底到所 述第一半导体衬底的方向上的厚度范围为 5 μ ηι-10 μ ηι, 包括端点值, 但本发 明对此并不做限定。
步骤 304: 对所述第一半导体衬底进行离子注入, 在所述第一半导体衬底 上表面内形成阱区 306, 并在 1000°C-1200°C的条件下, 对所述第一半导体衬 底进行高温退火, 使所述阱区 306达到所需的深度。 在本实施例中, 所述阱区 306为 P型阱区, 其掺杂离子优选为硼离子。
步骤 305: 对所述第一半导体衬底内形成栅极结构, 所述栅极结构贯穿所
述阱区 306。
在本发明的一个实施例中, 步骤 305包括:
步骤 30501 :在所述第一半导体衬底内形成凹槽,所述凹槽贯穿所述阱区; 步骤 30502: 在具有凹槽的第一半导体衬底表面形成栅介质层;
步骤 30502: 在所述栅介质层表面形成栅电极层, 并刻蚀多余的栅介质层 和栅电极层,形成栅极结构 305。其中, 所述栅电极层的形成工艺优选为淀积。
步骤 306: 在所述第一半导体衬底内形成源极结构。
在本发明的一个实施例中, 步骤 306包括:
步骤 30601 : 在所述栅极结构 305和阱区 306表面形成钝化层, 并在所 述钝化层内形成刻蚀窗口, 所述刻蚀窗口与所述阱区 306 内待形成源区 307 的位置相对应;
步骤 30602: 对所述阱区 306进行离子注入, 在所述阱区 306内形成重掺 杂的 N型掺杂区域;
步骤 30603: 在所述 N型掺杂区域表面形成钝化层, 并在 800°C-1000°C的 条件下, 对所述 N型掺杂区域进行退火, 形成源区 307, 其掺杂离子优选为砷 离子。
步骤 30604:去除所述阱区 306和源区 307表面的钝化层,在所述阱区 306 与源区 307的表面形成与所述阱区 306与源区 307电连接的源极电极 308。 在 本发明的一个实施例中, 所述源极电极 308优选为铝电极, 其形成工艺优选为 淀积。
步骤 307: 在所述栅极结构和源极结构表面形成保护层, 以避免所述栅极 结构和源极结构受到外界环境的污染。
步骤 308: 对所述第二半导体衬底的下表面进行离子注入, 并在 450°C的 条件下进行退火, 形成集电区 304, 所述集电区 304的掺杂类型与所述漂移区 的掺杂类型不同, 为 P型集电区。
步骤 309: 在所述集电区 304的下表面形成与所述集电区 306电连接的集 电极, 所述集电极优选为铝电极, 其形成工艺优选为淀积。
利用本发明实施例所提供的 IGBT形成方法制作的 IGBT, 具有良好的开 关损耗与导通损耗之间的折中关系,提高了 IGBT的整体性能,且制作成本低。 本说明书中各个部分采用递进的方式描述,每个部分重点说明的都是与其 他部分的不同之处, 各个部分之间相同相似部分互相参见即可。
对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本 发明。 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见 的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在 其它实施例中实现。 因此, 本发明将不会被限制于本文所示的实施例, 而是要 符合与本文所公开的原理和新颖特点相一致的最宽的范围。
Claims
权 利 要 求
I、 一种 IGBT元胞结构, 其特征在于, 包括:
第一漂移区和位于所述第一漂移区下表面的第二漂移区 ,所述第一漂移区 与所述第二漂移区的掺杂类型和浓度均相同;
至少一个位于所述第一漂移区和第二漂移区之间的掺杂区,所述掺杂区的 掺杂类型与所述第二漂移区的掺杂类型相同,且所述掺杂区的掺杂浓度大于所 述第二漂移区的掺杂浓度;
位于所述第二漂移区背离所述掺杂区一侧的集电区,所述集电区的掺杂类 型与所述第二漂移区的掺杂类型相反。
2、 根据权利要求 1所述的元胞结构, 其特征在于 , 所述掺杂区的个数至 少为两个时, 相邻的掺杂区间隔分布。
3、 根据权利要求 2所述的元胞结构, 其特征在于 , 所述掺杂区的掺杂离 子为砷离子或锑离子。
4、 根据权利要求 3所述的元胞结构, 其特征在于 , 所述掺杂区掺杂浓度 范围为 5*1015cm_3-9*1017cm_3, 包括端点值。
5、 根据权利要求 2所述的元胞结构, 其特征在于 , 所述掺杂区的个数范 围为 2-4, 包括端点值。
6、 根据权利要求 5所述的元胞结构, 其特征在于, 所述掺杂区均匀分布。
7、 根据权利要求 6所述的元胞结构, 其特征在于 , 相邻掺杂区之间的间 距为所述掺杂区宽度的 1-3倍。
8、 根据权利要求 1所述的元胞结构, 其特征在于 , 所述掺杂区的深度范 围为 3 μ m-8 μ m, 包括端点值。
9、 根据权利要求 1所述的元胞结构, 其特征在于 , 所述掺杂区与所述集 电区的间距范围为 4 μ m-9 μ m, 包括端点值。
10、 一种 IGBT, 其特征在于, 包括至少一个权利要求 1-9任一项中所述 的元胞结构。
II、 一种 IGBT的形成方法, 其特征在于, 包括:
提供第一半导体衬底, 所述第一半导体衬底包括第一漂移区; 在所述第一半导体衬底的下表面内形成至少一个掺杂区,所述掺杂区的掺 杂类型与所述第一漂移区的掺杂类型相同,且所述掺杂区的掺杂浓度大于所述 第一漂移区的掺杂浓度;
在所述第一半导体衬底下表面形成第二半导体衬底,所述第二半导体衬底 与所述第一半导体衬底的掺杂类型和浓度均相同,且所述第二半导体衬底包括 第二漂移区, 所述第二漂移区完全覆盖所述第一漂移区和所述掺杂区;
在所述第二半导体衬底下表面内形成集电区。
12、 根据权利要求 11所述的形成方法, 其特征在于, 在所述第一半导体 衬底的下表面内形成至少一个掺杂区包括:
在所述第一半导体下表面内形成氧化层;
在所述氧化层内形成刻蚀窗口,所述刻蚀窗口与所述第一半导体衬底内待 形成掺杂区的位置相对应;
以具有刻蚀窗口的氧化层为掩膜 ,在所述第一半导体衬底内形成至少一个 掺杂区。
13、 根据权利要求 12所述的形成方法, 其特征在于, 所述掺杂区的形成 工艺为离子注入或热淀积。
14、 根据权利要求 13所述的形成方法, 其特征在于, 所述掺杂区的形成 工艺为离子注入时, 掺杂离子的注入能量小于 40keV。
15、 根据权利要求 11所述的形成方法, 其特征在于, 所述第二半导体衬 底的形成工艺为外延。
16、 根据权利要求 15所述的形成方法, 其特征在于, 所述第二半导体衬 底的厚度范围为 5 μ ηι-10 μ ηι, 包括端点值。
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