CN103872108A - 一种igbt结构及其制备方法 - Google Patents

一种igbt结构及其制备方法 Download PDF

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CN103872108A
CN103872108A CN201210526291.9A CN201210526291A CN103872108A CN 103872108 A CN103872108 A CN 103872108A CN 201210526291 A CN201210526291 A CN 201210526291A CN 103872108 A CN103872108 A CN 103872108A
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trench gate
shallow
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drift region
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CN103872108B (zh
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赵佳
朱阳军
胡爱斌
卢烁今
田晓丽
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Institute of Microelectronics of CAS
Jiangsu IoT Research and Development Center
Jiangsu CAS IGBT Technology Co Ltd
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Institute of Microelectronics of CAS
Jiangsu IoT Research and Development Center
Jiangsu CAS IGBT Technology Co Ltd
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

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Abstract

本发明公开了一种IGBT结构及其制备方法，属于半导体大功率器件的技术领域。该结构包括n-漂移区、一个以上的沟槽栅、p基区、n+发射极区、浅p基区、层间氧化层、金属层和p+集电极区；其中，n-漂移区的上方有至少两个的沟槽栅，p基区分别位于沟槽栅的内侧，沟槽栅之间为浅p基区，层间氧化层在沟槽栅和浅p基区上，n+发射极区分别位于沟槽栅的两侧，金属层在层间氧化层上，p+集电极区在n-漂移区的背面。本发明拉宽沟槽型IGBT中发射极之间的距离，大大降低了翘曲发生的概率。另外，电流密度比较低，能够降低整个器件的短路电流，拓宽器件安全工作区。

Description

一种IGBT结构及其制备方法
技术领域
本发明属于半导体大功率器件的技术领域，特别涉及一种IGBT结构及其制备方法。
背景技术
IGBT的全称是Insulate Gate Bipolar Transistor，即绝缘栅双极晶体管。它兼具MOSFET和GTR的多项优点，极大的扩展了功率半导体器件的应用领域。作为新型电力半导体器件的主要代表，IGBT被广泛用于工业、信息、新能源、医学、交通、军事和航空领域。
高压IGBT目前还是设计上的一个难点。为了减小器件本身的功率损耗,希望器件的导通压降越小越好；为了达到更高的反向阻断电压，需要增加N-漂移区的厚度及电阻率，而这样势必加大器件的导通压降。为了调和反向阻断电压和导通压降二者的矛盾，要求IGBT各个结构参数做尽可能的最优化设计。
沟槽栅型IGBT是IGBT的一个发展方向，它采用沟槽栅代替平面栅，改善了器件的导通特性，降低了导通电阻，现有技术中IGBT的结构如图1所示，1为n-漂移区，2为沟槽栅（器件的栅极G），其中，两个沟槽栅之间的距离在10um之内，5为层间氧化层，6为发射极金属，7为p+集电极区（器件的集电极C），在沟槽栅结构中，n+发射极区4和p型基区3内形成了垂直于硅片表面的沟道。工作时电流从p+集电极区出发经过N-漂移区1直接流进垂直沟道而进入n+发射极区4。
为了达到更高的电压，需要增加N-漂移区的厚度及电阻率，而这样势必加大器件的导通电阻。而且现有的沟槽IGBT的饱和电流密度过大，也使得短路安全工作区（SCSOA）减小。因为有源区域中沟槽所占比例较高，在圆片制备过程中，发生翘曲的风险很大。翘曲一旦发生，可能会导致后续光刻版无法对准，严重的会导致碎片。
发明内容
本发明所要解决的技术问题是提供一种IGBT结构及其制备方法，解决了现有技术中IGBT结构容易翘曲的技术问题。
为解决上述技术问题，本发明提供了一种IGBT结构，包括n-漂移区、一个以上的沟槽栅、p基区、n+发射极区、浅p基区、层间氧化层、金属层和p+集电极区；其中，所述n-漂移区的上方有至少两个的沟槽栅，所述p基区分别位于所述沟槽栅的内侧，所述沟槽栅之间为所述浅p基区，所述层间氧化层在所述沟槽栅和所述浅p基区上，所述n+发射极区分别位于所述沟槽栅的两侧，所述金属层在所述层间氧化层上，所述p+集电极区在所述n-漂移区的背面。
进一步地，所述沟槽栅之间的距离在20um以上。
进一步地，所述浅p基区的深度大于所述沟槽栅的深度。
一种IGBT结构的制备方法，包括如下步骤：
将N-型衬底制备成n-漂移区；在所述n-漂移区的上方刻蚀出一个以上的沟槽栅，在所述沟槽栅之间依次经过离子注入和高温退火形成浅p基区；然后在所述沟槽栅的两侧通过离子注入和高温退火形成p基区和n+发射极区，在所述沟槽栅和浅p基区上通过低压化学沉积方法形成层间氧化层，在所述层间氧化层上淀积金属层，在N-型衬底的背面，通过高能离子注入形成p+集电极区。
进一步地，所述形成浅p基区的离子为B离子。
进一步地，所述B离子的剂量为1e14atom/cm2。
本发明提供的一种IGBT结构，拉宽沟槽型IGBT中发射极之间的距离，增强了电导调制效应，降低了器件的导通压降，降低了整个芯片中，沟槽所占比例，从而大大降低了翘曲发生的概率。另外，电流密度比较低，能够降低整个器件的短路电流，拓宽器件安全工作区。
附图说明
图1为现有技术提供的IGBT结构示意图；
图2为本发明实施例提供的一种IGBT结构示意图；
附图标记：
1、n-漂移区，2、沟槽栅，3、p基区，4、n+发射极区，5、浅p基区，6、层间氧化层，7、金属层，8、p+集电极区。
具体实施方式
参见图1，本发明实施例提供的一种IGBT结构，包括n-漂移区1、一个以上的沟槽栅2、p基区3、n+发射极区4、浅p基区5、层间氧化层6、金属层7和p+集电极区8；其中，n-漂移区1的上方刻蚀至少两个沟槽,形成沟槽栅2，p基区3分别位于沟槽栅2的两侧，沟槽栅2之间为浅p基区5，层间氧化层6在沟槽栅2和浅p基区5上，n+发射极区4分别位于沟槽栅2的两侧，金属层7在层间氧化层6上，p+集电极区8在n-漂移区1的背面。另外，该IGBT结构同时适用于NPT及FS型IGBT器件。
其中，沟槽栅2之间的距离在20um以上。本发明实施例增大了沟槽型IGBT的两个发射极的距离。当IGBT的集射极加以正向电压(VCE>0)，栅射极电压（VGE）超过栅极的阈值电压（VT）时，在p基区与沟槽栅的交界面开始形成导电沟道，电子由n+发射区经沟道流向n-漂移区，导致n-漂移区电位下降，于是IGBT的p+集电极区不断向n-漂移区注入空穴。注入的空穴一部分与沟道过来的电子在这里复合，形成电子电流，一部分会在n-漂移区中扩散，经过p基区最终到达发射极，形成空穴电流。
本发明实施例提供的IGBT结构的制备方法如下：
步骤101：选择N-型衬底，将所述N-型衬底制备成n-漂移区1；
步骤102：使用第二块光刻掩膜版，在n-漂移区的上方刻蚀出一个以上的沟槽栅；
步骤103：使用第一块光刻掩膜版，在沟槽栅之间注入B离子，其中，注入的剂量为1e14atom/cm2,注入的能量80kev，约150min-200min后，经1000℃-1200℃的退火，形成浅p基区5；
步骤104:在在所述沟槽栅的两侧注入B离子，其中，注入的剂量约为1e13atom/cm2,注入的能量为80kev，通过100min后退火，退火温度为1000℃，形成p基区3；
步骤105：使用第四块光刻掩膜版，在沟槽栅的两侧注入AS离子及P离子，形成n+发射极区4，注入能量和剂量分别为80kev和2e15atom/cm2；
步骤106：在N-型衬底表面，采用低压化学淀积工艺，在580℃-650℃下热分解硅烷，形成厚度约为1um的多晶硅层；使用第三块光刻掩膜版，刻蚀除沟槽以外的多晶硅层，形成栅极；
步骤107：使用低压化学沉积工艺，在650℃-750℃下分解正硅酸乙酯，在N-型衬底表面形成层间氧化层6；
步骤108：在层间氧化层上淀积金属层7，该金属层的金属为Al；
步骤109：在N-型衬底的背面，通过高能离子注入形成p+集电极区8；p+集电极区的离子为B元素,离子的能量50kev,离子的剂量1e15atom/cm2。
本发明实施例提出的IGBT结构中，两个沟槽中间间隔较大，且没有连接发射极。因此注入的空穴在n-漂移区扩散过程中，会在浅p基区积累起来，因为浅p基区与n-漂移区电位相连，因此积累的空穴导致n-漂移区的电位升高。为了保持n-漂移区的电中性，n+发射区向n-漂移区注入大量的电子，即产生电导调制效应，此时IGBT体内充满了大量的非平衡载流子。上述过程不断重复，最终达到动态平衡，n-基区充满了非平衡载流子，具有很低的通态压降。
当IGBT的VGE低于阈值电压VT，并降为零或负值时，导电沟道立即消失，从发射极注入的电子电流很快减小到零，此时，n-漂移区中的非平衡载流子除不断复合外，一部分电子进入集电极区，一部分空穴通过扩散进入p基区，直到所有的非平衡截流子复合消失，器件彻底关断。
本发明实施例通过改变栅极结构，在集电极侧空穴注入不增加的情况下，大大增加发射极侧的电子注入量，从而器件内部靠阴极侧的载流子浓度明显提高，其分布类似于通态时的pin二极管。由于注入增强效应引起的是阴极侧的电子注入增强，而集电极侧的空穴注入并没有增强，所以，与传统IGBT相比，本发明的关断时间不会明显增大。
随着现代硅片加工工艺的进步，硅晶片尺寸越来越大，厚度越来越薄。在这样的硅晶片上进行复杂的刻蚀、淀积等操作，以及多步升降温及高温处理，其中产生的机械应力及热应力容易使平整的硅片发生翘曲。翘曲一旦发生，轻则使掩膜版对准困难，光刻图形出现偏差，影响最终器件的性能。重则整枚硅片破碎废片。对沟槽型IGBT来说，沟槽密度越大，则发生翘曲的风险也越高。本发明提出的结构，加大了沟槽间距，因而降低了沟槽密度，能够有效防止翘曲。
如果只是一味的加大沟槽间的距离，则器件的反向阻断电压会随着沟槽间距的增大而降低。在两个沟槽中间注入p型离子，形成掺杂较浅，深度较深（深于沟槽的深度）的p型掺杂区，浅p基区的深度大于沟槽栅的深度，可以平衡电场，保证反向阻断电压不会随沟槽间距的增加而降低。从而保持反向阻断电压不降低。
本发明的优点：
1、本发明在传统IGBT的基础上，拉宽沟槽型IGBT中发射极之间的距离，增强了电导调制效应，降低了器件的导通压降；
2、在相邻的两个沟槽之间，注入B离子，形成浅P基区，此区域深度大于沟槽底部，可以平衡电场，保证反向阻断电压不会随沟槽间距的增加而降低；
3、本发明降低了整个芯片中，沟槽所占比例，从而大大降低了翘曲发生的概率；
4、本发明电流密度比较低，能够降低整个器件的短路电流，拓宽器件安全工作区。
最后所应说明的是，以上具体实施方式仅用以说明本发明的技术方案而非限制，尽管参照实例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (6)

1.一种IGBT结构，其特征在于，包括n-漂移区、一个以上的沟槽栅、p基区、n+发射极区、浅p基区、层间氧化层、金属层和p+集电极区；其中，所述n-漂移区的上方有至少两个的沟槽栅，所述p基区分别位于所述沟槽栅的内侧，所述沟槽栅之间为所述浅p基区，所述层间氧化层在所述沟槽栅和所述浅p基区上，所述n+发射极区分别位于所述沟槽栅的两侧，所述金属层在所述层间氧化层上，所述p+集电极区在所述n-漂移区的背面。
2.根据权利要求1所述的IGBT结构，其特征在于，所述沟槽栅之间的距离在20um以上。
3.根据权利要求1所述的IGBT结构，其特征在于，所述浅p基区的深度大于所述沟槽栅的深度。
4.一种IGBT结构的制备方法，其特征在于，包括如下步骤：
将N-型衬底制备成n-漂移区；在所述n-漂移区的上方刻蚀出一个以上的沟槽栅，在所述沟槽栅之间依次经过离子注入和高温退火形成浅p基区；然后在所述沟槽栅的两侧通过离子注入和高温退火形成p基区和n+发射极区，在所述沟槽栅和浅p基区上通过低压化学沉积方法形成层间氧化层，在所述层间氧化层上淀积金属层，在N-型衬底的背面，通过高能离子注入形成p+集电极区。
5.根据权利要求4所述的方法，其特征在于，所述形成浅p基区的离子为B离子。
6.根据权利要求5所述的方法，其特征在于，所述B离子的剂量为1e14atom/cm2。
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