WO2014086075A1 - 一种igbt结构及其制备方法 - Google Patents

一种igbt结构及其制备方法 Download PDF

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Publication number
WO2014086075A1
WO2014086075A1 PCT/CN2012/088110 CN2012088110W WO2014086075A1 WO 2014086075 A1 WO2014086075 A1 WO 2014086075A1 CN 2012088110 W CN2012088110 W CN 2012088110W WO 2014086075 A1 WO2014086075 A1 WO 2014086075A1
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region
shallow
base region
trench
igbt
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PCT/CN2012/088110
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English (en)
French (fr)
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朱阳军
赵佳
卢烁今
田晓丽
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中国科学院微电子研究所
江苏物联网研究发展中心
江苏中科君芯科技有限公司
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Publication of WO2014086075A1 publication Critical patent/WO2014086075A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

Definitions

  • the invention belongs to the technical field of semiconductor high-power devices, and particularly relates to an IGBT structure and a preparation method thereof. Background technique
  • IGBT Insu la te Ga te Bi ar Trans i s tor , that is, an insulated gate bipolar transistor. It combines the advantages of M0SFET and GTR, greatly expanding the application area of power semiconductor devices. As the main representative of new power semiconductor devices, IGBTs are widely used in industrial, information, new energy, medical, transportation, military and aerospace fields.
  • High voltage IGBTs are still a difficult design.
  • the on-state voltage drop of the device is as small as possible; in order to achieve a higher reverse blocking voltage, it is necessary to increase the thickness and resistivity of the N-drift region, which is bound to increase the device.
  • the conduction voltage drop In order to reconcile the contradiction between the reverse blocking voltage and the conduction voltage drop, it is required to optimize the individual structural parameters of the IGBT as much as possible.
  • Trench gate IGBT is a development direction of IGBT. It uses trench gate instead of planar gate, which improves the conduction characteristics of the device and reduces the on-resistance.
  • the structure of IGBT in the prior art is shown in Figure 1, 1 N-drift region, 2 is the trench gate (gate G of the device), wherein the distance between the two trench gates is within 10, 5 is the interlayer oxide layer, 6 is the emitter metal, 7 is The p+ collector region (collector C of the device), in the trench gate structure, a channel perpendicular to the surface of the silicon wafer is formed in the n+ emitter region 4 and the p-type base region 3. During operation, current flows from the p+ collector region through the N-drift region 1 and directly into the vertical channel into the n+ emitter region 4.
  • the technical problem to be solved by the present invention is to provide an I GBT structure and a preparation method thereof, which solves the technical problem that the IGBT structure is easily warped in the prior art.
  • the present invention provides an IGBT structure including an n_drift region, one or more trench gates, a p-base region, an n+ emitter region, a shallow p-base region, an interlayer oxide layer, a metal layer, and p+ a collector region; wherein, the n-drift region has at least two trench gates thereon, the p-base regions are respectively located inside the trench gates, and the shallow trenches between the trench gates a base region, the interlayer oxide layer is on the trench gate and the shallow p base region, the n+ emitter regions are respectively located at two sides of the trench gate, and the metal layer is between the layers On the oxide layer, the p+ collector region is on the back side of the n-drift region.
  • the distance between the trench gates is above 2 Oum.
  • a method for preparing an IGBT structure includes the following steps:
  • Forming an N-type substrate into an n-drift region etching more than one trench gate over the n-drift region, and sequentially performing ion implantation and high-temperature annealing between the trench gates to form a shallow p a base region; then forming a p-base region and an n+ emitter region by ion implantation and high-temperature annealing on both sides of the trench gate, and forming an interlayer oxidation by the low-pressure chemical deposition method on the trench gate and the shallow p-base region a layer deposited on the interlayer oxide layer
  • the metal layer forms a p+ collector region by high energy ion implantation on the back side of the N-type substrate.
  • the ions forming the shallow p base region are B ions.
  • the dose of the B ion is l el 4a tom/cm 2 .
  • the invention provides an IGBT structure, which widens the distance between the emitters in the trench IGBT, enhances the conductance modulation effect, reduces the on-voltage drop of the device, and reduces the proportion of the trench in the whole chip. Thereby greatly reducing the probability of warpage occurring.
  • the current density is relatively low, which can reduce the short-circuit current of the entire device and widen the safe working area of the device.
  • FIG. 1 is a schematic structural view of an IGBT provided by the prior art
  • FIG. 2 is a schematic structural diagram of an IGBT according to an embodiment of the present invention.
  • an IGBT structure includes an n-drift region, one or more trench gates 2, a p-base region 3, an n+ emitter region 4, a shallow p-base region 5, and interlayer oxidation.
  • the IGBT structure is suitable for both NPT and FS type IGBT devices.
  • the distance between the trench gates 2 is 20 or more.
  • Embodiments of the present invention increase the distance between the two emitters of a trench IGBT.
  • VCE forward voltage
  • VGE gate emitter voltage
  • VT threshold voltage
  • Embodiments of the present invention increase the distance between the two emitters of a trench IGBT.
  • VCE forward voltage
  • VGE gate emitter voltage
  • VT threshold voltage
  • a conductive channel is formed at the interface between the p-base region and the trench gate.
  • the electrons flow from the n+ emitter region through the channel to the n-drift region, causing the potential of the n-drift region to drop, and the p+ collector region of the IGBT continuously injects holes into the n-drift region.
  • a portion of the injected holes recombine with the electrons coming from the channel to form an electron current, a portion of which will diffuse in the n-drift region, and finally pass through the p-base region to the emitter to form a hole current.
  • Step 101 Select an N-type bottom, and prepare the N-type bottom as an n-drift area
  • Step 102 using a second lithography mask, etching more than one trench gate over the n-drift region;
  • Step 103 Injecting B ions between the trench gates using the first photolithography mask, wherein the implanted dose is lel4 atom/cm 2 , and the injected energy is 80 keV.
  • Step 104 B ions are implanted on both sides of the trench gate, wherein the implanted dose is about ll3 atom / cm 2 , injected The energy is 80 keV, after annealing through 100 min, the annealing temperature is 1000 ° C, forming a p-base region 3;
  • Step 105 using a fourth lithography mask, implanting AS ions and P ions on both sides of the trench gate to form an n+ emitter region 4, the implantation energy and the dose are 80 keV and 2el5 atom/cm 2 respectively ;
  • Step 106 On the surface of the N-type substrate, a low-pressure chemical deposition process is used to thermally decompose the silane at 580 ° C to 650 ° C to form a polysilicon layer having a thickness of about lum; using a third photolithography mask, Etching a polysilicon layer other than the trench to form a gate; Step 107: Decomposing tetraethyl orthosilicate at 650 ° C -750 ° C using a low pressure chemical deposition process to form an interlayer oxide layer 6 on the surface of the N - type substrate;
  • Step 108 depositing a metal layer 7 on the interlayer oxide layer, the metal of the metal layer is
  • Step 109 On the back side of the N-type substrate, the p+ collector region 8 is formed by high-energy ion implantation; the ions in the p+ collector region are B elements, the energy of the ions is 50 keV, and the dose of ions is l el 5a tom/cm 2 .
  • the two trenches are spaced apart in the middle and are not connected to the emitter. Therefore, the injected holes will accumulate in the shallow P base region during the diffusion process of the n-drift region, because the shallow p-base region is connected to the n-drift region potential, so the accumulated holes cause the potential of the n-drift region to rise. .
  • the n+ emitter region injects a large amount of electrons into the n-drift region, which produces a conductance modulation effect.
  • the IGBT body is filled with a large number of unbalanced carriers. The above process is repeated, eventually achieving dynamic equilibrium, and the n-base region is filled with unbalanced carriers with a very low on-state voltage drop.
  • the conductive channel disappears immediately, and the electron current injected from the emitter is quickly reduced to zero.
  • the unbalanced load in the n_drift region In addition to continuous recombination, a portion of the electrons enter the collector region, and a portion of the holes diffuse into the P-base region until all of the non-equilibrium interceptors disappear and the device is completely turned off.
  • the hole injection on the collector side is not increased, and the electron injection amount on the emitter side is greatly increased, so that the carrier concentration on the cathode side of the device is obviously improved, and the distribution thereof is similar.
  • P in diode in the on state Since the injection enhancement effect causes the electron injection enhancement on the cathode side, and the hole injection on the collector side is not enhanced, the present invention is compared with the conventional IGBT. The turn-off time does not increase significantly.
  • the reverse blocking voltage of the device will decrease as the pitch of the trench increases.
  • P-type ions are implanted in the middle of the two trenches to form a P-doped region with shallower doping and deeper depth (deeper than the depth of the trench), shallow!
  • the depth of the base region is greater than the depth of the trench gate, and the electric field can be balanced to ensure that the reverse blocking voltage does not decrease as the trench pitch increases. Thereby keeping the reverse blocking voltage from decreasing.
  • the invention widens the distance between the emitters of the trench type IGBT on the basis of the conventional IGBT, enhances the conductance modulation effect, and reduces the conduction voltage drop of the device;
  • B ions are implanted between two adjacent trenches to form a shallow P-base region.
  • the depth of this region is greater than the bottom of the trench, and the electric field can be balanced to ensure that the reverse blocking voltage does not increase with the pitch of the trench.
  • the invention reduces the proportion of trenches in the entire chip, thereby greatly reducing the probability of occurrence of warpage

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Abstract

一种IGBT结构及其制备方法。IGBT的结构包括n-漂移区（1）、一个以上的沟槽栅（2）、p基区（3）、n+发射极区（4）、浅p基区（5）、层间氧化层（6）、金属层（7）和p+集电极区（8），其中n-漂移区（1）的上方有至少两个沟槽栅（2），p基区（3）位于沟槽栅（2）的内侧，沟槽栅（2）之间为浅p基区（5），层间氧化层（6）在沟槽栅（2）和浅p基区（5）上，n+发射极区（4）分别位于沟槽栅（2）的两侧，金属层（7）在层间氧化层（6）上，p+集电极区（8）在n-漂移区（1）的背面。该IGBT通过拉宽沟槽型IGBT中发射极之间的距离，降低了翘曲发生的概率；电流密度比较低，能够降低整个器件的短路电流，拓宽器件的安全工作区。

Description

一种 IGBT结构及其制备方法
技术领域
本发明属于半导体大功率器件的技术领域， 特别涉及一种 IGBT结构及其制备方法。 背景技术
IGBT的全称是 Insu la te Ga te Bi po l ar Trans i s tor , 即绝缘 栅双极晶体管。 它兼具 M0SFET和 GTR的多项优点， 极大的扩展了 功率半导体器件的应用领域。 作为新型电力半导体器件的主要代 表， IGBT被广泛用于工业、 信息、 新能源、 医学、 交通、 军事和 航空领域。
高压 IGBT目前还是设计上的一个难点。 为了减小器件本身的 功率损耗，希望器件的导通压降越小越好； 为了达到更高的反向阻 断电压， 需要增加 N-漂移区的厚度及电阻率， 而这样势必加大器 件的导通压降。 为了调和反向阻断电压和导通压降二者的矛盾， 要求 IGBT 各个结构参数做尽可能的最优化设计。
沟槽栅型 IGBT是 IGBT的一个发展方向， 它采用沟槽栅代替 平面栅， 改善了器件的导通特性， 降低了导通电阻， 现有技术中 IGBT的结构如图 1所示， 1为 n-漂移区， 2为沟槽栅（器件的栅 极 G ) , 其中， 两个沟槽栅之间的距离在 10画之内， 5 为层间氧 化层， 6为发射极金属， 7为 p+集电极区 （器件的集电极 C ) , 在 沟槽栅结构中， n+发射极区 4和 p型基区 3 内形成了垂直于硅片 表面的沟道。 工作时电流从 p+集电极区出发经过 N-漂移区 1直接 流进垂直沟道而进入 n+发射极区 4。
为了达到更高的电压， 需要增加 N-漂移区的厚度及电阻率， 而这样势必加大器件的导通电阻。 而且现有的沟槽 IGBT的饱和电 流密度过大， 也使得短路安全工作区 （SCS0A ) 减小。 因为有源区 域中沟槽所占比例较高， 在圓片制备过程中， 发生翘曲的风险很 大。 翘曲一旦发生， 可能会导致后续光刻版无法对准， 严重的会 导致碎片。 发明内容
本发明所要解决的技术问题是提供一种 I GBT结构及其制备方 法， 解决了现有技术中 IGBT结构容易翘曲的技术问题。
为解决上述技术问题， 本发明提供了一种 IGBT结构， 包括 n_ 漂移区、 一个以上的沟槽栅、 p基区、 n+发射极区、 浅 p基区、 层 间氧化层、 金属层和 p+集电极区； 其中， 所述 n-漂移区的上方有 至少两个的沟槽栅， 所述 p基区分别位于所述沟槽栅的内侧， 所 述沟槽栅之间为所述浅 P基区， 所述层间氧化层在所述沟槽栅和 所述浅 p基区上， 所述 n+发射极区分别位于所述沟槽栅的两侧， 所述金属层在所述层间氧化层上， 所述 p+集电极区在所述 n-漂移 区的背面。
进一步地， 所述沟槽栅之间的距离在 2 Oum以上。
进一步地， 所述浅 p基区的深度大于所述沟槽栅的深度。 一种 IGBT结构的制备方法， 包括如下步骤：
将 N-型村底制备成 n-漂移区；在所述 n-漂移区的上方刻蚀出 一个以上的沟槽栅， 在所述沟槽栅之间依次经过离子注入和高温 退火形成浅 p基区； 然后在所述沟槽栅的两侧通过离子注入和高 温退火形成 p基区和 n+发射极区， 在所述沟槽栅和浅 p基区上通 过低压化学沉积方法形成层间氧化层， 在所述层间氧化层上淀积 金属层，在 N-型村底的背面，通过高能离子注入形成 p+集电极区。 进一步地， 所述形成浅 p基区的离子为 B离子。
进一步地， 所述 B离子的剂量为 l el 4a tom/cm2。
本发明提供的一种 IGBT结构， 拉宽沟槽型 IGBT中发射极之 间的距离， 增强了电导调制效应， 降低了器件的导通压降， 降低 了整个芯片中， 沟槽所占比例， 从而大大降低了翘曲发生的概率。 另外， 电流密度比较低， 能够降低整个器件的短路电流， 拓宽器 件安全工作区。 附图说明
图 1为现有技术提供的 IGBT结构示意图；
图 2为本发明实施例提供的一种 IGBT结构示意图；
附图标记：
1、 n -漂移区， 2、 沟槽栅， 3、 p基区， 4、 n+发射极区， 5、 浅！基区， 6、 层间氧化层， 7、 金属层， 8、 p+集电极区。 具体实施方式
参见图 1 , 本发明实施例提供的一种 IGBT结构， 包括 n-漂移 区 1、 一个以上的沟槽栅 2、 p基区 3、 n+发射极区 4、 浅 p基区 5、 层间氧化层 6、 金属层 7和 p+集电极区 8 ; 其中， n-漂移区 1的上 方刻蚀至少两个沟槽，形成沟槽栅 2 , p基区 3分别位于沟槽栅 2 的两侧， 沟槽栅 2之间为浅 p基区 5 , 层间氧化层 6在沟槽栅 2和 浅 P基区 5上， n+发射极区 4分别位于沟槽栅 2的两侧， 金属层 7 在层间氧化层 6上， p+集电极区 8在 n-漂移区 1的背面。 另外， 该 IGBT结构同时适用于 NPT及 FS型 IGBT器件。 其中， 沟槽栅 2之间的距离在 20画以上。 本发明实施例增大 了沟槽型 IGBT的两个发射极的距离。 当 IGBT的集射极加以正向 电压（VCE>0) , 栅射极电压 （VGE)超过栅极的阈值电压 （VT) 时， 在 p基区与沟槽栅的交界面开始形成导电沟道， 电子由 n+发射区 经沟道流向 n-漂移区， 导致 n-漂移区电位下降， 于是 IGBT的 p+ 集电极区不断向 n-漂移区注入空穴。 注入的空穴一部分与沟道过 来 的电子在这里复合， 形成电子电流， 一部分会在 n-漂移区中扩 散， 经过 p基区最终到达发射极， 形成空穴电流。
本发明实施例提供的 IGBT结构的制备方法如下：
步骤 101: 选择 N-型村底， 将所述 N-型村底制备成 n-漂移区
1;
步骤 102: 使用第二块光刻掩膜版， 在 n-漂移区的上方刻蚀 出一个以上的沟槽栅；
步骤 103:使用第一块光刻掩膜版，在沟槽栅之间注入 B离子， 其中， 注入的剂量为 lel4atom/cm2，注入的能量 80kev, 约
150min_200min后， 经 1000°C_1200°C的退火， 形成浅 p基区 5; 步骤 104:在在所述沟槽栅的两侧注入 B离子， 其中， 注入的 剂量约为 lel3atom/cm2，注入的能量为 80kev,通过 lOOmin后退火， 退火温度为 1000°C, 形成 p基区 3;
步骤 105: 使用第四块光刻掩膜版， 在沟槽栅的两侧注入 AS 离子及 P离子， 形成 n+发射极区 4, 注入能量和剂量分别为 80kev 和 2el5atom/ cm2;
步骤 106: 在 N-型村底表面， 采用低压化学淀积工艺， 在 580 °C-650°C下热分解硅烷， 形成厚度约为 lum的多晶硅层； 使用第 三块光刻掩膜版， 刻蚀除沟槽以外的多晶硅层， 形成栅极； 步骤 107 : 使用低压化学沉积工艺， 在 650 °C -750 °C下分解正 硅酸乙酯， 在 N-型村底表面形成层间氧化层 6 ;
步骤 108 : 在层间氧化层上淀积金属层 7 , 该金属层的金属为
A 1 ;
步骤 109 : 在 N-型村底的背面， 通过高能离子注入形成 p+集 电极区 8 ; p+集电极区的离子为 B元素，离子的能量 50kev，离子 的剂量 l el 5a tom/cm2。
本发明实施例提出的 IGBT结构中， 两个沟槽中间间隔较大， 且没有连接发射极。 因此注入的空穴在 n-漂移区扩散过程中， 会 在浅 P基区积累起来， 因为浅 p基区与 n-漂移区电位相连， 因此 积累的空穴导致 n-漂移区的电位升高。 为了保持 n-漂移区的电中 性， n+发射区向 n-漂移区注入大量的电子， 即产生电导调制效应， 此时 IGBT体内充满了大量的非平衡载流子。 上述过程不断重复， 最终达到动态平衡， n-基区充满了非平衡载流子， 具有很低的通 态压降。
当 IGBT的 VGE低于阈值电压 VT, 并降为零或负值时， 导电沟 道立即消失， 从发射极注入的电子电流很快减小到零， 此时， n_ 漂移区中的非平衡载流子除不断复合外， 一部分电子进入集电极 区， 一部分空穴通过扩散进入 P基区， 直到所有的非平衡截流子 复合消失， 器件彻底关断。
本发明实施例通过改变栅极结构， 在集电极侧空穴注入不增 加的情况下， 大大增加发射极侧的电子注入量， 从而器件内部靠 阴极侧的载流子浓度明显提高， 其分布类似于通态时的 p in二极 管。 由于注入增强效应引起的是阴极侧的电子注入增强， 而集电 极侧的空穴注入并没有增强， 所以， 与传统 IGBT相比， 本发明的 关断时间不会明显增大。
随着现代硅片加工工艺的进步， 硅晶片尺寸越来越大， 厚度 越来越薄。 在这样的硅晶片上进行复杂的刻蚀、 淀积等操作， 以 及多步升降温及高温处理， 其中产生的机械应力及热应力容易使 平整的硅片发生翘曲。 翘曲一旦发生， 轻则使掩膜版对准困难， 光刻图形出现偏差， 影响最终器件的性能。 重则整枚硅片破碎废 片。 对沟槽型 IGBT来说， 沟槽密度越大， 则发生翘曲的风险也越 高。 本发明提出的结构， 加大了沟槽间距， 因而降低了沟槽密度， 能够有效防止翘曲。
如果只是一味的加大沟槽间的距离， 则器件的反向阻断电压 会随着沟槽间距的增大而降低。 在两个沟槽中间注入 p型离子， 形成掺杂较浅， 深度较深（深于沟槽的深度）的 P型掺杂区， 浅！ 基区的深度大于沟槽栅的深度， 可以平衡电场， 保证反向阻断电 压不会随沟槽间距的增加而降低。 从而保持反向阻断电压不降低。
本发明的优点：
1、 本发明在传统 IGBT的基础上， 拉宽沟槽型 IGBT中发射极 之间的距离， 增强了电导调制效应， 降低了器件的导通压降；
2、 在相邻的两个沟槽之间， 注入 B离子， 形成浅 P基区， 此 区域深度大于沟槽底部， 可以平衡电场， 保证反向阻断电压不会 随沟槽间距的增加而降低；
3、 本发明降低了整个芯片中， 沟槽所占比例， 从而大大降低 了翘曲发生的概率；
4、 本发明电流密度比较低， 能够降低整个器件的短路电流， 拓宽器件安全工作区。 术^案口而非 :限制， 尽管参照实例 ^本发^进行了详细说明'， 本领 域的普通技术人员应当理解， 可以对本发明的技术方案进行修改 或者等同替换， 而不脱离本发明技术方案的精神和范围， 其均应 涵盖在本发明的权利要求范围当中。

Claims

权 利 要 求 书
1、 一种 IGBT结构， 其特征在于， 包括 n-漂移区、 一个以上 的沟槽栅、 P基区、 n+发射极区、 浅 p基区、 层间氧化层、 金属层 和 P+集电极区；其中，所述 n-漂移区的上方有至少两个的沟槽栅， 所述 P基区分别位于所述沟槽栅的内侧， 所述沟槽栅之间为所述 浅！基区， 所述层间氧化层在所述沟槽栅和所述浅 P基区上， 所 述 n+发射极区分别位于所述沟槽栅的两侧， 所述金属层在所述层 间氧化层上， 所述 p+集电极区在所述 n-漂移区的背面。
2、 根据权利要求 1所述的 IGBT结构， 其特征在于， 所述沟 槽栅之间的距离在 20画以上。
3、 根据权利要求 1所述的 IGBT结构， 其特征在于， 所述浅 p 基区的深度大于所述沟槽栅的深度。
4、 一种 IGBT结构的制备方法， 其特征在于， 包括如下步骤： 将 N-型村底制备成 n-漂移区；在所述 n-漂移区的上方刻蚀出 一个以上的沟槽栅， 在所述沟槽栅之间依次经过离子注入和高温 退火形成浅 p基区； 然后在所述沟槽栅的两侧通过离子注入和高 温退火形成 p基区和 n+发射极区， 在所述沟槽栅和浅 p基区上通 过低压化学沉积方法形成层间氧化层， 在所述层间氧化层上淀积 金属层，在 N-型村底的背面，通过高能离子注入形成 p+集电极区。
5、 根据权利要求 4所述的方法， 其特征在于， 所述形成浅 p 基区的离子为 B离子。
6、 根据权利要求 5所述的方法， 其特征在于， 所述 B离子的剂 量为 l el 4a tom/ cm2。
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