WO2014075314A1 - Cmos输入缓冲器 - Google Patents

Cmos输入缓冲器 Download PDF

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Publication number
WO2014075314A1
WO2014075314A1 PCT/CN2012/084832 CN2012084832W WO2014075314A1 WO 2014075314 A1 WO2014075314 A1 WO 2014075314A1 CN 2012084832 W CN2012084832 W CN 2012084832W WO 2014075314 A1 WO2014075314 A1 WO 2014075314A1
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WIPO (PCT)
Prior art keywords
nmos transistor
circuit
cmos input
source
linearity
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PCT/CN2012/084832
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English (en)
French (fr)
Inventor
陈玺
胡刚毅
徐学良
黄兴发
李梁
沈晓峰
徐鸣远
张磊
王妍
叶荣科
王友华
黄旭
李皎雪
Original Assignee
中国电子科技集团公司第二十四研究所
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Application filed by 中国电子科技集团公司第二十四研究所 filed Critical 中国电子科技集团公司第二十四研究所
Priority to US14/355,580 priority Critical patent/US9337834B2/en
Publication of WO2014075314A1 publication Critical patent/WO2014075314A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic

Definitions

  • the present invention relates to a CMOS input buffer circuit, and more particularly to a CMOS input buffer circuit based on linearity compensation techniques.
  • Applications are in the field of CMOS analog ICs and digital-analog hybrid ICs that require high linear input buffers.
  • CMOS input buffer circuits are very important for CMOS analog ICs and digital-to-analog hybrid IC designs.
  • the linearity of the input buffer directly limits the accuracy specifications at the system level.
  • the technical problem to be solved by the present invention is to provide a linearity improvement technique suitable for a CMOS input buffer circuit to overcome the problem that the parameters of the CMOS device are low and the nonlinearity changes significantly.
  • the CMOS input buffer provided by the invention comprises a CMOS input follower circuit, a follower tube linearity improving circuit, a current source load and a load impedance linearity improving circuit;
  • the CMOS input follower circuit for following an input signal change, the output following the input signal output signal;
  • the follower tube linearity improving circuit is configured to acquire a change trend of the input signal, and apply an input signal feedback to the CMOS input follower circuit;
  • the current source load is used to provide a bias current for the CMOS input follower circuit to operate normally; the load impedance linearity improving circuit is connected between the CMOS input follower circuit and the current source load for enhancing the current source load impedance The absolute value of the absolute value is reduced, and the linearity of the load impedance of the CMOS input buffer is increased.
  • the CMOS input follower circuit includes an NMOS transistor No. M0, a gate of the NMOS transistor of No. M0 is used as an input terminal of a CMOS input follower circuit, and a source of the NMOS transistor of the No. M0 is used as a CMOS input follower circuit.
  • the output end, the follower tube linearity improving circuit is connected between the gate of the M0th NMOS transistor and the drain of the M0th NMOS transistor, and the load impedance linearity improving circuit is provided at one end of the circuit and the source of the M0th NMOS transistor
  • the pole connection, the other end of the load impedance linearity improving circuit is connected to the current source load.
  • the follower tube linearity improving circuit comprises a capacitor and an M1 NMOS transistor, one end of the capacitor is connected to the gate of the M0th NMOS transistor, and the other end of the capacitor C1 is connected to the gate of the M1th NMOS transistor.
  • the drain of the NMOS transistor of the M1th is connected to the power supply voltage, and the source of the NMOS transistor of the M1th is connected to the drain of the NMOS transistor of the M0th.
  • the follower tube linearity improving circuit includes a M4th PMOS transistor and an M1th NMOS transistor, the gate of the M4th PMOS transistor is connected to the drain of the M0th NMOS transistor, and the source of the M4th PMOS transistor The pole is connected to the source of the M0th NMOS transistor, the gate of the M1th NMOS transistor is connected to the bias voltage, and the drain of the Mth PMOS transistor is connected to the power supply voltage.
  • the current source load includes a M3th NMOS transistor, a gate of the M3th NMOS transistor is connected to a bias voltage, a source of the M3th NMOS transistor is connected to a power supply ground, and the M3th NMOS transistor is The drain and load impedance linearity increase the circuit connection.
  • the load impedance linearity improving circuit includes an M2nd NMOS transistor and an operational amplifier, and a drain of the M2th NMOS transistor is connected to a source of the M0th NMOS transistor, and a source of the M2th NMOS transistor is connected.
  • the drain of the M3 NMOS transistor is connected to the drain of the M3 NMOS transistor, and the output of the op amp is connected to the gate of the M2 NMOS transistor.
  • the load impedance linearity improving circuit includes an M2nd NMOS transistor and an M4th NMOS transistor, and a source of the M2th NMOS transistor is connected to a drain of the M4th NMOS transistor, and an M4th NMOS transistor The source is connected to the drain of the M3 NMOS transistor, the gate of the M2th NMOS transistor is connected to the bias voltage, and the gate of the M4th NMOS transistor is connected to the bias voltage.
  • NMOS transistors are all replaced by PMOS transistors.
  • the PM0S tube is replaced by an NMOS tube.
  • the advantages of the present invention are:
  • the high linearity CMOS input buffer circuit of the present invention has the following features compared to conventional input buffer circuits:
  • the components used in the present invention can be provided by a standard CMOS process, and have a wide range of applications, simple implementation, and low cost compared to a bipolar or BiCMOS process.
  • the linearity of the CMOS input buffer circuit of the present invention is significantly improved, and the linearity decreases slowly with the increase of the input signal frequency, and the high frequency characteristic is better than some linear improvement techniques adopted by the conventional structure.
  • the linearity improving circuit of the invention has a simple structure and fewer components, and the linearity improvement technology of the conventional structure not only has a small modification of the circuit layout, but also saves at least 50%-70% of power consumption.
  • Figure 1 is a conventional structure of a CMOS input buffer circuit
  • FIG. 2 is a circuit diagram of Embodiment 1 of a high linearity CMOS input buffer circuit of the present invention
  • FIG. 3 is a circuit diagram of Embodiment 2 of a high linearity CMOS input buffer circuit of the present invention
  • FIG. 4 is a high linearity CMOS input buffer of the present invention.
  • Circuit diagram of Embodiment 3 of the circuit
  • Figure 5 is a circuit diagram of Embodiment 4 of the high linearity CMOS input buffer circuit of the present invention.
  • CMOS input follower circuit -1 the follower tube linearity improvement circuit -2, the current source load -3, and the load impedance linearity improvement circuit -4.
  • the CMOS input buffer provided by the present invention includes a CMOS input follower circuit 1. Following the tube linearity improving circuit 2, the current source load 3 and the load impedance linearity improving circuit 4; the CMOS input following circuit 1 for following the input signal change, outputting an output signal following the input signal; the CMOS input
  • the follower circuit includes an NMOS transistor No. M0, the gate of the NMOS transistor No. 0 is used as an input terminal of the CMOS input follower circuit, and the source of the NMOS transistor No.
  • the tube linearity improving circuit 2 is connected between the gate of the M0th NMOS transistor and the drain of the M0th NMOS transistor, and the end of the load impedance linearity improving circuit 4 is connected to the source of the M0th NMOS transistor.
  • the other end of the load impedance linearity improving circuit 4 is connected to the current source load 3.
  • the M0 NMOS tube (following tube) linearity improving circuit is configured to acquire a change trend of the input signal, and feedback the input signal to the CMOS input follower circuit; cancel the follower tube self-transconductance value brought by the change of the input signal And the nonlinear variation of the output impedance improves the linearity of the CMOS input buffer.
  • the follower tube linearity improving circuit comprises a capacitor and an M1 NMOS transistor, one end of the capacitor is connected to the gate of the M0th NMOS transistor, and the other end of the capacitor C1 is connected to the gate of the M1th NMOS transistor.
  • the drain of the NMOS transistor of the M1th is connected to the power supply voltage, and the source of the NMOS transistor of the M1th is connected to the drain of the NMOS transistor of the M0th.
  • the follower tube linearity improving circuit in this embodiment may further adopt the following manner, the following tube linearity improving circuit includes a M4th PMOS transistor and an M1th NMOS transistor, and a gate connection of the M4th PMOS transistor
  • the drain of the M0 NMOS transistor, the source of the M4 PMOS transistor is connected to the source of the M0th NMOS transistor, the gate of the M1th NMOS transistor is connected to the bias voltage, and the drain of the M4th PMOS transistor is connected. voltage.
  • the current source load is used to provide a bias current for the CMOS input follower circuit to operate normally;
  • the current source load includes a M3th NMOS transistor, a gate connection bias of the M3th NMOS transistor,
  • the source of the M3 NMOS transistor is connected to the power supply ground, and the drain of the M3th NMOS transistor is connected to the load impedance linearity improving circuit.
  • the load impedance linearity improving circuit is connected between the CMOS input follower circuit and the current source load for enhancing the absolute value of the current source load impedance, reducing the relative variation amplitude, and improving the linearity of the CMOS input buffer load impedance.
  • the load impedance linearity improving circuit includes an M2th NMOS transistor and an operational amplifier, a drain of the M2th NMOS transistor is connected to a source of the M0th NMOS transistor, and a source of the M2th NMOS transistor is connected to the M3th.
  • the load impedance linearity improving circuit may further adopt a method in which the load impedance linearity improving circuit includes an M2nd NMOS transistor and an M4th NMOS transistor, a source of the M2th NMOS transistor, and a M4th NMOS transistor.
  • the drain of the NMOS transistor is connected, the gate of the M2th NMOS transistor is connected to the bias voltage, and the M4th
  • the gate of the NMOS transistor is connected to a bias voltage.
  • the NMOS transistors in this embodiment are all replaced by PMOS transistors.
  • the M4 PMOS transistors are correspondingly changed to NMOS transistors, and the changed circuit connections are connected according to the corresponding circuit connections.
  • the M0 NMOS transistor, the M1 NMOS transistor, the M2 NMOS transistor, the M3 NMOS transistor, and the M4 NMOS transistor in the following embodiments may also be respectively indicated by the following symbols: NMOS transistor M0, NMOS transistor Ml, NMOS transistor M2, NMOS transistor M3, NMOS transistor M4;
  • the operational amplifier is represented by an operational amplifier A1
  • the capacitance is represented by a capacitance C1.
  • FIG. 2 A general structure of a specific implementation of the present invention is shown in FIG. 2, and its composition includes an operational amplifier A1, four MOS transistors ( ⁇ 3, a capacitor C1.
  • A1 An operational amplifier
  • MOS transistors ⁇ 3, a capacitor C1.
  • g m is the MOS tube (following tube) transconductance of the MO number, and is the output resistance of the M0 NMOS tube (following tube) and the tail current, respectively.
  • the gain of the input buffer circuit is connected to the transconductance g m of the input follower, the output resistance, and the output resistance r of the tail current. 2 related.
  • the output follows the input signal change, the voltage at the output continues to change, causing the drain-source voltage change of the input follower tube and the tail current tube.
  • the transconductance g m or the output resistance varies with the MOS tube drain-source voltage VDS. Significantly, usually reaching ten percent Nonlinear.
  • the linearity improving circuit of the NMOS transistor M0 (input follower tube MO) is composed of the following capacitor C1 and the follower tube M1, and mainly solves the nonlinear problem caused by the variation of the drain-source voltage VDS of the NMOS transistor M0.
  • the output signal of the source of the NMOS transistor M0 changes with the input signal of the M0 gate. Since one end of the following capacitor C1 is connected to the input signal terminal, when the input signal changes, the other end of the capacitor C1 changes following the input, further causing the source of the follower tube M1 to follow its gate voltage change.
  • the drain of the follower NMOS transistor M0 is in the same direction as the source and the input signal. Moreover, because of the good high-frequency characteristics of the capacitor itself, even if the speed of the input signal is fast, the gate voltage of the follower tube M1 is almost synchronized with the change of the input signal, ensuring that the drain and source voltages of the follower transistor NMOS transistor M0 are both Only follow the change of one MOS tube itself. The dependence of the input signal frequency on the linearity is limited only by the matching degree of the MOS tube itself in the modern process, that is, the VDS voltage of the NMOS tube M0 following the tube can be kept substantially constant.
  • the load impedance linearity improving circuit is composed of the NMOS transistor M2 and the operational amplifier A1, and mainly solves the nonlinear variation problem in the tail current load NMOS tube M3 impedance as a function of the output variation.
  • the output impedance of the tail current increases.
  • the meaning of the high output impedance now "shields" the input device so that it is not affected by changes in the output node c voltage.
  • the CMOS input buffer circuit of the present invention has high linearity and high frequency characteristics.
  • Embodiment 3 is a circuit diagram of Embodiment 2 of the high linearity CMOS input buffer circuit of the present invention.
  • MOS tube in Embodiment 1 that is, NMOS tube M0, NMOS tube Ml, NMOS tube M2, NMOS tube M3 are PMOS, the load tube is a PMOS tube, the impedance is slightly decreased, but the substrate of the PMOS tube can be connected to the potential separately, so the linearity of the input follower tube is higher.
  • Embodiment 4 is a circuit diagram of Embodiment 3 of the high linearity CMOS input buffer circuit of the present invention, as shown in FIG.
  • the difference between this embodiment and the first embodiment is that: the operational amplifier Al is removed, the NMOS transistor M4 is added, the drain of the NMOS transistor M4 is connected to the source of the NMOS transistor M2, and the source of the NMOS transistor M4 is connected to the NMOS transistor M3.
  • the drain, the gates of the NMOS transistor M2 and the NMOS transistor M4 are connected to a bias voltage. Since the op amp A 1 unit is reduced, the circuit power consumption is further reduced, but the increased MOS transistor M4 reduces the output swing.
  • Embodiment 4 is a circuit diagram of Embodiment 4 of the high linearity CMOS input buffer circuit of the present invention.
  • the difference between this embodiment and Embodiment 1 is that the capacitor C1 is removed, and the PMOS transistor M4 and the PMOS transistor M4 are added.
  • the gate is connected to the drain of the NMOS transistor M0, the source of the PMOS transistor M4 is connected to the source of the NMOS transistor M0, and the gate of the NMOS transistor M1 is connected to the bias voltage.
  • the capacitor unit is reduced, that is, the input drive capability is reduced, but the PMOS tube M4 is used to follow the change of the input signal, and the input follower tube NMOS tube M0 is compensated.
  • the tube that is, the NMOS transistor M0 and the PMOS transistor M4, and the normal output signal passes through only one MOS transistor, that is, the NMOS transistor M0, and a time matching problem occurs, generating harmonics.

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Abstract

提供一种CMOS输入缓冲器。该CMOS输入缓冲器包括CMOS输入跟随电路、跟随管线性度提高电路、电流源负载和负载阻抗线性度提高电路，其中：该CMOS输入跟随电路，用于跟随输入信号变化，输出跟随输入信号的输出信号；该跟随管线性度提高电路，用于获取输入信号的变化趋势，并将输入信号反馈作用于CMOS输入跟随电路；该电流源负载，用于提供该CMOS输入跟随电路正常工作的偏置电流；该负载阻抗线性度提高电路连接于CMOS输入跟随电路和电流源负载之间，用于增强电流源负载阻抗的绝对值，减小绝对值相对变化幅度，提高CMOS输入缓冲器负载阻抗的线性度。该CMOS输入缓冲器线性度高，并且实现简单成本低。

Description

CMOS输入缓冲器 技术领域
本发明涉及一种 CMOS输入缓冲器电路， 特别涉及一种基于线性度补偿技 术的 CMOS输入缓冲器电路。 应用领域是需要高线性输入缓冲器的 CMOS模拟 IC和数模混合 IC领域。
背景技术
高线性 CMOS输入缓冲器电路对于 CMOS模拟 IC和数模混合 IC设计具有 非常重要的意义。作为输入信号与信号处理电路的接口单元，输入缓冲器的线性 度将直接限制系统级的精度指标。
传统的输入缓冲器电路多采用 BJT器件， 以射极跟随结构搭建。 而随着现 代 CMOS工艺的发展和大规模应用， 使用 CMOS器件， 以源极跟随结构搭建的 CMOS输入缓冲器电路开始取代传统 BJT结构， 如图 1所示。 虽然 CMOS工艺 比双极性工艺有许多的优势， 但是 CMOS器件相对于 BJT器件来说， 输入跨导 和输出阻抗更低，最主要是寄生更严重，器件参数非线性变化显著。因此， CMOS 输入缓冲器的线性度相比传统结构要低。 原有的一些 BJT输入缓冲器电路线性 提高技术不适合 CMOS工艺， 在 CMOS输入缓冲器电路中为了提高其线性度， 通常采用的解决方式是增大尾电流管的电流值来提高输入跨导，但这种做法不仅 加大了电路的版图面积， 且极大增加了系统功耗。
基于以上所述， 需要一种能够适用于 CMOS输入缓冲器电路的线性度提高 技术， 来满足当前 CMOS模拟 IC和数模混合 IC的设计需要。
发明内容
有鉴于此， 本发明所要解决的技术问题是提供一种适用于 CMOS输入缓冲 器电路的线性度提高技术，来克服 CMOS器件参数低且非线性变化显著的问题。
本发明的目的是这样实现的：
本发明提供的 CMOS输入缓冲器， 包括 CMOS输入跟随电路、 跟随管线性 度提高电路、 电流源负载和负载阻抗线性度提高电路；
所述 CMOS输入跟随电路， 用于跟随输入信号变化， 输出跟随输入信号的 输出信号；
所述跟随管线性度提高电路，用于获取输入信号的变化趋势， 并将输入信号 反馈作用于 CMOS输入跟随电路；
所述电流源负载，用于提供所述 CMOS输入跟随电路正常工作的偏置电流; 所述负载阻抗线性度提高电路连接于 CMOS输入跟随电路和电流源负载之 间， 用于增强电流源负载阻抗的绝对值， 减小绝对值相对变化幅度， 提高 CMOS 输入缓冲器负载阻抗的线性度。
进一步， 所述 CMOS输入跟随电路包括第 M0号 NMOS管， 所述第 M0号 NMOS管的栅极作为 CMOS输入跟随电路的输入端， 所述第 M0号 NMOS管的 源极作为 CMOS输入跟随电路的输出端， 所述跟随管线性度提高电路连接于第 M0号 NMOS管的栅极和第 M0号 NMOS管的漏极之间， 所述负载阻抗线性度 提高电路一端与第 M0号 NMOS管的源极连接， 所述负载阻抗线性度提高电路 另一端与电流源负载连接。
进一步， 所述跟随管线性度提高电路包括电容和第 Ml号 NMOS管， 所述 电容的一端连接第 M0号 NMOS管的栅极，所述电容 C1的另一端连接第 Ml号 NMOS管的栅极，所述第 Ml号 NMOS管的漏极连接电源电压，第 Ml号 NMOS 管的源极连接第 M0号 NMOS管的漏极。
进一步， 所述跟随管线性度提高电路包括第 M4 号 PMOS 管和第 Ml 号 NMOS管， 所述第 M4号 PMOS管的栅极连接第 M0号 NMOS管的漏极， 第 M4号 PMOS管的源极连接第 M0号 NMOS管的源极， 第 Ml号 NMOS管的栅 极连接偏置电压， 所述第 M4号 PMOS管的漏极连接电源电压。
进一步， 所述电流源负载包括第 M3号 NMOS管， 所述第 M3号 NMOS管 的栅极连接偏压，所述第 M3号 NMOS管的源极连接电源地，所述第 M3号 NMOS 管的漏极与负载阻抗线性度提高电路连接。
进一步， 所述负载阻抗线性度提高电路包括第 M2号 NMOS管和运放， 所 述第 M2号 NMOS管的漏极连接第 M0号 NMOS管的源极，第 M2号 NMOS管 的源极连接第 M3号 NMOS管的漏极， 所述运放的输入端连接第 M3号 NMOS 管的漏极， 所述运放的输出端连接第 M2号 NMOS管的栅极。 进一步， 所述负载阻抗线性度提高电路包括第 M2号 NMOS管和第 M4号 NMOS管， 所述第 M2号 NMOS管的源极与第 M4号 NMOS管的漏极连接， 第 M4号 NMOS管的源极与第 M3号 NMOS管的漏极连接， 所述第 M2号 NMOS 管的栅极连接偏压， 所述第 M4号 NMOS管的栅极连接偏压。
进一步， 所述 NMOS管均由 PMOS管代替。
进一步， 所述 PM0S管由 NMOS管代替。
本发明的优点在于： 本发明的高线性 CMOS输入缓冲器电路， 与传统的输 入缓冲器电路相比， 它具有以下特点：
1 . 本发明采用的元器件均可以由标准 CMOS 工艺提供， 相对于双极或 BiCMOS工艺， 应用范围广， 实现简单且成本低。
2. 本发明的 CMOS输入缓冲器电路线性度提高显著， 且与传统结构采取的 一些线性提高技术相比，线性度随输入信号频率的增加下降缓慢，高频特性更好。
3. 本发明的线性提高电路结构简单， 增加的元器件少， 相比于传统结构的 线性度提高技术， 不仅电路版图改动小， 功耗至少节约 50%-70%。
附图说明
为了使本发明的目的、技术方案和优点更加清楚， 下面将结合附图对本发明 作进一步的详细描述， 其中：
图 1是传统结构的 CMOS输入缓冲器电路；
图 2是本发明的高线性 CMOS输入缓冲器电路的实施例 1电路图； 图 3是本发明的高线性 CMOS输入缓冲器电路的实施例 2电路图； 图 4是本发明的高线性 CMOS输入缓冲器电路的实施例 3电路图； 图 5是本发明的高线性 CMOS输入缓冲器电路的实施例 4电路图。
图中， CMOS输入跟随电路 -1、 跟随管线性度提高电路 -2、 电流源负载 -3、 负载阻抗线性度提高电路 -4。
具体实施方式
以下将结合附图， 对本发明的优选实施例进行详细的描述； 应当理解， 优选 实施例仅为了说明本发明， 而不是为了限制本发明的保护范围。
实施例 1
如图 2所示： 本发明提供的 CMOS输入缓冲器， 包括 CMOS输入跟随电路 1、 跟随管线性度提高电路 2、 电流源负载 3和负载阻抗线性度提高电路 4; 所述 CMOS输入跟随电路 1，用于跟随输入信号变化，输出跟随输入信号的 输出信号；所述 CMOS输入跟随电路包括第 M0号 NMOS管，所述第 M0号 NMOS 管的栅极作为 CMOS输入跟随电路的输入端， 所述第 M0号 NMOS管的源极作 为 CMOS输入跟随电路的输出端， 所述跟随管线性度提高电路 2连接于第 M0 号 NMOS管的栅极和第 M0号 NMOS管的漏极之间， 所述负载阻抗线性度提高 电路 4一端与第 M0号 NMOS管的源极连接， 所述负载阻抗线性度提高电路 4 另一端与电流源负载 3连接。
所述第 M0号 NMOS管 （跟随管） 线性度提高电路， 用于获取输入信号的 变化趋势， 并将输入信号反馈作用于 CMOS输入跟随电路； 抵消输入信号变化 带来的跟随管自身跨导值和输出阻抗的非线性变化， 提高 CMOS输入缓冲器的 线性度。 所述跟随管线性度提高电路包括电容和第 Ml号 NMOS管， 所述电容 的一端连接第 M0号 NMOS管的栅极，所述电容 C1的另一端连接第 Ml号 NMOS 管的栅极， 所述第 Ml号 NMOS管的漏极连接电源电压， 第 Ml号 NMOS管的 源极连接第 M0号 NMOS管的漏极。
本实施例中的跟随管线性度提高电路还可以采用以下方式，所述跟随管线性 度提高电路包括第 M4号 PMOS管和第 Ml号 NMOS管， 所述第 M4号 PMOS 管的栅极连接第 M0号 NMOS管的漏极， 第 M4号 PMOS管的源极连接第 M0 号 NMOS管的源极，第 Ml号 NMOS管的栅极连接偏置电压，所述第 M4号 PMOS 管的漏极连接电源电压。
所述电流源负载，用于提供所述 CMOS输入跟随电路正常工作的偏置电流; 所述电流源负载包括第 M3号 NMOS管， 所述第 M3号 NMOS管的栅极连接偏 压， 所述第 M3号 NMOS管的源极连接电源地， 所述第 M3号 NMOS管的漏极 与负载阻抗线性度提高电路连接。
所述负载阻抗线性度提高电路连接于 CMOS输入跟随电路和电流源负载之 间， 用于增强电流源负载阻抗的绝对值， 减小其相对变化幅度， 提高 CMOS输 入缓冲器负载阻抗的线性度。所述负载阻抗线性度提高电路包括第 M2号 NMOS 管和运放， 所述第 M2号 NMOS管的漏极连接第 M0号 NMOS管的源极， 第 M2号 NMOS管的源极连接第 M3号 NMOS管的漏极， 所述运放的输入端连接 第 M3号 NMOS管的漏极， 所述运放的输出端连接第 M2号 NMOS管的栅极。 所述负载阻抗线性度提高电路还可以采用以下方式，所述负载阻抗线性度提 高电路包括第 M2号 NMOS管和第 M4号 NMOS管，所述第 M2号 NMOS管的 源极与第 M4号 NMOS管的漏极连接， 第 M4号 NMOS管的源极与第 M3号
NMOS管的漏极连接， 所述第 M2号 NMOS管的栅极连接偏压， 所述第 M4号
NMOS管的栅极连接偏压。
本实施例中的 NMOS管均由 PMOS管代替也可以实现， 第 M4号 PMOS管 相应的变为 NMOS管， 变化后的电路连接方式按照相应的电路连接方式进行连 接。
下面详细描述本发明提供的高线性 CMOS输入缓冲器电路的原理和具体实 施方式：
以下实施例中的第 M0号 NMOS管、 第 Ml号 NMOS管、 第 M2号 NMOS 管、第 M3号 NMOS管、第 M4号 NMOS管、也可以分别采用如下标记来说明： NMOS管 M0、 NMOS管 Ml、 NMOS管 M2、 NMOS管 M3、 NMOS管 M4; 运 放采用运算放大器 A1来表示， 电容采用电容 C1来表示。
本发明具体实施的一种总体结构如图 2所示，它的组成包含一个运算放大器 Al、 四个 MOS管 Μ(ΓΜ3、 一个电容 Cl。 图 2中的具体连接关系与本说明书的 发明内容部分相同， 它的工作原理如下：
传统结构的输入缓冲器电路， 其小信号增益 A v表达式为：
Figure imgf000007_0001
其中， gm为第 MO号 NMOS管（跟随管）跨导， 、 分别为第 M0号 NMOS 管 （跟随管） 与尾电流的输出电阻。
从 （1 ) 式可以看出， 输入缓冲器电路的增益与输入跟随管的跨导 gm、 输出 电阻 和尾电流的输出电阻 r。2相关。 当输出跟随输入信号变化时， 输出端的电 压持续变化，造成输入跟随管和尾电流管的漏源电压变化，在现代亚微米工艺中， 跨导 gm或输出电阻 随 MOS管漏源电压 VDS变化显著，通常达到百分之十的 非线性。
本发明中， NMOS管 M0 (输入跟随管 MO) 的线性度提高电路由跟随电容 C1与跟随管 Ml组成，主要解决 NMOS管 M0的漏源电压 VDS变化引起的非线 性问题。 当输入信号在输入节点 a变化时， NMOS管 M0源极的输出信号随 M0 栅极的输入信号变化。 因为跟随电容 C1一端连接输入信号端， 因此输入信号变 化时， 电容 C1的另一端跟随输入而变化， 进一步引起跟随管 Ml的源极跟随其 栅极电压变化。 因为跟随管 Ml的源极连接跟随管 NMOS管 M0的漏极， 所以 跟随管 NMOS管 M0的漏极与源极和输入信号的变化同方向。 并且， 因为电容 自身的良好高频特性， 即使输入信号的速度快， 跟随管 Ml的栅极电压也几乎与 输入信号的变化同步， 保证了跟随管 NMOS管 M0的漏极和源极电压都是仅经 过一个 MOS管自身的跟随变化。 输入信号频率对线性度的制约， 仅受限于现代 工艺中 MOS管自身的匹配度， 即跟随管 NMOS管 M0的 VDS电压， 基本能够 保持恒定。
本发明中，负载阻抗线性度提高电路由 NMOS管 M2和运算放大器 A1组成， 主要解决尾电流负载 NMOS管 M3阻抗随输出变化表现出来的非线性变化问题。 使用负载阻抗线性度提高电路后，尾电流的输出阻抗增大。高输出阻抗的意义体 现在 "屏蔽"输入器件， 使得其不受输出节点 c电压变化的影响。
因此， 使用本发明的 CMOS输入缓冲器电路， 具有高线性度， 且高频特性 好。
实施例 2
本实施例与实施例 1的区别仅在于：
图 3是本发明的高线性 CMOS输入缓冲器电路的实施例 2电路图， 如图所 示，本实施例与实施例 1的区别在于： 实施例 1中的 MOS管， 即 NMOS管 M0、 NMOS管 Ml、 NMOS管 M2、 NMOS管 M3为 PMOS,负载管因为是 PMOS管， 阻抗略有下降， 但是 PMOS 管的衬底可以单独接电位， 因此输入跟随管的线性 度更高。
实施例 3
本实施例与实施例 1的区别仅在于：
图 4是本发明的高线性 CMOS输入缓冲器电路的实施例 3电路图， 如图所 示， 本实施例与实施例 1的区别在于： 去除了运放 Al， 增加了 NMOS管 M4， NMOS管 M4的漏极连接 NMOS管 M2的源极， NMOS管 M4的源极连接 NMOS 管 M3的漏极， NMOS管 M2和 NMOS管 M4的栅极连接偏置电压。 因为减少 了运放 A 1单元， 电路功耗进一步降低， 但是增加的 MOS管 M4减少了输出摆 幅。
实施例 3
本实施例与实施例 1的区别仅在于：
图 5是本发明的高线性 CMOS输入缓冲器电路的实施例 4电路图， 如图所 示， 本实施例与实施例 1的区别在于： 去除了电容 Cl， 增加了 PMOS管 M4， PMOS管 M4的栅极连接 NMOS管 M0的漏极， PMOS管 M4的源极连接 NMOS 管 M0的源极， NMOS管 Ml的栅极连接偏置电压。 减少了电容单元， 即减少了 输入驱动能力的要求， 但使用 PMOS管 M4跟随输入信号的变化， 对输入跟随 管 NMOS管 M0进行补偿， 在高频时候， 会因为补偿信号进过了两个 MOS管， 即 NMOS管 M0、PMOS管 M4，而正常的输出信号，仅经过一个 MOS管即 NMOS 管 M0,出现时间匹配问题， 产生谐波。
以上所述仅为本发明的优选实施例， 并不用于限制本发明， 显然， 本领域的 技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。 这 样， 倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之 内， 则本发明也意图包含这些改动和变型在内。

Claims

权利要求书
1. CMOS输入缓冲器， 其特征在于： 包括 CMOS输入跟随电路、 跟随管线性度 提高电路、 电流源负载和负载阻抗线性度提高电路；
所述 CMOS输入跟随电路， 用于跟随输入信号变化， 输出跟随输入信号的输出信 号；
所述跟随管线性度提高电路，用于获取输入信号的变化趋势，并将输入信号反馈作 用于 CMOS输入跟随电路；
所述电流源负载， 用于提供所述 CMOS输入跟随电路正常工作的偏置电流； 所述负载阻抗线性度提高电路连接于 CMOS输入跟随电路和电流源负载之间， 用 于增强电流源负载阻抗的绝对值， 减小绝对值相对变化幅度， 提高 CMOS输入缓冲器 负载阻抗的线性度。
2. 根据权利要求 1所述的 CMOS输入缓冲器电路， 其特征在于： 所述 CMOS输 入跟随电路包括第 M0号 NMOS管，所述第 M0号 NMOS管的栅极作为 CMOS输入跟 随电路的输入端， 所述第 M0号 NMOS管的源极作为 CMOS输入跟随电路的输出端， 所述跟随管线性度提高电路连接于第 M0号 NMOS管的栅极和第 M0号 NMOS管的漏 极之间， 所述负载阻抗线性度提高电路一端与第 M0号 NMOS管的源极连接， 所述负 载阻抗线性度提高电路另一端与电流源负载连接。
3. 根据权利要求 1所述的 CMOS输入缓冲器电路， 其特征在于： 所述跟随管线 性度提高电路包括电容和第 Ml号 NMOS管， 所述电容的一端连接第 M0号 NMOS管 的栅极， 所述电容 C1的另一端连接第 Ml号 NMOS管的栅极， 所述第 Ml号 NMOS 管的漏极连接电源电压， 第 Ml号 NMOS管的源极连接第 M0号 NMOS管的漏极。
4. 根据权利要求 1所述的 CMOS输入缓冲器电路， 其特征在于： 所述跟随管线 性度提高电路包括第 M4号 PMOS管和第 Ml号 NMOS管， 所述第 M4号 PMOS管的 栅极连接第 M0号 NMOS管的漏极， 第 M4号 PMOS管的源极连接第 M0号 NMOS管 的源极， 第 Ml号 NMOS管的栅极连接偏置电压， 所述第 M4号 PMOS管的漏极连接 电源电压。
5. 根据权利要求 1所述的 CMOS输入缓冲器电路， 其特征在于： 所述电流源负 载包括第 M3号 NMOS管，所述第 M3号 NMOS管的栅极连接偏压，所述第 M3号 NMOS 管的源极连接电源地，所述第 M3号 NMOS管的漏极与负载阻抗线性度提高电路连接。
6. 根据权利要求 1所述的 CMOS输入缓冲器电路， 其特征在于： 所述负载阻抗 线性度提高电路包括第 M2号 NMOS管和运放， 所述第 M2号 NMOS管的漏极连接第 M0号 NMOS管的源极， 第 M2号 NMOS管的源极连接第 M3号 NMOS管的漏极， 所 述运放的输入端连接第 M3号 NMOS管的漏极，所述运放的输出端连接第 M2号 NMOS 管的栅极。
7. 根据权利要求 1所述的 CMOS输入缓冲器电路， 其特征在于： 所述负载阻抗 线性度提高电路包括第 M2号 NMOS管和第 M4号 NMOS管，所述第 M2号 NMOS管 的源极与第 M4号 NMOS管的漏极连接， 第 M4号 NMOS管的源极与第 M3号 NMOS 管的漏极连接， 所述第 M2号 NMOS管的栅极连接偏压， 所述第 M4号 NMOS管的栅 极连接偏压。
8. 根据权利要求 2、 3、 5、 6或 7所述的 CMOS输入缓冲器电路， 其特征在于： 所述 NMOS管由 PMOS管代替。
9. 根据权利要求 4所述的 CMOS输入缓冲器电路， 其特征在于： 所述 NMOS管 由 PMOS管代替， 所述 PMOS管由 NMOS管代替。
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CN113300708A (zh) * 2021-04-09 2021-08-24 西安电子科技大学 一种应用于超高速模数转换器的宽带输入信号缓冲器
CN113300708B (zh) * 2021-04-09 2023-03-21 西安电子科技大学 一种应用于超高速模数转换器的宽带输入信号缓冲器

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