WO2014063386A1 - 液晶面板的驱动电路 - Google Patents

液晶面板的驱动电路 Download PDF

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Publication number
WO2014063386A1
WO2014063386A1 PCT/CN2012/084107 CN2012084107W WO2014063386A1 WO 2014063386 A1 WO2014063386 A1 WO 2014063386A1 CN 2012084107 W CN2012084107 W CN 2012084107W WO 2014063386 A1 WO2014063386 A1 WO 2014063386A1
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Prior art keywords
gate
film transistor
electrode
thin film
liquid crystal
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PCT/CN2012/084107
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English (en)
French (fr)
Inventor
陈胤宏
田夏
贾沛
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/805,658 priority Critical patent/US9025102B2/en
Publication of WO2014063386A1 publication Critical patent/WO2014063386A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a driving circuit for a liquid crystal panel. Background technique
  • liquid crystal displays have been widely seen in life, and people are increasingly demanding liquid crystal displays, and are beginning to pursue large display screens and fast response speeds.
  • TFT Thin Film Transistor
  • FIG. 1 is a schematic diagram of a circuit driving structure of a basic TFT array substrate.
  • pixel electrodes are distributed on the entire TFT substrate, and each pixel electrode is connected to at least one drain D of a thin film transistor, and a source S of each thin film transistor is at least A data line is connected, and a plurality of data lines together constitute a data bus structure; at least one gate line is connected to the gate G of each thin film transistor, and a plurality of gate lines collectively constitute a gate bus structure; a data bus and a strobe bus
  • the data writing of the pixel electrodes is commonly controlled by the thin film transistors, and the pixel electrodes P(i, j) on the substrate and the pixel electrodes P(i, j) on the substrate are collectively subjected to the gate line G(j) and the data.
  • the gate line G(j) is at a high level to ensure that the thin film transistor T(i, j) is in an on state, at this time through the data line S (i)
  • the magnitude of the driving voltage applied thereto causes the liquid crystal molecules in the vicinity of the pixel electrode P(i, j) to be deflected in a predetermined deflection direction, thereby realizing display of an image.
  • This write operation is also performed in rows, and all pixel electrodes of the jth row are written when the gate line G1 is at a high level.
  • the thin film transistor T(n, j) cannot be turned on, or the source driving voltage V s (n, j) for deflecting the liquid crystal molecules is applied. It can't be turned on or not turned on within a fixed time. This will cause the liquid crystal molecules on the pixel electrode to not deflect or deflect in a predetermined direction, thus causing a change in transmittance and a change in contrast near the region. Affect the display quality.
  • FIG. 2 is a schematic diagram of a driving line connection of each of the pixel electrodes, wherein the i-th data line S(i) is connected to the source S of the thin film transistor T(i, j) of the i-th column and the j-th row, and the j-th gate is connected
  • the line G(j) is connected to the gate G of the thin film transistor T(i, j) of the jth row of the i-th column, and the drain D and the ith column of the thin film transistor T(i, j) of the jth row of the i-th column
  • the pixel electrodes P(i, j) of the jth row are connected.
  • C gd is a parasitic capacitance between the gate G and the drain D, and the parasitic capacitance C gd is inherent in the structural characteristics of the thin film transistor.
  • C lc is a liquid crystal capacitor between the TFT substrate and the CF substrate
  • C s is a compensation capacitor between the TFT substrate and the Vcom terminal, and the compensation capacitor is present to ensure that the voltage on the c lc is lowered by discharging
  • the compensation is to appropriately increase the deflection direction of the liquid crystal molecules in the c lc region to maintain the time.
  • V 3 is a driving voltage waveform in the case of the thin film transistor structure of FIG. 1, VG(j) is an ideal waveform outputted by the strobe bus at the jth row, and the waveform of V g (N, j) is passed through the front N-1 thin film transistors.
  • the parasitic capacitance C gd and the waveform of the line delay, V gh and V gl are the high voltage and the low voltage of V g (N, j), respectively, and the thin film transistor is turned on when the voltage is greater than the conduction threshold voltage VT of the thin film transistor.
  • the driving voltage V S (N, j) on the data line S(N) writes to the pixel electrode, and drives the liquid crystal molecules in the vicinity of the pixel electrode to be deflected.
  • V g (N, j) is greater than the turn-on voltage of the thin film transistor
  • C lc , C s , C gd are charged through the rising edge of Vg(N , j), respectively, and the charge is saturated, and V g (N, j)
  • the reverse discharge of C s , C gd at the falling edge forms a linear voltage drop; especially in the reverse discharge of c s , c gd at the falling edge of V g (N, j), it will bring delay, from the curve It can be seen that the time longer than the VT voltage is lengthened, that is, the thin film transistor that should be turned off is turned on under the influence of the parasitic capacitance.
  • An object of the present invention is to provide a driving circuit for a liquid crystal panel, which can reduce the influence of delay caused by parasitic capacitance and improve the quality of a large-sized liquid crystal display.
  • the present invention provides a driving circuit for a liquid crystal panel, including: a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines, wherein the plurality of gate lines and data lines define a plurality of pixels
  • Each of the pixel units includes a thin film transistor, a common electrode, a pixel electrode electrically connected to the thin film transistor, and a correction capacitor, wherein the thin film transistor and the gate driver and the source are respectively connected through the gate line and the data line
  • the driver is electrically connected, the common electrode is
  • the pixel electrode forms a liquid crystal capacitor
  • the thin film transistor includes a gate and a drain
  • the correction capacitor is electrically connected between the gate and the drain, and performs parasitic capacitance formed by the structural characteristics of the gate and the drain. Corrected.
  • the thin film transistor further includes a source electrically connected to the source driver through the data line.
  • the gate of the thin film transistor is electrically connected to the gate driving source through a gate line, and the drain of the thin film transistor is electrically connected to the pixel electrode.
  • the correction capacitor is connected to the gate of the thin film transistor at one end and to the pixel electrode at the other end.
  • the correction capacitor is a voltage stabilizing capacitor whose capacitance is smaller than the capacitance of the parasitic capacitance generated by the gate and drain due to structural characteristics.
  • the correction capacitor has a rated voltage that is less than a rated voltage of the parasitic capacitance of the gate and drain due to structural characteristics.
  • the correction capacitor has a high voltage withstand capability.
  • a storage capacitor is further included, and the storage capacitor is connected in parallel with the liquid crystal capacitor.
  • the present invention also provides a driving circuit for a liquid crystal panel, comprising: a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines, the plurality of gate lines and data lines defining a plurality of pixel units, each
  • the pixel unit includes a thin film transistor, a common electrode, a pixel electrode electrically connected to the thin film transistor, and a correction capacitor.
  • the thin film transistor is electrically connected to the gate driver and the source driver through the gate line and the data line, respectively.
  • the common electrode and the pixel electrode form a liquid crystal capacitor
  • the thin film transistor includes a gate and a drain
  • the correction capacitor is electrically connected between the gate and the drain, and the gate and the drain are connected by a structure.
  • the parasitic capacitance formed by the characteristic is corrected; wherein the thin film transistor further includes a source, the source is electrically connected to the source driver through the data line;
  • the gate of the thin film transistor is electrically connected to the gate driving source through a gate line, and the drain of the thin film transistor is electrically connected to the pixel electrode;
  • correction capacitor is connected to the gate of the thin film transistor at one end and to the pixel electrode at the other end;
  • the correction capacitor is a voltage stabilizing capacitor whose capacitance is smaller than the capacitance of the parasitic capacitance generated by the gate and the drain due to structural characteristics;
  • the rated voltage of the correction capacitor is smaller than a rated voltage of the parasitic capacitance generated by the gate and the drain due to structural characteristics;
  • correction capacitor has a high pressure resistance capability
  • a storage capacitor is further included, and the storage capacitor is connected in parallel to the liquid crystal capacitor.
  • the driving circuit of the liquid crystal panel of the present invention limits the voltage of the parasitic capacitance generated by the gate and the drain by parallelizing a correction capacitor between the gate and the drain of the thin film transistor, thereby reducing the parasitic capacitance
  • the discharge leads to extend the conduction time of the thin film transistor, thereby reducing the possibility of abnormal conduction of the thin film transistor in a non-conducting state, further improving the precision of the thin film transistor control, and avoiding the transmittance of the abnormal deflection of the liquid crystal molecule.
  • the phenomenon of abnormality in contrast and contrast is improved, and the quality of a liquid crystal display using a large-sized circuit is improved.
  • FIG. 1 is a schematic diagram of a circuit driving structure of a conventional TFT array substrate
  • FIG. 2 is a schematic diagram showing a driving circuit connection of a pixel electrode in a conventional TFT array substrate
  • FIG. 3 is a schematic diagram showing a waveform of a gate driving voltage when a thin film transistor of the TFT array substrate is turned on;
  • FIG. 4 is a schematic diagram of a circuit driving structure of a TFT array substrate according to the present invention.
  • FIG. 5 is a schematic diagram showing the circuit connection of a pixel unit in a driving circuit of a liquid crystal panel of the present invention
  • FIG. 6 is a schematic view showing a waveform of a gate driving voltage of a driving circuit thin film transistor of the liquid crystal panel of the present invention.
  • the present invention provides a driving circuit for a liquid crystal panel, including: a gate driver 2, a source driver 4, a plurality of gate lines G(j), and a plurality of data lines S(i).
  • the plurality of gate lines G(j) and the data lines S(i) define a plurality of pixel units, each of the pixel units including a thin film transistor T(i, j), a common electrode 8, and a thin film transistor T(i, j) the electrically connected pixel electrode 6 and a correction capacitor Co, wherein the thin film transistor T(i, j) is electrically connected to the gate driver 2 and the source driver 4 through the gate line G1 and the data line S(i), respectively
  • the common electrode 8 and the pixel electrode 6 form a liquid crystal capacitor C k
  • the storage capacitor Cs is connected in parallel with the liquid crystal capacitor C k
  • the thin film transistor T(i, j) includes a gate G and a Drain D, the correction capacitor C. Electrical connection The parasitic capac
  • the plurality of data lines S(1), S(2), S(i) form a data bus structure S
  • the plurality of gate lines G(l), G(2).. ... G(j) constitutes a strobe bus structure G, which drives the pixel electrode 6 together with the strobe bus structure G.
  • each of the data lines S(i) is connected to each of the pixel electrodes 6 by being connected to a source S of one of the thin film transistors T(i, j); each gate line G1 is passed through one The gate G of the thin film transistor T(i, j) is connected to each of the pixel electrodes 6.
  • the thin film transistor T(i, j) further includes a source S electrically connected to the source driver 4 via a data line S(i).
  • the driving circuit of the liquid crystal panel of the present invention further includes a storage capacitor Cs connected to both ends of the liquid crystal capacitor C lc for voltage compensation of the liquid crystal capacitor ( ⁇ 1 £ ;
  • the gate G of the thin film transistor T(i, j) is electrically connected to the gate driving source 2 through the gate line G1, and the drain D of the thin film transistor T(i, j) is electrically connected to the pixel electrode 6. .
  • the correction capacitor C One end is connected to the gate G of the thin film transistor T(i, j), and the other end is connected to the pixel electrode 6.
  • the correction capacitor Co is a constant voltage capacitor whose capacitance and rated voltage are smaller than the capacitance and rated voltage of the parasitic capacitance C gd generated by the gate G and the drain D due to structural characteristics, and the correction capacitor Co withstand voltage strong ability.
  • the correction capacitance Co is a constant voltage capacitor and the capacitance value is smaller than the parasitic capacitance C gd between the gate G and the drain D of the thin film transistor T(i, j), when the gate voltage V When g (i, j) is larger than the on-voltage VT of the thin film transistor T(i, j), the correction capacitor C is applied to the rising edge of the gate voltage Vg(i, j), respectively.
  • the liquid crystal capacitor C k , the storage capacitor C s and the parasitic capacitor C gd are charged, the charge is saturated, and the gate voltage V g (i, j) falls along the storage capacitor C s , and the reverse discharge of the parasitic capacitor C gd forms a linear voltage drop.
  • the voltage v co on the falling voltage of the storage capacitor C s and the parasitic capacitance C gd at the falling edge of the gate voltage V g (i , j) is the same as the forward case, the discharge time is reduced, and the reverse discharge is performed.
  • the feedback voltage amplitude is small, and the delay time is short, that is, ⁇ ⁇ ," ⁇ ⁇ ⁇ , which can be seen from the gate drive voltage waveform in Fig. 5 when it is larger than the threshold voltage VT of the gate G.
  • the gate voltage V, gG ) is changed by the correction capacitor C per unit time.
  • the gate voltage V gG decreases, the amount of change per unit time is small, that is, the thin film crystal T(i, j) which is turned off can be turned on under the influence of the parasitic capacitance C gd . The energy is reduced.
  • the present invention provides a driving circuit for a liquid crystal panel, by limiting a voltage between a gate and a drain of a thin film transistor by a correction capacitor, thereby reducing the voltage of the parasitic capacitance generated by the gate and the drain, thereby reducing
  • the parasitic capacitance is extended by the thin film transistor due to the discharge, thereby reducing the possibility of abnormal conduction of the thin film transistor in a non-conducting state, further improving the precision of the thin film transistor control, and avoiding the abnormal deflection of the liquid crystal molecule.
  • the change in transmittance and the phenomenon of abnormal contrast improve the quality of a liquid crystal display using a large-sized circuit.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
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  • General Physics & Mathematics (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Abstract

一种液晶面板的驱动电路，包括：栅极驱动器（2）、源极驱动器（4）、多条选通线G（j）以及多条数据线S（j）。该多条选通线G（j）和多条数据线S（j）界定多个像素单元，每个像素单元包括：薄膜晶体管T（i，j）、公共电极（8）、像素电极（6）及修正电容（C0）。该薄膜晶体管T（i，j）通过选通线G（j）及数据线S（j）分别与栅极驱动器（2）及源极驱动器（4）电性连接，该公共电极（8）与像素电极（6）形成液晶电容（Clc）。该薄膜晶体管T（i，j）包括栅极（G）及漏极（D），该修正电容（C0）电性连接于栅极（G）与漏极（D）之间，对栅极（G）与漏极（D）因结构特性形成的寄生电容（Cgd）进行修正。通过设置修正电容（C0）来减少寄生电容（Cgd）对薄膜晶体管T（i，j）的影响，提高薄膜晶体管T（i，j）的控制精度，避免液晶分子异常偏转产生的透射率的改变和对比度的异常。

Description

液晶面板的驱动电路 技术领域
本发明涉及一种液晶显示器领域， 尤其涉及一种液晶面板的驱动电 路。 背景技术
随着科学技术的发展以及人们生活质量的提高， 液晶显示器在生活中 已经随处可见， 并且人们对液晶显示器的要求越来越高， 开始追求大的显 示画面、 快的响应速度。 但是随着液晶显示面板的增大布线的复杂度提 高， 而且随着 TFT ( Thin Film Transistor 、 薄膜场效应晶体管）基板驱动 像素电极数量的增加线路延时以及因为 TFT寄生电容的存在所带来的反馈 电压对每个像素电极的影响使得精确控制像素电极的难度也跟着增加。
图 1为基本的 TFT阵列基板的电路驱动结构示意图， 图中在整个 TFT 基板上分布着像素电极， 每一个像素电极至少与一个薄膜晶体管的漏极 D 相连， 每个薄膜晶体管的源极 S至少连接一条数据线， 数条数据线共同构 成了数据总线结构； 每一个薄膜晶体管的栅极 G至少连接一条选通线， 数 条选通线共同构成了选通总线结构； 数据总线和选通总线通过薄膜晶体管 共同控制这些像素电极的数据写入， 如图所示的基板上的第 i歹' j、 第 j 行 的像素电极 P(i,j)共同受到选通线 G(j)和数据线 S(i)的控制， 当对该像素电 极进行写操作时， 选通线 G(j)处于高电平， 保证薄膜晶体管 T(i,j)处于导通 状态， 此时通过数据线 S(i)上所加的驱动电压的大小使与像素电极 P(i,j)相 对的附近的液晶分子按照预定的偏转方向偏转， 从而实现图像的显示。 这 样的写操作同时也是按行进行的， 当选通线 G①处于高电平时将对第 j 行 的所有像素电极进行写操作。
然而随着矩阵分布的 TFT基板中像素电极的行和列数量的增加， 增长 的选通线和数据线的会带来驱动线路的延时； 另一方面薄膜晶体管中的栅 极 G和漏极 D之间寄生电容 Cgd的存在将直接影响栅极电压 Vg对薄膜晶 体管的导通和截止的控制， 特别是在离选通总线电路较远的末端的像素电 极 P(n, j)附近， 由于选通信号在之前所经过的 n-1个薄膜晶体管的寄生电 容 Cgd带来的的负反馈电压的影响以及线路延时影响， 此处不但响应时间 较长， 同时也存在选通电压因负反馈带来的衰减， 有可能使得薄膜晶体管 T(n, j)不能导通， 或者在施加使液晶分子偏转的源极驱动电压 Vs(n, j)的 固定时间内不能导通或者不能全部导通， 这将会使得该像素电极上的液晶 分子不偏转或者不能按照预定的方向偏转， 因此会带来该区域附近的透射 率的改变和对比度的变化， 影响显示质量。
图 2是每一个像素电极的驱动线路连接示意图， 其中第 i条数据线 S(i) 与第 i列第 j行的薄膜晶体管 T(i, j)的源极 S相连， 第 j条选通线 G(j)与第 i列第 j行的薄膜晶体管 T(i, j)的栅极 G相连， 第 i列第 j行的薄膜晶体管 T(i, j)的漏极 D与第 i列第 j行的像素电极 P(i, j)相连。 Cgd是栅极 G和漏 极 D之间的寄生电容， 该寄生电容 Cgd是在薄膜晶体管结构特性所固有 的。 其中 Clc是处在 TFT基板和 CF基板之间的液晶电容， Cs是处在 TFT 基板和 Vcom端之间的一个补偿电容， 该补偿电容的存在是为了通过放电 保证 clc上电压降低时的补偿， 以适当增大 clc区域中的液晶分子的偏转方 向保持时间。
图 3是图 1薄膜晶体管结构情况下驱动电压波形， VG(j)为由选通总线 在第 j 行输出理想波形， Vg(N, j)的波形是经过前边 N-1 个薄膜晶体管的 寄生电容 Cgd以及线路延时的波形， Vgh和 Vgl分别是 Vg(N,j)的高电压和低 电压， 当电压大于薄膜晶体管的导通阔值电压 VT 时薄膜晶体管导通， 同 时数据线 S(N)上的驱动电压 VS(N, j)对该像素电极写操作， 驱动该像素电 极附近的液晶分子偏转。 当栅极电压 Vg(N, j)大于薄膜晶体管的导通电压 时， 分别经过 Vg(N , j)上升沿对 Clc , Cs , Cgd充电， 充电饱和， 以及 Vg(N, j)下降沿 Cs, Cgd的反向放电形成线性压降； 特别是在 Vg(N, j)下降 沿 cs, cgd的反向放电过程中， 会带来延时， 从曲线上可以看出处于大于 VT 电压的时间加长， 也就是说本该截止的薄膜晶体管在寄生电容的影响 下导通了。 这样的影响在漏极 D—端就表现为 Vd(N, j)的电压漂移， 加大 了液晶分子处于偏转状态的时间， 表现为本该不偏转的液晶分子偏转了， 带来对比度显示的异常。 发明内容
本发明的目的在于提供一种液晶面板的驱动电路， 能够减小寄生电容 带来的延时影响， 提高大尺寸液晶显示器的质量。
为实现上述目的， 本发明提供一种液晶面板的驱动电路， 包括： 栅极 驱动器、 源极驱动器、 多条选通线及多条数据线， 该多条选通线和数据线 界定多个像素单元， 每一像素单元包括一薄膜晶体管、 一公共电极、 一与 薄膜晶体管电性连接的像素电极、 及一修正电容， 所述薄膜晶体管通过选 通线及数据线分别与栅极驱动器及源极驱动器电性连接， 所述公共电极与 像素电极形成一液晶电容， 所述薄膜晶体管包括一栅极及一漏极， 所述修 正电容电性连接于栅极与漏极之间， 对栅极与漏极因结构特性形成的寄生 电容进行修正。
所述薄膜晶体管还包括一源极， 该源极通过数据线电性连接至源极驱 动器。
所述薄膜晶体管的栅极通过选通线电性连接至栅极驱动源， 所述薄膜 晶体管的漏极与像素电极电性连接。
所述修正电容一端连接至薄膜晶体管的栅极， 另一端连接至像素电 极。
所述修正电容为一稳压电容， 其容值小于栅极与漏极因结构特性产生 的寄生电容的容值。
所述修正电容的额定电压小于所述栅极与漏极因结构特性产生的寄生 电容的额定电压。
所述修正电容耐压能力强。
还包括一存储电容， 所述存储电容与所述液晶电容并联连接。
本发明还提供一种液晶面板的驱动电路， 包括： 栅极驱动器、 源极驱 动器、 多条选通线及多条数据线， 该多条选通线和数据线界定多个像素单 元， 每一像素单元包括一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性 连接的像素电极、 及一修正电容， 所述薄膜晶体管通过选通线及数据线分 别与栅极驱动器及源极驱动器电性连接， 所述公共电极与像素电极形成一 液晶电容， 所述薄膜晶体管包括一栅极及一漏极， 所述修正电容电性连接 于栅极与漏极之间， 对栅极与漏极因结构特性形成的寄生电容进行修正； 其中， 所述薄膜晶体管还包括一源极， 该源极通过数据线电性连接至 源极驱动器；
其中， 所述薄膜晶体管的栅极通过选通线电性连接至栅极驱动源， 所 述薄膜晶体管的漏极与像素电极电性连接；
其中， 所述修正电容一端连接至薄膜晶体管的栅极， 另一端连接至像 素电极；
其中， 所述修正电容为一稳压电容， 其容值小于栅极与漏极因结构特 性产生的寄生电容的容值；
其中， 所述修正电容的额定电压小于所述栅极与漏极因结构特性产生 的寄生电容的额定电压；
其中， 所述修正电容耐压能力强；
还包括一存储电容， 所述存储电容并联连接于所述液晶电容。 本发明的有益效果： 本发明液晶面板的驱动电路通过在薄膜晶体管的 栅极与漏极之间并联一修正电容， 对栅极与漏极产生的寄生电容的电压进 行限制， 从而减少寄生电容因放电带来的延长薄膜晶体管导通的时间， 进 而减小薄膜晶体管非导通状态下的异常导通的可能性， 进一步提高薄膜晶 体管控制的精度， 避免了液晶分子异常偏转带来的透射率的改变和对比度 异常的现象， 提高大尺寸使用该电路的液晶显示器的质量。
为了能更进一步了解本发明的特征以及技术内容， 请参阅以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1为现有 TFT阵列基板的电路驱动结构示意图；
图 2为现有 TFT阵列基板中像素电极的驱动线路连接示意图； 图 3为图 1中 TFT阵列基板的薄膜晶体管导通延时时栅极驱动电压波 形示意图；
图 4为本发明中 TFT阵列基板的电路驱动结构示意图；
图 5为本发明液晶面板的驱动电路中像素单元的电路连接示意图； 图 6为本发明液晶面板的驱动电路薄膜晶体管栅极驱动电压波形示意 图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 4至 6, 本发明提供一种液晶面板的驱动电路， 包括： 栅极 驱动器 2、 源极驱动器 4、 多条选通线 G(j)及多条数据线 S(i), 该多条选通 线 G(j)和数据线 S(i)界定多个像素单元， 每一像素单元包括一薄膜晶体管 T(i, j)、 一公共电极 8、 一与薄膜晶体管 T(i, j)电性连接的像素电极 6、 及一修正电容 Co, 所述薄膜晶体管 T(i, j)通过选通线 G①及数据线 S(i)分 别与栅极驱动器 2及源极驱动器 4电性连接， 所述公共电极 8与像素电极 6形成一液晶电容 Ck, 所述存储电容 Cs与该液晶电容 Ck并联连接， 所述 薄膜晶体管 T(i, j)包括一栅极 G及一漏极 D, 所述修正电容 C。电性连接 于栅极 G与漏极 D之间 , 对栅极 G与漏极 D因结构特性形成的寄生电容 Cgd进行修正。
所述多条数据线 S(l) , S(2) ... ... S(i)构成一数据总线结构 S , 所述多 条选通线 G(l) , G(2) ... ... G(j)构成一选通总线结构 G, 所述数据总线结构 S与所述选通总线结构 G共同驱动所述像素电极 6。 其中， 每条数据线 S(i) 通过与一个所述薄膜晶体管 T(i, j)的源极 S连接进而与每一个所述像素电 极 6连接； 每条选通线 G①通过与一个所述薄膜晶体管 T(i, j)的栅极 G连 接进而与每一个所述像素电极 6连接。
所述薄膜晶体管 T(i, j)还包括一源极 S , 该源极 S通过数据线 S(i)电 性连接至源极驱动器 4。
本发明液晶面板的驱动电路还包括一存储电容 Cs , 该一存储电容 Cs 连接于液晶电容 Clc的两端， 对液晶电容 (^1£；进行电压补偿。
所述薄膜晶体管 T(i, j)的栅极 G通过选通线 G①电性连接至栅极驱动 源 2 , 所述薄膜晶体管 T(i, j)的漏极 D与像素电极 6电性连接。 所述修正 电容 C。一端连接至薄膜晶体管 T(i, j)的栅极 G, 另一端连接至像素电极 6。
所述修正电容 Co为一种稳压电容， 其容值及额定电压小于栅极 G与 漏极 D因结构特性产生的寄生电容 Cgd的容值及额定电压， 且所述修正电 容 Co耐压能力强。
由于所述修正电容 Co为一种稳压电容， 且其电容值小于所述薄膜晶 体管 T(i, j)的栅极 G 与漏极 D 之间的寄生电容 Cgd, 所以当栅极电压 Vg(i, j)大于薄膜晶体管 T(i, j)导通电压 VT时， 分别经过栅极电压 Vg(i, j)上升沿对修正电容 C。、 液晶电容 Ck、 存储电容 Cs及寄生电容 Cgd充电， 充电饱和， 以及栅极电压 Vg(i, j)下降沿存储电容 Cs、 寄生电容 Cgd的反 向放电形成线性压降， 在对存储电容 Cs、 寄生电容 Cgd充电过程中修正电 容 C。先于寄生电容 cgd饱和， 且其上的电压值为 vc。， vc。小于使寄生电 容 Cgd饱和时的电压 VCgd, 同时由于寄生电容 Cgd与修正电容 C。是并联结 构， 所以寄生电容 Cgd上的实际电压 V，Cgd等于修正电容 C。上的电压 vco; 在栅极电压 Vg(i , j)下降沿存储电容 Cs、 寄生电容 Cgd的反向放电过程 中， 与正向情况相同， 放电时间减小， 反向放电的反馈电压幅值较小， 带 来的延时时间较短， 即 Δ Τ，」< Δ η, 从图 5 中栅极驱动电压波形可以看出 处于大于栅极 G的阔值电压 VT值时的栅极电压 V，gG)单位时间变化量比起 没有添加此修正电容 C。时的栅极电压 VgG)的单位时间内下降变化量要少， 也就是说本该截止的薄膜晶体 T(i, j)管在寄生电容 Cgd的影响下导通的可 能性减小了。
综上所述， 本发明提供一种液晶面板的驱动电路， 通过在薄膜晶体管 的栅极与漏极之间并联一修正电容， 对栅极与漏极产生的寄生电容的电压 进行限制， 从而减少寄生电容因放电带来的延长薄膜晶体管导通的时间， 进而减小薄膜晶体管非导通状态下的异常导通的可能性， 进一步提高薄膜 晶体管控制的精度， 避免了液晶分子异常偏转带来的透射率的改变和对比 度异常的现象， 提高大尺寸使用该电路的液晶显示器的质量。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

权 利 要 求
1、 一种液晶面板的驱动电路， 包括： 栅极驱动器、 源极驱动器、 多 条选通线及多条数据线， 该多条选通线和数据线界定多个像素单元， 每一 像素单元包括一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性连接的像 素电极、 及一修正电容， 所述薄膜晶体管通过选通线及数据线分别与栅极 驱动器及源极驱动器电性连接， 所述公共电极与像素电极形成一液晶电 容， 所述薄膜晶体管包括一栅极及一漏极， 所述修正电容电性连接于栅极 与漏极之间， 对栅极与漏极因结构特性形成的寄生电容进行修正。
2、 如权利要求 1 所述的液晶面板的驱动电路， 其中， 所述薄膜晶体 管还包括一源极， 该源极通过数据线电性连接至源极驱动器。
3、 如权利要求 2 所述的液晶面板的驱动电路， 其中， 所述薄膜晶体 管的栅极通过选通线电性连接至栅极驱动源， 所述薄膜晶体管的漏极与像 素电极电性连接。
4、 如权利要求 3 所述的液晶面板的驱动电路， 其中， 所述修正电容 一端连接至薄膜晶体管的栅极， 另一端连接至像素电极。
5、 如权利要求 4 所述的液晶面板的驱动电路， 其中， 所述修正电容 为一稳压电容， 其容值小于栅极与漏极因结构特性产生的寄生电容的容 值。
6、 如权利要求 5 所述的液晶面板的驱动电路， 其中， 所述修正电容 的额定电压小于所述栅极与漏极因结构特性产生的寄生电容的额定电压。
7、 如权利要求 6 所述的液晶面板的驱动电路， 其中， 所述修正电容 耐压能力强。
8、 如权利要求 1 所述的液晶面板的驱动电路， 还包括一存储电容， 所述存储电容并联连接于所述液晶电容。
9、 一种液晶面板的驱动电路， 包括： 栅极驱动器、 源极驱动器、 多 条选通线及多条数据线， 该多条选通线和数据线界定多个像素单元， 每一 像素单元包括一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性连接的像 素电极、 及一修正电容， 所述薄膜晶体管通过选通线及数据线分别与栅极 驱动器及源极驱动器电性连接， 所述公共电极与像素电极形成一液晶电 容， 所述薄膜晶体管包括一栅极及一漏极， 所述修正电容电性连接于栅极 与漏极之间， 对栅极与漏极因结构特性形成的寄生电容进行修正；
其中， 所述薄膜晶体管还包括一源极， 该源极通过数据线电性连接至 源极驱动器；
其中， 所述薄膜晶体管的栅极通过选通线电性连接至栅极驱动源， 所 述薄膜晶体管的漏极与像素电极电性连接；
其中， 所述修正电容一端连接至薄膜晶体管的栅极， 另一端连接至像 素电极；
其中， 所述修正电容为一稳压电容， 其容值小于栅极与漏极因结构特 性产生的寄生电容的容值；
其中， 所述修正电容的额定电压小于所述栅极与漏极因结构特性产生 的寄生电容的额定电压；
其中， 所述修正电容耐压能力强；
还包括一存储电容， 所述存储电容并联连接于所述液晶电容。
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