WO2014063390A1 - 液晶显示驱动电路 - Google Patents

液晶显示驱动电路 Download PDF

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Publication number
WO2014063390A1
WO2014063390A1 PCT/CN2012/084259 CN2012084259W WO2014063390A1 WO 2014063390 A1 WO2014063390 A1 WO 2014063390A1 CN 2012084259 W CN2012084259 W CN 2012084259W WO 2014063390 A1 WO2014063390 A1 WO 2014063390A1
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WIPO (PCT)
Prior art keywords
thin film
gate
film transistor
electrically connected
liquid crystal
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PCT/CN2012/084259
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English (en)
French (fr)
Inventor
俞刚
顾毓波
贾沛
杨流洋
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/805,663 priority Critical patent/US9024853B2/en
Publication of WO2014063390A1 publication Critical patent/WO2014063390A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a liquid crystal display driving circuit. Background technique
  • liquid crystal displays have been widely seen in life, and people are increasingly demanding liquid crystal display devices, and have begun to pursue large display screens and fast response speed.
  • the wiring delay increases with the number of pixel electrodes driven by the TFT (Thin Film Transistor) array substrate and the parasitic capacitance of the TFT The effect of the feedback voltage on each pixel electrode increases the difficulty of accurately controlling the pixel electrode.
  • FIG. 1 is a schematic structural diagram of a driving circuit of a basic TFT array substrate.
  • the pixel electrodes 100 are distributed on the entire TFT array substrate, and each pixel electrode 100 is connected to at least one TFT drain d.
  • At least one data line is connected to the source s of each thin film transistor, and a plurality of data lines together form a data bus structure; at least one gate line is connected to the gate g of each thin film transistor, and a plurality of gate lines together form a gate Bus structure; the data bus and the strobe bus jointly control data writing of the pixel electrodes through the thin film transistors, and the pixel electrodes 100 of the jth row of the i-th column on the TFT array substrate are collectively subjected to the gate lines G(j) and the data lines S (i) control, when the pixel electrode P, (i, j) is written, the gate line G(j) is at a high level to ensure that the thin film transistor T(i, j) is in a conducting state, At the time of the driving voltage applied to the data line S(i), the liquid crystal molecules in the vicinity of the pixel electrode 100 are deflected in a predetermined deflection direction, thereby realizing display of an image. Such a write operation is also
  • FIG. 2 is a schematic diagram of an equivalent driving circuit connection of each pixel electrode, wherein the ith data line S(i) is connected to the source s of the ith column jth thin film transistor T(i, j),
  • the jth gate line G(j) is connected to the gate g of the thin film transistor T(i, j) of the i-th column and the jth row, and the drain d of the thin film transistor T(i, j) of the i-th column j-th row
  • the pixel electrodes 100 of the i-th column and the j-th row are connected.
  • the increased gate line and data line will bring delay to the driving line; as shown in FIG. 3, on the other hand, in the thin film transistor
  • the presence of the parasitic capacitance C gd between the gate g and the drain d will directly affect the control of the turn-on and turn-off of the thin film transistor by the gate voltage V g , particularly at the end of the pixel electrode far from the gate bus line. Nearby, due to the influence of the discharge voltage caused by the strobe signal on the parasitic capacitance C gd of the n-1 thin film transistors and the delay of the line, there is not only a long response time but also a gate voltage.
  • the decay caused by the discharge from high to low causes the on-time ⁇ of the thin film transistor T(n, j) to be extended by ⁇ , that is, the thin film transistor which should be turned off is abnormally turned on, which brings about the drain of the thin film transistor.
  • the driving time of the connected pixel electrode P(n, j) is extended by AT dx , resulting in a difference in transmittance and contrast abnormality caused by abnormal deflection of liquid crystal molecules in the vicinity of the pixel electrode.
  • An object of the present invention is to provide a liquid crystal display driving circuit capable of reducing the influence of delay caused by parasitic capacitance and improving the quality of a large-sized liquid crystal display using the circuit.
  • the present invention provides a liquid crystal display driving circuit, including: a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines, the plurality of gate lines and data lines defining a plurality of pixel units
  • Each of the pixel units includes: a thin film transistor, a common electrode, a pixel electrode electrically connected to the thin film transistor, a storage capacitor, and a timing switch, wherein the pixel electrode is electrically connected to the thin film transistor, and the common electrode is The pixel electrode forms a liquid crystal capacitor, and the storage capacitor is connected in parallel with the liquid crystal capacitor.
  • the thin film transistor includes: a gate and a source, wherein the gate is electrically connected to the gate line through a timing switch, the film The transistor is electrically connected to the gate driver and the source driver through the gate line and the data line, respectively.
  • the plurality of gate lines and the plurality of data lines are arranged in an intersecting manner, and are electrically connected to the pixel unit through the thin film transistor at an intersection.
  • the gate line includes a rectangular strobe signal, and the thin film transistor is controlled to be turned on or off by the strobe signal.
  • the rectangular strobe signal includes: a plurality of high levels and a plurality of low levels, the number A high level and a plurality of low levels are arranged in disorder, and each high level includes: a first time period and a second time period.
  • the timing switch is closed during the first time period and is disconnected during the second time period.
  • the thin film transistor further includes a drain, and the pixel electrode is electrically connected to the drain.
  • the gate and the drain of the thin film transistor form a parasitic capacitance due to structural characteristics, and the discharge time required when the parasitic capacitance is fully charged and discharged to a voltage equal to the threshold voltage of the thin film transistor is a third period of time.
  • the second time period is equal to the third time period.
  • the timing switch includes: an electric switch and a timer, the electric switch includes first, second, and third pins, and one end of the timer is electrically connected to the gate line, and the other end and the second pin are The first pin is electrically connected to the gate line, and the third pin is electrically connected to the gate of the thin film transistor.
  • the timer triggers the electrical switch to open or close.
  • the present invention also provides a liquid crystal display driving circuit, comprising: a gate driver, a source driver, a plurality of gate lines and a plurality of data lines, the plurality of gate lines and data lines defining a plurality of pixel units, each pixel
  • the unit includes: a thin film transistor, a common electrode, a pixel electrode electrically connected to the thin film transistor, a storage capacitor and a timing switch, wherein the pixel electrode is electrically connected to the thin film transistor, and the common electrode and the pixel electrode form a a liquid crystal capacitor, the storage capacitor is connected in parallel with the liquid crystal capacitor, the thin film transistor includes: a gate and a source, the gate is electrically connected to the gate line through a timing switch, and the thin film transistor passes the The gate line and the data line are electrically connected to the gate driver and the source driver, respectively;
  • the plurality of gate lines and the plurality of data lines are arranged in an intersecting manner, and are electrically connected to the pixel unit through the thin film transistor at an intersection;
  • the gate line includes a rectangular strobe signal, and the thin film transistor is controlled to be turned on or off by the strobe signal.
  • the rectangular strobe signal includes: a plurality of high levels and a plurality of low levels. The plurality of high levels and the plurality of low levels are randomly arranged, and each high level includes: first and second time periods;
  • the timing switch is closed in a first period of time, and is disconnected in a second period of time; wherein the thin film transistor further includes a drain, and the pixel electrode is electrically connected to the drain;
  • the gate and the drain of the thin film transistor form a parasitic capacitance due to structural characteristics, and the discharge time required when the parasitic capacitance is fully charged and discharged to a voltage equal to the threshold voltage of the thin film transistor is the third time.
  • the second time period is equal to the third time period
  • the timing switch includes: an electric switch and a timer, the electric switch includes first, second, and third pins, one end of the timer is electrically connected to the gate line, and the other end is second The first pin is electrically connected to the gate line, and the third pin is electrically connected to the gate of the thin film transistor;
  • timer triggers the electrical switch to open or close.
  • the liquid crystal display driving circuit of the present invention disconnects the gate signal in advance at a high level by connecting a timing switch having a switching function in series with the gate of the thin film transistor. No., and use the parasitic capacitor discharge to complete the drive, thereby reducing the influence of the gate conduction delay caused by the parasitic capacitor discharge voltage, avoiding the abnormal turn-on of the thin film transistor that should be turned off, further improving the thin film transistor.
  • the precision of the control avoids the change of the transmittance and the abnormality of the contrast caused by the abnormal deflection of the liquid crystal molecules, and improves the quality of the large-sized liquid crystal display using the circuit.
  • 1 is a schematic structural view of a driving circuit of a TFT array substrate
  • FIG. 2 is a schematic diagram showing an equivalent connection of a driving circuit of a pixel unit
  • Figure 3 shows the gate drive voltage waveform brought by the parasitic capacitance
  • FIG. 4 is a schematic view showing the circuit structure of a liquid crystal display driving circuit applied to a TFT array substrate according to the present invention
  • FIG. 5 is a schematic diagram showing a connection of a driving circuit in a pixel unit in a liquid crystal display driving circuit of the present invention
  • FIG. 6 is a waveform diagram of a driving voltage on a gate of a thin film transistor in the liquid crystal display driving circuit of the present invention.
  • the present invention provides a liquid crystal display driving circuit, including: a gate driver 10, a source driver 20, a plurality of gate lines G(j), and a plurality of data lines S(i), which are
  • the strip gate line G(j) and the data line S(i) define a plurality of pixel units P(i, j), and each pixel unit P(i, j) comprises: a thin film transistor T(i, j), a a common electrode 40, a pixel electrode 30 electrically connected to the thin film transistor T(i, j), a storage capacitor Cs and a timing switch Z, wherein the pixel electrode 30 is electrically connected to the thin film transistor T(i, j),
  • the common electrode 40 and the pixel electrode 30 form a liquid crystal capacitor Clc
  • the gate driver 10 and the source driver 20 form a driving voltage on the liquid crystal capacitor Clc through the thin film transistor T(i, j) to drive the liquid crystal molecules to rotate and display Graphics.
  • the storage capacitor Cs is connected in parallel with the liquid crystal capacitor Clc, and the thin film transistor T(i, j) comprises: a gate a gate g and a source s, the gate g is electrically connected to the gate line G(j) through a timing switch Z, and the thin film transistor T(i, j) passes through the gate line G(j) and The data line S(i) is electrically connected to the gate driver 10 and the source driver 20, respectively.
  • the plurality of data lines S(1), S(2), S(i) form a data bus structure S
  • the plurality of gate lines G(l), G(2).. ... G(j) constitutes a strobe bus structure G
  • the plurality of gate lines G(j) are arranged in an intersecting manner with the plurality of data lines S(i), and pass through at the intersection
  • the thin film transistor T(i, j) is electrically connected to the pixel unit P(i, j).
  • the gate line G (0 includes a rectangular strobe signal Vg (0), the thin film transistor T (i, j) is controlled to be turned on or off by the strobe signal, and the rectangular strobe signal Vg(j) includes : a plurality of high levels and a plurality of low levels, the thin film transistor T(i, j) is turned on under the plurality of high level control, and is turned off under the plurality of low level control.
  • the plurality of high levels are preferably equal in phase, and the plurality of high levels and the plurality of low levels are randomly arranged.
  • Each high level includes: first, second time periods T1, ⁇ 2,
  • the second period of time ⁇ 2 is determined according to a discharge time of the parasitic capacitance Cgd formed by the gate g and the drain d of the thin film transistor T(i, j) due to structural characteristics, and the first period T1 is determined by the rectangular strobe signal Vg. (j)
  • the high-level duration TO is subtracted from the second period T2.
  • the timing switch Z is closed in the first period T1 and is disconnected in the second period T2.
  • the thin film transistor T(i j) When the rectangular strobe signal Vg(j) on the gate line G(j) is at a low level, the timing switch Z may be closed or may be turned off. In the preferred embodiment, It is preferably in an off state, which reduces the complexity of the control circuit to some extent.
  • the timing switch Z includes: an electric switch K and a timer 50, the electric switch K includes first, second, and third pins 1, 2, 3, the timer 50-end and the gate line G(j) is electrically connected, and the other end is electrically connected to the second pin 2, the first pin 1 is electrically connected to the gate line G(j), and the third pin 3 and the thin film transistor T are electrically connected.
  • the gate g of (i, j) is electrically connected.
  • the timer 50 stores a first time period T1. When the rectangular strobe signal Vg(j) on the gate line G(j) changes from a low level to a high level, the trigger timer 50 starts counting and triggers.
  • the electric switch K is closed, and when the timer 50 counts to the end of the first time period T1, the electric switch K is triggered to be turned off, and remains off to the next gate line G(j).
  • the rectangular strobe signal Vg(j) turns from a low level to a high level, that is, when the rectangular strobe signal Vg(j) on the gate line G(j) changes from a high level to a low level,
  • the timer 50 and the electric switch K do not respond, that is, the timer 50 does not count, and the electric switch K remains in the off state.
  • the thin film transistor T(i, j) further includes a drain d, and the pixel electrode 30 is electrically connected to the drain d.
  • the gate g and the drain d of the thin film transistor T(i, j) form a parasitic capacitance Cgd due to structural characteristics, and the parasitic capacitance Cgd is charged and discharged until the voltage across the two ends is equal to the thin film transistor T(i, j)
  • the discharge time required for the threshold voltage VT is the third time period t.
  • the third time The interval t is equal to the second period T2. Referring to FIGS.
  • the determination of the second/third time period T2/t can be determined according to the following experimental measurements:
  • a high level is continuously added to the data line S(i) ( That is, write operation), and a high level is added to the gate line G(j), after the thin film transistor T , (i, j) is turned on, the gate line G(j) is turned off, and timing is started at the same time, and detection is started.
  • the other pixel unit also measures the time A t required to determine the discharge of the parasitic capacitance Cgd in the thin film transistor to the thin film transistor threshold voltage VT according to the method, and the timer in each pixel unit triggers the electrical switch K, the time of which is turned off. It is determined based on the above measured time value A t .
  • the high-level driving voltage of the gate g on the thin film transistor T(i, j) is turned off in advance by the timer 50 in the timing switch Z, and the gate of the thin film transistor T(i, j) is utilized.
  • the parasitic capacitance Cgd discharge generated by g and drain d due to structural characteristics drives the liquid crystal molecules to deflect, avoiding the phenomenon that the thin film transistor T(i, j) is turned on due to the discharge voltage of the parasitic capacitance Cgd, so that even the liquid crystal display
  • the size is made larger, and the control precision of the thin film transistor T(i, j) can be ensured to ensure the display quality.
  • the liquid crystal display driving circuit of the present invention cuts off the gate signal in advance at a high level by serially connecting a timing switch having a switching function on the gate of the thin film transistor, and performs driving by using parasitic capacitance discharge, thereby reducing
  • the effect of the gate conduction delay caused by the parasitic capacitor discharge voltage avoids the abnormal turn-on of the thin film transistor that is turned off, further improves the precision of the thin film transistor control, and avoids the abnormal deflection of the liquid crystal molecules.
  • the change in transmittance and the phenomenon of abnormal contrast improve the quality of a large-sized liquid crystal display using the circuit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶显示驱动电路，包括：栅极驱动器（10）、源极驱动器（20）、多条选通线G（j）及多条数据线S（i），该多条选通线G（j）和数据线S（i）界定多个像素单元P（i，j）。每个像素单元P（i，j）包括：薄膜晶体管T（i，j）、公共电极（40）、像素电极（30）、存储电容（Cs）及计时开关（Z）。该薄膜晶体管T（i，j）包括：栅极（g）及源极（s），该栅极（g）通过计时开关（Z）电性连接至选通线G（j），该薄膜晶体管T（i，j）通过选通线G（j）及数据线S（i）分别与栅极驱动器（10）及源极驱动器（20）电性连接。通过在薄膜晶体管T（i，j）的栅极（g）上串联一个计时开关（Z），在高电平时提前断开栅极信号，从而减小因寄生电容放电电压带来的栅极（g）导通延时的影响，避免了本该截止的薄膜晶体管T（i，j）却异常导通的情况，进一步提高薄膜晶体管T（i，j）控制的精度，提高使用该驱动电路的大尺寸液晶显示器的质量。

Description

液晶显示驱动电路 技术领域
本发明涉及液晶显示领域， 尤其涉及一种液晶显示驱动电路。 背景技术
随着科学技术的发展以及人们生活质量的提高， 液晶显示器在生活中 已经随处可见， 并且人们对液晶显示器件的要求也越来越高， 开始追求大 的显示画面， 快的响应速度。 但是随着液晶显示器件的增大布线的复杂度 提高， 而且随着 TFT ( Thin Film Transistor、 薄膜场效应晶体管） 阵列基板 驱动像素电极数量的增加线路延时以及因为 TFT寄生电容的存在所带来的 反馈电压对每个像素电极的影响使得精确控制像素电极的难度跟着增加。
请参阅图 1及图 2 , 图 1为基本的 TFT阵列基板的驱动电路结构示意 图， 图中在整个 TFT 阵列基板上分布着像素电极 100 , 每一个像素电极 100至少与一个 TFT漏极 d相连， 每个薄膜晶体管的源极 s至少连接一条 数据线， 数条数据线共同构成了数据总线结构； 每一个薄膜晶体管的栅极 g 至少连接一条选通线， 数条选通线共同构成了选通总线结构； 数据总线 和选通总线通过薄膜晶体管共同控制这些像素电极的数据写入， TFT 阵列 基板上的第 i列第 j行的像素电极 100共同受到选通线 G(j)和数据线 S(i)的 控制， 当对该像素电极 P，(i, j)进行写操作时， 选通线 G(j)处于高电平， 保 证薄膜晶体管 T(i, j)处于导通状态， 此时通过数据线 S(i)上所加的驱动电 压的大小使与像素电极 100相对的附近的液晶分子按照预定的偏转方向偏 转， 从而实现图像的显示。 这样的写操作同时也是按行进行的， 当选通线
G(j)处于高电平时将对第 j行的所有像素电极进行写操作。
请参阅图 2 , 其为每一个像素电极的等效驱动线路连接示意图， 其中 第 i条数据线 S(i)与第 i列第 j行薄膜晶体管 T(i, j)的源极 s相连， 第 j条 选通线 G(j)与第 i列第 j行薄膜晶体管 T(i, j)的栅极 g相连， 第 i列第 j行 薄膜晶体管 T(i, j)的漏极 d与第 i列第 j行像素电极 100相连。 Cgd是栅极 g和漏极 d之间的寄生电容， 该寄生电容 Cgd是在薄膜晶体管因结构特性 所固有的， Clc是处在 TFT基板和 CF ( color filter, 彩色滤光片）基板之间 的液晶层的等效电容， Cs是处在 TFT基板和 Vcom之间的一个补偿电容， 该电容 Cs的存在是为了通过放电保证液晶等效电容 Clc上电压降低时的补 偿， 以适当增大液晶等效电容 Clc区域中的液晶分子的偏转方向保持时 间。 然而随着矩阵分布的 TFT阵列基板中像素电极的行和列数量的增加， 增长的选通线和数据线的会带来驱动线路的延时； 如图 3 所示， 另一方面 薄膜晶体管中的栅极 g和漏极 d之间寄生电容 Cgd的存在将直接影响栅极 电压 Vg对薄膜晶体管的导通和截止的控制， 特别是在离选通总线线路较 远的末端的像素电极附近， 由于选通信号在之前所经过的 n-1 个薄膜晶体 管的寄生电容 Cgd带来的的放电电压的影响以及线路延时影响， 此处不但 响应时间较长， 同时也存在选通电压由高变低时因放电带来的衰减使得薄 膜晶体管 T(n, j)导通时间 η延长 Δη, 也就是说本来应该截止的薄膜晶体 管异常导通， 这样会带来在薄膜晶体管漏极 d相连的像素电极 P(n, j)的驱 动时间延长 ATdx, 导致该像素电极附近的液晶分子偏转异常带来的透射率 差异和对比度异常。 发明内容
本发明的目的在于提供一种液晶显示驱动电路， 能够减小寄生电容带 来的延时影响， 提高使用该电路的大尺寸液晶显示器的质量。
为实现上述目的， 本发明提供一种液晶显示驱动电路， 包括： 栅极驱 动器、 源极驱动器、 多条选通线及多条数据线， 该多条选通线和数据线界 定多个像素单元， 每一像素单元包括： 一薄膜晶体管、 一公共电极、 一与 薄膜晶体管电性连接的像素电极、 一存储电容及一计时开关， 所述像素电 极与薄膜晶体管电性连接， 所述公共电极与像素电极形成一液晶电容， 所 述存储电容与该液晶电容并联连接， 所述薄膜晶体管包括： 一栅极及一源 极， 所述栅极通过计时开关电性连接至选通线， 所述薄膜晶体管通过所述 选通线及数据线分别与栅极驱动器及源极驱动器电性连接。
所述多条选通线与所述多条数据线以交叉方式排列， 并在交叉点处通 过所述薄膜晶体管电性连接至所述像素单元。
所述选通线包括一矩形选通信号， 通过所述选通信号控制所述薄膜晶 体管导通或截止， 该矩形选通信号包括： 数个高电平及数个低电平， 所述 数个高电平及数个低电平错乱排列， 每一高电平包括： 第一、 第二时间 段。
所述计时开关在第一时间段内闭合， 在第二时间段内断开。
所述薄膜晶体管还包括一漏极， 所述像素电极与所述漏极电性连接。 所述薄膜晶体管的栅极与漏极因结构特性形成一寄生电容， 所述寄生 电容充满电后放电至两端电压等于所述薄膜晶体管阔值电压时所需的放电 时间为第三时间段。 所述第二时间段等于所述第三时间段。
所述计时开关包括： 一电开关及一计时器， 所述电开关包括第一、 第 二、 第三引脚， 所述计时器一端与选通线电性连接， 另一端与第二引脚电 性连接， 所述第一引脚与选通线电性连接， 所述第三引脚与薄膜晶体管的 栅极电性连接。
所述计时器触发该电开关断开或闭合。
本发明还提供一种液晶显示驱动电路， 包括： 栅极驱动器、 源极驱动 器、 多条选通线及多条数据线， 该多条选通线和数据线界定多个像素单 元， 每一像素单元包括： 一薄膜晶体管、 一公共电极、 一与薄膜晶体管电 性连接的像素电极、 一存储电容及一计时开关， 所述像素电极与薄膜晶体 管电性连接， 所述公共电极与像素电极形成一液晶电容， 所述存储电容与 该液晶电容并联连接， 所述薄膜晶体管包括： 一栅极及一源极， 所述栅极 通过计时开关电性连接至选通线， 所述薄膜晶体管通过所述选通线及数据 线分别与栅极驱动器及源极驱动器电性连接；
其中， 所述多条选通线与所述多条数据线以交叉方式排列， 并在交叉 点处通过所述薄膜晶体管电性连接至所述像素单元；
其中， 所述选通线包括一矩形选通信号， 通过所述选通信号控制所述 薄膜晶体管导通或截止， 该矩形选通信号包括： 数个高电平及数个低电 平， 所述数个高电平及数个低电平错乱排列， 每一高电平包括： 第一、 第 二时间段；
其中， 所述计时开关在第一时间段内闭合， 在第二时间段内断开； 其中， 所述薄膜晶体管还包括一漏极， 所述像素电极与所述漏极电性 连接；
其中， 所述薄膜晶体管的栅极与漏极因结构特性形成一寄生电容， 所 述寄生电容充满电后放电至两端电压等于所述薄膜晶体管阔值电压时所需 的放电时间为第三时间段；
其中， 所述第二时间段等于所述第三时间段；
其中， 所述计时开关包括： 一电开关及一计时器， 所述电开关包括第 一、 第二、 第三引脚， 所述计时器一端与选通线电性连接， 另一端与第二 引脚电性连接， 所述第一引脚与选通线电性连接， 所述第三引脚与薄膜晶 体管的栅极电性连接；
其中， 所述计时器触发该电开关断开或闭合。
本发明的有益效果： 本发明液晶显示驱动电路， 通过在薄膜晶体管的 栅极上串联一个具有开关功能的计时开关， 在高电平时提前断开栅极信 号， 并利用寄生电容放电完成驱动， 从而减小因寄生电容放电电压带来的 栅极导通延时的影响， 避免了本该截止的薄膜晶体管却异常导通的情况发 生， 进一步提高薄膜晶体管控制的精度， 避免了液晶分子异常偏转带来的 透射率的改变和对比度异常的现象， 提高使用该电路的大尺寸液晶显示器 的质量。
为了能更进一步了解本发明的特征以及技术内容， 请参阅以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1为 TFT阵列基板的驱动电路结构示意图；
图 2为像素单元的驱动电路等效连接示意图；
图 3为寄生电容带来的选通驱动电压波形；
图 4为本发明液晶显示驱动电路应用于 TFT阵列基板的电路结构示意 图；
图 5为本发明液晶显示驱动电路中像素单元中驱动电路连接示意图； 图 6为本发明液晶显示驱动电路中薄膜晶体管的栅极上驱动电压的波 形图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 4至 6, 本发明提供一种液晶显示驱动电路， 包括： 栅极驱 动器 10、 源极驱动器 20、 多条选通线 G(j)及多条数据线 S(i), 该多条选通 线 G(j)和数据线 S(i)界定多个像素单元 P(i, j) , 每一像素单元 P(i, j)包 括： 一薄膜晶体管 T(i, j)、 一公共电极 40、 一与薄膜晶体管 T(i, j)电性 连接的像素电极 30、 一存储电容 Cs及一计时开关 Z, 所述像素电极 30与 薄膜晶体管 T(i, j)电性连接， 所述公共电极 40与像素电极 30形成一液晶 电容 Clc, 所述栅极驱动器 10及源极驱动器 20通过薄膜晶体管 T(i, j)在 液晶电容 Clc上形成驱动电压， 驱动液晶分子旋转， 显示图形。 所述存储 电容 Cs与该液晶电容 Clc并联连接， 所述薄膜晶体管 T(i, j)包括： 一栅 极 g及一源极 s , 所述栅极 g通过计时开关 Z电性连接至选通线 G(j), 所 述薄膜晶体管 T(i, j)通过所述选通线 G(j)及数据线 S(i)分别与栅极驱动器 10及源极驱动器 20电性连接。
所述多条数据线 S(l), S(2) ... ... S(i)构成一数据总线结构 S , 所述多 条栅极线 G(l), G(2) ... ... G(j)构成一选通总线结构 G, 所述多条选通线 G(j) 与所述多条数据线 S(i)以交叉方式排列， 并在交叉点处通过所述薄膜晶体 管 T(i, j)电性连接至所述像素单元 P(i, j)。
所述选通线 G(0包括一矩形选通信号 Vg(0, 通过所述选通信号控制所 述薄膜晶体管 T(i, j)导通或截止， 该矩形选通信号 Vg(j)包括： 数个高电 平及数个低电平， 所述薄膜晶体管 T(i, j)在该数个高电平控制下导通， 在 该数个低电平控制下截止。 在本较佳实施例中， 数个高电平优选为相位大 小相等， 且所述数个高电平及数个低电平错乱排列， 每一高电平包括： 第 一、 第二时间段 Tl、 Τ2, 所述第二时间段 Τ2根据薄膜晶体管 T(i, j)的栅 极 g与漏极 d因结构特性形成的寄生电容 Cgd的放电时间确定， 所述第一 时间段 T1由矩形选通信号 Vg(j)高电平持续的时间 TO减去第二时间段 T2 得到。 所述计时开关 Z在第一时间段 T1 内闭合， 在第二时间段 T2 内断 开。 所述薄膜晶体管 T(i, j)在选通线 G(j)上的矩形选通信号 Vg(j)为低电 平时， 计时开关 Z可闭合， 也可以断开， 在本较佳实施例中， 优选为断开 状态， 在一定程度上降低控制电路的复杂程度。
所述计时开关 Z包括： 一电开关 K及一计时器 50, 所述电开关 K包 括第一、 第二、 第三引脚 1、 2、 3 , 所述计时器 50—端与选通线 G(j)电性 连接， 另一端与第二引脚 2电性连接， 所述第一引脚 1与选通线 G(j)电性 连接， 所述第三引脚 3与薄膜晶体管 T(i, j)的栅极 g电性连接。 所述计时 器 50内储存有第一时间段 T1 , 当选通线 G(j)上的矩形选通信号 Vg(j)由低 电平转为高电平时， 触发计时器 50 开始计时， 并触发所述电开关 K, 使 其闭合， 当计时器 50计时到第一时间段 T1结束时刻， 触发该电开关 K, 使其断开， 并保持断开状态至下一个选通线 G(j)上的矩形选通信号 Vg(j)由 低电平转为高电平的到来， 即当选通线 G(j)上的矩形选通信号 Vg(j)由高电 平转为低电平时， 所述计时器 50及电开关 K均不响应， 即计时器 50不计 时， 电开关 K保持断开状态。
所述薄膜晶体管 T(i, j)还包括一漏极 d, 所述像素电极 30与所述漏极 d电性连接。 所述薄膜晶体管 T(i, j)的栅极 g与漏极 d因结构特性形成一 寄生电容 Cgd, 所述寄生电容 Cgd充电后放电至两端电压等于所述薄膜晶 体管 T(i, j)阔值电压 VT 时所需的放电时间为第三时间段 t。 所述第三时 间段 t等于所述第二时间段 T2。 请参阅图 1 至 3 , 所述第二 /第三时间段 T2/t 的确定可根据以下实验测量确定： 在现有液晶显示驱动中， 在数据线 S(i)上持续加入高电平 （即进行写操作） ， 并在选通线 G(j)上加入高电 平， 薄膜晶体管 T，(i, j)导通后， 断开选通线 G(j), 并同时开始计时， 检测 薄膜晶体管 T，(i, j)的漏极 d上的电压， 当漏极 g上的电压为零时， 则停 止计时， 并记录时间， 所记录到的时间则为该像素单元 P，(i,j)中薄膜晶体 管 T，(i, j)的寄生电容放电至薄膜晶体管 T，(i, j)阔值电压 VT时所需的时 间 A tl , 即第二 /第三时间段确定为 A tl。 其它像素单元亦根据该方法测量 确定其中薄膜晶体管中寄生电容 Cgd的放电至薄膜晶体管阔值电压 VT时 所需的时间 A t, 各像素单元中的计时器触发电开关 K, 其断开的时间根据 上述测量时间值 A t确定。
如图 6 所示， 通过计时开关 Z 中的计时器 50提前断开薄膜晶体管 T(i, j)上栅极 g的高电平驱动电压， 并利用薄膜晶体管 T(i, j)的栅极 g与 漏极 d因结构特性而产生的寄生电容 Cgd放电进行驱动液晶分子偏转， 避 免因寄生电容 Cgd的放电电压带来薄膜晶体管 T(i, j)导通延时的现象， 这 样即使液晶显示器尺寸做得更大， 也可以保证薄膜晶体管 T(i, j)的控制精 度， 保证显示质量。
综上所述， 本发明液晶显示驱动电路， 通过在薄膜晶体管的栅极上串 联一个具有开关功能的计时开关， 在高电平时提前断开栅极信号， 并利用 寄生电容放电完成驱动， 从而减小因寄生电容放电电压带来的栅极导通延 时的影响， 避免了本该截止的薄膜晶体管却异常导通的情况发生， 进一步 提高薄膜晶体管控制的精度， 避免了液晶分子异常偏转带来的透射率的改 变和对比度异常的现象， 提高使用该电路的大尺寸液晶显示器的质量。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

权 利 要 求
1、 一种液晶显示驱动电路， 包括： 栅极驱动器、 源极驱动器、 多条 选通线及多条数据线， 该多条选通线和数据线界定多个像素单元， 每一像 素单元包括： 一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性连接的像 素电极、 一存储电容及一计时开关， 所述像素电极与薄膜晶体管电性连 接， 所述公共电极与像素电极形成一液晶电容， 所述存储电容与该液晶电 容并联连接， 所述薄膜晶体管包括： 一栅极及一源极， 所述栅极通过计时 开关电性连接至选通线， 所述薄膜晶体管通过所述选通线及数据线分别与 栅极驱动器及源极驱动器电性连接。
2、 如权利要求 1 所述的液晶显示驱动电路， 其中， 所述多条选通线 与所述多条数据线以交叉方式排列， 并在交叉点处通过所述薄膜晶体管电 性连接至所述像素单元。
3、 如权利要求 2 所述的液晶显示驱动电路， 其中， 所述选通线包括 一矩形选通信号， 通过所述选通信号控制所述薄膜晶体管导通或截止， 该 矩形选通信号包括： 数个高电平及数个低电平， 所述数个高电平及数个低 电平错乱排列， 每一高电平包括： 第一、 第二时间段。
4、 如权利要求 3 所述的液晶显示驱动电路， 其中， 所述计时开关在 第一时间段内闭合， 在第二时间段内断开。
5、 如权利要求 3 所述的液晶显示驱动电路， 其中， 所述薄膜晶体管 还包括一漏极， 所述像素电极与所述漏极电性连接。
6、 如权利要求 5 所述的液晶显示驱动电路， 其中， 所述薄膜晶体管 的栅极与漏极因结构特性形成一寄生电容， 所述寄生电容充满电后放电至 两端电压等于所述薄膜晶体管阔值电压时所需的放电时间为第三时间段。
7、 如权利要求 6 所述的液晶显示驱动电路， 其中， 所述第二时间段 等于所述第三时间段。
8、 如权利要求 7 所述的液晶显示驱动电路， 其中， 所述计时开关包 括： 一电开关及一计时器， 所述电开关包括第一、 第二、 第三引脚， 所述 计时器一端与选通线电性连接， 另一端与第二引脚电性连接， 所述第一引 脚与选通线电性连接， 所述第三引脚与薄膜晶体管的栅极电性连接。
9、 如权利要求 8 所述的液晶显示驱动电路， 其中， 所述计时器触发 该电开关断开或闭合。
10、 一种液晶显示驱动电路， 包括： 栅极驱动器、 源极驱动器、 多条 选通线及多条数据线， 该多条选通线和数据线界定多个像素单元， 每一像 素单元包括： 一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性连接的像 素电极、 一存储电容及一计时开关， 所述像素电极与薄膜晶体管电性连 接， 所述公共电极与像素电极形成一液晶电容， 所述存储电容与该液晶电 容并联连接， 所述薄膜晶体管包括： 一栅极及一源极， 所述栅极通过计时 开关电性连接至选通线， 所述薄膜晶体管通过所述选通线及数据线分别与 栅极驱动器及源极驱动器电性连接；
其中， 所述多条选通线与所述多条数据线以交叉方式排列， 并在交叉 点处通过所述薄膜晶体管电性连接至所述像素单元；
其中， 所述选通线包括一矩形选通信号， 通过所述选通信号控制所述 薄膜晶体管导通或截止， 该矩形选通信号包括： 数个高电平及数个低电 平， 所述数个高电平及数个低电平错乱排列， 每一高电平包括： 第一、 第 二时间段；
其中， 所述计时开关在第一时间段内闭合， 在第二时间段内断开； 其中， 所述薄膜晶体管还包括一漏极， 所述像素电极与所述漏极电性 连接；
其中， 所述薄膜晶体管的栅极与漏极因结构特性形成一寄生电容， 所 述寄生电容充满电后放电至两端电压等于所述薄膜晶体管阔值电压时所需 的放电时间为第三时间段；
其中， 所述第二时间段等于所述第三时间段；
其中， 所述计时开关包括： 一电开关及一计时器， 所述电开关包括第 一、 第二、 第三引脚， 所述计时器一端与选通线电性连接， 另一端与第二 引脚电性连接， 所述第一引脚与选通线电性连接， 所述第三引脚与薄膜晶 体管的栅极电性连接；
其中， 所述计时器触发该电开关断开或闭合。
PCT/CN2012/084259 2012-10-26 2012-11-08 液晶显示驱动电路 WO2014063390A1 (zh)

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