WO2018232923A1 - 驱动装置及其驱动方法和显示装置 - Google Patents

驱动装置及其驱动方法和显示装置 Download PDF

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Publication number
WO2018232923A1
WO2018232923A1 PCT/CN2017/097603 CN2017097603W WO2018232923A1 WO 2018232923 A1 WO2018232923 A1 WO 2018232923A1 CN 2017097603 W CN2017097603 W CN 2017097603W WO 2018232923 A1 WO2018232923 A1 WO 2018232923A1
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Prior art keywords
gate
driving circuit
signal
duration
lines
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PCT/CN2017/097603
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English (en)
French (fr)
Inventor
郭东胜
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/082,890 priority Critical patent/US20190295488A1/en
Publication of WO2018232923A1 publication Critical patent/WO2018232923A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections

Definitions

  • the present application relates to the field of display technologies, and in particular, to a driving device, a driving method thereof and a display device.
  • the required signal traces are routed by the array layer (Array) in the liquid crystal panel.
  • the traces in the array layer are thinner, so the corresponding impedance values are compared. Big.
  • the gate side of the gate driving circuit that is, the side on which the gate IC is disposed, the longer the Wire On Array (WOA), the larger the corresponding impedance value.
  • the gate voltage (VGH) obtained on the last gate integrated circuit in the gate drive circuit is higher than the gate on the first gate integrated circuit connected to the source driver circuit. The voltage is much lower. The smaller the gate voltage value is, the worse the charging efficiency of the pixel storage capacitor and the liquid crystal capacitor is, which ultimately affects the uniformity of the liquid crystal panel display.
  • an object of the present invention is to provide a driving device, a driving method thereof, and a display device, which improve display uniformity of a liquid crystal panel by adjusting a duty ratio of an enable signal.
  • the driving device includes: a gate driving circuit, the gate driving circuit is connected to a plurality of gate lines, and the gate driving circuit sequentially inputs a gate driving signal to the a gate line of the plurality of gate lines; enabling the driving circuit to provide an enable signal to the gate driving circuit during each scanning period, and controlling the time when the gate driving circuit inputs the gate driving signal Wherein, in the different scanning period, the duration of the enable signal provided by the enable driving circuit is different, and the input time of the gate driving circuit is different from the duration of the enabling signal.
  • the enable driving circuit provides the enable signal of the first duration to the gate driving circuit in a first scanning period; in the second scanning period, the enabling driving The circuit provides the enable signal of the second duration to the gate a driving circuit; the first duration is greater than the second duration.
  • the gate driving circuit inputs the gate driving signal to a first gate line during the first scanning period; and the gate driving during the second scanning period The circuit inputs the gate driving signal to the second gate line; wherein a trace distance between the first gate line and the source driving circuit is smaller than the second gate line and the source driving circuit The distance between the lines.
  • the plurality of gate lines are divided into a first group of lines and a second group of lines, and the enabling driving circuit provides the enabling signal for a first duration, and the gate driving is controlled.
  • the enable driving circuit Inputting an input time to any one of the first set of lines; the enable driving circuit provides the enable signal for a second duration, and controlling the input of the gate drive signal to the second set of lines An input time of any one of the gate lines; wherein the first duration is greater than the second duration.
  • a trace distance between the first set of lines and the source drive circuit is smaller than a trace distance between the second set of lines and the source drive circuit.
  • the enable driving circuit includes a period counting unit and a signal generating unit, the signal generating unit provides a duration of the enabling signal, and the period of the scanning period provided by the period counting unit.
  • a source driving circuit is further connected to each of the data lines, and each of the data lines and each of the gate lines is provided with a pixel storage capacitor and a liquid crystal capacitor, and the different gate lines are disposed.
  • the charging time for connecting the pixel storage capacitor and the liquid crystal capacitor is different.
  • a second object of the present application is a display device, including: a display panel; and a driving device, comprising: a gate driving circuit, the gate driving circuit is connected to a plurality of gate lines, and the gate driving circuit is sequentially Inputting a gate driving signal to one of the plurality of gate lines; enabling a driving circuit, providing an enable signal to the gate driving circuit and controlling the gate driving circuit input in each scanning period The time of the gate driving signal; wherein, in the different scanning period, the duration of the enable signal provided by the enable driving circuit is different, and the gate driving circuit inputs time and the The duration of the signal can be different.
  • the enable driving circuit provides the enable signal of the first duration to the gate driving circuit in a first scanning period; in the second scanning period, the enabling driving The circuit provides the enable signal for the second duration to the gate drive circuit; wherein the first duration is greater than the second duration.
  • the gate driving circuit inputs the gate driving signal to a first gate line during the first scanning period; and the gate driving during the second scanning period The circuit inputs the gate drive signal to the second gate line.
  • a trace distance between the first gate line and the source driving circuit is smaller than a trace distance between the second gate line and the source driving circuit.
  • the plurality of gate lines are divided into a first group of lines and a second group of lines, and the enabling driving circuit provides the enabling signal for a first duration, and the gate driving is controlled.
  • the enable driving circuit Inputting an input time to any one of the first set of lines; the enable driving circuit provides the enable signal for a second duration, and controlling the input of the gate drive signal to the second set of lines An input time of any one of the gate lines; wherein the first duration is greater than the second duration.
  • a trace distance between the first set of lines and the source drive circuit is smaller than a trace distance between the second set of lines and the source drive circuit.
  • the enable driving circuit includes a period counting unit and a signal generating unit, the signal generating unit provides a duration of the enabling signal, and the period of the scanning period provided by the period counting unit.
  • a source driving circuit is further connected to each of the data lines, and each of the data lines and each of the gate lines is provided with a pixel storage capacitor and a liquid crystal capacitor, and the different gate lines are disposed.
  • the charging time for connecting the pixel storage capacitor and the liquid crystal capacitor is different.
  • a further object of the present application is a driving method of a driving device, comprising: providing an enable signal to the gate driving circuit by enabling a driving circuit in each scanning period; in each scanning period, in the After the enable signal, the gate driving signal is input to a gate line through the gate driving circuit; wherein, in the different scanning period, the enabling signal length provided by the enabling driving circuit is different, and at the same time The time at which the gate driving circuit inputs the gate driving signal is different from the duration of the enabling signal.
  • the application can not significantly change the premise of the existing production process, maintain the original process requirements and product costs, and solve the pixel storage capacitance and the liquid crystal capacitor charging unevenness of the display panel caused by the difference of the array trace impedance of the panel, and improve the display panel. Show uniformity.
  • Figure 1a is a schematic view of the structure of an exemplary driving device.
  • Figure 1b is a schematic diagram of the driving waveforms of an exemplary driving device.
  • FIG. 2a is a block diagram showing the application of an embodiment to a driving device in accordance with the method of the present application.
  • FIG. 2b is a schematic diagram showing the structure of a pixel circuit applied to a display panel according to the method of the present application.
  • 2c is a schematic diagram showing driving waveforms applied to a driving device according to a method of the present application.
  • FIG. 3a is a schematic diagram showing the architecture of a driving device applied to a display panel according to the method of the present application.
  • 3b is a waveform diagram showing an embodiment applied to a driving device in accordance with the method of the present application.
  • FIG. 4 is a block diagram showing the application of an embodiment to a driving device in accordance with the method of the present application.
  • FIG. 5 is a schematic diagram showing the structure of an embodiment applied to a display device according to the method of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • the liquid crystal panel of the present application may include a first substrate and a second substrate and a liquid crystal layer formed between the two substrates.
  • the first substrate and the second substrate may be, for example, a Thin Film Transistor (TFT) substrate, and color filter. Layer (Color Filter, CF) substrate.
  • TFT Thin Film Transistor
  • CF Color Filter
  • the active array switch and the color filter layer of the present application may also be formed on the same substrate.
  • the liquid crystal panel of the present application may be a curved display panel.
  • the display driving circuit includes a timing controller 110, a source driving circuit 120, and a gate driving circuit 130.
  • the timing controller 110 typically includes the following signals: a frame start signal (STV), a gate line clock signal (CPV), an output enable signal (OE, Output Enable), a data read in and output signal (TP), and a pixel polarity control signal. (POL), Data Enable Signal (DE, Data Enable).
  • the signals STV, CPV, and OE jointly control and drive the gate lines of the array substrate 140 of the display device; wherein the rising edge of the CPV signal triggers driving the respective gate lines, and sequentially triggers the gate line driving signals of the respective gate lines through the shift register;
  • the OE signal is used to separate the gate line drive signals of adjacent rows to avoid crosstalk.
  • the gate driving circuit 130 triggers according to the gate line clock signal
  • the gate line driving signal separates the gate line driving signals of the adjacent rows according to the output enable signal, and then outputs the separated gate line driving signals to the gate lines.
  • the corresponding gate line driving signal is triggered to a high level; at the rising edge of OE, the corresponding gate line driving signal (Gate1) is pulled low to a low level. Flat, the gate line drive signal (Gate1) is turned off. In the next scan period, at the rising edge of OE, the corresponding gate line drive signal (Gate2) is pulled low to the low level, and the gate line drive signal (Gate2) is turned off. It is known that in the high level region of the OE, the gate line driving signal of the adjacent row is low level and is shielded to form an interval between the plurality of gate line driving signals, in which the corresponding gate is forced Closed, avoiding crosstalk when adjacent gates are driven.
  • the gate driving circuit 130 includes a plurality of gate integrated circuits. The farther away from the gate integrated circuit of the source driving circuit 120, the longer the required trace, the higher the relative trace impedance, and the obtained gate voltage ( VGH) is relatively low.
  • FIG. 2a is a schematic diagram showing the structure of a driving device applied to a display panel according to the method of the present application
  • FIG. 2b is a schematic diagram showing the structure of a pixel circuit applied to a display panel according to the method of the present application
  • FIG. A schematic diagram of a driving waveform applied to a driving device according to the method of the present application is shown. Referring to FIG.
  • the driving device includes: a gate driving circuit 230 connected to a plurality of gate lines, wherein the gate driving circuit 230 sequentially inputs a gate driving signal to One of the plurality of gate lines; the enable driving circuit 210, in each scan period, provides an enable signal (OE) to the gate drive circuit 230, and controls the gate drive circuit 230 input The timing of the gate driving signal; wherein, in the different scanning period, the enabling driving circuit 210 provides the duration of the enable signal (OE) to be different, and simultaneously inputs the gate driving circuit 210 The time of the gate drive signal is different from the duration of the enable signal.
  • FIG. 2b a schematic diagram of a pixel circuit architecture is shown in FIG. 2b, and a waveform diagram of the driving device is shown in FIG. 2c.
  • FIG. 2a the trace distance between the first gate line 231 and the source driver circuit 220 connected to the gate driving circuit 230 is smaller than the distance between the second gate line 232 and the source driving circuit 220.
  • the line distance, that is, the first gate line 231 as a whole is closer to the source drive circuit 220 than the second gate line 232.
  • each of the data lines and each of the gate lines is disposed with a pixel storage capacitor and a liquid crystal capacitor, and the different gate lines are connected to the pixel storage capacitor and the liquid crystal capacitor.
  • the charging time is different.
  • the enable driving circuit 210 in the first scanning period (T1), provides the enable signal (OE) of the first duration (H1) to the gate driving circuit 230. After the enable signal (OE) falls, the gate driving circuit 230 inputs the gate driving signal (Gate1) to the first gate line 231. In the second scanning period (T2), the enable driving circuit 210 supplies the enable signal (OE) of the second duration (H2) to the gate driving circuit 230. After the enable signal (OE) drops, The gate driving circuit 230 inputs the gate driving signal (Gate2) to the second gate line 232.
  • the first duration (H1) is greater than the second duration (H2).
  • the time at which the gate line driving signal (Gate1) is input to the first gate line 231 is opposite to the time point when the gate line driving signal (Gate2) is input to the second gate line 232. Later; the duration of the gate line drive signal (Gate1) is also less than the duration of the gate line drive signal (Gate2).
  • the pixel storage capacitor 281a and the liquid crystal capacitor 281b connected between the data line 291 and the first gate line 231, and the pixel storage capacitor 282a and the liquid crystal connected between the data line 291 and the second gate line 232 The charging time of the capacitor 282b is different. Moreover, the charging time of the pixel storage capacitor 282a and the liquid crystal capacitor 282b connected by the second gate line 232 is relatively short.
  • FIG. 3a is a schematic diagram showing the architecture of a driving device applied to a display panel according to the method of the present application.
  • the gate driving circuit includes a plurality of gate integrated circuits (Gate ICs) 239, and each gate integrated circuit 239 is connected with a set of gate lines.
  • Gate ICs gate integrated circuits
  • two gate integrated circuits 239 are taken as an example, and each of the gate integrated circuits 239 is connected to the first group line 231n and the second group line 232n.
  • the waveform of the driving device is shown in Figure 3b, please cooperate with Figure 3a to facilitate understanding.
  • the trace distance between the first set of lines 231n and the source drive circuit 220 connected to the gate drive circuit 230 is smaller than the trace distance between the second set of lines 232n and the source drive circuit 220. That is, the first set of lines 231n are generally closer to the source drive circuit 220 than the second set of lines 232n.
  • the enable driving circuit 210 provides the enable signal (OE) of the first duration (H1), and controls the gate driving signal (Gate1) to be input to any one of the first group lines 231n. The input time of the gate line.
  • the enable driving circuit 210 provides the enable signal (OE) of the second duration (H2), and controls the input time of the gate driving signal (Gate2) input to any one of the second group lines 232n.
  • the first duration (H1) is greater than the second duration (H2).
  • the gate line driving signal (Gate1) is supplied to the input time point of any one of the first group lines 231n, and is input to the second gate line than the gate line driving signal (Gate2).
  • the time point of 232 is relatively late; the duration of the gate line driving signal (Gate1) is also smaller than the duration of the gate line driving signal (Gate2).
  • the pixel storage capacitor and the liquid crystal capacitor connected between the data line and the first group line 231n are different from the charging time of the pixel storage capacitor and the liquid crystal capacitor connected between the data line and the second group line 232n. Moreover, the charging time of the pixel storage capacitor and the liquid crystal capacitor connected by the second group of lines 232n is relatively short.
  • the enable driving circuit 210 includes a period counting unit 211 and a signal generating unit 212, the signal generating unit 212 provides the duration of the enable signal OE, and the number of scanning cycles provided by the period counting unit 211 .
  • the signal generating unit 212 provides the duration of the enable signal OE, and the number of scanning cycles provided by the period counting unit 211 .
  • FIG. 5 is a schematic diagram showing the structure of an embodiment applied to a display device according to the method of the present application.
  • a display device 200 of the present application includes: a display panel 250; and further includes any one of the foregoing embodiments.
  • the display panel 250 can be an active switch array substrate, that is, the array substrate 240.
  • a driving method of a driving apparatus of the present application includes: providing an enable signal OE to the gate driving circuit 230 by enabling the driving circuit 210 in each scanning period; a gate drive signal is input to a gate line through the gate drive circuit 230 after the enable signal OE in one scan period; wherein, in the different scan period, the enable drive circuit 210 provides the The duration of the enable signal (OE) is different, and the time during which the gate drive circuit 230 inputs the gate drive signal is different from the duration of the enable signal OE.
  • the application can not significantly change the premise of the existing production process, maintain the original process requirements and product cost, adjust the duty ratio of the enable signal according to the distance between the output channel of the gate drive circuit and the source drive circuit, so that the panels are each
  • the final charging effect of the pixel storage capacitor and the liquid crystal capacitor reaches an equilibrium value.
  • the problem that the pixel storage capacitance of the display panel and the liquid crystal capacitor are not uniformly charged due to factors such as differences in the trace impedance of the array are solved, and the uniformity of display of the display panel is improved. Since there is no need to adjust the production process, there is no special process requirement and difficulty, so it will not increase the cost and is highly competitive in the market. Moreover, without increasing the array trace area, it is suitable for a variety of display panel designs today, and of course also for the narrow frame design of the panel, in line with market and technology trends.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

一种驱动装置及其驱动方法和显示装置。驱动装置包括：栅极驱动电路230与每一条栅线相连，栅极驱动电路230与多条栅线连接，栅极驱动电路230依序输入栅极驱动信号Gate给多条栅线中的一条栅线；使能驱动电路210，在不同扫描周期内，向栅极驱动电路230提供不同时长的使能信号OE，管控栅极驱动电路230输入栅极驱动信号Gate至栅线的输入时间与时长。

Description

驱动装置及其驱动方法和显示装置 技术领域
本申请涉及一种显示技术领域，特别涉及一种驱动装置及其驱动方法和显示装置。
背景技术
现行液晶显示面板的栅极驱动电路(Gate Driver，Gate IC)，其所需信号走线都是由液晶面板中阵列层(Array)进行布线传输，阵列层中走线较细所以相应阻抗值较大。
而且栅极驱动电路的栅极侧，也就是配置栅极集成电路(Gate IC)的一侧，其阵列走线(Wire On Array，WOA)越长，相应的阻抗值就越大。再加上电阻分压原理，栅极驱动电路中最后一颗栅极集成电路上所得到的栅极电压(VGH)，会比连接源极驱动电路的第一颗栅极集成电路上的栅极电压低很多。栅极电压值越小，像素储存电容和液晶电容的充电效率越差，最终影响到液晶面板显示均齐性。
为解决此问题，有些厂商采用铜制程，改变阵列走线材质，或是增加阵列走线面积，藉以降低栅极驱动电路的走线电阻，缩小各栅极电压的差值。但铜制程的制作环境要求与制作难度相对较高，也不容易降低成本。增加阵列走面积则是难以满足面板窄边框设计的需求。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种驱动装置及其驱动方法和显示装置，通过调整使能信号的占空比，改善液晶面板显示均齐性。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种驱动装置，所述驱动装置包括：栅极驱动电路，所述栅极驱动电路与多条栅线连接，所述栅极驱动电路依序输入栅极驱动信号给所述多条栅线中的一条栅线；使能驱动电路，在每一个扫描周期内，提供使能信号给所述栅极驱动电路，管控所述栅极驱动电路输入所述栅极驱动信号的时间；其中，在相异扫描周期中，所述使能驱动电路提供的所述使能信号时长为相异，同时使所述栅极驱动电路输入时间与所述使能信号时长为相异。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，在第一扫描周期，所述使能驱动电路提供第一时长的所述使能信号给所述栅极驱动电路；在第二扫描周期，所述使能驱动电路提供第二时长的所述使能信号给所述栅极 驱动电路；所述第一时长大于所述第二时长。
在本申请的一实施例中，在所述第一扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第一条栅线；在所述第二扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第二条栅线；其中，所述第一条栅线与源极驱动电路之间的走线距离小于所述第二条栅线与所述源极驱动电路之间的走线距离。
在本申请的一实施例中，所述多条栅线区分为第一组线与第二组线，所述使能驱动电路提供第一时长的所述使能信号，管控所述栅极驱动信号输入至所述第一组线中任一条栅线的输入时间；所述使能驱动电路提供第二时长的所述使能信号，管控所述栅极驱动信号输入至所述第二组线中任一条栅线的输入时间；其中，所述第一时长大于所述第二时长。
在本申请的一实施例中，所述第一组线与源极驱动电路之间的走线距离小于所述第二组线与所述源极驱动电路之间的走线距离。
在本申请的一实施例中，所述使能驱动电路包括周期计数单元与信号产生单元，所述信号产生单元提供所述使能信号的时长，所述周期计数单元提供的扫描周期数。
在本申请的一实施例中，更包括源极驱动电路，与每一条数据线相连，每一条数据线与每一条栅线交集点设置有像素储存电容和液晶电容，相异的所述栅线连接所述像素储存电容和所述液晶电容的充电时间为相异。
在本申请的一实施例中，走线距离越接近所述源极驱动电路的所述栅线，其连接所述像素储存电容和所述液晶电容的充电时间越短。
本申请的次一目的为一种显示装置，其包括：显示面板；及驱动装置，包括：栅极驱动电路，所述栅极驱动电路与多条栅线连接，所述栅极驱动电路依序输入栅极驱动信号给所述多条栅线中的一条栅线；使能驱动电路，在每一个扫描周期内，提供使能信号给所述栅极驱动电路，管控所述栅极驱动电路输入所述栅极驱动信号的时间；其中，在相异扫描周期中，所述使能驱动电路提供的所述使能信号时长为相异，同时使所述栅极驱动电路输入时间与所述使能信号时长为相异。
在本申请的一实施例中，在第一扫描周期，所述使能驱动电路提供第一时长的所述使能信号给所述栅极驱动电路；在第二扫描周期，所述使能驱动电路提供第二时长的所述使能信号给所述栅极驱动电路；其中，所述第一时长大于所述第二时长。
在本申请的一实施例中，在所述第一扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第一条栅线；在所述第二扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第二条栅线。
在本申请的一实施例中，所述第一条栅线与源极驱动电路之间的走线距离小于所述第二条栅线与所述源极驱动电路之间的走线距离。
在本申请的一实施例中，所述多条栅线区分为第一组线与第二组线，所述使能驱动电路提供第一时长的所述使能信号，管控所述栅极驱动信号输入至所述第一组线中任一条栅线的输入时间；所述使能驱动电路提供第二时长的所述使能信号，管控所述栅极驱动信号输入至所述第二组线中任一条栅线的输入时间；其中，所述第一时长大于所述第二时长。
在本申请的一实施例中，所述第一组线与源极驱动电路之间的走线距离小于所述第二组线与所述源极驱动电路之间的走线距离。
在本申请的一实施例中，所述使能驱动电路包括周期计数单元与信号产生单元，所述信号产生单元提供所述使能信号的时长，所述周期计数单元提供的扫描周期数。
在本申请的一实施例中，更包括源极驱动电路，与每一条数据线相连，每一条数据线与每一条栅线交集点设置有像素储存电容和液晶电容，相异的所述栅线连接所述像素储存电容和所述液晶电容的充电时间为相异。
在本申请的一实施例中，走线距离越接近所述源极驱动电路的所述栅线，其连接所述像素储存电容和所述液晶电容的充电时间越短。
本申请的又一目的为一种驱动装置的驱动方法，包括：在每一个扫描周期内，通过使能驱动电路向所述栅极驱动电路提供使能信号；在每一个扫描周期内，在所述使能信号之后，通过栅极驱动电路向一条栅线输入栅极驱动信号；其中，在相异扫描周期中，所述使能驱动电路提供的所述使能信号时长为相异，同时使所述栅极驱动电路输入所述栅极驱动信号的时间与所述使能信号的时长为相异。
本申请可以不大幅改变现有生产流程的前提，维持原制程需求和产品成本，解决了面板因阵列走线阻抗差异问题导致的显示面板的像素储存电容和液晶电容充电不均，改善显示面板的显示均齐度。
附图说明
图1a为范例性的驱动装置的结构示意图。
图1b为范例性的驱动装置的驱动波形示意图。
图2a为显示依据本申请的方法，一实施例应用于驱动装置的架构示意图。
图2b为显示依据本申请的方法，一实施例应用于显示面板的像素电路架构示意图。
图2c为显示依据本申请的方法，一实施例应用于驱动装置的驱动波形示意图。
图3a为显示依据本申请的方法，一实施例应用于显示面板的驱动装置架构示意图。
图3b为显示依据本申请的方法，一实施例应用于驱动装置的波形示意图。
图4为显示依据本申请的方法，一实施例应用于驱动装置的架构示意图。
图5为显示依据本申请的方法，一实施例应用于显示装置的架构示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种驱动装置及其驱动方法和显示装置，其具体实施方式、结构、特征及其功效，详细说明如后。
本申请的液晶面板可包括第一基板及第二基板与形成于两基板之间的液晶层，第一基板及第二基板可例如为主动阵列开关(Thin Film Transistor，TFT)基板、彩色滤光层(Color Filter，CF)基板。然不限于此，在一些实施例中，本申请的主动阵列开关及彩色滤光层亦可形成于同一基板上。
在一些实施例中，本申请的液晶面板可为曲面型显示面板。
图1a为范例性的驱动装置的结构示意图、图1b为范例性的驱动装置的驱动波形示意图。如图1a所示，显示驱动电路包括：时序控制器110、源极驱动电路120与栅极驱动电路130。时序控制器110通常包含以下信号：帧开始信号(STV)，栅线时钟信号(CPV)，输出使能信号(OE，Output Enable)，数据读入与输出信号(TP)，像素极性控制信号(POL)，数据使能信号(DE，Data Enable)。其中信号STV、CPV、OE联合控制并驱动显示装置的阵列基板140的栅线；其中CPV信号的上升沿触发驱动各个栅线，通过移位寄存器，依次触发各条栅线的栅线驱动信号；OE信号用于分隔相邻行的栅线驱动信号，以避免串扰的发生。所述栅极驱动电路130根据所述栅线时钟信号触发所 述栅线驱动信号，根据输出使能信号分隔相邻行的栅线驱动信号，然后输出经过分隔的所述栅线驱动信号至栅线。
如图1b所示，在栅线时钟信号的上升沿，触发相应所述栅线驱动信号至高电平；在OE的上升沿，把相应的所述栅线驱动信号(Gate1)拉低至低电平，关闭所述栅线驱动信号(Gate1)。在次一扫描周期，在OE的上升沿，把相应的所述栅线驱动信号(Gate2)拉低至低电平，关闭所述栅线驱动信号(Gate2)。得知，在OE的高电平区域，相邻行的栅线驱动信号为低电平，被屏蔽，形成了多个栅线驱动信号间的间隔，在该间隔区域内，相应栅极被强制关闭，避免了相邻栅极在驱动时的串扰现象。
其中，栅极驱动电路130包括多个栅极集成电路，越远离源极驱动电路120的栅极集成电路，其需求的走线越长，相对走线阻抗越高，所获取得栅极电压(VGH)相对较低。
图2a为显示依据本申请的方法，一实施例应用于显示面板的驱动装置的架构示意图；图2b为显示依据本申请的方法，一实施例应用于显示面板的像素电路架构示意图；图2c为显示依据本申请的方法，一实施例应用于驱动装置的驱动波形示意图。请参照图2a，在本申请一实施例中，所述一种驱动装置，包括：栅极驱动电路230，与多条栅线连接，所述栅极驱动电路230依序输入栅极驱动信号给所述多条栅线中的一条栅线；使能驱动电路210，在每一个扫描周期内，提供使能信号(OE)给所述栅极驱动电路230，管控所述栅极驱动电路230输入所述栅极驱动信号的时间；其中，在相异扫描周期中，所述使能驱动电路210提供所述使能信号(OE)的时长为相异，同时使所述栅极驱动电路210输入所述栅极驱动信号的时间与所述使能信号的时长为相异。
在一些实施例中，像素电路架构示意图如图2b所示，驱动装置的波形示意图如图2c所示，请配合图2a以利于理解。如图2a所绘示，栅极驱动电路230所连接的第一条栅线231与源极驱动电路220之间的走线距离小于第二条栅线232与源极驱动电路220之间的走线距离，即第一条栅线231整体上是比第二条栅线232更相对接近源极驱动电路220。
在一些实施例中，在阵列基板240上，每一条数据线与每一条栅线交集点设置有像素储存电容和液晶电容，相异的所述栅线连接所述像素储存电容和所述液晶电容的充电时间为相异。
在一些实施例中，走线距离越接近所述源极驱动电路的所述栅线，其连接所述像素储存电容和所述液晶电容的充电时间越短。
如图2b及图2c绘示，在第一扫描周期(T1)，所述使能驱动电路210提供第一时长(H1)的所述使能信号(OE)给所述栅极驱动电路230。在所述使能信号(OE)下降后，所述栅极驱动电路230输入所述栅极驱动信号(Gate1)于第一条栅线231。在第二扫描周期(T2)，所述使能驱动电路210提供第二时长(H2)的所述使能信号(OE)给所述栅极驱动电路230。在所述使能信号(OE)下降后，所 述栅极驱动电路230输入所述栅极驱动信号(Gate2)于第二条栅线232。其中，所述第一时长(H1)大于所述第二时长(H2)。如此，相同时长的扫描周期，所述栅线驱动信号(Gate1)输入至第一条栅线231的时间点，会比栅线驱动信号(Gate2)输入至第二条栅线232的时间点相对较晚；栅线驱动信号(Gate1)的时长也会小于栅线驱动信号(Gate2)的时长。
因此，数据线291与第一条栅线231之间连接的像素储存电容281a和液晶电容281b，与数据线291与第二条栅线232之间连接的所述像素储存电容282a和所述液晶电容282b的充电时间为相异。而且第二条栅线232连接的所述像素储存电容282a和所述液晶电容282b的充电时间相对较短。
图3a为显示依据本申请的方法，一实施例应用于显示面板的驱动装置的架构示意图。请参照图3a，所述栅极驱动电路包括多个栅极集成电路(Gate IC)239，每一栅极集成电路239连接有一组栅线。此处暂以两个栅极集成电路239为例，每一栅极集成电路239各别连接第一组线231n与第二组线232n。
在一些实施例中，驱动装置的波形示意图如图3b所示，请配合图3a以利于理解。如图3a所绘示，栅极驱动电路230所连接的第一组线231n与源极驱动电路220之间的走线距离小于第二组线232n与源极驱动电路220之间的走线距离，即第一组线231n整体上是比第二组线232n更相对接近源极驱动电路220。如图3b绘示，所述使能驱动电路210提供第一时长(H1)的所述使能信号(OE)，管控所述栅极驱动信号(Gate1)输入至第一组线231n中任一条栅线的输入时间。所述使能驱动电路210提供第二时长(H2)的所述使能信号(OE)，管控所述栅极驱动信号(Gate2)输入至第二组线232n中任一条栅线的输入时间。所述第一时长(H1)大于所述第二时长(H2)。如此，相同时长的扫描周期，所述栅线驱动信号(Gate1)提供给第一组线231n中任一条栅线的输入时间点，会比栅线驱动信号(Gate2)输入至第二条栅线232的时间点相对较晚；栅线驱动信号(Gate1)的时长也会小于栅线驱动信号(Gate2)的时长。
因此，数据线与第一组线231n之间连接的像素储存电容和液晶电容，与数据线与第二组线232n之间连接的所述像素储存电容和所述液晶电容的充电时间为相异。而且第二组线232n连接的所述像素储存电容和所述液晶电容的充电时间相对较短。
图4为显示依据本申请的方法，一实施例应用于显示面板的驱动装置的架构示意图。请参照图4，所述使能驱动电路210包括周期计数单元211与信号产生单元212，所述信号产生单元212提供所述使能信号OE的时长，所述周期计数单元211提供的扫描周期数。原则上，配合前述，扫描周期对应的栅线，其走线距离越接近源极驱动电路220者，控管此栅线的使能信号OE的时长就越长。
图5为显示依据本申请的方法，一实施例应用于显示装置的架构示意图。在本申请一实施例中， 本申请的一种显示装置200，其包括：显示面板250；还包括前述各实施例中的任一种驱动电路。其中，所述显示面板250可为主动开关阵列基板，即前述阵列基板240。
在本申请一实施例中，本申请的一种驱动装置的驱动方法，包括：在每一个扫描周期内，通过使能驱动电路210向所述栅极驱动电路230提供使能信号OE；在每一个扫描周期内，在所述使能信号OE之后，通过栅极驱动电路230向一条栅线输入栅极驱动信号；其中，在相异扫描周期中，所述使能驱动电路210提供的所述使能信号(OE)的时长为相异，同时使所述栅极驱动电路230输入所述栅极驱动信号的时间与所述使能信号OE时长为相异。
本申请可以不大幅改变现有生产流程的前提，维持原制程需求和产品成本，根据栅极驱动电路的输出信道与源极驱动电路的远近距离，调整使能信号的占空比，使得面板各像素储存电容和液晶电容最终充电效果达到一个平衡值。解决了面板因阵列走线阻抗差异等因素而导致的显示面板的像素储存电容和液晶电容充电不均的问题，从改善显示面板的显示均齐度。因不需调整生产流程，故没有特别的制程要求与难度，故不会提升成本，极具备市场竞争性。而且，不用增加阵列走线面积，适用于现今多种的显示面板设计，当然也适用于面板窄边框设计，符合市场及技术趋势。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以较佳实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种驱动装置，包括：
    栅极驱动电路，所述栅极驱动电路与多条栅线连接，所述栅极驱动电路依序输入栅极驱动信号给所述多条栅线中的一条栅线；
    使能驱动电路，在每一个扫描周期内，提供使能信号给所述栅极驱动电路，管控所述栅极驱动电路输入所述栅极驱动信号的时间；
    其中，在相异扫描周期中，所述使能驱动电路提供的所述使能信号时长为相异，同时使所述栅极驱动电路输入所述栅极驱动信号时间与所述使能信号时长为相异。
  2. 如权利要求1所述的驱动装置，其中，在第一扫描周期，所述使能驱动电路提供第一时长的所述使能信号给所述栅极驱动电路；在第二扫描周期，所述使能驱动电路提供第二时长的所述使能信号给所述栅极驱动电路。
  3. 如权利要求2所述的驱动装置，其中，所述第一时长大于所述第二时长。
  4. 如权利要求2所述的驱动装置，其中，在所述第一扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第一条栅线；在所述第二扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第二条栅线。
  5. 如权利要求4所述的驱动装置，其中，所述第一条栅线与源极驱动电路之间的走线距离小于所述第二条栅线与所述源极驱动电路之间的走线距离。
  6. 如权利要求2所述的驱动装置，其中，所述多条栅线区分为第一组线与第二组线，所述使能驱动电路提供第一时长的所述使能信号，管控所述栅极驱动信号输入至所述第一组线中任一条栅线的输入时间；所述使能驱动电路提供第二时长的所述使能信号，管控所述栅极驱动信号输入至所述第二组线中任一条栅线的输入时间；其中，所述第一时长大于所述第二时长。
  7. 如权利要求6所述的驱动装置，其中，所述第一组线与源极驱动电路之间的走线距离小于所述第二组线与所述源极驱动电路之间的走线距离。
  8. 如权利要求1所述的驱动装置，其中，所述使能驱动电路包括周期计数单元与信号产生单元，所述信号产生单元提供所述使能信号的时长，所述周期计数单元提供的扫描周期数。
  9. 如权利要求1所述的驱动装置，其中，更包括源极驱动电路，与每一条数据线相连，每一条数据线与每一条栅线交集点设置有像素储存电容和液晶电容，相异的所述栅线连接所述像素储存电容和所述液晶电容的充电时间为相异。
  10. 如权利要求9所述的驱动装置，其中，走线距离越接近所述源极驱动电路的所述栅线，其连接所述像素储存电容和所述液晶电容的充电时间越短。
  11. 一种显示装置，包括：
    显示面板；及
    驱动装置，包括：
    栅极驱动电路，所述栅极驱动电路与多条栅线连接，所述栅极驱动电路依序输入栅极驱动信号给所述多条栅线中的一条栅线；
    使能驱动电路，在每一个扫描周期内，提供使能信号给所述栅极驱动电路，管控所述栅极驱动电路输入所述栅极驱动信号的时间；
    其中，在相异扫描周期中，所述使能驱动电路提供的所述使能信号时长为相异，同时使所述栅极驱动电路输入所述栅极驱动信号时间与所述使能信号时长为相异。
  12. 如权利要求11所述的显示装置，其中，在第一扫描周期，所述使能驱动电路提供第一时长的所述使能信号给所述栅极驱动电路；在第二扫描周期，所述使能驱动电路提供第二时长的所述使能信号给所述栅极驱动电路；其中，所述第一时长大于所述第二时长。
  13. 如权利要求12所述的显示装置，其中，在所述第一扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第一条栅线；在所述第二扫描周期，所述栅极驱动电路输入所述栅极驱动信号于第二条栅线。
  14. 如权利要求13所述的显示装置，其中，所述第一条栅线与源极驱动电路之间的走线距离小于所述第二条栅线与所述源极驱动电路之间的走线距离。
  15. 如权利要求12所述的显示装置，其中，所述多条栅线区分为第一组线与第二组线，所述使能驱动电路提供第一时长的所述使能信号，管控所述栅极驱动信号输入至所述第一组线中任一条栅线的输入时间；所述使能驱动电路提供第二时长的所述使能信号，管控所述栅极驱动信号输入至所述第二组线中任一条栅线的输入时间；其中，所述第一时长大于所述第二时长。
  16. 如权利要求15所述的显示装置，其中，所述第一组线与源极驱动电路之间的走线距离小于所述第二组线与所述源极驱动电路之间的走线距离。
  17. 如权利要求11所述的显示装置，其中，所述使能驱动电路包括周期计数单元与信号产生单元，所述信号产生单元提供所述使能信号的时长，所述周期计数单元提供的扫描周期数。
  18. 如权利要求11所述的显示装置，其中，更包括源极驱动电路，与每一条数据线相连，每一条数据线与每一条栅线交集点设置有像素储存电容和液晶电容，相异的所述栅线连接所述像素储存电容和所述液晶电容的充电时间为相异。
  19. 如权利要求18所述的显示装置，其中，走线距离越接近所述源极驱动电路的所述栅线，其连接所述像素储存电容和所述液晶电容的充电时间越短。
  20. 一种驱动装置的驱动方法，其中，包括：
    在每一个扫描周期内，通过使能驱动电路向所述栅极驱动电路提供使能信号；
    在每一个扫描周期内，于所述使能信号之后，通过栅极驱动电路向一条栅线输入栅极驱动信号；
    其中，在相异扫描周期中，所述使能驱动电路提供的所述使能信号时长为相异，同时使所述栅极驱动电路输入所述栅极驱动信号的时间与所述使能信号的时长为相异。
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