WO2014061204A1 - Dispositif à semi-conducteurs et procédé pour fabriquer celui-ci - Google Patents

Dispositif à semi-conducteurs et procédé pour fabriquer celui-ci Download PDF

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Publication number
WO2014061204A1
WO2014061204A1 PCT/JP2013/005665 JP2013005665W WO2014061204A1 WO 2014061204 A1 WO2014061204 A1 WO 2014061204A1 JP 2013005665 W JP2013005665 W JP 2013005665W WO 2014061204 A1 WO2014061204 A1 WO 2014061204A1
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Prior art keywords
semiconductor chip
lead
conductive adhesive
semiconductor device
convex portions
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PCT/JP2013/005665
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English (en)
Japanese (ja)
Inventor
雄一 近藤
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株式会社デンソー
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Publication of WO2014061204A1 publication Critical patent/WO2014061204A1/fr

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Definitions

  • the present disclosure relates to a semiconductor device in which a semiconductor chip and a lead are mechanically and electrically connected by a conductive adhesive and a method for manufacturing the same.
  • Patent Document 1 a conductive adhesive in which a metal powder, an adhesive resin, and a spacer made of resin beads are blended has been proposed.
  • the conductive adhesive is used to electrically connect the main member on which the electronic circuit is formed and the support member on which the wiring is formed.
  • the thickness of the conductive adhesive is set to a predetermined thickness by the spacer blended in the conductive adhesive.
  • the conductive adhesive has fluidity, the number of spacers arranged in the direction in which the main member and the support member face each other varies. In extreme terms, there are regions where spacers are stacked and regions where spacers are not stacked. As a result, the film thickness of the conductive adhesive may vary.
  • the thickness of the conductive adhesive varies, when thermal stress is generated due to the difference in coefficient of linear expansion between the main member and the support member and the conductive adhesive, the thermal stress locally increases. A site occurs between them. In other words, stress concentration occurs. For this reason, the conductive adhesive is peeled off from the main member and the support member, and mechanical and electrical connection failure occurs between the main member and the support member.
  • An object of the present disclosure is to provide a semiconductor device in which occurrence of poor mechanical and electrical connection is suppressed by suppressing occurrence of variation in the thickness of the conductive adhesive, and a manufacturing method thereof. .
  • a semiconductor device includes a semiconductor chip, a lead, a conductive adhesive that mechanically and electrically connects the semiconductor chip and the lead, and a plurality of convex portions.
  • the plurality of protrusions are formed on at least one of a surface of the semiconductor chip facing the lead and a surface of the lead facing the semiconductor chip, and extends from one facing surface to the other facing surface.
  • the ends of the plurality of protrusions are in contact with the opposing surfaces of the semiconductor chip and the leads, respectively, and the intervals between the semiconductor chip and the leads are determined by the plurality of protrusions. .
  • variations in the thickness of the conductive adhesive can be suppressed, and mechanical and electrical connection failures between the semiconductor chip and the leads can be suppressed.
  • the semiconductor device can be manufactured, for example, by the following method.
  • the plurality of convex portions are formed on at least one of the facing surface of the semiconductor chip and the facing surface of the lead.
  • the conductive adhesive in a liquid state is applied to at least one of the opposing surface of the semiconductor chip and the opposing surface of the lead.
  • the liquid state conductive adhesive adheres to both the opposing surface of the semiconductor chip and the opposing surface of the lead, and the tips of the plurality of convex portions are opposing surfaces of the semiconductor chip.
  • the semiconductor chip and the lead are opposed to each other so as to contact at least one of the opposing surfaces of the lead, and the conductive adhesive in a liquid state is cured, whereby the semiconductor chip and the lead are electrically conductive. And mechanically and electrically connected through the adhesive.
  • the plurality of convex portions are formed on at least one of the opposing surfaces of the semiconductor chip and the lead. Therefore, the distribution and shape of the plurality of protrusions that define the thickness of the conductive adhesive can be visually recognized in the manufacturing process of the semiconductor device. Thereby, the quality of the plurality of convex portions can be easily evaluated. As described above, the variation in the thickness of the conductive adhesive is suppressed due to the quality variation of the plurality of convex portions.
  • FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.
  • FIG. 2 is an enlarged cross-sectional view showing a main part of the semiconductor device shown in FIG.
  • FIG. 3 is a top view of the main part shown in FIG.
  • FIG. 4 is a cross-sectional view for explaining the forming process.
  • FIG. 5 is a cross-sectional view for explaining the coating process.
  • FIG. 6 is a cross-sectional view for explaining the connection process.
  • FIG. 7 is a cross-sectional view showing a modification of the main part of the semiconductor device.
  • FIG. 8 is a cross-sectional view showing a modification of the main part of the semiconductor device.
  • FIG. 9 is a cross-sectional view showing a modification of the main part of the semiconductor device.
  • FIG. 10 is a cross-sectional view showing a modification of the main part of the semiconductor device.
  • FIG. 11 is a cross-sectional view showing a modification of the main part of the semiconductor device.
  • FIG. 12 is a cross-sectional view for explaining a modification of the forming process.
  • FIG. 13 is a cross-sectional view for explaining a modification of the coating process.
  • FIG. 14 is a cross-sectional view for explaining a modified example of the connecting step.
  • FIG. 15 is a cross-sectional view for explaining a modification of the forming process.
  • FIG. 16 is a cross-sectional view for explaining a modified example of the connecting step.
  • the semiconductor device 100 includes a semiconductor chip 10, a lead 20, a conductive adhesive 30, and a protrusion 40 as main parts.
  • the semiconductor device 100 according to this embodiment includes a housing 50, a wire 60, and a coating resin 70 in addition to the main part described above.
  • the semiconductor chip 10 is mechanically and electrically connected to the lead 20 via a conductive adhesive 30, and a part of the lead 20 is insert-molded in the housing 50.
  • the semiconductor chip 10 is electrically connected to the lead 20 via the wire 60, and the semiconductor chip 10, the conductive adhesive 30, and the wire 60 are covered and protected by the coating resin 70.
  • the feature of the semiconductor device 100 is a convex portion 40 disposed between the semiconductor chip 10 and the lead 20, and this convex portion 40 causes the gap between the semiconductor chip 10 and the lead 20 as shown in FIG. 2.
  • the thickness of the provided conductive adhesive 30 is constant in the z direction.
  • the semiconductor chip 10 is obtained by forming an electronic element 12 on a semiconductor substrate 11.
  • the semiconductor substrate 11 according to the present embodiment is a silicon substrate, and the electronic element 12 is an LED.
  • the electronic element 12 is formed on the surface layer of the surface 11a of the semiconductor substrate 11, and the pad 13 for connecting to the wire 60 is formed on the surface 11a.
  • a conductive adhesive 30 is attached to the back surface 11 b of the front surface 11 a, and the semiconductor chip 10 is mechanically and electrically connected to the lead 20 through the conductive adhesive 30.
  • the semiconductor chip 10 has a configuration in which current flows between the front surface 11a and the back surface 11b, and the light emission amount of the electronic element 12 is adjusted by adjusting the current amount in the thickness direction of the semiconductor chip 10.
  • each of the front surface 11a and the back surface 11b is along an xy plane defined by the x direction and the y direction, and is orthogonal to the z direction.
  • the lead 20 is a part of a lead frame made of a metal such as Cu or Al, and the surface thereof is plated.
  • a plurality of leads 20 are insert-molded in the housing 50, and both end portions thereof are exposed from the housing 50. As shown in FIG. 1, one end of the lead 20 is exposed to the outside, and the other end is covered with a coating resin 70.
  • the semiconductor chip 10 is mechanically and electrically connected to one other end of the plurality of leads 20 via a conductive adhesive 30.
  • the semiconductor chip 10 is electrically connected via a wire 60 to a lead 20 different from the lead 20 to which the semiconductor chip 10 is connected. As a result, the semiconductor chip 10 can be electrically connected to the outside via the lead 20, the conductive adhesive 30, and the wire 60. As shown in FIG.
  • the upper surface 20a of the lead 20 to which the semiconductor chip 10 is mechanically and electrically connected via the conductive adhesive 30 is the same as the front surface 11a and the back surface 11b, respectively.
  • the y plane it is orthogonal to the z direction.
  • the conductive adhesive 30 is formed by curing a silver paste. As shown in FIG. 2, the conductive adhesive 30 is provided between the back surface 11 b of the semiconductor substrate 11 and the top surface 20 a of the lead 20. The conductive adhesive 30 mechanically and electrically connects the semiconductor chip 10 and the lead 20 by contacting the back surface 11b of the semiconductor substrate 11 (semiconductor chip 10) and the top surface 20a of the lead 20. .
  • the back surface 11 b corresponds to a surface facing the lead 20 in the semiconductor chip 10
  • the top surface 20 a corresponds to a surface facing the semiconductor chip 10 in the lead 20.
  • the convex portion 40 is located between the back surface 11b and the top surface 20a, and by defining the distance between the back surface 11b and the top surface 20a, the thickness of the conductive adhesive 30 that contacts the back surface 11b and the top surface 20a, respectively. It prescribes.
  • a plurality of convex portions 40 according to the present embodiment are formed on the upper surface 20a of the lead 20, extend from the upper surface 20a to the back surface 11b, and a tip portion thereof is in contact with the back surface 11b.
  • the plurality of convex portions 40 have the same length in the z direction, and the back surface 11b and the top surface 20a are along the xy plane.
  • the distance between the opposing surfaces of the back surface 11b and the top surface 20a in the z direction is constant by the plurality of convex portions 40.
  • the thickness of the conductive adhesive 30 provided between the back surface 11b and the top surface 20a and contacting the back surface 11b and the top surface 20a is constant.
  • the four convex portions 40 are formed on the lead 20, and the end portions of the four convex portions 40 are in contact with the corners of the back surface 11 b of the semiconductor chip 10. . As shown in FIG. 2, the side surfaces of all the convex portions 40 are covered with the conductive adhesive 30.
  • the convex portion 40 is made of a material softer (lower Young's modulus) than the conductive adhesive 30 in the cured state. Specifically, it is made of a UV curable resin that is cured by irradiation with ultraviolet rays.
  • a UV curable resin an ultraviolet curable epoxy resin, an ultraviolet curable silicone resin, or the like can be employed.
  • the housing 50 is for mounting the semiconductor chip 10.
  • the housing 50 is made of a resin having a property of reflecting light emitted from the electronic element 12 of the semiconductor chip 10.
  • the housing 50 is made of polyphthalamide (PPA) and is white.
  • the housing 50 includes a pedestal 51 having a rectangular cross-sectional shape, and a cylindrical portion 52 having an inner space and openings at both ends thereof.
  • the edge of the opening is fixed to one surface of the pedestal 51 in such a manner that one opening of the cylinder 52 is closed.
  • the semiconductor chip 10 is provided on one surface of the pedestal 51 surrounded by the inner wall surface of the cylindrical portion 52. Further, the distance between the inner wall surfaces of the cylindrical portion 52 in the xy plane increases as the distance from the pedestal 51 increases, and the other opening farther from the pedestal 51 than the one opening blocked by the pedestal 51 is provided.
  • the section has a larger opening cross-sectional area. With this configuration, a part of the light emitted from the electronic element 12 is reflected by the inner wall surface of the cylindrical portion 52 and is emitted to the outside through the opening.
  • the wire 60 is for electrically connecting the lead 20 and the semiconductor chip 10. As shown in FIG. 1, one end of the wire 60 is connected to the lead 20, and the other end is connected to the pad 13 of the semiconductor chip 10.
  • the covering resin 70 covers and protects the semiconductor chip 10, the wire 60, and the electrical connection portion between the semiconductor chip 10 and the lead 20, and is filled in the inner space of the cylindrical portion 52.
  • the coating resin 70 is made of a resin having a property of transmitting light emitted from the electronic element 12 of the semiconductor chip 10.
  • the coating resin 70 is made of an epoxy resin and is transparent.
  • the lead 20 is prepared.
  • a UV curable resin which is a material for forming the convex portion 40, is applied to the upper surface 20 a of the lead 20.
  • the UV curable resin is cured by irradiating ultraviolet rays, and the convex portion 40 is formed.
  • the application of the UV curable resin to the upper surface 20a is performed by well-known and publicly used ink jet printing or dispensing.
  • a conductive adhesive 30 in a liquid state that is, a silver paste is applied to the upper surface 20a.
  • a silver paste is applied to the upper surface 20a so that the convex portions 40 are covered.
  • the conductive adhesive 30 does not include a spacer that defines the distance between the semiconductor chip 10 and the lead 20 and defines the thickness of the conductive adhesive 30.
  • the semiconductor chip 10 is placed on the convex portion 40 and the silver paste so that the silver paste adheres to the back surface 11b of the semiconductor substrate 11 and the tip of the convex portion 40 contacts the back surface 11b. Deploy. Thereafter, the silver paste is cured by volatilizing the solvent contained in the silver paste, and the conductive adhesive 30 is formed. Thereby, the semiconductor chip 10 and the lead 20 are mechanically and electrically connected via the conductive adhesive 30. The above is the connection process. Through the above steps, the main part of the semiconductor device 100 is manufactured.
  • the protrusions 40 that define the distance between the semiconductor chip 10 and the leads 20 are formed on the leads 20.
  • the conductive adhesive includes a spacer that defines the thickness of the conductive adhesive
  • the fluidity of the conductive adhesive 30 in the liquid state in the connection process. Therefore, the distribution and shape of the member (convex portion 40) that defines the thickness of the conductive adhesive 30 are suppressed from changing. For this reason, variation in the thickness (film thickness) of the conductive adhesive 30 is suppressed.
  • a convex portion 40 is formed on the lead 20. Therefore, unlike the configuration in which the conductive adhesive includes a spacer that defines the thickness of the conductive adhesive, the distribution and shape of the members (projections 40) that define the thickness of the conductive adhesive 30 are different. It can be visually recognized in the forming process. Thereby, the quality of the convex part 40 can be evaluated easily. As described above, the variation in the thickness of the conductive adhesive 30 due to the variation in the quality of the protrusions 40 is suppressed.
  • the semiconductor device 100 As described above, according to the semiconductor device 100 according to the present embodiment, variation in the thickness of the conductive adhesive 30 is suppressed. Therefore, when a thermal stress is generated due to a difference in coefficient of linear expansion between each of the semiconductor chip 10 and the lead 20 and the conductive adhesive 30, a portion where the thermal stress is locally increased may be generated between the two. It is suppressed. In other words, the occurrence of stress concentration is suppressed. For this reason, the conductive adhesive 30 is prevented from being peeled off from the semiconductor chip 10 and the lead 20 due to the stress concentration of thermal stress, and mechanical and electrical connection failure occurs between the semiconductor chip 10 and the lead 20. Is suppressed.
  • the end of the convex portion 40 formed on the lead 20 is in contact with the back surface 11b and the top surface 20a. Therefore, the number of convex portions 40 arranged in the z direction, which is the direction in which the semiconductor chip 10 and the lead 20 face each other, is one. According to this, unlike the configuration in which spacers are included in the conductive adhesive, the number of spacers arranged in the z direction is constant, and the facing distance between the semiconductor chip 10 and the leads 20 in the z direction is constant. Therefore, it is not necessary to apply a force for approaching at least one of the semiconductor chip 10 and the lead 20 to both.
  • the side surface of the convex portion 40 is covered with the conductive adhesive 30. According to this, the contact area of the conductive adhesive 30 is increased as compared with the configuration in which the side surface of the convex portion is not in contact with the conductive adhesive. Further, unlike the configuration in which the side surface of the convex portion is not covered with the conductive adhesive, an anchor effect occurs. Therefore, the mechanical connection strength between the semiconductor chip 10 and the lead 20 is improved, and the occurrence of poor mechanical and electrical connection in both is suppressed.
  • the convex portion 40 is softer than the conductive adhesive 30 in the cured state. According to this, unlike the structure in which the convex portion is harder than the conductive adhesive in the cured state, the thermal stress caused by the difference in the linear expansion coefficient between the convex portion 40 and the conductive adhesive 30 is Even if it occurs in the meantime, since the convex portion 40 is deformed by the thermal stress, the strength of the thermal stress applied to the conductive adhesive 30 is relaxed. Therefore, peeling of the conductive adhesive 30 from the semiconductor chip 10 and the lead 20 is suppressed, and mechanical and electrical connection failures between the semiconductor chip 10 and the lead 20 are suppressed.
  • the convex portion 40 is made of a UV curable resin. According to this, the resin in the liquid state can be cured faster than the configuration in which the convex portion is made of the thermosetting resin. Therefore, the convex part 40 can be formed reflecting the shape of the resin in the liquid state, and the convex part 40 is prevented from becoming unstable. Thereby, variation in the quality of the convex part 40 is suppressed, and variation in the thickness of the conductive adhesive 30 is suppressed. Therefore, the conductive adhesive 30 is prevented from being peeled off from the semiconductor chip 10 and the lead 20 due to the stress concentration of the thermal stress, and mechanical and electrical connection failures occur between the semiconductor chip 10 and the lead 20. It is suppressed.
  • the semiconductor chip 10 is covered and protected by the covering resin 70. Therefore, thermal stress due to the difference in linear expansion coefficient between the semiconductor chip 10 and the coating resin 70 is applied to the semiconductor chip 10.
  • variation in the thickness of the conductive adhesive 30 is suppressed, and the mechanical bonding between the semiconductor chip 10 and the lead 20 by the conductive adhesive 30 is suppressed. Connection strength has been improved. Therefore, it is possible to suppress mechanical and electrical connection failures between the semiconductor chip 10 and the leads 20 due to the thermal stress resulting from the difference in linear expansion coefficient between the semiconductor chip 10 and the coating resin 70 described above.
  • the semiconductor device 100 is the main part, the semiconductor chip 10, the lead 20, the conductive adhesive 30, the convex part 40, the housing 50, the wire 60, and the coating resin 70.
  • the semiconductor device 100 may not include the housing 50, the wire 60, and the coating resin 70.
  • the semiconductor chip 10 has been described as an example in which a current flows between the front surface 11a and the back surface 11b.
  • the current flowing through the semiconductor chip 10 may be the front surface 11a or the back surface 11b.
  • a configuration in which two electrically independent leads 20 are electrically connected via the semiconductor chip 10 may be employed.
  • the example in which the convex portion 40 is formed on the upper surface 20a of the lead 20 is shown.
  • a configuration in which the convex portion 40 is formed on the back surface 11 b of the semiconductor chip 10 can be adopted.
  • the structure formed in both the upper surface 20a and the back surface 11b is also employable.
  • the convex portion 40 is formed on the upper surface 20a of the lead 20 in the forming step.
  • the protrusion 40 may be formed on the back surface 11 b of the semiconductor substrate 11 in the forming step.
  • the convex portion 40 may be formed of a resist film using a known exposure technique.
  • a liquid conductive adhesive 30 (silver paste) is applied to the upper surface 20 a of the lead 20 in the application process.
  • the semiconductor chip 10 is installed on a silver paste so that a silver paste may adhere to the back surface 11b, and the front-end
  • the silver paste is cured by volatilizing the solvent contained in the silver paste, and the conductive adhesive 30 is formed. Thereby, the main part of the semiconductor device 100 shown in FIG. 10 is manufactured.
  • the electronic element 12 is an LED
  • the electronic element 12 is not limited to the above example, and, for example, a photodiode can be employed.
  • the conductive adhesive 30 may be any adhesive that mechanically and electrically connects the semiconductor chip 10 and the lead 20 and is not limited to the above example.
  • the conductive adhesive 30 may be formed by curing C paste or Cu paste.
  • the number of convex portions 40 is not limited to the above example. In the connection process, the number of the semiconductor chips 10 and the leads 20 may be stably supported. The number of convex portions 40 is preferably three or more.
  • the arrangement of the convex portions 40 is not limited to the above example. Any arrangement that stably supports the semiconductor chip 10 and the leads 20 in the connection step may be used. For example, it is possible to adopt a configuration in which a regular polygon is formed by a line connecting the vertices of the convex portions 40 by arranging three or more at equal intervals around the center of gravity of the semiconductor chip 10.
  • the linear expansion coefficient between the convex portion 40 and the conductive adhesive 30 is preferably the same. According to this, unlike the configuration in which the convex portion and the conductive adhesive have different linear expansion coefficients, the thermal stress caused by the difference in the linear expansion coefficient is between the convex portion 40 and the conductive adhesive 30. Occurrence is suppressed. Therefore, peeling of the conductive adhesive 30 from the semiconductor chip 10 and the lead 20 is suppressed, and mechanical and electrical connection failures between the semiconductor chip 10 and the lead 20 are suppressed.
  • the size of the semiconductor chip 10 (the size of the xy plane) and the height of the convex portion 40 (the length in the z direction) are not particularly mentioned.
  • the size of the semiconductor chip 10 may be 200 ⁇ m ⁇ 200 ⁇ m, 250 ⁇ m ⁇ 150 ⁇ m, or 250 ⁇ m ⁇ 250 ⁇ m.
  • the height of the convex portion 40 can be 2 ⁇ m to 100 ⁇ m.
  • UV curable resin is adopted as the forming material of the convex portion 40 and ink jet printing is adopted as the forming method, the height and width of the convex portion 40 are determined after the UV curable resin is printed on the lead 20 or the semiconductor chip 10.
  • the time until the printed UV curable resin is irradiated with UV (the time when the printed UV curable resin flows and the height gradually decreases) is determined.
  • the convex part 40 having a height of 20 ⁇ m and a diameter of 5 to 10 ⁇ m can be formed.
  • the adjacent distance of the convex portion 40 is determined according to the size of the semiconductor chip 10 and the lead 20. For example, when 200 ⁇ m ⁇ 200 ⁇ m is adopted as the size of the semiconductor chip 10, the adjacent distance between the convex portions 40 is approximately 150 ⁇ m.
  • the convex portion 40 is made of a UV curable resin
  • the protrusions 40 may be formed of the material for forming the leads 20 by projecting a part of the leads 20 toward the semiconductor chip 10.
  • the number of parts of the semiconductor device 100 is reduced and the manufacturing process is simplified as compared with the configuration in which the leads 20 and the protrusions 40 are made of different materials. The As a result, the manufacturing cost is reduced.
  • the convex portion 40 In order to form the convex portion 40 by projecting a part of the lead 20, it is possible to provide irregularities at predetermined positions of the lead frame forming punch and die. Further, the formation of irregularities on the punch or die is performed by a known technique such as a machining center or an end mill electric discharge machining when the height of the convex portion 40 is 2 ⁇ m to 100 ⁇ m.
  • the projecting portion 40 may be formed only at the mounting portion of the semiconductor chip 10 on the lead 20, or may be other than the mounting portion of the semiconductor chip 10. It may be adopted.
  • the convex portion 40 is formed only on the mounting portion of the semiconductor chip 10 in the lead 20, the light irradiated from the electronic element 12 formed on the semiconductor chip 10 is suppressed from being irregularly reflected by the convex portion 40.
  • the convex portion 40 is formed in each of the mounting portion of the semiconductor chip 10 and the other portion of the lead 20, a member different from the semiconductor chip 10 is bonded and fixed to the lead 20 via the conductive adhesive 30.
  • the convex portion 40 suppresses variations in the thickness of the conductive adhesive 30 between the member and the lead 20. Therefore, when a thermal stress is generated due to a difference in linear expansion coefficient between the lead 20 and each of the above-described members and the conductive adhesive 30, a portion where the thermal stress is locally increased may be generated between the two. It is suppressed. In other words, the occurrence of stress concentration is suppressed. For this reason, due to the stress concentration of thermal stress, the conductive adhesive 30 is prevented from peeling off from the lead 20 and the above-described members, and mechanical and electrical connection failures are suppressed from occurring in both.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

La présente invention porte sur un dispositif à semi-conducteurs qui possède : une puce à semi-conducteurs (10); un conducteur (20); un adhésif conducteur (30) qui connecte mécaniquement et électriquement la puce à semi-conducteurs et le conducteur l'un à l'autre; et une pluralité de sections en saillie (40). Les sections en saillie sont formées sur une surface de regard (11b) de la puce à semi-conducteurs, ladite surface de regard étant tournée vers le conducteur, et/ou sur une surface de regard (20a) du conducteur, ladite surface de regard étant tournée vers la puce à semi-conducteurs, et les sections en saillie s'étendant depuis une surface de regard vers l'autre surface de regard. Des parties d'extrémité de chacune des sections en saillie sont en contact avec la surface de regard de la puce à semi-conducteurs et la surface de regard du conducteur, respectivement, et un intervalle entre la puce à semi-conducteurs et le conducteur est spécifié au moyen des sections en saillie.
PCT/JP2013/005665 2012-10-18 2013-09-25 Dispositif à semi-conducteurs et procédé pour fabriquer celui-ci WO2014061204A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150129833A1 (en) * 2013-11-08 2015-05-14 Mi Jeong Yun Light emitting device package
US9515237B2 (en) 2015-03-27 2016-12-06 Nichia Corporation Method for producing a light emitting device
CN110326092A (zh) * 2017-03-03 2019-10-11 株式会社电装 半导体装置及其制造方法
EP4207271A4 (fr) * 2020-08-25 2024-03-27 Vivo Mobile Communication Co Ltd Module d'encapsulation de puce et dispositif électronique

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6371699B2 (ja) * 2014-12-25 2018-08-08 株式会社フジクラ 半導体パッケージの製造方法
EP3675190B1 (fr) 2018-12-25 2023-05-03 Nichia Corporation Procédé de fabrication d'un dispositif de source lumineuse et dispositif de source lumineuse
WO2020175619A1 (fr) * 2019-02-28 2020-09-03 京セラ株式会社 Boîtier de montage de composant électronique, dispositif électronique et dispositif électroluminescent
CN114450794A (zh) * 2019-09-04 2022-05-06 索尼半导体解决方案公司 半导体封装、电子装置和用于制造半导体封装的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207645A (ja) * 1982-05-28 1983-12-03 Fujitsu Ltd 半導体装置
JPS5935434A (ja) * 1982-08-24 1984-02-27 Nec Corp 半導体装置
JPH02146757A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体装置
JPH05243469A (ja) * 1992-02-28 1993-09-21 Nec Kyushu Ltd 半導体装置用リードフレーム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207645A (ja) * 1982-05-28 1983-12-03 Fujitsu Ltd 半導体装置
JPS5935434A (ja) * 1982-08-24 1984-02-27 Nec Corp 半導体装置
JPH02146757A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体装置
JPH05243469A (ja) * 1992-02-28 1993-09-21 Nec Kyushu Ltd 半導体装置用リードフレーム

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150129833A1 (en) * 2013-11-08 2015-05-14 Mi Jeong Yun Light emitting device package
US9515237B2 (en) 2015-03-27 2016-12-06 Nichia Corporation Method for producing a light emitting device
US9768152B2 (en) 2015-03-27 2017-09-19 Nichia Corporation Method for producing a light emitting device
CN110326092A (zh) * 2017-03-03 2019-10-11 株式会社电装 半导体装置及其制造方法
CN110326092B (zh) * 2017-03-03 2023-08-04 株式会社电装 半导体装置及其制造方法
EP4207271A4 (fr) * 2020-08-25 2024-03-27 Vivo Mobile Communication Co Ltd Module d'encapsulation de puce et dispositif électronique

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