WO2014049915A1 - Dispositif de traitement de substrat, procédé de traitement de substrat et procédé de fabrication de dispositif à semiconducteur - Google Patents

Dispositif de traitement de substrat, procédé de traitement de substrat et procédé de fabrication de dispositif à semiconducteur Download PDF

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WO2014049915A1
WO2014049915A1 PCT/JP2013/003937 JP2013003937W WO2014049915A1 WO 2014049915 A1 WO2014049915 A1 WO 2014049915A1 JP 2013003937 W JP2013003937 W JP 2013003937W WO 2014049915 A1 WO2014049915 A1 WO 2014049915A1
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substrate
processing
gas
plasma
supplied
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PCT/JP2013/003937
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English (en)
Japanese (ja)
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貴信 西田
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds

Definitions

  • the present invention relates to a substrate processing apparatus used when performing predetermined processing such as plasma dry etching on a substrate to be processed while electrostatically attracting and fixing the substrate to be processed, a substrate processing method using the same, and
  • the present invention relates to a method for manufacturing a used semiconductor device.
  • the substrate to be processed needs to be supported in a fixed state on the substrate support member for the dry etching process. For this reason, for example, when the substrate to be processed is a semiconductor wafer, the semiconductor wafer is supported by a static force such as Coulomb force.
  • An electrostatic attraction apparatus is used which is supported by being attracted onto a substrate support member with electric power.
  • FIG. 11 is a schematic diagram for explaining the principle of electrostatic attraction of the conventional electrostatic attraction apparatus disclosed in Patent Document 1.
  • the conventional electrostatic adsorption device 100 is provided in a space where plasma is formed, and adsorbs the insulating substrate 101 to the insulator 102 side.
  • An adsorbing member 104 is composed of the insulator 102 and the electrode 103 provided therein. The adsorption member 104 is mounted and supported on the substrate support member 105.
  • FIG. 12 is a main part configuration diagram schematically showing a conventional substrate processing apparatus disclosed in Patent Document 2. As shown in FIG.
  • the conventional plasma processing apparatus 200 applies a DC voltage to the electrodes 202 and 203 of the electrostatic chuck 201 on which the insulating substrate K is mounted, and supplies an inert gas into the processing chamber 204.
  • An inert gas is supplied from the unit 205, and the inert gas is turned into plasma.
  • the insulating substrate K is charged from the plasma-ized inert gas, and the insulating substrate K is attracted and held on the electrostatic chuck 201. Thereafter, supply of cooling gas is started between the back surface of the insulating substrate K attracted and held on the electrostatic chuck 201 and the upper surface of the electrostatic chuck 201.
  • a processing gas for plasma processing is supplied from the processing gas supply unit 206 into the processing chamber 204 instead of the inert gas, and the processing gas is replaced with the processing gas. Then, the insulating substrate K is attracted and held on the electrostatic chuck 201. Thereafter, the insulating substrate K is plasma-etched by the plasma processing gas while cooling gas is supplied from the cooling gas supply unit 207 to cool the insulating substrate K with the cooling gas.
  • the exhaust device 208 includes an exhaust pump 209 and an exhaust pipe 211 that connects the exhaust pump 209 and the lower container 210.
  • the exhaust device 208 exhausts the gas in the lower container 210 through the exhaust pipe 211, and the inside of the processing chamber 204.
  • the inert gas and the processing gas are set to a predetermined pressure.
  • the insulating substrate K can be cooled before the start of the plasma etching process, and the plasma etching process can be uniformly and efficiently performed on the entire surface of the insulating substrate K.
  • the number of chips that can be taken is reduced because the mechanical chuck covers at least a part of the outer peripheral edge of the wafer substrate.
  • the pressure on the back surface He for cooling necessary for achieving the process is secured, and the surface area on the wafer substrate is maximized by the substrate adsorption holding without using the mechanical chuck, thereby increasing the number of chips that can be obtained. Can do.
  • the conventional electrostatic adsorption apparatus 100 is an RIE (anode coupling) apparatus, and only an upper electrode for plasma generation exists, and the electrode 103 provided in the insulator 102 in the adsorption member 104 is predetermined.
  • An electrostatic adsorption principle is described in which a voltage is applied to electrostatically attract the insulating substrate 101.
  • the adsorption member 104 for electrostatically adsorbing the insulating substrate 101 is required separately.
  • the conventional substrate processing apparatus 200 disclosed in Patent Document 2 is an ICP (inductively coupled plasma) apparatus while securing a back surface He for cooling at a pressure necessary for achieving the process. Can be controlled independently. First, only the upper electrode is driven and controlled, the inert gas introduced into the processing chamber 204 is turned into plasma, and the wafer substrate is electrostatically adsorbed and held on the electrostatic chuck 201. The substrate adsorption holding process is separately performed before the stabilization process and the subsequent plasma etching process in which the processing gas is introduced into the processing chamber 204 from the processing gas supply unit 206 to adjust the processing gas pressure to a desired pressure.
  • ICP inductively coupled plasma
  • the present invention solves the above-mentioned conventional problems, and improves the number of chips per substrate by making the best use of the area on the insulator substrate, while eliminating the need for a separate adsorbing member and increasing the efficiency of manufacturing. It is an object of the present invention to provide a substrate processing apparatus, a substrate processing method using the same, and a semiconductor device manufacturing method using the same.
  • the substrate processing method of the present invention includes a substrate processing step in which a substrate is disposed in a processing chamber, power is independently supplied to each of the upper electrode and the lower electrode, and the processing gas in the processing chamber is turned into plasma to perform substrate processing.
  • power is supplied only to the upper electrode in the processing gas pressure adjustment step for adjusting the pressure of the processing gas supplied into the processing chamber to a predetermined pressure.
  • a process gas supplied into the process chamber is turned into plasma to charge the substrate and charge the substrate to electrostatically adsorb the substrate to the lower electrode side, thereby achieving the above object.
  • a gas species having a high electron emission rate that is more easily converted to plasma than an inert gas is selected as a processing gas in the substrate processing method of the present invention.
  • the gas species having a high electron emission rate that is easily converted to plasma in the substrate processing method of the present invention is a processing gas having an ionization potential lower than a predetermined value and a gas ionization voltage Vi lower than another predetermined value.
  • the processing gas in the substrate processing method of the present invention is a gas containing an element having an ionization potential of 320 kcal / mol or less as an adsorption gas.
  • the processing gas in the substrate processing method of the present invention is a gas containing at least one of O (oxygen) and Cl (chlorine).
  • the substrate is an insulating substrate, and the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • the substrate processing is performed by controlling the substrate temperature while cooling the substrate with a cooling medium introduced to the back surface of the substrate in the substrate processing method of the present invention.
  • the electrostatic attraction force that can ensure the pressure of the cooling medium necessary for cooling the back surface of the substrate in the substrate processing method of the present invention is secured.
  • the cooling medium necessary for cooling the back surface of the substrate in the substrate processing method of the present invention is He gas.
  • the RF power (applied voltage) to the upper electrode is 0.45 w / cm 2 or more and 75 w / cm 2 or less, or 500 W or more and 2000 W or less as a substrate processing condition in the substrate processing method of the present invention.
  • the RF power (applied voltage) is 500 W or more and 1200 W or less.
  • the substrate in the substrate processing method of the present invention is a sapphire substrate.
  • the substrate in the substrate processing method of the present invention is a SiC substrate or a compound semiconductor substrate.
  • the substrate in the substrate processing method of the present invention is provided with an insulating film that is easily affected by an electric charge and is easily charged with electric charges from the plasma.
  • the film that is susceptible to electrical influence in the substrate processing method of the present invention is a photoresist film.
  • the film state on the substrate in the substrate processing method of the present invention is a state in which the photoresist film remains during the substrate processing.
  • the method for manufacturing a semiconductor device of the present invention includes a plasma etching process using the substrate processing method of the present invention, whereby the above object is achieved.
  • the substrate processing apparatus of the present invention is a substrate processing apparatus in which a substrate is disposed in a processing chamber, power is independently supplied to each of an upper electrode and a lower electrode, and a processing gas in the processing chamber is turned into plasma to perform substrate processing.
  • the electric power is supplied only to the upper electrode, and the electron emission rate is higher than that of an inert gas.
  • the processing gas supplied into the processing chamber is turned into plasma to charge the substrate to charge the lower electrode.
  • the substrate processing can be performed in a state where the substrate is electrostatically adsorbed on the side, thereby achieving the above object.
  • a substrate processing method includes a substrate processing step in which a substrate is disposed in a processing chamber, power is independently supplied to each of the upper electrode and the lower electrode, and a processing gas in the processing chamber is turned into plasma to perform substrate processing.
  • the processing gas pressure adjusting step of adjusting the pressure of the processing gas supplied into the processing chamber to a predetermined pressure before the substrate processing step, the processing gas supplied to the processing chamber by supplying power only to the upper electrode is supplied.
  • There is a substrate adsorption step in which the substrate is charged to charge the substrate and electrostatically adsorb the substrate to the lower electrode side.
  • the area on the insulator substrate is maximized to improve the number of chips per substrate, and the process gas pressure adjustment process is also used as the substrate adsorption process. Therefore, manufacturing can be performed efficiently and manufacturing cost performance can be improved.
  • the processing gas supplied to the processing chamber by supplying power only to the upper electrode in the processing gas pressure adjusting step for adjusting the pressure of the processing gas supplied to the processing chamber to a predetermined pressure is converted into plasma. Since the substrate is charged and the substrate is electrostatically attracted to the lower electrode side, the suction member is separately used while making the most of the area on the insulator substrate and improving the number of chips per substrate. It is not necessary and manufacturing can be performed efficiently and manufacturing cost performance can be improved.
  • FIG. 1 It is a longitudinal cross-sectional view which shows the principal part structural example of the nitride semiconductor light-emitting device in Embodiment 2 of this invention. It is a schematic diagram for demonstrating the electrostatic attraction principle of the conventional electrostatic attraction apparatus currently disclosed by patent document 1.
  • FIG. It is a principal part block diagram which shows schematically the conventional substrate processing apparatus currently disclosed by patent document 2.
  • FIG. 1 It is a principal part block diagram which shows schematically the conventional substrate processing apparatus currently disclosed by patent document 2.
  • each thickness, length, etc. of the structural member in FIG. 1 and FIG. 10 are not limited to the structure to illustrate from a viewpoint on drawing preparation.
  • FIG. 1 is a main part configuration diagram schematically showing a cross-sectional structure of a substrate processing apparatus in Embodiment 1 of the present invention.
  • the substrate processing apparatus 1 in Embodiment 1 of the present invention is an ICP (inductively coupled plasma) apparatus
  • an upper electrode 3 and a lower electrode 4 provided in the processing chamber 2 can be controlled independently.
  • the wafer substrate 5 which is an insulating substrate is directly mounted on the lower electrode 4.
  • a wafer substrate 5 is disposed in a processing chamber 2 as a processing chamber, and power is independently supplied to each of the upper electrode 3 and the lower electrode 4.
  • the power is supplied only to the upper electrode 3 and the processing is supplied into the processing chamber 2 which has a higher electron emission rate and is more easily converted to plasma than the inert gas.
  • the substrate processing can be performed in a state where the gas is turned into plasma to charge the wafer substrate 5 and the wafer substrate 5 is electrostatically attracted to the lower electrode 4 side.
  • This substrate processing apparatus 1 controls only the upper electrode 3 to secure the back surface He for cooling at a pressure necessary for achieving the process, while keeping the surface area of the insulating substrate on the wafer substrate 5 without using a mechanical chuck as a chuck.
  • a process gas pressure adjusting process in which a process gas is introduced into the process chamber 2 instead of an inert gas and the process gas pressure is adjusted to a predetermined pressure as in the prior art, in a state where it is fully utilized by electrostatic adsorption.
  • the negative charge of the plasma 6 is charged on the wafer substrate 5 by the plasma 6 obtained by converting the processing gas into plasma, and the wafer substrate 5 is electrostatically adsorbed on the lower electrode 4 and held and fixed.
  • a holding step is provided. Thereafter, the upper electrode 3 and the lower electrode 4 are both controlled to perform a plasma etching process.
  • a gas species having a high electron emission rate is selected as a processing gas.
  • RF radio frequency
  • a plasma 6 of a gas species having a high electron emission rate is generated, and supply of electric charges sufficient to secure an adsorption force to the surface of the wafer substrate 5 is ensured.
  • the ESC voltage By applying the ESC voltage to the ESC electrode 7, it is possible to obtain a sufficient adsorption force on the surface of the lower electrode 4 of the wafer substrate 5 together with the charge charged on the surface of the wafer substrate 5.
  • the application timing of the ESC voltage to the ESC electrode 7 in the adsorption holding process starts at the start of the stability process.
  • the wafer substrate 5 as an insulating substrate is electrostatically attracted by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • FIG. 2 is a diagram showing the ionization voltage Vi of various gases.
  • Electrons in the plasma 6 are created by ionization of gas molecules or atoms. Ionization also occurs due to collisions between atoms and molecules in an excited state or photoionization due to light energy, but most of them are mainly direct ionization due to accelerated electron collisions. In order for gas molecules or atoms to ionize, a certain amount of energy must be obtained by collision. The minimum energy required for ionization is called an ionization voltage Vi, which varies depending on the type of gas as shown in FIG. It can be seen that rare gases such as He and Ar have a relatively high ionization voltage Vi of 10V to 20V, but alkali metals are easily ionized because the ionization voltage Vi is as low as 3V to 4V.
  • FIG. 3 is a diagram showing a long-period periodic table of atomic number, atomic radius (unit: angstrom), element symbol, electronegativity, and ionization potential (unit: kcal / mol).
  • the plurality of elements can be divided into non-metallic elements, metallic elements, metalloid elements, and rare gas elements.
  • the element symbols in italics are gases at room temperature.
  • Nonmetallic elements that are gaseous at room temperature are H, N, O, F, and Cl.
  • N is not used as an etching gas.
  • Elements having a low ionization potential (unit: kcal / mol) are O, F, and Cl. Therefore, a processing gas that is used for plasma etching and has a high electron emission rate that is easily converted to plasma may be selected from processing gases containing non-metallic elements O and Cl having a low ionization potential.
  • FIG. 4 is a diagram showing the relationship of the ionization potential (kcal / mol) to the gas ionization voltage Vi.
  • the gas ionization voltage Vi and the ionization potential (kcal / mol) have a correlation.
  • the lower the ionization potential (kcal / mol) the lower the ionization voltage Vi of the gas, and the gas species having a high electron emission rate that is easily plasmatized have a lower ionization potential and lower ionization voltage Vi of the gas. Processing gas.
  • a lower ionization potential tends to ionize at a lower voltage (applied voltage).
  • FIG. 5 is a graph showing the relationship between gas ionization voltage Vi and ionization potential (kcal / mol) for various gases.
  • the gas with lower ionization potential (kcal / mol) is more easily ionized, the electrostatic adsorption is better.
  • gaseous O2, O and Cl were good in electrostatic adsorption.
  • the processing gas containing Cl include Cl2 (chlorine), SiCl4 (silicon tetrachloride), and BCl3 (boron trichloride).
  • a layer such as a GaN layer can be etched using Cl2 (chlorine) or SiCl4 (silicon tetrachloride) as a processing gas.
  • An etching process using BCl 3 (boron trichloride) as a processing gas can form a surface uneven shape such as a sapphire substrate.
  • FIG. 6 is a diagram showing the wafer substrate temperature dependence of the concavo-convex shape aspect ratio on the surface of the wafer substrate 5.
  • the wafer substrate is obtained in order to obtain the desired concavo-convex shape aspect ratio on the surface of the sapphire substrate. It is necessary to set a temperature of 5.
  • the temperature of the wafer substrate 5 is affected by the temperature of the lower electrode 4 and the pressure of the back surface He that conveys the temperature of the lower electrode 4 when the wafer substrate 5 is warped.
  • FIG. 7 is a diagram showing the relationship of the He leak amount (CC) to the back surface He pressure (KPa) as the pressure dependence of the He leak amount.
  • the wafer substrate 5 cannot be cooled because it is controlled to a predetermined temperature.
  • the aspect ratio of the concavo-convex shape to be etched also changes and does not reach the desired aspect ratio. In order to prevent this, by securing the adsorption force, the leak amount of the back surface He is suppressed, and the uniformity of the in-plane temperature is improved, thereby increasing the shape margin of the uneven shape to be etched.
  • FIG. 8 is a diagram showing the relationship of the temperature of the wafer substrate to the backside He pressure (KPa) when the temperature of the lower electrode 4 is high or low.
  • the temperature of the substrate to be processed decreases as the backside He pressure (KPa) increases. This indicates that the temperature decreases when the temperature of the lower electrode 4 is 35 degrees Celsius and when the temperature of the lower electrode 4 is 55 degrees Celsius. As the pressure on the back surface He increases, the temperature of the wafer substrate 5 decreases. However, in order to obtain a desired uneven shape, it is necessary to control the temperature of the desired wafer substrate 5.
  • FIG. 9 is a diagram showing the relationship between the in-plane temperatures of the center and outer periphery of the wafer substrate with respect to the back surface cooling He pressure (Pa).
  • the temperature of the wafer substrate 5 becomes equal as the back surface cooling He pressure (Pa) increases at the center (Center) and the outer periphery (Top) of the wafer substrate 5.
  • Pa back surface cooling He pressure
  • the wafer substrate 5 is disposed in the processing chamber 2 as a processing chamber, and power is independently supplied to the upper electrode 3 and the lower electrode 4.
  • the pressure of the processing gas supplied into the processing chamber 2 is adjusted to a predetermined pressure before the substrate processing step of plasma etching processing
  • the processing gas supplied to the processing chamber 2 by supplying power only to the upper electrode 3 is turned into plasma to charge the wafer substrate 5 to the lower electrode 4 side.
  • a substrate adsorption step for electrostatically adsorbing the wafer substrate 5 is provided. In this case, a gas species having a high electron emission rate is selected as a processing gas to be used.
  • an adsorption gas containing an element having an ionization potential of 320 kcal / mol or less is used.
  • the processing gas is a gas containing at least one of O (oxygen) and Cl (chlorine) gas as an adsorption gas.
  • the substrate is an insulating substrate, and the wafer substrate 5 as an insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • the substrate processing is performed by controlling the substrate temperature while cooling the substrate with the cooling medium introduced to the back surface of the wafer substrate 5. It is necessary to secure an electrostatic attraction force that can ensure the pressure of the cooling medium necessary for cooling the back surface of the wafer substrate 5. He gas is used as a cooling medium necessary for cooling the back surface of the wafer substrate 5.
  • the RF power (applied voltage) to the upper electrode 3 is 0.45 w / cm 2 or more and 75 w / cm 2 or less, or 500 W or more and 2000 W or less. More preferably, the RF power (applied voltage) is 500 W or more and 1200 W or less as a substrate processing condition. The RF power of 1200 W to 2000 W is the current maximum output RF power.
  • the sapphire substrate is used as the wafer substrate 5, it may be a SiC substrate or a compound semiconductor substrate. It is preferable that the wafer substrate 5 is provided with an insulating film that is easily affected by an electric charge and is easily charged with electric charges from plasma because the electrostatic adsorption force is improved. Examples of the film that is susceptible to electrical influence include a photoresist film. Further, the film state on the wafer substrate 5 is preferably left with the photoresist film during the substrate processing in order to maintain the electrostatic attraction force.
  • the wafer substrate 5 is an insulating substrate, and the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • a gas species having a high electron emission rate that is easily converted to plasma is selected as the processing gas.
  • a gas species having a high electron emission rate that is easily converted to plasma is a processing gas having a low ionization potential and a low ionization voltage Vi.
  • More charge on the surface of the wafer substrate 5 is indispensable in order to secure the attractive force with the electrostatic chuck (ESC). More charging of the surface of the wafer substrate 5 depends on the element species having a low ionization potential and a low gas ionization voltage Vi.
  • FIG. 10 is a longitudinal sectional view showing an example of the configuration of the main part of the nitride semiconductor light-emitting device according to Embodiment 2 of the present invention.
  • the nitride semiconductor light emitting device 11 of the second embodiment has a film thickness of about 15 nm made of aluminum nitride (AlN) on a sapphire substrate 12, for example, as a substrate having a thickness of about 1300 ⁇ m with irregularities formed on the surface.
  • a buffer layer 13 is formed.
  • a non-doped GaN layer 14 made of non-doped GaN and having a thickness of about 500 nm is formed.
  • the n-type contact layer 15 (high carrier) having a film thickness of about 5 ⁇ m made of GaN doped with silicon (Si) 1 ⁇ 10 18 / cm 3 on the single crystalline substrate. (Concentration n + layer) is formed.
  • a multi-layer 16 is formed on the n-type contact layer 15, and a light-emitting layer 17 having a multi-quantum well structure is formed on the multi-layer 16.
  • the multi-layer 16 is formed by alternately laminating a plurality of first layers made of InxGa1-xN (0 ⁇ x ⁇ 0.3) and second layers made of GaN.
  • first layers made of InxGa1-xN (0 ⁇ x ⁇ 0.3) and second layers made of GaN.
  • this multilayer 16 for example, five pairs of a first layer made of In0.03Ga0.97N with a thickness of 3 nm and a second layer made of GaN with a thickness of 20 nm are stacked.
  • the first layer of the multi-layer 16 has a concentration of Si as one conductivity type impurity of 5 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 (more preferably 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ ).
  • the electrostatic breakdown energy (mJ / cm 2) that is added in the range of 3) and received by the light emitting layer 17 is 20 or more and 40 or less (more preferably, 20 or more and 35 or less).
  • the Si concentration corresponding to the minimum value of electrostatic breakdown energy (mJ / cm 2) is set.
  • the well layer of the light emitting layer 17 having a multiple quantum well structure is made of InyGa1-yN (0 ⁇ y ⁇ 0.3) containing at least In.
  • the light emitting layer 17 having a multiple quantum well structure has, for example, three pairs of well layers made of In0.2Ga0.8N with a thickness of 3 nm and barrier layers made of GaN with a thickness of 20 nm. .
  • an electron which is a p-type layer made of p-type Al0.15Ga0.85N with a thickness of 25 nm doped with Mg 2 ⁇ 1019 / cm3 on the light-emitting layer 17.
  • a block layer 18 is formed.
  • a p-type contact layer 19 made of p-type GaN having a thickness of 100 nm doped with 8 ⁇ 1019 Mg is formed on the electron block layer 18.
  • a translucent thin film electrode 20 (ITO) is formed by metal vapor deposition.
  • a p-electrode 21 is formed on part of the translucent thin film electrode 20.
  • the end of the n-type contact layer 15 is exposed partway, and the n-electrode 22 is formed thereon.
  • a protective film 23 for moisture resistance or the like made of a SiO2 film as a SixOy film is formed.
  • the protective film 23 includes the light-transmitting thin film electrode 20, the p-electrode 21, the n-electrode 22, and the exposed surface of the n-type contact layer 15, and further to the middle of the end of the n-type contact layer 15.
  • the electron blocking layer 18, the p-type contact layer 19, and the translucent thin film electrode 20 (ITO) are formed on the etching side surfaces.
  • the protective film 23 covers and protects the p electrode 21 and the n electrode 22 and the element surface.
  • the protective film 23 may have a single-layer structure of a SiO2 film, but may have a two-layer structure of a SiN film as a SixNy film and a SiO2 film as a SixOy film thereon. Further, the structure may be a two-layer structure in which the SiO2 film as the SixOy film and the SiN film as the SixNy film thereon are upside down. In these cases, the SiN film functions as a passivation film.
  • the protective film 23 has at least a SixOy film among a SixOy film, a SixNy film, and a SixOyNz film.
  • the method for manufacturing the nitride semiconductor light emitting device 11 includes a substrate receiving process for receiving the sapphire substrate 12 at a predetermined position, and a predetermined aspect ratio on the surface of the sapphire substrate 12.
  • a substrate receiving process for receiving the sapphire substrate 12 at a predetermined position and a predetermined aspect ratio on the surface of the sapphire substrate 12.
  • a buffer layer 13 On the surface unevenness processed surface of the sapphire substrate 12 by the MOCVD method, and a buffer layer 13, a non-doped GaN layer 14, an n-type contact layer 15, a multiple layer 16, and a multiple quantum well structure.
  • MOCVD step of sequentially forming the light emitting layer 17, the electron blocking layer 18 and the p-type contact layer 19 in this order, a transparent electrode forming step of forming the translucent thin film electrode 20 on the p-type contact layer 19, and the edge of the substrate Is etched halfway through the n-type contact layer 15 to expose the end of the n-type contact layer 15 in the middle, Forming the n-electrode 22 on the surface of the end portion of the light-emitting layer 15 and forming the p-electrode 21 on the partial surface of the translucent thin-film electrode 20; A protective film forming step for forming a protective film 23 for moisture resistance on the exposed surface of the conductive thin film electrode 20, the p electrode 21, the n electrode 22 and the n-type contact layer 15 and further on the side surface to which etching is removed; an electrode opening step for opening the protective film 23 on the n-electrode 22.
  • a surface unevenness forming step for forming unevenness on the surface of the sapphire substrate 12 and etching and removing the substrate end partway into the n-type contact layer 15.
  • An accurate and better plasma etching process is performed using the substrate processing method of the first embodiment in the etching process in which the end portion of the n-type contact layer 15 is exposed halfway.
  • the method for manufacturing the nitride semiconductor light emitting device 11 supplies power only to the upper electrode 3 in the process gas pressure adjusting step for adjusting the pressure of the process gas supplied into the process chamber 2 to a predetermined pressure.
  • a plasma etching process using the substrate processing method of the first embodiment in which the processing gas supplied into the processing chamber 2 is converted into plasma to charge the wafer substrate 5 and electrostatically attract the wafer substrate 5 to the lower electrode 4 side. Have.
  • the area on the insulator substrate is utilized to the maximum while the number of chips that can be taken per substrate is improved and the adsorption is performed.
  • a member is not required separately, and it can manufacture efficiently and can improve manufacturing cost performance.
  • this Embodiment 2 demonstrated the manufacturing method of the nitride semiconductor light-emitting element 11 of LED, it is not restricted to this, The manufacturing method of the semiconductor device which has a plasma etching process using the substrate processing method of the said Embodiment 1 If it is.
  • the present invention relates to a substrate processing apparatus used when performing predetermined processing such as plasma dry etching on a substrate to be processed while electrostatically attracting and fixing the substrate to be processed, a substrate processing method using the same, and
  • the processing gas supplied to the processing chamber by supplying power only to the upper electrode in the processing gas pressure adjusting step for adjusting the pressure of the processing gas supplied to the processing chamber to a predetermined pressure. Since the substrate is turned into plasma to charge the substrate and electrostatically adsorb the substrate to the lower electrode side, the adsorption member is improved while maximizing the area on the insulator substrate and improving the number of chips per substrate. The manufacturing cost performance can be improved by efficiently performing the manufacturing.

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  • Drying Of Semiconductors (AREA)

Abstract

L'objectif de la présente invention est d'utiliser pleinement la zone d'un substrat isolant et d'augmenter le nombre de puces, par substrat, pouvant être fabriquées sans nécessiter d'élément de fixation distinct et tout en effectuant efficacement la fabrication afin d'améliorer son rapport coût/performances. L'invention porte sur un procédé de traitement de substrat, comprenant une étape de traitement de substrat dans laquelle un substrat de plaquette (5) est disposé à l'intérieur d'une chambre de traitement (2) qui sert de chambre de traitement, une électrode supérieure (3) et une électrode inférieure (4) sont alimentées de façon indépendante, et le gaz de traitement à l'intérieur de la chambre de traitement (2) est plasmifié afin de traiter le substrat. Une étape de réglage de la pression d'un gaz de traitement (étape de stabilisation), dans laquelle la pression d'un gaz de traitement envoyé dans la chambre de traitement (2) est réglée selon une pression déterminée, est effectuée avant une étape de traitement de substrat pour un traitement de gravure au plasma, et ladite étape de réglage de la pression d'un gaz de traitement comprend une étape de fixation de substrat dans laquelle seule l'électrode supérieure (3) est alimentée, le gaz de traitement envoyé dans la chambre de traitement (2) est plasmifié, le substrat de plaquette (5) est rempli de charge électrique, et le substrat de plaquette (5) est fixé de manière électrostatique à l'électrode inférieure (4).
PCT/JP2013/003937 2012-09-26 2013-06-24 Dispositif de traitement de substrat, procédé de traitement de substrat et procédé de fabrication de dispositif à semiconducteur WO2014049915A1 (fr)

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Cited By (1)

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CN109148270A (zh) * 2017-06-19 2019-01-04 东京毅力科创株式会社 成膜方法、存储介质和成膜系统

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JPH0786250A (ja) * 1993-09-17 1995-03-31 Hitachi Ltd プラズマ処理方法
JP2004095909A (ja) * 2002-08-30 2004-03-25 Tokyo Electron Ltd プラズマ処理方法及びプラズマ処理装置
JP2007227604A (ja) * 2006-02-23 2007-09-06 Seiko Epson Corp プラズマ処理方法及び電気光学装置の製造方法
JP2007250874A (ja) * 2006-03-16 2007-09-27 Tokyo Electron Ltd プラズマエッチング方法およびコンピュータ読み取り可能な記憶媒体

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Publication number Priority date Publication date Assignee Title
JPH0786250A (ja) * 1993-09-17 1995-03-31 Hitachi Ltd プラズマ処理方法
JP2004095909A (ja) * 2002-08-30 2004-03-25 Tokyo Electron Ltd プラズマ処理方法及びプラズマ処理装置
JP2007227604A (ja) * 2006-02-23 2007-09-06 Seiko Epson Corp プラズマ処理方法及び電気光学装置の製造方法
JP2007250874A (ja) * 2006-03-16 2007-09-27 Tokyo Electron Ltd プラズマエッチング方法およびコンピュータ読み取り可能な記憶媒体

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148270A (zh) * 2017-06-19 2019-01-04 东京毅力科创株式会社 成膜方法、存储介质和成膜系统
CN109148270B (zh) * 2017-06-19 2023-11-03 东京毅力科创株式会社 成膜方法、存储介质和成膜系统

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