WO2014049915A1 - Substrate treatment device, substrate treatment method, and production method for semiconductor device - Google Patents

Substrate treatment device, substrate treatment method, and production method for semiconductor device Download PDF

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Publication number
WO2014049915A1
WO2014049915A1 PCT/JP2013/003937 JP2013003937W WO2014049915A1 WO 2014049915 A1 WO2014049915 A1 WO 2014049915A1 JP 2013003937 W JP2013003937 W JP 2013003937W WO 2014049915 A1 WO2014049915 A1 WO 2014049915A1
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Prior art keywords
substrate
processing
gas
plasma
supplied
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PCT/JP2013/003937
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French (fr)
Japanese (ja)
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貴信 西田
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds

Definitions

  • the present invention relates to a substrate processing apparatus used when performing predetermined processing such as plasma dry etching on a substrate to be processed while electrostatically attracting and fixing the substrate to be processed, a substrate processing method using the same, and
  • the present invention relates to a method for manufacturing a used semiconductor device.
  • the substrate to be processed needs to be supported in a fixed state on the substrate support member for the dry etching process. For this reason, for example, when the substrate to be processed is a semiconductor wafer, the semiconductor wafer is supported by a static force such as Coulomb force.
  • An electrostatic attraction apparatus is used which is supported by being attracted onto a substrate support member with electric power.
  • FIG. 11 is a schematic diagram for explaining the principle of electrostatic attraction of the conventional electrostatic attraction apparatus disclosed in Patent Document 1.
  • the conventional electrostatic adsorption device 100 is provided in a space where plasma is formed, and adsorbs the insulating substrate 101 to the insulator 102 side.
  • An adsorbing member 104 is composed of the insulator 102 and the electrode 103 provided therein. The adsorption member 104 is mounted and supported on the substrate support member 105.
  • FIG. 12 is a main part configuration diagram schematically showing a conventional substrate processing apparatus disclosed in Patent Document 2. As shown in FIG.
  • the conventional plasma processing apparatus 200 applies a DC voltage to the electrodes 202 and 203 of the electrostatic chuck 201 on which the insulating substrate K is mounted, and supplies an inert gas into the processing chamber 204.
  • An inert gas is supplied from the unit 205, and the inert gas is turned into plasma.
  • the insulating substrate K is charged from the plasma-ized inert gas, and the insulating substrate K is attracted and held on the electrostatic chuck 201. Thereafter, supply of cooling gas is started between the back surface of the insulating substrate K attracted and held on the electrostatic chuck 201 and the upper surface of the electrostatic chuck 201.
  • a processing gas for plasma processing is supplied from the processing gas supply unit 206 into the processing chamber 204 instead of the inert gas, and the processing gas is replaced with the processing gas. Then, the insulating substrate K is attracted and held on the electrostatic chuck 201. Thereafter, the insulating substrate K is plasma-etched by the plasma processing gas while cooling gas is supplied from the cooling gas supply unit 207 to cool the insulating substrate K with the cooling gas.
  • the exhaust device 208 includes an exhaust pump 209 and an exhaust pipe 211 that connects the exhaust pump 209 and the lower container 210.
  • the exhaust device 208 exhausts the gas in the lower container 210 through the exhaust pipe 211, and the inside of the processing chamber 204.
  • the inert gas and the processing gas are set to a predetermined pressure.
  • the insulating substrate K can be cooled before the start of the plasma etching process, and the plasma etching process can be uniformly and efficiently performed on the entire surface of the insulating substrate K.
  • the number of chips that can be taken is reduced because the mechanical chuck covers at least a part of the outer peripheral edge of the wafer substrate.
  • the pressure on the back surface He for cooling necessary for achieving the process is secured, and the surface area on the wafer substrate is maximized by the substrate adsorption holding without using the mechanical chuck, thereby increasing the number of chips that can be obtained. Can do.
  • the conventional electrostatic adsorption apparatus 100 is an RIE (anode coupling) apparatus, and only an upper electrode for plasma generation exists, and the electrode 103 provided in the insulator 102 in the adsorption member 104 is predetermined.
  • An electrostatic adsorption principle is described in which a voltage is applied to electrostatically attract the insulating substrate 101.
  • the adsorption member 104 for electrostatically adsorbing the insulating substrate 101 is required separately.
  • the conventional substrate processing apparatus 200 disclosed in Patent Document 2 is an ICP (inductively coupled plasma) apparatus while securing a back surface He for cooling at a pressure necessary for achieving the process. Can be controlled independently. First, only the upper electrode is driven and controlled, the inert gas introduced into the processing chamber 204 is turned into plasma, and the wafer substrate is electrostatically adsorbed and held on the electrostatic chuck 201. The substrate adsorption holding process is separately performed before the stabilization process and the subsequent plasma etching process in which the processing gas is introduced into the processing chamber 204 from the processing gas supply unit 206 to adjust the processing gas pressure to a desired pressure.
  • ICP inductively coupled plasma
  • the present invention solves the above-mentioned conventional problems, and improves the number of chips per substrate by making the best use of the area on the insulator substrate, while eliminating the need for a separate adsorbing member and increasing the efficiency of manufacturing. It is an object of the present invention to provide a substrate processing apparatus, a substrate processing method using the same, and a semiconductor device manufacturing method using the same.
  • the substrate processing method of the present invention includes a substrate processing step in which a substrate is disposed in a processing chamber, power is independently supplied to each of the upper electrode and the lower electrode, and the processing gas in the processing chamber is turned into plasma to perform substrate processing.
  • power is supplied only to the upper electrode in the processing gas pressure adjustment step for adjusting the pressure of the processing gas supplied into the processing chamber to a predetermined pressure.
  • a process gas supplied into the process chamber is turned into plasma to charge the substrate and charge the substrate to electrostatically adsorb the substrate to the lower electrode side, thereby achieving the above object.
  • a gas species having a high electron emission rate that is more easily converted to plasma than an inert gas is selected as a processing gas in the substrate processing method of the present invention.
  • the gas species having a high electron emission rate that is easily converted to plasma in the substrate processing method of the present invention is a processing gas having an ionization potential lower than a predetermined value and a gas ionization voltage Vi lower than another predetermined value.
  • the processing gas in the substrate processing method of the present invention is a gas containing an element having an ionization potential of 320 kcal / mol or less as an adsorption gas.
  • the processing gas in the substrate processing method of the present invention is a gas containing at least one of O (oxygen) and Cl (chlorine).
  • the substrate is an insulating substrate, and the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • the substrate processing is performed by controlling the substrate temperature while cooling the substrate with a cooling medium introduced to the back surface of the substrate in the substrate processing method of the present invention.
  • the electrostatic attraction force that can ensure the pressure of the cooling medium necessary for cooling the back surface of the substrate in the substrate processing method of the present invention is secured.
  • the cooling medium necessary for cooling the back surface of the substrate in the substrate processing method of the present invention is He gas.
  • the RF power (applied voltage) to the upper electrode is 0.45 w / cm 2 or more and 75 w / cm 2 or less, or 500 W or more and 2000 W or less as a substrate processing condition in the substrate processing method of the present invention.
  • the RF power (applied voltage) is 500 W or more and 1200 W or less.
  • the substrate in the substrate processing method of the present invention is a sapphire substrate.
  • the substrate in the substrate processing method of the present invention is a SiC substrate or a compound semiconductor substrate.
  • the substrate in the substrate processing method of the present invention is provided with an insulating film that is easily affected by an electric charge and is easily charged with electric charges from the plasma.
  • the film that is susceptible to electrical influence in the substrate processing method of the present invention is a photoresist film.
  • the film state on the substrate in the substrate processing method of the present invention is a state in which the photoresist film remains during the substrate processing.
  • the method for manufacturing a semiconductor device of the present invention includes a plasma etching process using the substrate processing method of the present invention, whereby the above object is achieved.
  • the substrate processing apparatus of the present invention is a substrate processing apparatus in which a substrate is disposed in a processing chamber, power is independently supplied to each of an upper electrode and a lower electrode, and a processing gas in the processing chamber is turned into plasma to perform substrate processing.
  • the electric power is supplied only to the upper electrode, and the electron emission rate is higher than that of an inert gas.
  • the processing gas supplied into the processing chamber is turned into plasma to charge the substrate to charge the lower electrode.
  • the substrate processing can be performed in a state where the substrate is electrostatically adsorbed on the side, thereby achieving the above object.
  • a substrate processing method includes a substrate processing step in which a substrate is disposed in a processing chamber, power is independently supplied to each of the upper electrode and the lower electrode, and a processing gas in the processing chamber is turned into plasma to perform substrate processing.
  • the processing gas pressure adjusting step of adjusting the pressure of the processing gas supplied into the processing chamber to a predetermined pressure before the substrate processing step, the processing gas supplied to the processing chamber by supplying power only to the upper electrode is supplied.
  • There is a substrate adsorption step in which the substrate is charged to charge the substrate and electrostatically adsorb the substrate to the lower electrode side.
  • the area on the insulator substrate is maximized to improve the number of chips per substrate, and the process gas pressure adjustment process is also used as the substrate adsorption process. Therefore, manufacturing can be performed efficiently and manufacturing cost performance can be improved.
  • the processing gas supplied to the processing chamber by supplying power only to the upper electrode in the processing gas pressure adjusting step for adjusting the pressure of the processing gas supplied to the processing chamber to a predetermined pressure is converted into plasma. Since the substrate is charged and the substrate is electrostatically attracted to the lower electrode side, the suction member is separately used while making the most of the area on the insulator substrate and improving the number of chips per substrate. It is not necessary and manufacturing can be performed efficiently and manufacturing cost performance can be improved.
  • FIG. 1 It is a longitudinal cross-sectional view which shows the principal part structural example of the nitride semiconductor light-emitting device in Embodiment 2 of this invention. It is a schematic diagram for demonstrating the electrostatic attraction principle of the conventional electrostatic attraction apparatus currently disclosed by patent document 1.
  • FIG. It is a principal part block diagram which shows schematically the conventional substrate processing apparatus currently disclosed by patent document 2.
  • FIG. 1 It is a principal part block diagram which shows schematically the conventional substrate processing apparatus currently disclosed by patent document 2.
  • each thickness, length, etc. of the structural member in FIG. 1 and FIG. 10 are not limited to the structure to illustrate from a viewpoint on drawing preparation.
  • FIG. 1 is a main part configuration diagram schematically showing a cross-sectional structure of a substrate processing apparatus in Embodiment 1 of the present invention.
  • the substrate processing apparatus 1 in Embodiment 1 of the present invention is an ICP (inductively coupled plasma) apparatus
  • an upper electrode 3 and a lower electrode 4 provided in the processing chamber 2 can be controlled independently.
  • the wafer substrate 5 which is an insulating substrate is directly mounted on the lower electrode 4.
  • a wafer substrate 5 is disposed in a processing chamber 2 as a processing chamber, and power is independently supplied to each of the upper electrode 3 and the lower electrode 4.
  • the power is supplied only to the upper electrode 3 and the processing is supplied into the processing chamber 2 which has a higher electron emission rate and is more easily converted to plasma than the inert gas.
  • the substrate processing can be performed in a state where the gas is turned into plasma to charge the wafer substrate 5 and the wafer substrate 5 is electrostatically attracted to the lower electrode 4 side.
  • This substrate processing apparatus 1 controls only the upper electrode 3 to secure the back surface He for cooling at a pressure necessary for achieving the process, while keeping the surface area of the insulating substrate on the wafer substrate 5 without using a mechanical chuck as a chuck.
  • a process gas pressure adjusting process in which a process gas is introduced into the process chamber 2 instead of an inert gas and the process gas pressure is adjusted to a predetermined pressure as in the prior art, in a state where it is fully utilized by electrostatic adsorption.
  • the negative charge of the plasma 6 is charged on the wafer substrate 5 by the plasma 6 obtained by converting the processing gas into plasma, and the wafer substrate 5 is electrostatically adsorbed on the lower electrode 4 and held and fixed.
  • a holding step is provided. Thereafter, the upper electrode 3 and the lower electrode 4 are both controlled to perform a plasma etching process.
  • a gas species having a high electron emission rate is selected as a processing gas.
  • RF radio frequency
  • a plasma 6 of a gas species having a high electron emission rate is generated, and supply of electric charges sufficient to secure an adsorption force to the surface of the wafer substrate 5 is ensured.
  • the ESC voltage By applying the ESC voltage to the ESC electrode 7, it is possible to obtain a sufficient adsorption force on the surface of the lower electrode 4 of the wafer substrate 5 together with the charge charged on the surface of the wafer substrate 5.
  • the application timing of the ESC voltage to the ESC electrode 7 in the adsorption holding process starts at the start of the stability process.
  • the wafer substrate 5 as an insulating substrate is electrostatically attracted by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • FIG. 2 is a diagram showing the ionization voltage Vi of various gases.
  • Electrons in the plasma 6 are created by ionization of gas molecules or atoms. Ionization also occurs due to collisions between atoms and molecules in an excited state or photoionization due to light energy, but most of them are mainly direct ionization due to accelerated electron collisions. In order for gas molecules or atoms to ionize, a certain amount of energy must be obtained by collision. The minimum energy required for ionization is called an ionization voltage Vi, which varies depending on the type of gas as shown in FIG. It can be seen that rare gases such as He and Ar have a relatively high ionization voltage Vi of 10V to 20V, but alkali metals are easily ionized because the ionization voltage Vi is as low as 3V to 4V.
  • FIG. 3 is a diagram showing a long-period periodic table of atomic number, atomic radius (unit: angstrom), element symbol, electronegativity, and ionization potential (unit: kcal / mol).
  • the plurality of elements can be divided into non-metallic elements, metallic elements, metalloid elements, and rare gas elements.
  • the element symbols in italics are gases at room temperature.
  • Nonmetallic elements that are gaseous at room temperature are H, N, O, F, and Cl.
  • N is not used as an etching gas.
  • Elements having a low ionization potential (unit: kcal / mol) are O, F, and Cl. Therefore, a processing gas that is used for plasma etching and has a high electron emission rate that is easily converted to plasma may be selected from processing gases containing non-metallic elements O and Cl having a low ionization potential.
  • FIG. 4 is a diagram showing the relationship of the ionization potential (kcal / mol) to the gas ionization voltage Vi.
  • the gas ionization voltage Vi and the ionization potential (kcal / mol) have a correlation.
  • the lower the ionization potential (kcal / mol) the lower the ionization voltage Vi of the gas, and the gas species having a high electron emission rate that is easily plasmatized have a lower ionization potential and lower ionization voltage Vi of the gas. Processing gas.
  • a lower ionization potential tends to ionize at a lower voltage (applied voltage).
  • FIG. 5 is a graph showing the relationship between gas ionization voltage Vi and ionization potential (kcal / mol) for various gases.
  • the gas with lower ionization potential (kcal / mol) is more easily ionized, the electrostatic adsorption is better.
  • gaseous O2, O and Cl were good in electrostatic adsorption.
  • the processing gas containing Cl include Cl2 (chlorine), SiCl4 (silicon tetrachloride), and BCl3 (boron trichloride).
  • a layer such as a GaN layer can be etched using Cl2 (chlorine) or SiCl4 (silicon tetrachloride) as a processing gas.
  • An etching process using BCl 3 (boron trichloride) as a processing gas can form a surface uneven shape such as a sapphire substrate.
  • FIG. 6 is a diagram showing the wafer substrate temperature dependence of the concavo-convex shape aspect ratio on the surface of the wafer substrate 5.
  • the wafer substrate is obtained in order to obtain the desired concavo-convex shape aspect ratio on the surface of the sapphire substrate. It is necessary to set a temperature of 5.
  • the temperature of the wafer substrate 5 is affected by the temperature of the lower electrode 4 and the pressure of the back surface He that conveys the temperature of the lower electrode 4 when the wafer substrate 5 is warped.
  • FIG. 7 is a diagram showing the relationship of the He leak amount (CC) to the back surface He pressure (KPa) as the pressure dependence of the He leak amount.
  • the wafer substrate 5 cannot be cooled because it is controlled to a predetermined temperature.
  • the aspect ratio of the concavo-convex shape to be etched also changes and does not reach the desired aspect ratio. In order to prevent this, by securing the adsorption force, the leak amount of the back surface He is suppressed, and the uniformity of the in-plane temperature is improved, thereby increasing the shape margin of the uneven shape to be etched.
  • FIG. 8 is a diagram showing the relationship of the temperature of the wafer substrate to the backside He pressure (KPa) when the temperature of the lower electrode 4 is high or low.
  • the temperature of the substrate to be processed decreases as the backside He pressure (KPa) increases. This indicates that the temperature decreases when the temperature of the lower electrode 4 is 35 degrees Celsius and when the temperature of the lower electrode 4 is 55 degrees Celsius. As the pressure on the back surface He increases, the temperature of the wafer substrate 5 decreases. However, in order to obtain a desired uneven shape, it is necessary to control the temperature of the desired wafer substrate 5.
  • FIG. 9 is a diagram showing the relationship between the in-plane temperatures of the center and outer periphery of the wafer substrate with respect to the back surface cooling He pressure (Pa).
  • the temperature of the wafer substrate 5 becomes equal as the back surface cooling He pressure (Pa) increases at the center (Center) and the outer periphery (Top) of the wafer substrate 5.
  • Pa back surface cooling He pressure
  • the wafer substrate 5 is disposed in the processing chamber 2 as a processing chamber, and power is independently supplied to the upper electrode 3 and the lower electrode 4.
  • the pressure of the processing gas supplied into the processing chamber 2 is adjusted to a predetermined pressure before the substrate processing step of plasma etching processing
  • the processing gas supplied to the processing chamber 2 by supplying power only to the upper electrode 3 is turned into plasma to charge the wafer substrate 5 to the lower electrode 4 side.
  • a substrate adsorption step for electrostatically adsorbing the wafer substrate 5 is provided. In this case, a gas species having a high electron emission rate is selected as a processing gas to be used.
  • an adsorption gas containing an element having an ionization potential of 320 kcal / mol or less is used.
  • the processing gas is a gas containing at least one of O (oxygen) and Cl (chlorine) gas as an adsorption gas.
  • the substrate is an insulating substrate, and the wafer substrate 5 as an insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • the substrate processing is performed by controlling the substrate temperature while cooling the substrate with the cooling medium introduced to the back surface of the wafer substrate 5. It is necessary to secure an electrostatic attraction force that can ensure the pressure of the cooling medium necessary for cooling the back surface of the wafer substrate 5. He gas is used as a cooling medium necessary for cooling the back surface of the wafer substrate 5.
  • the RF power (applied voltage) to the upper electrode 3 is 0.45 w / cm 2 or more and 75 w / cm 2 or less, or 500 W or more and 2000 W or less. More preferably, the RF power (applied voltage) is 500 W or more and 1200 W or less as a substrate processing condition. The RF power of 1200 W to 2000 W is the current maximum output RF power.
  • the sapphire substrate is used as the wafer substrate 5, it may be a SiC substrate or a compound semiconductor substrate. It is preferable that the wafer substrate 5 is provided with an insulating film that is easily affected by an electric charge and is easily charged with electric charges from plasma because the electrostatic adsorption force is improved. Examples of the film that is susceptible to electrical influence include a photoresist film. Further, the film state on the wafer substrate 5 is preferably left with the photoresist film during the substrate processing in order to maintain the electrostatic attraction force.
  • the wafer substrate 5 is an insulating substrate, and the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
  • ESC electrostatic chuck
  • a gas species having a high electron emission rate that is easily converted to plasma is selected as the processing gas.
  • a gas species having a high electron emission rate that is easily converted to plasma is a processing gas having a low ionization potential and a low ionization voltage Vi.
  • More charge on the surface of the wafer substrate 5 is indispensable in order to secure the attractive force with the electrostatic chuck (ESC). More charging of the surface of the wafer substrate 5 depends on the element species having a low ionization potential and a low gas ionization voltage Vi.
  • FIG. 10 is a longitudinal sectional view showing an example of the configuration of the main part of the nitride semiconductor light-emitting device according to Embodiment 2 of the present invention.
  • the nitride semiconductor light emitting device 11 of the second embodiment has a film thickness of about 15 nm made of aluminum nitride (AlN) on a sapphire substrate 12, for example, as a substrate having a thickness of about 1300 ⁇ m with irregularities formed on the surface.
  • a buffer layer 13 is formed.
  • a non-doped GaN layer 14 made of non-doped GaN and having a thickness of about 500 nm is formed.
  • the n-type contact layer 15 (high carrier) having a film thickness of about 5 ⁇ m made of GaN doped with silicon (Si) 1 ⁇ 10 18 / cm 3 on the single crystalline substrate. (Concentration n + layer) is formed.
  • a multi-layer 16 is formed on the n-type contact layer 15, and a light-emitting layer 17 having a multi-quantum well structure is formed on the multi-layer 16.
  • the multi-layer 16 is formed by alternately laminating a plurality of first layers made of InxGa1-xN (0 ⁇ x ⁇ 0.3) and second layers made of GaN.
  • first layers made of InxGa1-xN (0 ⁇ x ⁇ 0.3) and second layers made of GaN.
  • this multilayer 16 for example, five pairs of a first layer made of In0.03Ga0.97N with a thickness of 3 nm and a second layer made of GaN with a thickness of 20 nm are stacked.
  • the first layer of the multi-layer 16 has a concentration of Si as one conductivity type impurity of 5 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 (more preferably 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ ).
  • the electrostatic breakdown energy (mJ / cm 2) that is added in the range of 3) and received by the light emitting layer 17 is 20 or more and 40 or less (more preferably, 20 or more and 35 or less).
  • the Si concentration corresponding to the minimum value of electrostatic breakdown energy (mJ / cm 2) is set.
  • the well layer of the light emitting layer 17 having a multiple quantum well structure is made of InyGa1-yN (0 ⁇ y ⁇ 0.3) containing at least In.
  • the light emitting layer 17 having a multiple quantum well structure has, for example, three pairs of well layers made of In0.2Ga0.8N with a thickness of 3 nm and barrier layers made of GaN with a thickness of 20 nm. .
  • an electron which is a p-type layer made of p-type Al0.15Ga0.85N with a thickness of 25 nm doped with Mg 2 ⁇ 1019 / cm3 on the light-emitting layer 17.
  • a block layer 18 is formed.
  • a p-type contact layer 19 made of p-type GaN having a thickness of 100 nm doped with 8 ⁇ 1019 Mg is formed on the electron block layer 18.
  • a translucent thin film electrode 20 (ITO) is formed by metal vapor deposition.
  • a p-electrode 21 is formed on part of the translucent thin film electrode 20.
  • the end of the n-type contact layer 15 is exposed partway, and the n-electrode 22 is formed thereon.
  • a protective film 23 for moisture resistance or the like made of a SiO2 film as a SixOy film is formed.
  • the protective film 23 includes the light-transmitting thin film electrode 20, the p-electrode 21, the n-electrode 22, and the exposed surface of the n-type contact layer 15, and further to the middle of the end of the n-type contact layer 15.
  • the electron blocking layer 18, the p-type contact layer 19, and the translucent thin film electrode 20 (ITO) are formed on the etching side surfaces.
  • the protective film 23 covers and protects the p electrode 21 and the n electrode 22 and the element surface.
  • the protective film 23 may have a single-layer structure of a SiO2 film, but may have a two-layer structure of a SiN film as a SixNy film and a SiO2 film as a SixOy film thereon. Further, the structure may be a two-layer structure in which the SiO2 film as the SixOy film and the SiN film as the SixNy film thereon are upside down. In these cases, the SiN film functions as a passivation film.
  • the protective film 23 has at least a SixOy film among a SixOy film, a SixNy film, and a SixOyNz film.
  • the method for manufacturing the nitride semiconductor light emitting device 11 includes a substrate receiving process for receiving the sapphire substrate 12 at a predetermined position, and a predetermined aspect ratio on the surface of the sapphire substrate 12.
  • a substrate receiving process for receiving the sapphire substrate 12 at a predetermined position and a predetermined aspect ratio on the surface of the sapphire substrate 12.
  • a buffer layer 13 On the surface unevenness processed surface of the sapphire substrate 12 by the MOCVD method, and a buffer layer 13, a non-doped GaN layer 14, an n-type contact layer 15, a multiple layer 16, and a multiple quantum well structure.
  • MOCVD step of sequentially forming the light emitting layer 17, the electron blocking layer 18 and the p-type contact layer 19 in this order, a transparent electrode forming step of forming the translucent thin film electrode 20 on the p-type contact layer 19, and the edge of the substrate Is etched halfway through the n-type contact layer 15 to expose the end of the n-type contact layer 15 in the middle, Forming the n-electrode 22 on the surface of the end portion of the light-emitting layer 15 and forming the p-electrode 21 on the partial surface of the translucent thin-film electrode 20; A protective film forming step for forming a protective film 23 for moisture resistance on the exposed surface of the conductive thin film electrode 20, the p electrode 21, the n electrode 22 and the n-type contact layer 15 and further on the side surface to which etching is removed; an electrode opening step for opening the protective film 23 on the n-electrode 22.
  • a surface unevenness forming step for forming unevenness on the surface of the sapphire substrate 12 and etching and removing the substrate end partway into the n-type contact layer 15.
  • An accurate and better plasma etching process is performed using the substrate processing method of the first embodiment in the etching process in which the end portion of the n-type contact layer 15 is exposed halfway.
  • the method for manufacturing the nitride semiconductor light emitting device 11 supplies power only to the upper electrode 3 in the process gas pressure adjusting step for adjusting the pressure of the process gas supplied into the process chamber 2 to a predetermined pressure.
  • a plasma etching process using the substrate processing method of the first embodiment in which the processing gas supplied into the processing chamber 2 is converted into plasma to charge the wafer substrate 5 and electrostatically attract the wafer substrate 5 to the lower electrode 4 side. Have.
  • the area on the insulator substrate is utilized to the maximum while the number of chips that can be taken per substrate is improved and the adsorption is performed.
  • a member is not required separately, and it can manufacture efficiently and can improve manufacturing cost performance.
  • this Embodiment 2 demonstrated the manufacturing method of the nitride semiconductor light-emitting element 11 of LED, it is not restricted to this, The manufacturing method of the semiconductor device which has a plasma etching process using the substrate processing method of the said Embodiment 1 If it is.
  • the present invention relates to a substrate processing apparatus used when performing predetermined processing such as plasma dry etching on a substrate to be processed while electrostatically attracting and fixing the substrate to be processed, a substrate processing method using the same, and
  • the processing gas supplied to the processing chamber by supplying power only to the upper electrode in the processing gas pressure adjusting step for adjusting the pressure of the processing gas supplied to the processing chamber to a predetermined pressure. Since the substrate is turned into plasma to charge the substrate and electrostatically adsorb the substrate to the lower electrode side, the adsorption member is improved while maximizing the area on the insulator substrate and improving the number of chips per substrate. The manufacturing cost performance can be improved by efficiently performing the manufacturing.

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Abstract

[Problem] To make full use of the area of an insulator substrate and improve the number of chips that can be produced per substrate while not requiring a separate attachment member and efficiently carrying out production in order to improve production cost performance. [Solution] A substrate treatment method that comprises a substrate treatment step in which a wafer substrate (5) is arranged within a treatment chamber (2) that serves as a treatment chamber, power is supplied independently to an upper electrode (3) and a lower electrode (4), and treatment gas within the treatment chamber (2) is plasmified in order to treat the substrate. A treatment gas pressure adjustment step (stability step) in which the pressure of a treatment gas that is supplied into the treatment chamber (2) is adjusted to a predetermined pressure is carried out prior to a substrate treatment step for plasma etching treatment, and said treatment gas pressure adjustment step includes a substrate attachment step in which power is supplied only to the upper electrode (3), the treatment gas supplied into the treatment chamber (2) is plasmified, the wafer substrate (5) is charged with an electrical load, and the wafer substrate (5) is electrostatically attached to the lower electrode (4) side.

Description

基板処理装置および基板処理方法、半導体装置の製造方法Substrate processing apparatus, substrate processing method, and semiconductor device manufacturing method
　本発明は、被処理基板を静電吸着して固定しつつ、被処理基板にプラズマドライエッチングなどの所定の処理を行う際に用いられる基板処理装置および、これを用いた基板処理方法、これを用いた半導体装置の製造方法に関する。 The present invention relates to a substrate processing apparatus used when performing predetermined processing such as plasma dry etching on a substrate to be processed while electrostatically attracting and fixing the substrate to be processed, a substrate processing method using the same, and The present invention relates to a method for manufacturing a used semiconductor device.
　従来、被処理基板のエッチングには、高真空下で行われるドライエッチングが採用されている。このドライエッチングはチャンバ内に被処理基板を配置し、チャンバ内にプラズマを形成して、そのプラズマによりエッチングを行っている。このようなドライエッチング処理において、プラズマドライエッチング特性は基板温度に大きく依存している。このため被処理基板を支持する基板支持部材に冷媒を通流させて基板温度を制御している。この場合、被処理基板と基板支持部材との間には冷媒の伝熱効率を向上させるためにＨｅガスなどの熱伝達ガスを流している。 Conventionally, dry etching performed under high vacuum has been adopted for etching a substrate to be processed. In this dry etching, a substrate to be processed is placed in a chamber, plasma is formed in the chamber, and etching is performed by the plasma. In such a dry etching process, the plasma dry etching characteristics greatly depend on the substrate temperature. For this reason, the substrate temperature is controlled by allowing a coolant to flow through the substrate support member that supports the substrate to be processed. In this case, a heat transfer gas such as He gas is allowed to flow between the substrate to be processed and the substrate support member in order to improve the heat transfer efficiency of the refrigerant.
　被処理基板は、ドライエッチング処理のために基板支持部材上に固定状態で支持する必要があり、このため、例えば被処理基板が半導体ウェハの場合には、この半導体ウェハをクーロン力のような静電力で基板支持部材上に吸着させて支持する静電吸着装置が用いられている。 The substrate to be processed needs to be supported in a fixed state on the substrate support member for the dry etching process. For this reason, for example, when the substrate to be processed is a semiconductor wafer, the semiconductor wafer is supported by a static force such as Coulomb force. An electrostatic attraction apparatus is used which is supported by being attracted onto a substrate support member with electric power.
　図１１は、特許文献１に開示されている従来の静電吸着装置の静電吸着原理を説明するための模式図である。 FIG. 11 is a schematic diagram for explaining the principle of electrostatic attraction of the conventional electrostatic attraction apparatus disclosed in Patent Document 1.
　図１１に示すように、従来の静電吸着装置１００は、プラズマが形成される空間に設けられ、絶縁基板１０１を絶縁体１０２側に吸着する。絶縁体１０２とその内部に設けられた電極１０３とから吸着部材１０４が構成されている。この吸着部材１０４は、基板支持部材１０５上に搭載されて支持されている。 As shown in FIG. 11, the conventional electrostatic adsorption device 100 is provided in a space where plasma is formed, and adsorbs the insulating substrate 101 to the insulator 102 side. An adsorbing member 104 is composed of the insulator 102 and the electrode 103 provided therein. The adsorption member 104 is mounted and supported on the substrate support member 105.
　プラズマが空間内に形成された状態で電極１０３に所定のＤＣ電圧を印加することにより、プラズマから絶縁基板１０１上に帯電して蓄積された電荷と電極１０３との間に生じる静電力により、絶縁基板１０１が吸着部材１０４の絶縁体１０２側に吸着されることになる。 By applying a predetermined DC voltage to the electrode 103 in a state where the plasma is formed in the space, insulation is generated by the electrostatic force generated between the charge charged and accumulated on the insulating substrate 101 from the plasma and the electrode 103. The substrate 101 is attracted to the insulator 102 side of the attracting member 104.
　図１２は、特許文献２に開示されている従来の基板処理装置を概略的に示す要部構成図である。 FIG. 12 is a main part configuration diagram schematically showing a conventional substrate processing apparatus disclosed in Patent Document 2. As shown in FIG.
　図１２に示すように、従来のプラズマ処理装置２００は、上面に絶縁基板Ｋが載置された静電チャック２０１の電極２０２，２０３に直流電圧を印加すると共に処理チャンバ２０４内に不活性ガス供給部２０５から不活性ガスを供給し、その不活性ガスをプラズマ化する。プラズマ化した不活性ガスから絶縁基板Ｋに帯電させて静電チャック２０１上に絶縁基板Ｋを吸着して保持する。その後、静電チャック２０１上に吸着，保持された絶縁基板Ｋの裏面と静電チャック２０１の上面との間に冷却ガスの供給を開始する。 As shown in FIG. 12, the conventional plasma processing apparatus 200 applies a DC voltage to the electrodes 202 and 203 of the electrostatic chuck 201 on which the insulating substrate K is mounted, and supplies an inert gas into the processing chamber 204. An inert gas is supplied from the unit 205, and the inert gas is turned into plasma. The insulating substrate K is charged from the plasma-ized inert gas, and the insulating substrate K is attracted and held on the electrostatic chuck 201. Thereafter, supply of cooling gas is started between the back surface of the insulating substrate K attracted and held on the electrostatic chuck 201 and the upper surface of the electrostatic chuck 201.
　次に、従来のプラズマ処理装置２００において、不活性ガスに代えプラズマ処理用の処理ガスを処理チャンバ２０４内に処理ガス供給部２０６から供給してその内部を処理ガスに置換すると共に、この処理ガスをプラズマ化して引き続き静電チャック２０１上に絶縁基板Ｋを吸着して保持する。その後、冷却ガス供給部２０７から冷却ガスを供給して冷却ガスにより絶縁基板Ｋを冷却しつつ、プラズマ化した処理ガスによって絶縁基板Ｋをプラズマエッチング処理する。 Next, in the conventional plasma processing apparatus 200, a processing gas for plasma processing is supplied from the processing gas supply unit 206 into the processing chamber 204 instead of the inert gas, and the processing gas is replaced with the processing gas. Then, the insulating substrate K is attracted and held on the electrostatic chuck 201. Thereafter, the insulating substrate K is plasma-etched by the plasma processing gas while cooling gas is supplied from the cooling gas supply unit 207 to cool the insulating substrate K with the cooling gas.
　排気装置２０８は、排気ポンプ２０９と、排気ポンプ２０９と下部容器２１０とを接続する排気管２１１とから構成され、排気管２１１を介して下部容器２１０内の気体を排気し、処理チャンバ２０４の内部の不活性ガスや処理ガスを所定圧力にしている。 The exhaust device 208 includes an exhaust pump 209 and an exhaust pipe 211 that connects the exhaust pump 209 and the lower container 210. The exhaust device 208 exhausts the gas in the lower container 210 through the exhaust pipe 211, and the inside of the processing chamber 204. The inert gas and the processing gas are set to a predetermined pressure.
　これによって、プラズマエッチング処理の開始前から絶縁基板Ｋを冷却し、絶縁基板Ｋの全面に対してプラズマエッチング処理を均一且つ効率的に行うことができる。 Thereby, the insulating substrate K can be cooled before the start of the plasma etching process, and the plasma etching process can be uniformly and efficiently performed on the entire surface of the insulating substrate K.
特開平１１－１１１８３０号公報JP-A-11-111830 特開２００９－１９４１９４号公報JP 2009-194194 A
　基板保持にメカニカルチャックを用いると、ウエハ基板の外周端縁部の少なくとも一部をメカニカルチャックが覆うためにチップ取れ数が削減されるところ、特許文献１に開示されている従来の静電吸着装置１００では、プロセス達成に必要な冷却用の裏面Ｈｅの圧力を確保しながら、メカニカルチャックを用いずに、基板吸着保持によりウエハ基板上の表面積を最大限に活用してチップ取れ数を増加させることができる。 When a mechanical chuck is used to hold the substrate, the number of chips that can be taken is reduced because the mechanical chuck covers at least a part of the outer peripheral edge of the wafer substrate. In 100, the pressure on the back surface He for cooling necessary for achieving the process is secured, and the surface area on the wafer substrate is maximized by the substrate adsorption holding without using the mechanical chuck, thereby increasing the number of chips that can be obtained. Can do.
　具体的には、従来の静電吸着装置１００では、ＲＩＥ（陽極結合）装置であってプラズマ生成用の上部電極だけが存在し、吸着部材１０４における絶縁体１０２内に設けられた電極１０３に所定電圧を印加して絶縁基板１０１を静電吸着させる静電吸着原理が説明されている。このように、絶縁基板１０１を静電吸着させるための吸着部材１０４が別途必要である。また、特許文献２でも後述するが、基板吸着保持工程を別途行わず、基板吸着保持用に処理ガスをプラズマ化してプラズマエッチング処理時に基板吸着保持工程を行うと予期しないところでプラズマエッチングが進んだりして正確なエッチング加工ができない。また、基板吸着保持工程を別途行うと、工程数が多くなって半導体装置の製造が効率的ではなくなる。 Specifically, the conventional electrostatic adsorption apparatus 100 is an RIE (anode coupling) apparatus, and only an upper electrode for plasma generation exists, and the electrode 103 provided in the insulator 102 in the adsorption member 104 is predetermined. An electrostatic adsorption principle is described in which a voltage is applied to electrostatically attract the insulating substrate 101. As described above, the adsorption member 104 for electrostatically adsorbing the insulating substrate 101 is required separately. As will be described later in Patent Document 2, if the substrate adsorption / holding step is not performed separately, the processing gas is converted into plasma for substrate adsorption / holding and the substrate adsorption / holding step is performed during the plasma etching process, plasma etching proceeds unexpectedly. Accurate etching process is not possible. Further, if the substrate adsorption holding process is performed separately, the number of processes increases and the semiconductor device is not efficiently manufactured.
　特許文献２に開示されている従来の基板処理装置２００では、プロセス達成に必要な圧力の冷却用の裏面Ｈｅを確保しながら、ICP（誘導結合プラズマ）装置であることから上部電極と下部電極とが独立して制御可能であり、まず、上部電極のみを駆動制御して、処理チャンバ２０４内に導入した不活性ガスをプラズマ化して静電チャック２０１上にウエハ基板を静電吸着して保持する基板吸着保持工程を、処理チャンバ２０４内に処理ガス供給部２０６から処理ガスを導入して処理ガス圧力を所望圧力に圧力調整するスタビリ工程およびその後のプラズマエッチング工程の前に別途行っている。これは、基板吸着保持工程を別途行わず、プラズマエッチング処理時に行うと予期しないところでプラズマエッチングが進んだりして正確なプラズマエッチング加工ができないためである。このように、基板吸着保持工程を別途行うと、工程数が多くなって半導体装置の製造が効率的ではなくなる。 The conventional substrate processing apparatus 200 disclosed in Patent Document 2 is an ICP (inductively coupled plasma) apparatus while securing a back surface He for cooling at a pressure necessary for achieving the process. Can be controlled independently. First, only the upper electrode is driven and controlled, the inert gas introduced into the processing chamber 204 is turned into plasma, and the wafer substrate is electrostatically adsorbed and held on the electrostatic chuck 201. The substrate adsorption holding process is separately performed before the stabilization process and the subsequent plasma etching process in which the processing gas is introduced into the processing chamber 204 from the processing gas supply unit 206 to adjust the processing gas pressure to a desired pressure. This is because if the substrate adsorption holding process is not performed separately and is performed during the plasma etching process, the plasma etching proceeds unexpectedly and accurate plasma etching cannot be performed. As described above, when the substrate adsorption holding process is performed separately, the number of processes increases and the semiconductor device is not efficiently manufactured.
　本発明は、上記従来の問題を解決するもので、絶縁体基板上の面積を最大限活用して基板１枚当たりのチップ取れ数を向上させつつ、吸着部材を別途必要とせず、製造を効率的に行って製造コストパフォーマンスを向上させることができる基板処理装置および、これを用いた基板処理方法、これを用いた半導体装置の製造方法を提供することを目的とする。 The present invention solves the above-mentioned conventional problems, and improves the number of chips per substrate by making the best use of the area on the insulator substrate, while eliminating the need for a separate adsorbing member and increasing the efficiency of manufacturing. It is an object of the present invention to provide a substrate processing apparatus, a substrate processing method using the same, and a semiconductor device manufacturing method using the same.
　本発明の基板処理方法は、処理室内に基板を配置し、上部電極と下部電極それぞれに独立して電力を供給して、該処理室内の処理ガスをプラズマ化して基板処理を行う基板処理工程を有する基板処理方法において、該基板処理工程の前に、該処理室内に供給する該処理ガスの圧力を所定圧力に調整する処理ガス圧力調整工程内に、該上部電極のみに電力を供給して該処理室内に供給した処理ガスをプラズマ化して該基板に電荷を帯電させて該下部電極側に該基板を静電吸着させる基板吸着工程を有するものであり、そのことにより上記目的が達成される。 The substrate processing method of the present invention includes a substrate processing step in which a substrate is disposed in a processing chamber, power is independently supplied to each of the upper electrode and the lower electrode, and the processing gas in the processing chamber is turned into plasma to perform substrate processing. In the substrate processing method of the present invention, before the substrate processing step, power is supplied only to the upper electrode in the processing gas pressure adjustment step for adjusting the pressure of the processing gas supplied into the processing chamber to a predetermined pressure. A process gas supplied into the process chamber is turned into plasma to charge the substrate and charge the substrate to electrostatically adsorb the substrate to the lower electrode side, thereby achieving the above object.
　また、好ましくは、本発明の基板処理方法における処理ガスとして不活性ガスに比べてプラズマ化し易い電子放出率の高いガス種を選択する。 Also preferably, a gas species having a high electron emission rate that is more easily converted to plasma than an inert gas is selected as a processing gas in the substrate processing method of the present invention.
　さらに、好ましくは、本発明の基板処理方法におけるプラズマ化し易い電子放出率の高いガス種は、イオン化ポテンシャルが所定値よりも低く気体の電離電圧Ｖｉも別の所定値よりも低い処理ガスである。 Furthermore, preferably, the gas species having a high electron emission rate that is easily converted to plasma in the substrate processing method of the present invention is a processing gas having an ionization potential lower than a predetermined value and a gas ionization voltage Vi lower than another predetermined value.
　さらに、好ましくは、本発明の基板処理方法における処理ガスは、吸着用ガスとしてイオン化ポテンシャルが３２０ｋｃａｌ/ｍｏｌ以下の元素を含むガスである。 Further preferably, the processing gas in the substrate processing method of the present invention is a gas containing an element having an ionization potential of 320 kcal / mol or less as an adsorption gas.
　さらに、好ましくは、本発明の基板処理方法における処理ガスは、Ｏ(酸素)およびＣｌ(塩素)のうちの少なくともいずれかを含むガスである。 Further preferably, the processing gas in the substrate processing method of the present invention is a gas containing at least one of O (oxygen) and Cl (chlorine).
　さらに、好ましくは、本発明の基板処理方法における基板吸着工程は、前記基板が絶縁基板であり、静電チャック（ＥＳＣ）により該絶縁基板を静電吸着させる。 Further preferably, in the substrate adsorption step in the substrate processing method of the present invention, the substrate is an insulating substrate, and the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
　さらに、好ましくは、本発明の基板処理方法における基板の裏面に導入する冷却媒体により基板を冷却しながら基板温度を制御して前記基板処理を行う。 Further preferably, the substrate processing is performed by controlling the substrate temperature while cooling the substrate with a cooling medium introduced to the back surface of the substrate in the substrate processing method of the present invention.
　さらに、好ましくは、本発明の基板処理方法における基板の裏面冷却に必要な冷却媒体の圧力を確保可能とする静電吸着力を確保している。 Furthermore, preferably, the electrostatic attraction force that can ensure the pressure of the cooling medium necessary for cooling the back surface of the substrate in the substrate processing method of the present invention is secured.
　さらに、好ましくは、本発明の基板処理方法における基板の裏面冷却に必要な冷却媒体は、Ｈｅガスである。 Further preferably, the cooling medium necessary for cooling the back surface of the substrate in the substrate processing method of the present invention is He gas.
　さらに、好ましくは、本発明の基板処理方法における基板処理の条件として前記上部電極へのＲＦパワー（印加電圧)を０．４５ｗ/ｃｍ２以上７５ｗ/ｃｍ２以下または５００Ｗ以上２０００Ｗ以下とする。 Further preferably, the RF power (applied voltage) to the upper electrode is 0.45 w / cm 2 or more and 75 w / cm 2 or less, or 500 W or more and 2000 W or less as a substrate processing condition in the substrate processing method of the present invention.
　さらに、好ましくは、本発明の基板処理方法における基板処理の条件としてＲＦパワー（印加電圧)は５００Ｗ以上１２００Ｗ以下である。 Further preferably, as a substrate processing condition in the substrate processing method of the present invention, the RF power (applied voltage) is 500 W or more and 1200 W or less.
　さらに、好ましくは、本発明の基板処理方法における基板はサファイア基板である。 Further preferably, the substrate in the substrate processing method of the present invention is a sapphire substrate.
　さらに、好ましくは、本発明の基板処理方法における基板はＳｉＣ基板または化合物半導体基板である。 Further preferably, the substrate in the substrate processing method of the present invention is a SiC substrate or a compound semiconductor substrate.
　さらに、好ましくは、本発明の基板処理方法における基板には電気的影響を受けやすい膜であって前記プラズマからの電荷が帯電し易い絶縁性膜が設けられている。 Furthermore, preferably, the substrate in the substrate processing method of the present invention is provided with an insulating film that is easily affected by an electric charge and is easily charged with electric charges from the plasma.
　さらに、好ましくは、本発明の基板処理方法における電気的影響を受けやすい膜はフォトレジスト膜である。 Furthermore, preferably, the film that is susceptible to electrical influence in the substrate processing method of the present invention is a photoresist film.
　さらに、好ましくは、本発明の基板処理方法における基板上の膜状態は基板処理中は前記フォトレジスト膜が残っている状態である。 Further preferably, the film state on the substrate in the substrate processing method of the present invention is a state in which the photoresist film remains during the substrate processing.
　本発明の半導体装置の製造方法は、本発明の上記基板処理方法を用いたプラズマエッチング工程を有したものであり、そのことにより上記目的が達成される。 The method for manufacturing a semiconductor device of the present invention includes a plasma etching process using the substrate processing method of the present invention, whereby the above object is achieved.
　本発明の基板処理装置は、処理室内に基板を配置し、上部電極と下部電極それぞれに独立して電力を供給して、該処理室内の処理ガスをプラズマ化して基板処理を行う基板処理装置において、該上部電極のみに電力を供給して、不活性ガスに比べてプラズマ化し易い電子放出率の高い、該処理室内に供給した処理ガスをプラズマ化して該基板に電荷を帯電させて該下部電極側に該基板を静電吸着させた状態で該基板処理が実施可能となるものであり、そのことにより上記目的が達成される。 The substrate processing apparatus of the present invention is a substrate processing apparatus in which a substrate is disposed in a processing chamber, power is independently supplied to each of an upper electrode and a lower electrode, and a processing gas in the processing chamber is turned into plasma to perform substrate processing. The electric power is supplied only to the upper electrode, and the electron emission rate is higher than that of an inert gas. The processing gas supplied into the processing chamber is turned into plasma to charge the substrate to charge the lower electrode. The substrate processing can be performed in a state where the substrate is electrostatically adsorbed on the side, thereby achieving the above object.
　上記構成により、以下、本発明の作用を説明する。 The operation of the present invention will be described below with the above configuration.
　本発明においては、処理室内に基板を配置し、上部電極と下部電極それぞれに独立して電力を供給して、処理室内の処理ガスをプラズマ化して基板処理を行う基板処理工程を有する基板処理方法において、基板処理工程の前に、処理室内に供給する該処理ガスの圧力を所定圧力に調整する処理ガス圧力調整工程内に、上部電極のみに電力を供給して処理室内に供給した処理ガスをプラズマ化して基板に電荷を帯電させて下部電極側に基板を静電吸着させる基板吸着工程を有している。 In the present invention, a substrate processing method includes a substrate processing step in which a substrate is disposed in a processing chamber, power is independently supplied to each of the upper electrode and the lower electrode, and a processing gas in the processing chamber is turned into plasma to perform substrate processing. In the processing gas pressure adjusting step of adjusting the pressure of the processing gas supplied into the processing chamber to a predetermined pressure before the substrate processing step, the processing gas supplied to the processing chamber by supplying power only to the upper electrode is supplied. There is a substrate adsorption step in which the substrate is charged to charge the substrate and electrostatically adsorb the substrate to the lower electrode side.
　これによって、絶縁体基板上の面積を最大限活用して基板１枚当たりのチップ取れ数を向上させつつ、処理ガス圧力調整工程に基板吸着工程を兼用させているため、吸着部材を別途必要とせず、製造を効率的に行って製造コストパフォーマンスを向上させることができる As a result, the area on the insulator substrate is maximized to improve the number of chips per substrate, and the process gas pressure adjustment process is also used as the substrate adsorption process. Therefore, manufacturing can be performed efficiently and manufacturing cost performance can be improved.
　以上により、本発明によれば、処理室内に供給する処理ガスの圧力を所定圧力に調整する処理ガス圧力調整工程内に、上部電極のみに電力を供給して処理室内に供給した処理ガスをプラズマ化して基板に電荷を帯電させて下部電極側に基板を静電吸着させるため、絶縁体基板上の面積を最大限活用して基板１枚当たりのチップ取れ数を向上させつつ、吸着部材を別途必要とせず、製造を効率的に行って製造コストパフォーマンスを向上させることができる。 As described above, according to the present invention, the processing gas supplied to the processing chamber by supplying power only to the upper electrode in the processing gas pressure adjusting step for adjusting the pressure of the processing gas supplied to the processing chamber to a predetermined pressure is converted into plasma. Since the substrate is charged and the substrate is electrostatically attracted to the lower electrode side, the suction member is separately used while making the most of the area on the insulator substrate and improving the number of chips per substrate. It is not necessary and manufacturing can be performed efficiently and manufacturing cost performance can be improved.
本発明の実施形態１における基板処理装置の断面構造を模式的に示す要部構成図である。It is a principal part block diagram which shows typically the cross-section of the substrate processing apparatus in Embodiment 1 of this invention. 各種気体の電離電圧Ｖｉを示す図である。It is a figure which shows the ionization voltage Vi of various gas. 原子番号、原子半径（単位はオングストローム）、元素記号、電気陰性度、イオン化ポテンシャル（単位はｋｃａｌ／ｍｏｌ）の長周期型周期表を示す図である。It is a figure which shows the long period type | mold periodic table of an atomic number, an atomic radius (a unit is angstrom), an element symbol, an electronegativity, and ionization potential (a unit is kcal / mol). 気体の電離電圧Ｖｉに対するイオン化ポテンシャル（ｋｃａｌ／ｍｏｌ）の関係を示す図である。It is a figure which shows the relationship of the ionization potential (kcal / mol) with respect to the ionization voltage Vi of gas. 各種気体に対する気体の電離電圧Ｖｉとイオン化ポテンシャル（ｋｃａｌ／ｍｏｌ）の関係を示す図である。It is a figure which shows the relationship between ionization voltage Vi and ionization potential (kcal / mol) of various gases. ウエハ基板５の温度に対するウエハ基板（サファイア基板）でその表面の凹凸形状のアスペクト比の関係を示す図である。It is a figure which shows the relationship of the aspect ratio of the uneven | corrugated shape of the surface with the wafer substrate (sapphire substrate) with respect to the temperature of the wafer substrate. Ｈｅリーク量の圧力依存性として、裏面Ｈｅ圧力（ＫＰａ）に対するＨｅリーク量（ＣＣ）の関係を示す図である。It is a figure which shows the relationship of He leak amount (CC) with respect to back surface He pressure (KPa) as pressure dependence of He leak amount. 下部電極４の温度の高低における裏面Ｈｅ圧力（ＫＰａ）に対するウエハ基板の温度の関係を示す図である。It is a figure which shows the relationship of the temperature of a wafer substrate with respect to the back surface He pressure (KPa) in the level of the temperature of the lower electrode. 裏面冷却Ｈｅ圧力（Ｐａ）に対するウエハ基板の中央と外周の面内温度の関係を示す図である。It is a figure which shows the relationship of the in-plane temperature of the center of a wafer substrate and an outer periphery with respect to back surface cooling He pressure (Pa). 本発明の実施形態２における窒化物半導体発光素子の要部構成例を示す縦断面図である。It is a longitudinal cross-sectional view which shows the principal part structural example of the nitride semiconductor light-emitting device in Embodiment 2 of this invention. 特許文献１に開示されている従来の静電吸着装置の静電吸着原理を説明するための模式図である。It is a schematic diagram for demonstrating the electrostatic attraction principle of the conventional electrostatic attraction apparatus currently disclosed by patent document 1. FIG. 特許文献２に開示されている従来の基板処理装置を概略的に示す要部構成図である。It is a principal part block diagram which shows schematically the conventional substrate processing apparatus currently disclosed by patent document 2. FIG.
　１　基板処理装置
　２　処理チャンバ
　３　上部電極
　４　下部電極
　５　ウエハ基板
　６　プラズマ
　７　ＥＳＣ電極
　１１　窒化物半導体発光素子
　１２　サファイヤ基板
　１３　バッファ層
　１４　ノンドープＧａＮ層
　１５　ｎ型コンタクト層
　１６　多重層
　１７　多重量子井戸構造の発光層
　１８　電子ブロック層
　１９　ｐ型コンタクト層
　２０　透光性薄膜電極
　２１　ｐ電極
　２２　ｎ電極
　２３　保護膜 DESCRIPTION OF SYMBOLS 1 Substrate processing apparatus 2 Processing chamber 3 Upper electrode 4 Lower electrode 5 Wafer substrate 6 Plasma 7 ESC electrode 11 Nitride semiconductor light emitting element 12 Sapphire substrate 13 Buffer layer 14 Non-doped GaN layer 15 N-type contact layer 16 Multiple layer 17 Multiple quantum well structure Light emitting layer 18 electron blocking layer 19 p-type contact layer 20 translucent thin film electrode 21 p electrode 22 n electrode 23 protective film
　以下に、本発明の基板処理方法の実施形態１および、これを用いた半導体装置の製造方法の実施形態２について図面を参照しながら詳細に説明する。なお、図１および図１０における構成部材のそれぞれの厚みや長さなどは図面作成上の観点から、図示する構成に限定されるものではない。 Hereinafter, Embodiment 1 of a substrate processing method of the present invention and Embodiment 2 of a semiconductor device manufacturing method using the same will be described in detail with reference to the drawings. In addition, each thickness, length, etc. of the structural member in FIG. 1 and FIG. 10 are not limited to the structure to illustrate from a viewpoint on drawing preparation.
　（実施形態１）
　図１は、本発明の実施形態１における基板処理装置の断面構造を模式的に示す要部構成図である。 (Embodiment 1)
FIG. 1 is a main part configuration diagram schematically showing a cross-sectional structure of a substrate processing apparatus in Embodiment 1 of the present invention.
　図１において、本発明の実施形態１における基板処理装置１は、ＩＣＰ（誘導結合プラズマ）装置であることから処理チャンバ２内に設けられた上部電極３と下部電極４とが独立して制御可能であり、下部電極４上に絶縁基板のウエハ基板５を直に搭載している。 In FIG. 1, since the substrate processing apparatus 1 in Embodiment 1 of the present invention is an ICP (inductively coupled plasma) apparatus, an upper electrode 3 and a lower electrode 4 provided in the processing chamber 2 can be controlled independently. The wafer substrate 5 which is an insulating substrate is directly mounted on the lower electrode 4.
　本実施形態１の基板処理装置１は、処理室としての処理チャンバ２内にウエハ基板５を配置し、上部電極３と下部電極４それぞれに独立して電力を供給して、処理チャンバ２内の処理ガスをプラズマ化して基板処理を行う基板処理装置１において、上部電極３のみに電力を供給して、不活性ガスに比べてプラズマ化し易い電子放出率の高い、処理チャンバ２内に供給した処理ガスをプラズマ化してウエハ基板５に電荷を帯電させて下部電極４側にウエハ基板５を静電吸着させた状態で基板処理が実施可能となるように構成されている。 In the substrate processing apparatus 1 according to the first embodiment, a wafer substrate 5 is disposed in a processing chamber 2 as a processing chamber, and power is independently supplied to each of the upper electrode 3 and the lower electrode 4. In the substrate processing apparatus 1 for processing a substrate by converting the processing gas into plasma, the power is supplied only to the upper electrode 3 and the processing is supplied into the processing chamber 2 which has a higher electron emission rate and is more easily converted to plasma than the inert gas. The substrate processing can be performed in a state where the gas is turned into plasma to charge the wafer substrate 5 and the wafer substrate 5 is electrostatically attracted to the lower electrode 4 side.
　この基板処理装置１は、上部電極３だけを制御して、プロセス達成に必要な圧力の冷却用の裏面Ｈｅを確保しながら絶縁基板のウエハ基板５上の表面積を、メカニカルチャックをチャックを用いず、静電吸着により最大限に活用した状態で、従来のように不活性ガスではなく処理ガスを処理チャンバ２内に導入して処理ガス圧力を所定圧力に調整する処理ガス圧力調整工程（スタビリティ工程）内で、処理ガスをプラズマ化したプラズマ６により、ウエハ基板５上にプラズマ６の陰電荷を帯電させて、下部電極４上にウエハ基板５を静電吸着してこれを保持固定する吸着保持工程を設けている。その後、上部電極３と下部電極４とが共に制御されてプラズマエッチング工程が実施される。 This substrate processing apparatus 1 controls only the upper electrode 3 to secure the back surface He for cooling at a pressure necessary for achieving the process, while keeping the surface area of the insulating substrate on the wafer substrate 5 without using a mechanical chuck as a chuck. A process gas pressure adjusting process (stability) in which a process gas is introduced into the process chamber 2 instead of an inert gas and the process gas pressure is adjusted to a predetermined pressure as in the prior art, in a state where it is fully utilized by electrostatic adsorption. In the step), the negative charge of the plasma 6 is charged on the wafer substrate 5 by the plasma 6 obtained by converting the processing gas into plasma, and the wafer substrate 5 is electrostatically adsorbed on the lower electrode 4 and held and fixed. A holding step is provided. Thereafter, the upper electrode 3 and the lower electrode 4 are both controlled to perform a plasma etching process.
　この吸着保持工程において、処理ガスとして電子放出率の高いガス種を選択する。上部電極３のみのＲＦ印加により、その電子放出率の高いガス種のプラズマ６を生成し、ウエハ基板５の表面への吸着力確保に十分な電荷の供給を確保する。ＥＳＣ電極７へのＥＳＣ電圧の印加により、ウエハ基板５の表面に帯電された電荷と合わせて十分なウエハ基板５の下部電極４の表面への吸着力を得ることができる。吸着保持工程のＥＳＣ電極７へのＥＳＣ電圧の印加タイミングは、スタビリティ工程の開始時に開始する。基板吸着工程は、絶縁基板のウエハ基板５を、静電チャック（ＥＳＣ）により静電吸着させる。 In this adsorption / holding step, a gas species having a high electron emission rate is selected as a processing gas. By applying RF only to the upper electrode 3, a plasma 6 of a gas species having a high electron emission rate is generated, and supply of electric charges sufficient to secure an adsorption force to the surface of the wafer substrate 5 is ensured. By applying the ESC voltage to the ESC electrode 7, it is possible to obtain a sufficient adsorption force on the surface of the lower electrode 4 of the wafer substrate 5 together with the charge charged on the surface of the wafer substrate 5. The application timing of the ESC voltage to the ESC electrode 7 in the adsorption holding process starts at the start of the stability process. In the substrate suction step, the wafer substrate 5 as an insulating substrate is electrostatically attracted by an electrostatic chuck (ESC).
　上部電極３と下部電極４のＲＦ個別制御、ＥＳＣ方式の採用およびウエハ基板５の絶縁体表面への電子放出率が効果的になる条件(ガス種、ＲＦ ＰＯＷＥＲ、印加タイミングなど)の選択を行う。要するに、処理ガスとしてプラズマ化し易い電子放出率の高いガス種を選択する。これについて図２～図５を用いて説明する。 Individual control of the RF of the upper electrode 3 and the lower electrode 4, adoption of the ESC method, and selection of conditions (gas type, RF power, application timing, etc.) that make the electron emission rate to the insulator surface of the wafer substrate 5 effective. . In short, a gas species having a high electron emission rate that is easily plasmatized is selected as the processing gas. This will be described with reference to FIGS.
　図２は、各種気体の電離電圧Ｖｉを示す図である。 FIG. 2 is a diagram showing the ionization voltage Vi of various gases.
　プラズマ６中の電子は、気体分子または原子の電離によって作られる。電離は、励起状態にある原子、分子同士の衝突または、光エネルギーによる光電離によっても起こるが、大部分は加速された電子の衝突による直接電離が主なものとなる。気体分子または原子が電離するためには、衝突によってある一定以上のエネルギーを得なければならない。電離に必要な最低エネルギーを電離電圧Ｖｉと呼び、図２に示すように、気体の種類によって異なっている。ＨｅやＡｒなどの希ガス類は電離電圧Ｖｉが１０Ｖ～２０Ｖと比較的高いが、アルカリ金属は電離電圧Ｖｉが３Ｖ～４Ｖと低いので電離し易いことが分かる。 Electrons in the plasma 6 are created by ionization of gas molecules or atoms. Ionization also occurs due to collisions between atoms and molecules in an excited state or photoionization due to light energy, but most of them are mainly direct ionization due to accelerated electron collisions. In order for gas molecules or atoms to ionize, a certain amount of energy must be obtained by collision. The minimum energy required for ionization is called an ionization voltage Vi, which varies depending on the type of gas as shown in FIG. It can be seen that rare gases such as He and Ar have a relatively high ionization voltage Vi of 10V to 20V, but alkali metals are easily ionized because the ionization voltage Vi is as low as 3V to 4V.
　図３は、原子番号、原子半径（単位はオングストローム）、元素記号、電気陰性度、イオン化ポテンシャル（単位はｋｃａｌ／ｍｏｌ）の長周期型周期表を示す図である。 FIG. 3 is a diagram showing a long-period periodic table of atomic number, atomic radius (unit: angstrom), element symbol, electronegativity, and ionization potential (unit: kcal / mol).
　図３に示すように、複数の元素は、非金属元素、金属元素、半金属元素および希ガス元素に分けることができる。このうち、元素記号が斜字体のものが常温で気体である。常温で気体の非金属元素は、Ｈ、Ｎ、Ｏ、Ｆ、Ｃｌである。この中でＮはエッチングガスとしては用いない。イオン化ポテンシャル（単位はｋｃａｌ／ｍｏｌ）が低い元素はＯ、Ｆ、Ｃｌである。したがって、プラズマエッチング処理に用いる処理ガスであって、プラズマ化し易い電子放出率の高いガス種は、イオン化ポテンシャルが低い非金属元素のＯ、Ｃｌを含む処理ガスを選択すればよい。 As shown in FIG. 3, the plurality of elements can be divided into non-metallic elements, metallic elements, metalloid elements, and rare gas elements. Of these, the element symbols in italics are gases at room temperature. Nonmetallic elements that are gaseous at room temperature are H, N, O, F, and Cl. Among these, N is not used as an etching gas. Elements having a low ionization potential (unit: kcal / mol) are O, F, and Cl. Therefore, a processing gas that is used for plasma etching and has a high electron emission rate that is easily converted to plasma may be selected from processing gases containing non-metallic elements O and Cl having a low ionization potential.
　なお、希ガス元素は化合物を作らないので、それについての電気陰性度はここでは記載されていない。 It should be noted that since noble gas elements do not form compounds, their electronegativity is not described here.
　図４は、気体の電離電圧Ｖｉに対するイオン化ポテンシャル（ｋｃａｌ／ｍｏｌ）の関係を示す図である。 FIG. 4 is a diagram showing the relationship of the ionization potential (kcal / mol) to the gas ionization voltage Vi.
　図４において、気体の電離電圧Ｖｉとイオン化ポテンシャル（ｋｃａｌ／ｍｏｌ）は、相関関係がある。要するに、イオン化ポテンシャル（ｋｃａｌ／ｍｏｌ）が低ければ低いほど、気体の電離電圧Ｖｉもリニアに低くなり、プラズマ化し易い電子放出率の高いガス種は、イオン化ポテンシャルが低く、気体の電離電圧Ｖｉも低い処理ガスである。イオン化ポテンシャルが低い方が低い電圧（印加電圧）でイオン化し易い。 In FIG. 4, the gas ionization voltage Vi and the ionization potential (kcal / mol) have a correlation. In short, the lower the ionization potential (kcal / mol), the lower the ionization voltage Vi of the gas, and the gas species having a high electron emission rate that is easily plasmatized have a lower ionization potential and lower ionization voltage Vi of the gas. Processing gas. A lower ionization potential tends to ionize at a lower voltage (applied voltage).
　図５は、各種気体に対する気体の電離電圧Ｖｉとイオン化ポテンシャル（ｋｃａｌ／ｍｏｌ）の関係を示す図である。 FIG. 5 is a graph showing the relationship between gas ionization voltage Vi and ionization potential (kcal / mol) for various gases.
　図５において、イオン化ポテンシャル（ｋｃａｌ／ｍｏｌ）の低い気体ほど電離し易いため、静電吸着が良好である。具体的には、気体のＯ２、ＯおよびＣｌが静電吸着において良好であった。Ｃｌを含む処理ガスとしてＣｌ２（塩素）、ＳｉＣｌ４（４塩化シリコン）、ＢＣｌ３（３塩化ホウ素）などがある。Ｃｌ２（塩素）やＳｉＣｌ４（４塩化シリコン）を処理ガスとして用いてＧａＮ層などの層をエッチング処理することができる。ＢＣｌ３（３塩化ホウ素）を処理ガスとして用いてエッチング処理してサファイア基板などの表面凹凸形状を形成することができる。 In FIG. 5, since the gas with lower ionization potential (kcal / mol) is more easily ionized, the electrostatic adsorption is better. Specifically, gaseous O2, O and Cl were good in electrostatic adsorption. Examples of the processing gas containing Cl include Cl2 (chlorine), SiCl4 (silicon tetrachloride), and BCl3 (boron trichloride). A layer such as a GaN layer can be etched using Cl2 (chlorine) or SiCl4 (silicon tetrachloride) as a processing gas. An etching process using BCl 3 (boron trichloride) as a processing gas can form a surface uneven shape such as a sapphire substrate.
　図６は、ウエハ基板５の表面における凹凸形状アスペクト比のウエハ基板温度依存性を示す図である。 FIG. 6 is a diagram showing the wafer substrate temperature dependence of the concavo-convex shape aspect ratio on the surface of the wafer substrate 5.
　図６において、ウエハ基板５の温度に応じてウエハ基板５（サファイア基板）の表面の凹凸形状のアスペクト比が変化することから、所望のサファイア基板表面の凹凸形状のアスペクト比を得るためにウエハ基板５の温度を設定する必要がある。ウエハ基板５の温度は、下部電極４の温度と、ウエハ基板５が反っている場合は下部電極４の温度を伝える裏面Ｈｅの圧力とに影響される。 In FIG. 6, since the aspect ratio of the concavo-convex shape on the surface of the wafer substrate 5 (sapphire substrate) changes according to the temperature of the wafer substrate 5, the wafer substrate is obtained in order to obtain the desired concavo-convex shape aspect ratio on the surface of the sapphire substrate. It is necessary to set a temperature of 5. The temperature of the wafer substrate 5 is affected by the temperature of the lower electrode 4 and the pressure of the back surface He that conveys the temperature of the lower electrode 4 when the wafer substrate 5 is warped.
　図７は、Ｈｅリーク量の圧力依存性として、裏面Ｈｅ圧力（ＫＰａ）に対するＨｅリーク量（ＣＣ）の関係を示す図である。 FIG. 7 is a diagram showing the relationship of the He leak amount (CC) to the back surface He pressure (KPa) as the pressure dependence of the He leak amount.
　図７において、裏面Ｈｅ圧力（ＫＰａ）が大きいほど裏面Ｈｅのリーク量も多くなる。ウエハ基板５の反り量が大きいほど裏面Ｈｅのリーク量も多くなる。リーク量が多くなると、ウエハ基板５は所定の温度に制御するために冷却できない。このように、リーク量が多くなると、ウエハ基板５を所望の温度に制御できないことから、エッチングされる凹凸形状のアスペクト比も変化して所望のアスペクト比にならない。これを防ぐために、吸着力を確保することにより、裏面Ｈｅのリーク量が抑えられて、面内温度の均一性が向上し、これによって、エッチングされる凹凸形状の形状マージンもアップする。 In FIG. 7, the larger the back surface He pressure (KPa), the greater the back surface He leak amount. The larger the warp amount of the wafer substrate 5, the greater the leak amount of the back surface He. If the amount of leakage increases, the wafer substrate 5 cannot be cooled because it is controlled to a predetermined temperature. As described above, when the amount of leakage increases, the wafer substrate 5 cannot be controlled to a desired temperature, and the aspect ratio of the concavo-convex shape to be etched also changes and does not reach the desired aspect ratio. In order to prevent this, by securing the adsorption force, the leak amount of the back surface He is suppressed, and the uniformity of the in-plane temperature is improved, thereby increasing the shape margin of the uneven shape to be etched.
　図８は、下部電極４の温度の高低における裏面Ｈｅ圧力（ＫＰａ）に対するウエハ基板の温度の関係を示す図である。 FIG. 8 is a diagram showing the relationship of the temperature of the wafer substrate to the backside He pressure (KPa) when the temperature of the lower electrode 4 is high or low.
　図８において、裏面Ｈｅ圧力（ＫＰａ）が高くなるほど、被処理基板の温度が下がる。これは、下部電極４の温度が摂氏３５度の場合と下部電極４の温度が摂氏５５度の場合、共に下がることを示している。裏面Ｈｅの圧力が高くなるほど、ウエハ基板５としては温度が下がるが、所望の凹凸形状を得るために所望のウエハ基板５の温度に制御する必要がある。 In FIG. 8, the temperature of the substrate to be processed decreases as the backside He pressure (KPa) increases. This indicates that the temperature decreases when the temperature of the lower electrode 4 is 35 degrees Celsius and when the temperature of the lower electrode 4 is 55 degrees Celsius. As the pressure on the back surface He increases, the temperature of the wafer substrate 5 decreases. However, in order to obtain a desired uneven shape, it is necessary to control the temperature of the desired wafer substrate 5.
　図９は、裏面冷却Ｈｅ圧力（Ｐａ）に対するウエハ基板の中央と外周の面内温度の関係を示す図である。 FIG. 9 is a diagram showing the relationship between the in-plane temperatures of the center and outer periphery of the wafer substrate with respect to the back surface cooling He pressure (Pa).
　図９において、ウエハ基板５の中央部（Ｃｅｎｔｅｒ）と外周部（Ｔｏｐ）で裏面冷却Ｈｅ圧力（Ｐａ）が高くなるほどウエハ基板５の温度が一致してくる。このように、裏面冷却Ｈｅ圧力（Ｐａ）の上昇に伴い、ウエハ基板５の面内温度の均一性が改善されていることが分かる。 In FIG. 9, the temperature of the wafer substrate 5 becomes equal as the back surface cooling He pressure (Pa) increases at the center (Center) and the outer periphery (Top) of the wafer substrate 5. Thus, it can be seen that the uniformity of the in-plane temperature of the wafer substrate 5 is improved as the back surface cooling He pressure (Pa) increases.
　以上により、本実施形態１の基板処理方法は、処理室としての処理チャンバ２内にウエハ基板５を配置し、上部電極３と下部電極４それぞれに独立して電力を供給して、処理チャンバ２内の処理ガスをプラズマ化して基板処理する基板処理工程を有する基板処理方法において、プラズマエッチング処理の基板処理工程の前であって、処理チャンバ２内に供給する処理ガスの圧力を所定圧力に調整する処理ガス圧力調整工程（スタビリティ工程）において、上部電極３のみに電力を供給して処理チャンバ２内に供給した処理ガスをプラズマ化してウエハ基板５に電荷を帯電させて下部電極４側にウエハ基板５を静電吸着させる基板吸着工程を有している。この場合に、用いる処理ガスとして電子放出率の高いガス種を選択している。 As described above, in the substrate processing method according to the first embodiment, the wafer substrate 5 is disposed in the processing chamber 2 as a processing chamber, and power is independently supplied to the upper electrode 3 and the lower electrode 4. In a substrate processing method having a substrate processing step of processing a substrate by converting the processing gas into plasma, the pressure of the processing gas supplied into the processing chamber 2 is adjusted to a predetermined pressure before the substrate processing step of plasma etching processing In the processing gas pressure adjustment process (stability process), the processing gas supplied to the processing chamber 2 by supplying power only to the upper electrode 3 is turned into plasma to charge the wafer substrate 5 to the lower electrode 4 side. A substrate adsorption step for electrostatically adsorbing the wafer substrate 5 is provided. In this case, a gas species having a high electron emission rate is selected as a processing gas to be used.
　このように、プラズマエッチング処理前の安定ステップを基板吸着ステップと兼ねることにより、従来のように基板吸着ステップを別途設けて不要なステップの増加およびプラズマエッチングの予期せぬ進行を回避することができて、より効率的に所望のプラズマエッチング処理などの基板処理を行うことができる。 In this way, by combining the stable step before the plasma etching process with the substrate adsorption step, it is possible to avoid the increase in unnecessary steps and the unexpected progress of plasma etching by providing a separate substrate adsorption step as in the past. Thus, desired substrate processing such as plasma etching processing can be performed more efficiently.
　処理ガスとしては、イオン化ポテンシャルが３２０ｋｃａｌ/ｍｏｌ以下の元素を含む吸着用ガスを用いる。処理ガスは、吸着用ガスとして、Ｏ(酸素)およびＣｌ(塩素)ガスのうちの少なくともいずれかを含むガスである。 As the processing gas, an adsorption gas containing an element having an ionization potential of 320 kcal / mol or less is used. The processing gas is a gas containing at least one of O (oxygen) and Cl (chlorine) gas as an adsorption gas.
　基板吸着工程は、基板が絶縁基板であり、静電チャック（ＥＳＣ）により絶縁基板のウエハ基板５を静電吸着させる。 In the substrate adsorption step, the substrate is an insulating substrate, and the wafer substrate 5 as an insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
　ウエハ基板５の裏面に導入する冷却媒体により基板を冷却しながら基板温度を制御して基板処理を行う。ウエハ基板５の裏面冷却に必要な冷却媒体の圧力を確保可能とする静電吸着力を確保する必要がある。ウエハ基板５の裏面冷却に必要な冷却媒体としてはＨｅガスを用いている。 The substrate processing is performed by controlling the substrate temperature while cooling the substrate with the cooling medium introduced to the back surface of the wafer substrate 5. It is necessary to secure an electrostatic attraction force that can ensure the pressure of the cooling medium necessary for cooling the back surface of the wafer substrate 5. He gas is used as a cooling medium necessary for cooling the back surface of the wafer substrate 5.
　プラズマエッチング処理（基板処理）の条件として上部電極３へのＲＦパワー（印加電圧)は０．４５ｗ/ｃｍ２以上７５ｗ/ｃｍ２以下または５００Ｗ以上２０００Ｗ以下である。さらに好ましくは、基板処理の条件としてＲＦパワー（印加電圧)は５００Ｗ以上１２００Ｗ以下である。ＲＦパワー１２００Ｗ～２０００Ｗが現在の最大出力ＲＦパワーである。 As the conditions for the plasma etching process (substrate process), the RF power (applied voltage) to the upper electrode 3 is 0.45 w / cm 2 or more and 75 w / cm 2 or less, or 500 W or more and 2000 W or less. More preferably, the RF power (applied voltage) is 500 W or more and 1200 W or less as a substrate processing condition. The RF power of 1200 W to 2000 W is the current maximum output RF power.
　ここでは、ウエハ基板５としてサファイア基板を用いているが、ＳｉＣ基板または化合物半導体基板であってもよい。ウエハ基板５には電気的影響を受けやすい膜であってプラズマからの電荷が帯電し易い絶縁性膜が設けられている方が静電吸着力が良好になって好ましい。電気的影響を受けやすい膜としてはフォトレジスト膜などがある。さらに、ウエハ基板５上の膜状態は、静電吸着力を保持するために、基板処理中はフォトレジスト膜が残っていることが好ましい。 Here, although the sapphire substrate is used as the wafer substrate 5, it may be a SiC substrate or a compound semiconductor substrate. It is preferable that the wafer substrate 5 is provided with an insulating film that is easily affected by an electric charge and is easily charged with electric charges from plasma because the electrostatic adsorption force is improved. Examples of the film that is susceptible to electrical influence include a photoresist film. Further, the film state on the wafer substrate 5 is preferably left with the photoresist film during the substrate processing in order to maintain the electrostatic attraction force.
　前述したが、メカニカルクランプなどではウエハーエッジでの取れ数でロスが発生することから、ウエハ基板５の表面積最大限有効活用のためにＥＳＣ使用が必要である。基板吸着工程は、ウエハ基板５が絶縁基板であり、静電チャック（ＥＳＣ）により絶縁基板を静電吸着させる。 As described above, mechanical clamps and the like cause loss due to the number of wafer edges, so ESC must be used for maximum effective use of the surface area of the wafer substrate 5. In the substrate adsorption process, the wafer substrate 5 is an insulating substrate, and the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).
　ウエハ基板５の材質が絶縁体であり、電気的吸着困難材質なため静電チャック（ＥＳＣ）を用いるうえで、吸着力確保が課題であるため、ウエハ基板５に十分に電荷をプラズマ６から帯電させるために、処理ガスとしてプラズマ化し易い電子放出率の高いガス種を選択する。プラズマ化し易い電子放出率の高いガス種とは、イオン化ポテンシャルが低く気体の電離電圧Ｖｉも低い処理ガスである。 Since the material of the wafer substrate 5 is an insulator and is difficult to electrically attract, it is necessary to secure an attracting force when using an electrostatic chuck (ESC). Therefore, a gas species having a high electron emission rate that is easily converted to plasma is selected as the processing gas. A gas species having a high electron emission rate that is easily converted to plasma is a processing gas having a low ionization potential and a low ionization voltage Vi.
　凹凸形状のアスペクト比制御などのプロセス性能向上やプロセス安定化、即ち面内均一性、マージン確保に必要な十分な基板温度制御の冷却力確保のため、ウエハ基板５の載置電極温度だけでなくその温度を伝達するため一定以上の裏面Ｈｅ圧力が必要である。 In order to improve the process performance such as the aspect ratio control of the concavo-convex shape and stabilize the process, that is, the in-plane uniformity and the sufficient substrate temperature control necessary for ensuring the margin, not only the mounting electrode temperature of the wafer substrate 5 but also In order to transmit the temperature, a certain amount of backside He pressure is required.
　ここでは、６インチのウエハ基板５に対して各種試験を行ったが、今後の大口径化に伴い、ウエハ基板５の反りも増大する。このウエハ基板５の反りの増大に伴い、裏面Ｈｅの封止が困難になりＨｅリーク量も増加する。 Here, various tests were performed on the 6-inch wafer substrate 5, but the warpage of the wafer substrate 5 increases as the diameter increases in the future. As the warpage of the wafer substrate 5 increases, it becomes difficult to seal the back surface He, and the amount of He leak increases.
　静電チャック（ＥＳＣ）での吸着力確保のため、ウエハ基板５の表面へのより多くの帯電が必須である。ウエハ基板５の表面へのより多くの帯電は、イオン化ポテンシャルが低く気体の電離電圧Ｖｉも低い元素種に依存している。 More charge on the surface of the wafer substrate 5 is indispensable in order to secure the attractive force with the electrostatic chuck (ESC). More charging of the surface of the wafer substrate 5 depends on the element species having a low ionization potential and a low gas ionization voltage Vi.
　（実施形態２）
　上記実施形態１では基板処理装置およびこれを用いた基板処理方法について説明し、本実施形態２では、この基板処理方法を用いたプラズマエッチング工程を有した半導体装置の製造方法を窒化物半導体発光素子の製造方法に適用した場合について図面を参照しながら詳細に説明する。 (Embodiment 2)
In the first embodiment, a substrate processing apparatus and a substrate processing method using the same will be described. In the second embodiment, a method for manufacturing a semiconductor device having a plasma etching process using the substrate processing method is used as a nitride semiconductor light emitting element. The case of applying to this manufacturing method will be described in detail with reference to the drawings.
　図１０は、本発明の実施形態２における窒化物半導体発光素子の要部構成例を示す縦断面図である。 FIG. 10 is a longitudinal sectional view showing an example of the configuration of the main part of the nitride semiconductor light-emitting device according to Embodiment 2 of the present invention.
　図１０において、本実施形態２の窒化物半導体発光素子１１は、表面に凹凸が形成された厚さ約１３００μｍの基板として例えばサファイヤ基板１２上に、窒化アルミニウム（ＡｌＮ）から成る膜厚約１５ｎｍのバッファ層１３が成膜されている。そのバッファ層１３上にノンドープのＧａＮから成る膜厚約５００ｎｍのノンドープＧａＮ層１４が成膜されている。これらのサファイヤ基板１２、バッファ層１３およびノンドープＧａＮ層１４により単結晶性基板が構成されている。 In FIG. 10, the nitride semiconductor light emitting device 11 of the second embodiment has a film thickness of about 15 nm made of aluminum nitride (AlN) on a sapphire substrate 12, for example, as a substrate having a thickness of about 1300 μm with irregularities formed on the surface. A buffer layer 13 is formed. On the buffer layer 13, a non-doped GaN layer 14 made of non-doped GaN and having a thickness of about 500 nm is formed. These sapphire substrate 12, buffer layer 13 and non-doped GaN layer 14 constitute a single crystal substrate.
　さらに、本実施形態１の窒化物半導体発光素子１１において、この単結晶性基板上にシリコン（Ｓｉ）を１×１０１８／ｃｍ３ドープしたＧａＮからなる膜厚約５μｍのｎ型コンタクト層１５（高キャリヤ濃度ｎ＋層）が形成されている。このｎ型コンタクト層１５上には多重層１６が形成され、この多重層１６上には多重量子井戸構造の発光層１７が形成されている。 Further, in the nitride semiconductor light emitting device 11 of the first embodiment, the n-type contact layer 15 (high carrier) having a film thickness of about 5 μm made of GaN doped with silicon (Si) 1 × 10 18 / cm 3 on the single crystalline substrate. (Concentration n + layer) is formed. A multi-layer 16 is formed on the n-type contact layer 15, and a light-emitting layer 17 having a multi-quantum well structure is formed on the multi-layer 16.
　この多重層１６は、ＩｎｘＧａ１－ｘＮ（０＜ｘ＜０．３）からなる第１の層とＧａＮからなる第２の層とを交互に複数積層されている。この多重層１６は、ここでは例えば、膜厚３ｎｍのＩｎ０．０３Ｇａ０．９７Ｎからなる第１の層と、膜厚２０ｎｍのＧａＮからなる第２の層とを５ペア積層している。 The multi-layer 16 is formed by alternately laminating a plurality of first layers made of InxGa1-xN (0 <x <0.3) and second layers made of GaN. In this multilayer 16, for example, five pairs of a first layer made of In0.03Ga0.97N with a thickness of 3 nm and a second layer made of GaN with a thickness of 20 nm are stacked.
　この多重層１６のうちの第１の層に、一導電型不純物としてＳｉがその濃度として、５×１０１６ｃｍ－３～１×１０１８ｃｍ－３（さらに好ましくは、１×１０１７ｃｍ－３～１×１０１８ｃｍ－３）の範囲で添加されて、発光層１７が受ける静電破壊エネルギ（ｍＪ／ｃｍ２）が２０以上４０以下（さらに好ましくは、２０以上３５以下）とされている。 The first layer of the multi-layer 16 has a concentration of Si as one conductivity type impurity of 5 × 10 16 cm −3 to 1 × 10 18 cm −3 (more preferably 1 × 10 17 cm −3 to 1 × 10 18 cm − The electrostatic breakdown energy (mJ / cm 2) that is added in the range of 3) and received by the light emitting layer 17 is 20 or more and 40 or less (more preferably, 20 or more and 35 or less).
　具体的には、所定項目の逆方向電気特性（逆方向電流）をパラメータとして、発光層１７が受ける静電破壊エネルギ（ｍＪ／ｃｍ２）と多重層１６の第１層におけるＳｉ濃度との関係を示す特性曲線において、静電破壊エネルギ（ｍＪ／ｃｍ２）の極小値に対応するＳｉの濃度に設定されている。 Specifically, the relationship between the electrostatic breakdown energy (mJ / cm 2) received by the light emitting layer 17 and the Si concentration in the first layer of the multi-layer 16 using the reverse electrical characteristics (reverse current) of a predetermined item as a parameter. In the characteristic curve shown, the Si concentration corresponding to the minimum value of electrostatic breakdown energy (mJ / cm 2) is set.
　多重量子井戸構造の発光層１７の井戸層は少なくともＩｎを含むＩｎｙＧａ１－ｙＮ（０≦ｙ＜０．３）からなっている。このように、多重量子井戸構造の発光層１７は、ここでは例えば、膜厚３ｎｍのＩｎ０．２Ｇａ０．８Ｎから成る井戸層と、膜厚２０ｎｍのＧａＮから成る障壁層とを３ペア積層している。 The well layer of the light emitting layer 17 having a multiple quantum well structure is made of InyGa1-yN (0 ≦ y <0.3) containing at least In. In this way, the light emitting layer 17 having a multiple quantum well structure has, for example, three pairs of well layers made of In0.2Ga0.8N with a thickness of 3 nm and barrier layers made of GaN with a thickness of 20 nm. .
　さらに、本実施形態２の窒化物半導体発光素子１１において、この発光層１７上に、Ｍｇを２×１０１９／ｃｍ３ドープした膜厚２５ｎｍのｐ型Ａｌ０．１５Ｇａ０．８５Ｎからなるｐ型層である電子ブロック層１８が形成されている。この電子ブロック層１８上には、Ｍｇを８×１０１９ドープした膜厚１００ｎｍのｐ型ＧａＮからなるｐ型コンタクト層１９が形成されている。 Furthermore, in the nitride semiconductor light emitting device 11 of the second embodiment, an electron which is a p-type layer made of p-type Al0.15Ga0.85N with a thickness of 25 nm doped with Mg 2 × 1019 / cm3 on the light-emitting layer 17. A block layer 18 is formed. A p-type contact layer 19 made of p-type GaN having a thickness of 100 nm doped with 8 × 1019 Mg is formed on the electron block layer 18.
　このｐ型コンタクト層１９上には、金属蒸着による透光性薄膜電極２０（ＩＴＯ）が形成されている。透光性薄膜電極２０の一部上にｐ電極２１が形成されている。 On the p-type contact layer 19, a translucent thin film electrode 20 (ITO) is formed by metal vapor deposition. A p-electrode 21 is formed on part of the translucent thin film electrode 20.
　一方、ｎ型コンタクト層１５の端部が途中まで露出され、その上にｎ電極２２が形成されている。ｐ電極２１およびｎ電極２２上の最上部には、ＳｉｘＯｙ膜としてのＳｉＯ２膜よりなる耐湿度用などの保護膜２３が形成されている。 On the other hand, the end of the n-type contact layer 15 is exposed partway, and the n-electrode 22 is formed thereon. On top of the p-electrode 21 and the n-electrode 22, a protective film 23 for moisture resistance or the like made of a SiO2 film as a SixOy film is formed.
　保護膜２３は、透光性薄膜電極２０、ｐ電極２１、ｎ電極２２およびｎ型コンタクト層１５の露出表面、さらに、ｎ型コンタクト層１５の端部途中までの、多重層１６、発光層１７、電子ブロック層１８、ｐ型コンタクト層１９および透光性薄膜電極２０（ＩＴＯ）のエッチング除去側面に形成されている。 The protective film 23 includes the light-transmitting thin film electrode 20, the p-electrode 21, the n-electrode 22, and the exposed surface of the n-type contact layer 15, and further to the middle of the end of the n-type contact layer 15. The electron blocking layer 18, the p-type contact layer 19, and the translucent thin film electrode 20 (ITO) are formed on the etching side surfaces.
　このように、保護膜２３は、ｐ電極２１およびｎ電極２２と素子表面とを覆って保護するものである。保護膜２３は、ＳｉＯ２膜の単層構造であってもよいが、ＳｉｘＮｙ膜としてのＳｉＮ膜と、その上のＳｉｘＯｙ膜としてのＳｉＯ２膜との２層構造であってもよい。また、上下が逆で、ＳｉｘＯｙ膜としてのＳｉＯ２膜と、その上のＳｉｘＮｙ膜としてのＳｉＮ膜との２層構造であってもよい。これらの場合は、ＳｉＮ膜がパッシベーション膜として機能する。 Thus, the protective film 23 covers and protects the p electrode 21 and the n electrode 22 and the element surface. The protective film 23 may have a single-layer structure of a SiO2 film, but may have a two-layer structure of a SiN film as a SixNy film and a SiO2 film as a SixOy film thereon. Further, the structure may be a two-layer structure in which the SiO2 film as the SixOy film and the SiN film as the SixNy film thereon are upside down. In these cases, the SiN film functions as a passivation film.
　要するに、保護膜２３は、ＳｉｘＯｙ膜、ＳｉｘＮｙ膜およびＳｉｘＯｙＮｚ膜のうちの少なくともＳｉｘＯｙ膜を有している。 In short, the protective film 23 has at least a SixOy film among a SixOy film, a SixNy film, and a SixOyNz film.
　次に、上記構成の窒化物半導体発光素子１１の製造方法について説明する。 Next, a method for manufacturing the nitride semiconductor light emitting device 11 having the above configuration will be described.
　図１０に示すように、本実施形態２の窒化物半導体発光素子１１の製造方法は、サファイヤ基板１２を所定位置に受け入れるサファイヤ基板１２の基板受け入れ工程と、サファイヤ基板１２の表面に所定のアスペクト比で凹凸を形成する表面凹凸加工工程と、ＭＯＣＶＤ法により、サファイヤ基板１２の表面凹凸加工面上に、バッファ層１３、ノンドープＧａＮ層１４、ｎ型コンタクト層１５、多重層１６、多重量子井戸構造の発光層１７、電子ブロック層１８およびｐ型コンタクト層１９をこの順に順次形成するＭＯＣＶＤ工程と、ｐ型コンタクト層１９上に透光性薄膜電極２０を形成する透明性電極形成工程と、基板端部をｎ型コンタクト層１５の途中までエッチング除去してｎ型コンタクト層１５の端部を途中で露出させ、ｎ型コンタクト層１５の端部表面上にｎ電極２２を形成すると共に、透光性薄膜電極２０の一部表面上にｐ電極２１を形成するｐ電極２１およびｎ電極２２の電極形成工程と、透光性薄膜電極２０、ｐ電極２１、ｎ電極２２およびｎ型コンタクト層１５の露出表面、さらにエッチング除去側面に耐湿度用などのために保護膜２３を形成する保護膜形成工程と、ｐ電極２１およびｎ電極２２上の保護膜２３をそれぞれ開口する電極開口部工程とを有している。 As shown in FIG. 10, the method for manufacturing the nitride semiconductor light emitting device 11 according to the second embodiment includes a substrate receiving process for receiving the sapphire substrate 12 at a predetermined position, and a predetermined aspect ratio on the surface of the sapphire substrate 12. On the surface unevenness processed surface of the sapphire substrate 12 by the MOCVD method, and a buffer layer 13, a non-doped GaN layer 14, an n-type contact layer 15, a multiple layer 16, and a multiple quantum well structure. MOCVD step of sequentially forming the light emitting layer 17, the electron blocking layer 18 and the p-type contact layer 19 in this order, a transparent electrode forming step of forming the translucent thin film electrode 20 on the p-type contact layer 19, and the edge of the substrate Is etched halfway through the n-type contact layer 15 to expose the end of the n-type contact layer 15 in the middle, Forming the n-electrode 22 on the surface of the end portion of the light-emitting layer 15 and forming the p-electrode 21 on the partial surface of the translucent thin-film electrode 20; A protective film forming step for forming a protective film 23 for moisture resistance on the exposed surface of the conductive thin film electrode 20, the p electrode 21, the n electrode 22 and the n-type contact layer 15 and further on the side surface to which etching is removed; an electrode opening step for opening the protective film 23 on the n-electrode 22.
　半導体装置の製造方法としての窒化物半導体発光素子１１の製造方法において、サファイヤ基板１２の表面に凹凸を形成する表面凹凸加工工程と、基板端部をｎ型コンタクト層１５の途中までエッチング除去してｎ型コンタクト層１５の端部を途中で露出させるエッチング工程とに、上記実施形態１の基板処理方法を用いて正確でより良好なプラズマエッチング処理を行なっている。このように、窒化物半導体発光素子１１の製造方法は、処理チャンバ２内に供給する処理ガスの圧力を所定圧力に調整する処理ガス圧力調整工程内に、上部電極３のみに電力を供給して処理チャンバ２内に供給した処理ガスをプラズマ化してウエハ基板５に電荷を帯電させて下部電極４側にウエハ基板５を静電吸着させる上記実施形態１の基板処理方法を用いたプラズマエッチング工程を有している。 In the method of manufacturing the nitride semiconductor light emitting device 11 as a method of manufacturing a semiconductor device, a surface unevenness forming step for forming unevenness on the surface of the sapphire substrate 12 and etching and removing the substrate end partway into the n-type contact layer 15. An accurate and better plasma etching process is performed using the substrate processing method of the first embodiment in the etching process in which the end portion of the n-type contact layer 15 is exposed halfway. As described above, the method for manufacturing the nitride semiconductor light emitting device 11 supplies power only to the upper electrode 3 in the process gas pressure adjusting step for adjusting the pressure of the process gas supplied into the process chamber 2 to a predetermined pressure. A plasma etching process using the substrate processing method of the first embodiment in which the processing gas supplied into the processing chamber 2 is converted into plasma to charge the wafer substrate 5 and electrostatically attract the wafer substrate 5 to the lower electrode 4 side. Have.
　したがって、本実施形態２の窒化物半導体発光素子１１の製造方法によっても、プラズマエッチング工程において、絶縁体基板上の面積を最大限活用して基板１枚当たりのチップ取れ数を向上させつつ、吸着部材を別途必要とせず、製造を効率的に行って製造コストパフォーマンスを向上させることができる。 Therefore, even in the method for manufacturing the nitride semiconductor light emitting device 11 of the second embodiment, in the plasma etching process, the area on the insulator substrate is utilized to the maximum while the number of chips that can be taken per substrate is improved and the adsorption is performed. A member is not required separately, and it can manufacture efficiently and can improve manufacturing cost performance.
　なお、本実施形態２では、ＬＥＤの窒化物半導体発光素子１１の製造方法について説明したが、これに限らず、上記実施形態１の基板処理方法を用いたプラズマエッチング工程を有する半導体装置の製造方法であればよい。 In addition, although this Embodiment 2 demonstrated the manufacturing method of the nitride semiconductor light-emitting element 11 of LED, it is not restricted to this, The manufacturing method of the semiconductor device which has a plasma etching process using the substrate processing method of the said Embodiment 1 If it is.
　以上のように、本発明の好ましい実施形態１、２を用いて本発明を例示してきたが、本発明は、この実施形態１、２に限定して解釈されるべきものではない。本発明は、特許請求の範囲によってのみその範囲が解釈されるべきであることが理解される。当業者は、本発明の具体的な好ましい実施形態１、２の記載から、本発明の記載および技術常識に基づいて等価な範囲を実施することができることが理解される。本明細書において引用した特許、特許出願および文献は、その内容自体が具体的に本明細書に記載されているのと同様にその内容が本明細書に対する参考として援用されるべきであることが理解される。 As described above, the present invention has been exemplified by using the first and second preferred embodiments of the present invention, but the present invention should not be construed as being limited to the first and second embodiments. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge, from the description of specific preferred embodiments 1 and 2 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.
　本発明は、被処理基板を静電吸着して固定しつつ、被処理基板にプラズマドライエッチングなどの所定の処理を行う際に用いられる基板処理装置および、これを用いた基板処理方法、これを用いた半導体装置の製造方法の分野において、処理室内に供給する処理ガスの圧力を所定圧力に調整する処理ガス圧力調整工程内に、上部電極のみに電力を供給して処理室内に供給した処理ガスをプラズマ化して基板に電荷を帯電させて下部電極側に基板を静電吸着させるため、絶縁体基板上の面積を最大限活用して基板１枚当たりのチップ取れ数を向上させつつ、吸着部材を別途必要とせず、製造を効率的に行って製造コストパフォーマンスを向上させることができる。 The present invention relates to a substrate processing apparatus used when performing predetermined processing such as plasma dry etching on a substrate to be processed while electrostatically attracting and fixing the substrate to be processed, a substrate processing method using the same, and In the field of the semiconductor device manufacturing method used, the processing gas supplied to the processing chamber by supplying power only to the upper electrode in the processing gas pressure adjusting step for adjusting the pressure of the processing gas supplied to the processing chamber to a predetermined pressure. Since the substrate is turned into plasma to charge the substrate and electrostatically adsorb the substrate to the lower electrode side, the adsorption member is improved while maximizing the area on the insulator substrate and improving the number of chips per substrate. The manufacturing cost performance can be improved by efficiently performing the manufacturing.

Claims (6)

  1. 　処理室内に基板を配置し、上部電極と下部電極それぞれに独立して電力を供給して、該処理室内の処理ガスをプラズマ化して基板処理を行う基板処理工程を有する基板処理方法において、
    　該基板処理工程の前であって、該処理室内に供給する該処理ガスの圧力を所定圧力に調整する処理ガス圧力調整工程内に、該上部電極のみに電力を供給して該処理室内に供給した処理ガスをプラズマ化して該基板に電荷を帯電させて該下部電極側に該基板を静電吸着させる基板吸着工程を有する基板処理方法。     In a substrate processing method comprising a substrate processing step of disposing a substrate in a processing chamber, supplying power independently to each of the upper electrode and the lower electrode, and converting the processing gas in the processing chamber into plasma to perform substrate processing,
    Before the substrate processing step, in the processing gas pressure adjusting step for adjusting the pressure of the processing gas supplied into the processing chamber to a predetermined pressure, power is supplied only to the upper electrode and supplied into the processing chamber. A substrate processing method comprising a substrate adsorption step of converting the processed gas into plasma and charging the substrate with electric charge to electrostatically adsorb the substrate to the lower electrode side.
  2. 　前記処理ガスとして不活性ガスに比べてプラズマ化し易い電子放出率の高いガス種を選択する請求項１に記載の基板処理方法。 The substrate processing method according to claim 1, wherein a gas species having a high electron emission rate that is more easily converted into plasma than an inert gas is selected as the processing gas.
  3. 　前記処理ガスは、Ｏ(酸素)およびＣｌ(塩素)のうちの少なくともいずれかを含むガスである請求項２に記載の基板処理方法。 3. The substrate processing method according to claim 2, wherein the processing gas is a gas containing at least one of O (oxygen) and Cl (chlorine).
  4. 　前記基板の裏面冷却に必要な冷却媒体の圧力を確保可能とする静電吸着力を確保している請求項１に記載の基板処理方法。 The substrate processing method according to claim 1, wherein an electrostatic attraction force capable of securing a pressure of a cooling medium necessary for cooling the back surface of the substrate is secured.
  5. 　請求項１～４のいずれかに記載の基板処理方法を用いたプラズマエッチング工程を有した半導体装置の製造方法。 A method for manufacturing a semiconductor device having a plasma etching process using the substrate processing method according to claim 1.
  6. 　処理室内に基板を配置し、上部電極と下部電極それぞれに独立して電力を供給して、該処理室内の処理ガスをプラズマ化して基板処理を行う基板処理装置において、
    　該上部電極のみに電力を供給して、不活性ガスに比べてプラズマ化し易い電子放出率の高い、該処理室内に供給した処理ガスをプラズマ化して該基板に電荷を帯電させて該下部電極側に該基板を静電吸着させた状態で該基板処理が実行可能となっている基板処理装置。     In a substrate processing apparatus that arranges a substrate in a processing chamber, supplies power independently to each of the upper electrode and the lower electrode, converts the processing gas in the processing chamber into plasma, and performs substrate processing,
    Electric power is supplied only to the upper electrode, and the electron emission rate is higher than that of an inert gas. The processing gas supplied into the processing chamber is turned into plasma to charge the substrate to charge the lower electrode. A substrate processing apparatus capable of executing the substrate processing in a state where the substrate is electrostatically attracted to the substrate.
PCT/JP2013/003937 2012-09-26 2013-06-24 Substrate treatment device, substrate treatment method, and production method for semiconductor device WO2014049915A1 (en)

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CN109148270B (en) * 2017-06-19 2023-11-03 东京毅力科创株式会社 Film forming method, storage medium, and film forming system

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