TW201421574A - Substrate treatment device, substrate treatment method, and production method for semiconductor device - Google Patents

Substrate treatment device, substrate treatment method, and production method for semiconductor device Download PDF

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TW201421574A
TW201421574A TW102134167A TW102134167A TW201421574A TW 201421574 A TW201421574 A TW 201421574A TW 102134167 A TW102134167 A TW 102134167A TW 102134167 A TW102134167 A TW 102134167A TW 201421574 A TW201421574 A TW 201421574A
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substrate
processing
gas
plasma
electrode
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Takanobu Nishida
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Sharp Kk
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833Details of electrostatic chucks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds

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  • Manufacturing & Machinery (AREA)
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Abstract

To make full use of the area of an insulator substrate and improve the number of chips that can be produced per substrate while not requiring a separate attachment member and efficiently carrying out production in order to improve production cost performance. A substrate treatment method that comprises a substrate treatment step in which a wafer substrate (5) is arranged within a treatment chamber (2) that serves as a treatment chamber, power is supplied independently to an upper electrode (3) and a lower electrode (4), and treatment gas within the treatment chamber (2) is plasmified in order to treat the substrate. A treatment gas pressure adjustment step (stability step) in which the pressure of a treatment gas that is supplied into the treatment chamber (2) is adjusted to a predetermined pressure is carried out prior to a substrate treatment step for plasma etching treatment, and said treatment gas pressure adjustment step includes a substrate attachment step in which power is supplied only to the upper electrode (3), the treatment gas supplied into the treatment chamber (2) is plasmified, the wafer substrate (5) is charged with an electrical load, and the wafer substrate (5) is electrostatically attached to the lower electrode (4) side.

Description

基板處理裝置及基板處理方法、半導體裝置之製造方法 Substrate processing apparatus, substrate processing method, and manufacturing method of semiconductor device

本發明係關於一種於將被處理基板靜電吸附並固定,並且對被處理基板進行電漿乾式蝕刻等特定之處理時所使用之基板處理裝置、及使用其之基板處理方法、使用其之半導體裝置之製造方法。 The present invention relates to a substrate processing apparatus used for electrostatically adsorbing and fixing a substrate to be processed, and performing specific processing such as plasma dry etching on a substrate to be processed, and a substrate processing method using the same, and a semiconductor device using the same Manufacturing method.

先前,於被處理基板之蝕刻中,採用於高真空下進行之乾式蝕刻。該乾式蝕刻係將被處理基板配置於腔室內,於腔室內形成電漿,藉由該電漿而進行蝕刻。於此種乾式蝕刻處理中,電漿乾式蝕刻特性較大地依存於基板溫度。因此使冷媒於支持被處理基板之基板支持構件中流通而控制基板溫度。該情形時,為了提高冷媒之傳熱效率,使被處理基板與基板支持構件之間流動有He氣體等熱傳遞氣體。 Previously, in the etching of the substrate to be processed, dry etching was performed under high vacuum. In the dry etching, the substrate to be processed is placed in a chamber, and a plasma is formed in the chamber, and etching is performed by the plasma. In such a dry etching process, the plasma dry etching characteristics largely depend on the substrate temperature. Therefore, the refrigerant is allowed to flow through the substrate supporting member supporting the substrate to be processed to control the substrate temperature. In this case, in order to improve the heat transfer efficiency of the refrigerant, a heat transfer gas such as He gas flows between the substrate to be processed and the substrate supporting member.

被處理基板為了進行乾式蝕刻處理而必須以固定狀態支持於基板支持構件上,因此,例如於被處理基板係半導體晶圓之情形時,使用使該半導體晶圓於庫倫力之類之靜電力作用下吸附並支持於基板支持構件上之靜電吸附裝置。 The substrate to be processed must be supported on the substrate supporting member in a fixed state in order to perform dry etching. Therefore, for example, in the case of a substrate-based semiconductor wafer to be processed, an electrostatic force acting on the semiconductor wafer in Coulomb force is used. The electrostatic adsorption device is adsorbed and supported on the substrate supporting member.

圖11係用以說明專利文獻1中揭示之先前之靜電吸附裝置之靜電吸附原理之模式圖。 Fig. 11 is a schematic view for explaining the principle of electrostatic adsorption of the prior electrostatic adsorption device disclosed in Patent Document 1.

如圖11所示,先前之靜電吸附裝置100係設置於形成有電漿之空間中,將絕緣基板101吸附於絕緣體102側。吸附構件104包含絕緣體102及設置於其內部之電極103。該吸附構件104係搭載並支持於基板支持構件105上。 As shown in FIG. 11, the conventional electrostatic adsorption device 100 is disposed in a space in which plasma is formed, and the insulating substrate 101 is adsorbed on the side of the insulator 102. The adsorption member 104 includes an insulator 102 and an electrode 103 provided inside thereof. The adsorption member 104 is mounted and supported on the substrate supporting member 105.

於空間內形成有電漿之狀態下對電極103施加特定之DC(Direct Current,直流)電壓,藉此使絕緣基板101上自電漿帶電而蓄積之電荷與電極103之間產生靜電力,藉此使絕緣基板101吸附於吸附構件104之絕緣體102側。 A specific DC (Direct Current) voltage is applied to the electrode 103 in a state where plasma is formed in the space, whereby an electrostatic force is generated between the charge accumulated on the insulating substrate 101 and charged by the plasma and the electrode 103. This causes the insulating substrate 101 to be adsorbed to the insulator 102 side of the adsorption member 104.

圖12係概略地表示專利文獻2中揭示之先前之基板處理裝置之主要部分構成圖。 FIG. 12 is a view schematically showing the configuration of a main part of a substrate processing apparatus disclosed in Patent Document 2.

如圖12所示,先前之電漿處理裝置200中,對於上表面上載置有絕緣基板K之靜電吸盤201之電極202、203施加直流電壓,並且自惰性氣體供給部205向處理腔室204內供給惰性氣體,使該惰性氣體電漿化。使絕緣基板K自電漿化之惰性氣體帶電而將絕緣基板K吸附並保持於靜電吸盤201上。其後,開始對吸附、保持於靜電吸盤201上之絕緣基板K之背面與靜電吸盤201之上表面之間供給冷卻氣體。 As shown in FIG. 12, in the conventional plasma processing apparatus 200, a DC voltage is applied to the electrodes 202, 203 of the electrostatic chuck 201 on which the insulating substrate K is placed on the upper surface, and is supplied from the inert gas supply portion 205 to the processing chamber 204. An inert gas is supplied to plasma the inert gas. The insulating substrate K is charged from the plasma-inert inert gas to adsorb and hold the insulating substrate K on the electrostatic chuck 201. Thereafter, the supply of the cooling gas between the back surface of the insulating substrate K adsorbed and held on the electrostatic chuck 201 and the upper surface of the electrostatic chuck 201 is started.

其次,於先前之電漿處理裝置200中,代替惰性氣體而將電漿處理用之處理氣體自處理氣體供給部206供給至處理腔室204內,使其內部置換為處理氣體,並且使該處理氣體電漿化,繼而使絕緣基板K吸附並保持於靜電吸盤201上。其後,一面自冷卻氣體供給部207供給冷卻氣體並藉由冷卻氣體而冷卻絕緣基板K,一面藉由電漿化之處理氣體而對絕緣基板K進行電漿蝕刻處理。 Next, in the conventional plasma processing apparatus 200, the processing gas for plasma processing is supplied from the processing gas supply unit 206 to the processing chamber 204 instead of the inert gas, and the inside thereof is replaced with the processing gas, and the processing is performed. The gas is plasmad, and then the insulating substrate K is adsorbed and held on the electrostatic chuck 201. Thereafter, the cooling gas is supplied from the cooling gas supply unit 207, and the insulating substrate K is cooled by the cooling gas, and the insulating substrate K is subjected to plasma etching treatment by the plasma processing gas.

排氣裝置208包含:排氣泵209;及連接排氣泵209與下部容器210之排氣管211;經由排氣管211而將下部容器210內之氣體排氣,使處理腔室204內部之惰性氣體或處理氣體成為特定壓力。 The exhaust device 208 includes: an exhaust pump 209; and an exhaust pipe 211 that connects the exhaust pump 209 and the lower container 210; and exhausts the gas in the lower container 210 via the exhaust pipe 211 to make the inside of the processing chamber 204 The inert gas or process gas becomes a specific pressure.

藉此,可自電漿蝕刻處理開始前冷卻絕緣基板K,對絕緣基板K之整個面均勻且有效地進行電漿蝕刻處理。 Thereby, the insulating substrate K can be cooled from the start of the plasma etching treatment, and the plasma etching treatment can be performed uniformly and efficiently on the entire surface of the insulating substrate K.

先前技術文獻 Prior technical literature 專利文獻 Patent literature

專利文獻1:日本專利特開平11-111830號公報 Patent Document 1: Japanese Patent Laid-Open No. Hei 11-111830

專利文獻2:日本專利特開2009-194194號公報 Patent Document 2: Japanese Patent Laid-Open Publication No. 2009-194194

若將機械夾盤用於基板保持,則由於機械夾盤覆蓋晶圓基板之外周端緣部之至少一部分而導致晶片可獲取數目削減,於專利文獻1中揭示之先前之靜電吸附裝置100中,可確保製程達成所需之冷卻用之背面He之壓力,而無需使用機械夾盤,藉由基板吸附保持最大限度地有效利用晶圓基板上之表面積以使晶片可獲取數目增加。 When the mechanical chuck is used for the substrate holding, the number of wafers that can be obtained is reduced due to the mechanical chuck covering at least a portion of the peripheral edge portion of the wafer substrate. In the prior electrostatic adsorption device 100 disclosed in Patent Document 1, This ensures that the process achieves the pressure of the backside He for the desired cooling without the need for a mechanical chuck to maximize the efficient use of the surface area on the wafer substrate by substrate adsorption to increase the number of wafers available.

具體而言,說明先前之靜電吸附裝置100中如下之靜電吸附原理:該靜電吸附裝置100係RIE(reactive ion etching,反應式離子蝕刻)(陽極耦合)裝置,僅存在電漿生成用之上部電極,對設置於吸附構件104之絕緣體102內之電極103施加特定電壓而靜電吸附絕緣基板101。如此,並不再另外需要用以靜電吸附絕緣基板101之吸附構件104。又,專利文獻2中亦有以下描述,若不再另外進行基板吸附保持步驟,為了用以基板吸附保持而將處理氣體電漿化並於電漿蝕刻處理時進行基板吸附保持步驟,則即便未預期,亦會推進電漿蝕刻而無法進行正確之蝕刻加工。又,若另外執行基板吸附保持步驟,則步驟數會變多,導致半導體裝置之製造失去效率。 Specifically, the electrostatic adsorption principle of the electrostatic adsorption device 100 described above is described. The electrostatic adsorption device 100 is a RIE (Reactive Ion Etching) device, and only the upper electrode for plasma generation is present. The specific voltage is applied to the electrode 103 provided in the insulator 102 of the adsorption member 104 to electrostatically adsorb the insulating substrate 101. Thus, the adsorption member 104 for electrostatically adsorbing the insulating substrate 101 is not additionally required. Further, Patent Document 2 also has the following description. If the substrate adsorption holding step is not performed separately, the substrate is adsorbed and held in the plasma etching process for the substrate adsorption holding, and the substrate adsorption holding step is performed even if It is expected that plasma etching will also be promoted and correct etching processing will not be possible. Moreover, if the substrate adsorption holding step is additionally performed, the number of steps will increase, resulting in loss of efficiency in the manufacture of the semiconductor device.

專利文獻2中揭示之先前之基板處理裝置200中,可確保為了製程達成所需之壓力之冷卻用之背面He,並且由於係ICP(Inductively coupled plasma,感應耦合電漿)裝置故而可獨立地控制上部電極與下部電極,首先,在自處理氣體供給部206將處理氣體導入至處理腔室204內而將處理氣體壓力進行壓力調整為所需壓力之穩定步驟及其後之電漿蝕刻步驟之前,而另外執行基板吸附保持步驟,該基板吸附保持步驟係僅驅動控制上部電極,將導入至處理腔室204內之惰性氣體電漿化而使晶圓基板靜電吸附並保持於靜電吸盤201上。其原因在 於,若不再另外執行基板吸附保持步驟而是於電漿蝕刻處理時執行,則即便未預期,亦會推進電漿蝕刻而無法進行正確之電漿蝕刻加工。如此,若另外執行基板吸附保持步驟,則步驟數會變多,導致半導體裝置之製造失去效率。 In the substrate processing apparatus 200 of the prior art disclosed in Patent Document 2, the back surface He for cooling which achieves the required pressure for the process can be secured, and can be independently controlled by the ICP (Inductively Coupled Plasma) device. The upper electrode and the lower electrode, first, before the process gas is introduced into the processing chamber 204 from the processing gas supply unit 206 to adjust the pressure of the processing gas to a desired pressure, and before the plasma etching step, In addition, the substrate adsorption holding step is performed to drive only the upper electrode, and the inert gas introduced into the processing chamber 204 is plasmaized to electrostatically adsorb and hold the wafer substrate on the electrostatic chuck 201. The reason is If the substrate adsorption holding step is not performed separately but is performed during the plasma etching process, even if it is not expected, the plasma etching is advanced and the correct plasma etching process cannot be performed. As described above, if the substrate adsorption holding step is additionally performed, the number of steps becomes large, resulting in loss of efficiency in the manufacture of the semiconductor device.

本發明係解決上述先前之問題者,其目的在於提供一種可最大限度地有效利用絕緣體基板上之面積而使每1塊基板之晶片可獲取數目提高,並且不再另外需要吸附構件便可有效地進行製造,從而使製造成本效益提昇之基板處理裝置,及使用其之基板處理方法,使用其之半導體裝置之製造方法。 The present invention has been made in view of the above problems, and an object thereof is to provide an apparatus for maximally utilizing an area on an insulator substrate to increase the number of wafers that can be taken per one substrate, and which can effectively be used without additionally requiring an adsorption member. A substrate processing apparatus which is manufactured to improve the manufacturing cost, and a substrate processing method using the same, and a method of manufacturing the semiconductor device using the same.

本發明之基板處理方法係包含基板處理步驟者,該基板處理步驟係將基板配置於處理室內,對上部電極與下部電極分別獨立地供給電力,將該處理室內之處理氣體電漿化而進行基板處理,該基板處理方法於該基板處理步驟之前的將供給至該處理室內之該處理氣體之壓力調整為特定壓力之處理氣體壓力調整步驟中包含基板吸附步驟,該基板吸附步驟係僅對該上部電極供給電力而將供給至該處理室內之處理氣體電漿化,而使該基板帶有電荷並使該基板靜電吸附於該下部電極側,藉此達成上述目的。 The substrate processing method of the present invention includes a substrate processing step of disposing a substrate in a processing chamber, supplying electric power independently to the upper electrode and the lower electrode, and plasma-treating the processing gas in the processing chamber to perform the substrate. Processing, the substrate processing method includes a substrate adsorption step in the process gas pressure adjustment step of adjusting the pressure of the processing gas supplied to the processing chamber to a specific pressure before the substrate processing step, the substrate adsorption step is only for the upper portion The electrode supplies electric power to plasma the processing gas supplied into the processing chamber, and the substrate is charged and the substrate is electrostatically adsorbed to the lower electrode side, thereby achieving the above object.

又,較佳為,選擇與惰性氣體相比較易電漿化之電子釋放率較高之氣體種類作為本發明之基板處理方法中的處理氣體。 Further, it is preferable to select a gas type having a higher electron emission rate which is easier to be plasma-pulverized than the inert gas as the processing gas in the substrate processing method of the present invention.

進而,較佳為,本發明之基板處理方法中之易電漿化之電子釋放率較高之氣體種類係離子化電位低於特定值且氣體之電離電壓Vi亦低於另一特定值之處理氣體。 Further, in the substrate processing method of the present invention, it is preferable that the gas species having a high electron emission rate which is easy to be pulverized is a treatment in which the ionization potential is lower than a specific value and the ionization voltage Vi of the gas is lower than another specific value. gas.

進而,較佳為,本發明之基板處理方法之處理氣體含有離子化電位為320kcal/mol以下之元素之氣體作為吸附用氣體。 Furthermore, it is preferable that the processing gas of the substrate processing method of the present invention contains a gas having an ionization potential of 320 kcal/mol or less as an adsorption gas.

進而,較佳為,本發明之基板處理方法中之處理氣體含有O(氧) 及Cl(氯)中之至少任一者之氣體。 Further, it is preferable that the processing gas in the substrate processing method of the present invention contains O (oxygen) And a gas of at least one of Cl (chlorine).

進而,較佳為,本發明之基板處理方法中之基板吸附步驟中,上述基板係絕緣基板,藉由靜電吸盤(ESC,Electric Static Chuck)而靜電吸附該絕緣基板。 Furthermore, in the substrate adsorption step in the substrate processing method of the present invention, the substrate-based insulating substrate is preferably electrostatically adsorbed by an electrostatic chuck (ESC).

進而,較佳為藉由本發明之基板處理方法中之導入至基板之背面之冷媒而冷卻基板,並且控制基板溫度而進行上述基板處理。 Furthermore, it is preferable to cool the substrate by the refrigerant introduced into the back surface of the substrate in the substrate processing method of the present invention, and to control the substrate temperature to perform the substrate processing.

進而,較佳為,確保靜電吸附力,該靜電吸附力可確保本發明之基板處理方法中之基板之背面冷卻所需之冷媒之壓力。 Further, it is preferable to secure an electrostatic adsorption force which ensures the pressure of the refrigerant required for cooling the back surface of the substrate in the substrate processing method of the present invention.

進而,較佳為,本發明之基板處理方法中之基板之背面冷卻所需之冷媒係He氣體。 Further, it is preferable that the back surface of the substrate in the substrate processing method of the present invention cools the refrigerant He gas required.

進而,較佳為,作為本發明之基板處理方法中之基板處理之條件,使對上述上部電極之RF功率(radio frequency power,射頻功率)(施加電壓)為0.45w/cm2以上且75w/cm2以下、或為500W以上且2000W以下。 Furthermore, it is preferable that the RF power (radio frequency power) (applied voltage) to the upper electrode is 0.45 w/cm 2 or more and 75 w/ as a condition of substrate processing in the substrate processing method of the present invention. It is below cm 2 or is 500 W or more and 2000 W or less.

進而,較佳為,作為本發明之基板處理方法中之基板處理之條件,RF功率(施加電壓)為500W以上且1200W以下。 Furthermore, it is preferable that the RF power (applied voltage) is 500 W or more and 1200 W or less in the substrate processing conditions in the substrate processing method of the present invention.

進而,較佳為,本發明之基板處理方法中之基板係藍寶石基板。 Further, the substrate-based sapphire substrate in the substrate processing method of the present invention is preferred.

進而,較佳為,本發明之基板處理方法中之基板係SiC基板或化合物半導體基板。 Further, the substrate-based SiC substrate or the compound semiconductor substrate in the substrate processing method of the present invention is preferable.

進而,較佳為,於本發明之基板處理方法中之基板上設置有絕緣性膜,該絕緣性膜係易受到電性影響之膜且易帶有來自上述電漿之電荷。 Furthermore, it is preferable that an insulating film is provided on the substrate in the substrate processing method of the present invention, and the insulating film is a film which is susceptible to electrical influence and is easily charged with electric charges from the plasma.

進而,較佳為,本發明之基板處理方法中之易受電性影響之膜係光阻膜。 Further, a film-based photoresist film which is susceptible to electrical properties in the substrate processing method of the present invention is preferred.

進而,較佳為,本發明之基板處理方法中之基板上之膜狀態為 基板處理中殘留有上述光阻膜之狀態。 Furthermore, it is preferable that the film state on the substrate in the substrate processing method of the present invention is The state of the above-mentioned photoresist film remains in the substrate processing.

本發明之半導體裝置之製造方法係包含使用本發明之上述基板處理方法之電漿蝕刻步驟者,藉此達成上述目的。 The method of manufacturing a semiconductor device of the present invention includes the plasma etching step using the substrate processing method of the present invention, thereby achieving the above object.

本發明之基板處理裝置係於處理室內配置基板,對上部電極與下部電極分別獨立地供給電力,將該處理室內之處理氣體電漿化而進行基板處理者,且係於如下狀態下可實施該基板處理者:僅對該上部電極供給電力,將與惰性氣體相比較易電漿化之電子釋放率較高之供給至該處理室內之處理氣體電漿化,使該基板帶有電荷而使該基板靜電吸附於該下部電極側,藉此達成上述目的。 In the substrate processing apparatus of the present invention, the substrate is disposed in the processing chamber, and the upper electrode and the lower electrode are independently supplied with electric power, and the processing gas in the processing chamber is plasma-treated to perform substrate processing, and the substrate can be processed in the following state. The substrate processor: only supplies electric power to the upper electrode, and plasma-processes the processing gas supplied to the processing chamber with a higher electron emission rate than the inert gas, so that the substrate is charged The substrate is electrostatically adsorbed on the lower electrode side, thereby achieving the above object.

以下,根據上述構成而說明本發明之作用。 Hereinafter, the action of the present invention will be described based on the above configuration.

於本發明中,基板處理方法包含基板處理步驟,該基板處理步驟係將基板配置於處理室內,對上部電極與下部電極分別獨立地供給電力,將處理室內之處理氣體電漿化而進行基板處理;該基板處理方法於基板處理步驟之前的將供給至處理室內之該處理氣體之壓力調整為特定壓力之處理氣體壓力調整步驟中包含基板吸附步驟,該基板吸附步驟係僅對上部電極供給電力而將供給至處理室內之處理氣體電漿化,使基板帶有電荷而使基板靜電吸附於下部電極側。 In the present invention, the substrate processing method includes a substrate processing step of disposing the substrate in the processing chamber, supplying electric power independently to the upper electrode and the lower electrode, and plasma-treating the processing gas in the processing chamber to perform substrate processing. The substrate processing method includes a substrate adsorption step in which the substrate gas adsorption step is performed to adjust the pressure of the processing gas supplied to the processing chamber to a specific pressure before the substrate processing step, and the substrate adsorption step supplies power only to the upper electrode. The processing gas supplied into the processing chamber is plasma-formed to charge the substrate to electrostatically adsorb the substrate to the lower electrode side.

藉此,最大限度地有效利用絕緣體基板上之面積而使每1塊基板之晶片可獲取數目提高,並且使處理氣體壓力調整步驟兼用作基板吸附步驟使用,因而不再另外需要吸附構件便可有效地進行製造,從而使製造成本效益提昇。 Thereby, the area on the insulator substrate is utilized to the maximum extent to increase the number of wafers that can be taken per one substrate, and the process gas pressure adjustment step is also used as the substrate adsorption step, so that the adsorption member can be effectively eliminated. Manufacturing is done to make manufacturing cost-effective.

由以上所述,根據本發明,於將供給至處理室內之處理氣體之壓力調整為特定壓力之處理氣體壓力調整步驟中,僅對上部電極供給電力而將供給至處理室內之處理氣體電漿化,使基板帶有電荷而使基板靜電吸附於下部電極側,因而可最大限度地有效利用絕緣體基板上 之面積而使每1塊基板之晶片可獲取數目提高,並且不再另外需要吸附構件便可有效地進行製造,從而使製造成本效益提昇。 As described above, according to the present invention, in the processing gas pressure adjusting step of adjusting the pressure of the processing gas supplied into the processing chamber to a specific pressure, only the electric power is supplied to the upper electrode to plasma the processing gas supplied into the processing chamber. The substrate is charged with electricity to electrostatically adsorb the substrate to the lower electrode side, thereby maximizing the effective use of the insulator substrate. The area allows an increase in the number of wafers per one substrate, and the manufacturing member can be efficiently manufactured without additionally requiring an adsorption member, thereby making the manufacturing cost-effective.

1‧‧‧基板處理裝置 1‧‧‧Substrate processing unit

2‧‧‧處理腔室 2‧‧‧Processing chamber

3‧‧‧上部電極 3‧‧‧Upper electrode

4‧‧‧下部電極 4‧‧‧ lower electrode

5‧‧‧晶圓基板 5‧‧‧ Wafer Substrate

6‧‧‧電漿 6‧‧‧ Plasma

7‧‧‧ESC電極 7‧‧‧ESC electrode

11‧‧‧氮化物半導體發光元件 11‧‧‧Nitride semiconductor light-emitting elements

12‧‧‧藍寶石基板 12‧‧‧Sapphire substrate

13‧‧‧緩衝層 13‧‧‧buffer layer

14‧‧‧非摻雜GaN層 14‧‧‧Undoped GaN layer

15‧‧‧n型接觸層 15‧‧‧n type contact layer

16‧‧‧多重層 16‧‧‧Multiple layers

17‧‧‧多重量子井結構之發光層 17‧‧‧Lighting layer of multiple quantum well structure

18‧‧‧電子阻擋層 18‧‧‧Electronic barrier

19‧‧‧p型接觸層 19‧‧‧p-type contact layer

20‧‧‧透光性薄膜電極 20‧‧‧Transmissive thin film electrode

21‧‧‧P電極 21‧‧‧P electrode

22‧‧‧n電極 22‧‧‧n electrode

23‧‧‧保護膜 23‧‧‧Protective film

100‧‧‧靜電吸附裝置 100‧‧‧Electrostatic adsorption device

101‧‧‧絕緣基板 101‧‧‧Insert substrate

102‧‧‧絕緣體 102‧‧‧Insulator

103‧‧‧電極 103‧‧‧electrode

104‧‧‧吸附構件 104‧‧‧Adsorption components

105‧‧‧基板支持構件 105‧‧‧Substrate support member

200‧‧‧電漿處理裝置 200‧‧‧ Plasma processing unit

201‧‧‧靜電吸盤 201‧‧‧Electrostatic suction cup

202‧‧‧電極 202‧‧‧electrode

203‧‧‧電極 203‧‧‧electrode

204‧‧‧處理腔室 204‧‧‧Processing chamber

205‧‧‧惰性氣體供給部 205‧‧‧Inert gas supply

206‧‧‧處理氣體供給部 206‧‧‧Process Gas Supply Department

207‧‧‧冷卻氣體供給部 207‧‧‧Cooling gas supply department

208‧‧‧排氣裝置 208‧‧‧Exhaust device

209‧‧‧排氣泵 209‧‧‧Exhaust pump

210‧‧‧下部容器 210‧‧‧ Lower container

211‧‧‧排氣管 211‧‧‧Exhaust pipe

K‧‧‧絕緣基板 K‧‧‧Insert substrate

圖1係模式性表示本發明之實施形態1之基板處理裝置之剖面構造之主要部分構成圖。 Fig. 1 is a view schematically showing the configuration of a main part of a cross-sectional structure of a substrate processing apparatus according to a first embodiment of the present invention.

圖2係表示各種氣體之電離電壓Vi之圖。 Fig. 2 is a view showing the ionization voltage Vi of various gases.

圖3係表示原子編號、原子半徑(單位為埃)、元素符號、陰電性、離子化電位(單位為kcal/mol)之長週期型週期表之圖。 Fig. 3 is a view showing a long period type periodic table of an atom number, an atomic radius (in angstrom), an element symbol, an anion potential, and an ionization potential (unit: kcal/mol).

圖4係表示離子化電位(kcal/mol)相對於氣體之電離電壓Vi之關係之圖。 Fig. 4 is a graph showing the relationship between the ionization potential (kcal/mol) and the ionization voltage Vi of the gas.

圖5係相對於各種氣體之氣體之電離電壓Vi與離子化電位(kcal/mol)之關係之圖。 Fig. 5 is a graph showing the relationship between the ionization voltage Vi and the ionization potential (kcal/mol) with respect to gases of various gases.

圖6係表示晶圓基板5(藍寶石基板)之表面之凹凸形狀之縱橫比相對於晶圓基板5之溫度之關係之圖。 FIG. 6 is a view showing the relationship between the aspect ratio of the uneven shape on the surface of the wafer substrate 5 (sapphire substrate) with respect to the temperature of the wafer substrate 5.

圖7係表示作為He洩漏量之壓力依存性的He洩漏量(CC)相對於背面He壓力(KPa)之關係之圖。 Fig. 7 is a graph showing the relationship between the He leak amount (CC) and the back surface He pressure (KPa) as the pressure dependency of the He leak amount.

圖8係表示下部電極4之溫度高低時之晶圓基板之溫度相對於背面He壓力(KPa)之關係之圖。 Fig. 8 is a view showing the relationship between the temperature of the wafer substrate and the back surface He pressure (KPa) when the temperature of the lower electrode 4 is high.

圖9係表示晶圓基板之中央與外周之面內溫度相對於背面冷卻He壓力(Pa)之之關係之圖。 Fig. 9 is a view showing the relationship between the in-plane temperature of the center and the outer periphery of the wafer substrate with respect to the back surface cooling He pressure (Pa).

圖10係表示本發明之實施形態2之氮化物半導體發光元件之主要部分構成例之縱剖面圖。 Fig. 10 is a vertical cross-sectional view showing an example of a configuration of a main part of a nitride semiconductor light-emitting device according to a second embodiment of the present invention.

圖11係用以說明專利文獻1中揭示之先前之靜電吸附裝置之靜電吸附原理之模式圖。 Fig. 11 is a schematic view for explaining the principle of electrostatic adsorption of the prior electrostatic adsorption device disclosed in Patent Document 1.

圖12係概略地表示專利文獻2中揭示之先前之基板處理裝置之主要部分構成圖。 FIG. 12 is a view schematically showing the configuration of a main part of a substrate processing apparatus disclosed in Patent Document 2.

以下,一面參照圖式,一面對本發明之基板處理方法之實施形態1、及使用有其之半導體裝置之製造方法之實施形態2詳細地進行說明。再者,自圖式製作上之觀點而言,圖1及圖10中之構成構件各自之厚度、長度等並非係限定於圖示之構成者。 Hereinafter, the first embodiment of the substrate processing method of the present invention and the second embodiment of the method for manufacturing a semiconductor device using the same will be described in detail with reference to the drawings. Further, from the viewpoint of the production of the drawings, the thicknesses, lengths, and the like of the constituent members in FIGS. 1 and 10 are not limited to those shown in the drawings.

(實施形態1) (Embodiment 1)

圖1係模式性表示本發明之實施形態1之基板處理裝置之剖面構造之主要部分構成圖。 Fig. 1 is a view schematically showing the configuration of a main part of a cross-sectional structure of a substrate processing apparatus according to a first embodiment of the present invention.

於圖1中,本發明之實施形態1之基板處理裝置1係ICP(感應耦合電漿)裝置,因而可獨立地控制設置於處理腔室2內之上部電極3與下部電極4,且於下部電極4上直接搭載有絕緣基板之晶圓基板5。 In FIG. 1, the substrate processing apparatus 1 according to the first embodiment of the present invention is an ICP (Inductively Coupled Plasma) device, so that the upper electrode 3 and the lower electrode 4 provided in the processing chamber 2 can be independently controlled, and in the lower portion. The wafer substrate 5 on which the insulating substrate is mounted is directly mounted on the electrode 4.

本實施形態1之基板處理裝置1係於作為處理室之處理腔室2內配置有晶圓基板5,對上部電極3與下部電極4分別獨立地供給電力,並將處理腔室2內之處理氣體電漿化而進行基板處理者,且構成為以於如下狀態下可實施基板處理:僅對上部電極3供給電力,將與惰性氣體相比易電漿化之電子釋放率較高之供給至處理腔室2內之處理氣體電漿化,而使晶圓基板5帶有電荷並使晶圓基板5靜電吸附於下部電極4側。 In the substrate processing apparatus 1 of the first embodiment, the wafer substrate 5 is disposed in the processing chamber 2 as the processing chamber, and the upper electrode 3 and the lower electrode 4 are independently supplied with electric power, and the processing in the processing chamber 2 is performed. In the case where the substrate is plasma-treated, the substrate can be processed in such a manner that only the upper electrode 3 is supplied with electric power, and the electron emission rate which is easier to be plasma-pulverized than the inert gas is supplied to the substrate. The processing gas in the processing chamber 2 is plasma-charged, and the wafer substrate 5 is charged with electric charges, and the wafer substrate 5 is electrostatically adsorbed to the lower electrode 4 side.

該基板處理裝置1僅控制上部電極3,確保製程達成所需之壓力之冷卻用之背面He,並且不使用機械夾盤,而是藉由靜電吸附最大限度地有效利用絕緣基板之晶圓基板5上之表面積,於該狀態下將處理氣體而並非如先前般之惰性氣體導入至處理腔室2內從而將處理氣體壓力調整為特定壓力之處理氣體壓力調整步驟(穩定步驟)內,設置吸附保持步驟,該吸附保持步驟係藉由將處理氣體電漿化而成之電漿6,使晶圓基板5上帶有電漿6之陰電荷而使晶圓基板5靜電吸附於下部電極4上並且將其保持固定。其後,一併控制上部電極3與下部電極4 而實施電漿蝕刻步驟。 The substrate processing apparatus 1 controls only the upper electrode 3, ensures that the process reaches the back surface He for cooling of the required pressure, and does not use a mechanical chuck, but utilizes the wafer substrate 5 of the insulating substrate to the maximum extent by electrostatic adsorption. The upper surface area, in which the process gas is introduced, and the inert gas is not introduced into the processing chamber 2 as before, so that the process gas pressure is adjusted to a specific pressure in the process gas pressure adjusting step (stabilization step), and the adsorption retention is set. In the step of adsorbing and holding the plasma 6 by plasma-treating the processing gas, the wafer substrate 5 is electrostatically adsorbed on the lower electrode 4 by the negative charge of the plasma 6 on the wafer substrate 5 and Keep it fixed. Thereafter, the upper electrode 3 and the lower electrode 4 are controlled together. A plasma etching step is performed.

於該吸附保持步驟中,選擇電子釋放率較高之氣體種類作為處理氣體。藉由僅上部電極3之RF施加,而生成上述電子釋放率較高之氣體種類之電漿6,從而確保對於確保晶圓基板5表面之吸附力而言充分之電荷供給。藉由對ESC電極7之ESC電壓之施加,可與晶圓基板5之表面上所帶之電荷合併而獲取晶圓基板5對下部電極4之表面之充分之吸附力。吸附保持步驟之對ESC電極7之ESC電壓之施加時序係於穩定步驟開始時開始。基板吸附步驟藉由靜電吸盤(ESC)而靜電吸附絕緣基板之晶圓基板5。 In the adsorption holding step, a gas species having a high electron emission rate is selected as the processing gas. The plasma 6 of the gas type having a high electron emission rate is generated by the RF application of only the upper electrode 3, thereby ensuring sufficient charge supply for securing the adsorption force on the surface of the wafer substrate 5. By applying the ESC voltage of the ESC electrode 7, the charge on the surface of the wafer substrate 5 can be combined to obtain a sufficient adsorption force of the wafer substrate 5 on the surface of the lower electrode 4. The application timing of the ESC voltage of the ESC electrode 7 by the adsorption holding step is started at the beginning of the stabilization step. The substrate adsorption step electrostatically adsorbs the wafer substrate 5 of the insulating substrate by an electrostatic chuck (ESC).

進行上部電極3與下部電極4之RF個別控制、ESC方式之採用及對晶圓基板5之絕緣體表面之電子釋放率成為有效之條件(氣體種類、射頻功率、施加時序等)之選擇。總之,選擇易電漿化之電子釋放率較高之氣體種類作為處理氣體。使用圖2~圖5對此進行說明。 The RF individual control of the upper electrode 3 and the lower electrode 4, the adoption of the ESC method, and the selection of the conditions (gas type, radio frequency power, application timing, etc.) for the electron emission rate of the insulator surface of the wafer substrate 5 are made. In short, a gas type having a high electron emission rate which is easy to be plasma-treated is selected as a processing gas. This will be described using FIG. 2 to FIG. 5.

圖2係表示各種氣體之電離電壓Vi之圖。 Fig. 2 is a view showing the ionization voltage Vi of various gases.

電漿6中之電子係藉由氣體分子或原子之電離而形成。電離亦會藉由處於激發狀態之原子、分子彼此之碰撞或由光能產生之光電離而引起,但大部分之由被加速之電子之碰撞而產生之直接電離成為主要者。為了使氣體分子或原子電離,必須藉由碰撞而獲取某一定程度以上之能量。將電離所需之最低能量稱為電離電壓Vi,如圖2所示,根據氣體之種類而不同。可知He或Ar等稀有氣體類之電離電壓Vi較高,為10V~20V,而鹼金屬之電離電壓Vi較低,為3V~4V,故而易電離。 The electrons in the plasma 6 are formed by ionization of gas molecules or atoms. Ionization is also caused by the collision of atoms or molecules in an excited state or photoionization by light energy, but most of the direct ionization caused by the collision of accelerated electrons becomes the main one. In order to ionize a gas molecule or atom, it is necessary to acquire a certain level of energy by collision. The lowest energy required for ionization is referred to as the ionization voltage Vi, as shown in Fig. 2, depending on the type of gas. It can be seen that the ionization voltage Vi of a rare gas such as He or Ar is relatively high, being 10V to 20V, and the ionization voltage Vi of the alkali metal is low, being 3V to 4V, and thus is easily ionized.

圖3係表示原子編號、原子半徑(單位為埃)、元素符號、陰電性、離子化電位(單位為kcal/mol)之長週期型週期表之圖。 Fig. 3 is a view showing a long period type periodic table of an atom number, an atomic radius (in angstrom), an element symbol, an anion potential, and an ionization potential (unit: kcal/mol).

如圖3所示,複數之元素可分為非金屬元素、金屬元素、半金屬元素及稀有氣體元素。其中,元素符號為傾斜字體者常溫下為氣體。 常溫下氣體之非金屬元素係H、N、O、F、Cl。其中N不用作蝕刻氣體。離子化電位(單位為kcal/mol)較低之元素係O、F、Cl。因此,用於電漿蝕刻處理之處理氣體、且易電漿化之電子釋放率較高之氣體種類可選擇含有離子化電位較低之非金屬元素O、Cl之處理氣體。 As shown in FIG. 3, the plural elements can be classified into non-metal elements, metal elements, semi-metal elements, and rare gas elements. Among them, the element symbol is a slanted font and is a gas at normal temperature. The non-metallic elements of the gas at normal temperature are H, N, O, F, and Cl. N is not used as an etching gas. The elements with lower ionization potential (in kcal/mol) are O, F, and Cl. Therefore, the type of gas which is used for the plasma etching treatment gas and which has a high electron emission rate which is easy to be pulverized may be a processing gas containing a non-metal element O and Cl having a low ionization potential.

再者,稀有氣體元素不會形成化合物,故而此處並未記載關於其之陰電性。 Further, since a rare gas element does not form a compound, the negative electrical properties thereof are not described herein.

圖4係表示離子化電位(kcal/mol)相對於氣體之電離電壓Vi之關係之圖。 Fig. 4 is a graph showing the relationship between the ionization potential (kcal/mol) and the ionization voltage Vi of the gas.

於圖4中,氣體之電離電壓Vi與離子化電位(kcal/mol)具相關關係。總之,離子化電位(kcal/mol)越低,則氣體之電離電壓Vi亦會越為線性變低,易電漿化之電子釋放率較高之氣體種類係離子化電位較低、且氣體之電離電壓Vi亦較低之處理氣體。離子化電位較低時,較易以低電壓(施加電壓)而離子化。 In FIG. 4, the ionization voltage Vi of the gas is correlated with the ionization potential (kcal/mol). In short, the lower the ionization potential (kcal/mol), the more linear the ionization voltage Vi of the gas will be, and the higher the electron emission rate of the plasma-producing ion is, the lower the ionization potential, and the gas The treatment gas is also low in ionization voltage Vi. When the ionization potential is low, it is easier to ionize with a low voltage (applied voltage).

圖5係表示相對於各種氣體之氣體之電離電壓Vi與離子化電位(kcal/mol)之關係之圖。 Fig. 5 is a graph showing the relationship between the ionization voltage Vi and the ionization potential (kcal/mol) with respect to gases of various gases.

於圖5中,離子化電位(kcal/mol)越低之氣體則越易電離,因而靜電吸附良好。具體而言,氣體O2、O及Cl於靜電吸附方面良好。作為含有Cl之處理氣體,有Cl2(氯)、SiCl4(四氯化矽)、BCl3(三氯化硼)等。可將Cl2(氯)或SiCl4(四氯化矽)用作處理氣體而將GaN層等層進行蝕刻處理。可將BCl3(三氯化硼)用作處理氣體進行蝕刻處理而形成藍寶石基板等之表面凹凸形狀。 In Fig. 5, the gas having a lower ionization potential (kcal/mol) is more ionized, and thus the electrostatic adsorption is good. Specifically, the gases O 2 , O and Cl are excellent in electrostatic adsorption. Examples of the processing gas containing Cl include Cl 2 (chlorine), SiCl 4 (cerium tetrachloride), and BCl 3 (boron trichloride). A layer such as a GaN layer may be etched by using Cl 2 (chlorine) or SiCl 4 (ruthenium tetrachloride) as a processing gas. BCl 3 (boron trichloride) can be used as a processing gas for etching treatment to form a surface uneven shape of a sapphire substrate or the like.

圖6係表示晶圓基板5之表面之凹凸形狀縱橫比之晶圓基板溫度依存性之圖。 Fig. 6 is a view showing the temperature dependence of the wafer substrate on the aspect ratio of the surface of the wafer substrate 5.

於圖6中,晶圓基板5(藍寶石基板)之表面之凹凸形狀之縱橫比會根據晶圓基板5之溫度而變化,因而為了獲得所需之藍寶石基板表面之凹凸形狀之縱橫比,必須設定晶圓基板5之溫度。晶圓基板5之溫度 會受到下部電極4之溫度、與晶圓基板5翹曲之情形時傳遞下部電極4之溫度之背面He之壓力的影響。 In FIG. 6, the aspect ratio of the uneven shape of the surface of the wafer substrate 5 (sapphire substrate) varies depending on the temperature of the wafer substrate 5, and therefore, in order to obtain the aspect ratio of the uneven shape of the surface of the sapphire substrate required, it is necessary to set The temperature of the wafer substrate 5. Wafer substrate 5 temperature The influence of the pressure of the back surface He of the temperature of the lower electrode 4 when the temperature of the lower electrode 4 is warped with the wafer substrate 5 is affected.

圖7係表示作為He洩漏量之壓力依存性的He洩漏量(CC)相對於背面He壓力(KPa)之關係之圖。 Fig. 7 is a graph showing the relationship between the He leak amount (CC) and the back surface He pressure (KPa) as the pressure dependency of the He leak amount.

於圖7中,背面He壓力(KPa)越大則背面He之洩漏量亦越多。晶圓基板5之翹曲量越大則背面He之洩漏量亦越多。若洩漏量變多,則晶圓基板5無法為了控制為特定之溫度而進行冷卻。如此,若洩漏量變多,則無法將晶圓基板5控制為所需之溫度,因而被蝕刻之凹凸形狀之縱橫比亦變化而不會成為所需之縱橫比。為了防止該情形,藉由確保吸附力而抑制背面He之洩漏量,使面內溫度之均勻性提高,藉此,被蝕刻之凹凸形狀之形狀容限亦提高。 In Fig. 7, the larger the back He pressure (KPa), the more the back surface He leaks. The larger the amount of warpage of the wafer substrate 5, the larger the amount of leakage of the back surface He. When the amount of leakage increases, the wafer substrate 5 cannot be cooled for control to a specific temperature. As described above, if the amount of leakage increases, the wafer substrate 5 cannot be controlled to a desired temperature, and thus the aspect ratio of the embossed uneven shape does not change to a desired aspect ratio. In order to prevent this, the amount of leakage of the back surface He is suppressed by securing the adsorption force, and the uniformity of the in-plane temperature is improved, whereby the shape tolerance of the embossed uneven shape is also improved.

圖8係表示下部電極4之溫度高低時之晶圓基板之溫度相對於背面He壓力(KPa)之關係之圖。 Fig. 8 is a view showing the relationship between the temperature of the wafer substrate and the back surface He pressure (KPa) when the temperature of the lower electrode 4 is high.

於圖8中,背面He壓力(KPa)越高,則被處理基板之溫度越降低。其表示於下部電極4之溫度為攝氏35度之情形及下部電極4之溫度為攝氏55度之情形時均降低。背面He之壓力越高,則作為晶圓基板5之溫度越降低,但為了獲得所需之凹凸形狀而必須控制為所需之晶圓基板5之溫度。 In Fig. 8, the higher the back He pressure (KPa), the lower the temperature of the substrate to be processed. It is shown that the temperature of the lower electrode 4 is 35 degrees Celsius and the temperature of the lower electrode 4 is 55 degrees Celsius. The higher the pressure of the back surface He, the lower the temperature as the wafer substrate 5. However, in order to obtain the desired uneven shape, it is necessary to control the temperature of the wafer substrate 5 required.

圖9係表示晶圓基板之中央與外周之面內溫度相對於背面冷卻He壓力(Pa)之關係之圖。 Fig. 9 is a view showing the relationship between the in-plane temperature of the center and the outer periphery of the wafer substrate with respect to the back surface cooling He pressure (Pa).

於圖9中,晶圓基板5之中央部(Center)與外周部(Top)之背面冷卻He壓力(Pa)越高,則晶圓基板5之溫度越一致。如此,可知伴隨背面冷卻He壓力(Pa)之上升,而使晶圓基板5之面內溫度之均勻性得以改善。 In FIG. 9, the higher the back surface cooling He pressure (Pa) of the center portion (Center) and the outer peripheral portion (Top) of the wafer substrate 5, the more uniform the temperature of the wafer substrate 5. As described above, it is understood that the uniformity of the in-plane temperature of the wafer substrate 5 is improved with an increase in the back surface cooling He pressure (Pa).

由以上所述,本實施形態1之基板處理方法係包含基板處理步驟者,該基板處理步驟係將晶圓基板5配置於作為處理室之處理腔室2 內,對上部電極3與下部電極4分別獨立地供給電力,將處理腔室2內之處理氣體電漿化而進行基板處理,且該基板處理方法於電漿蝕刻處理之基板處理步驟之前的將供給至處理腔室2內之處理氣體之壓力調整為特定壓力之處理氣體壓力調整步驟(穩定步驟)中,包含基板吸附步驟,該基板吸附步驟係僅對上部電極3供給電力而將供給至處理腔室2內之處理氣體電漿化,而使晶圓基板5帶有電荷,並使晶圓基板5靜電吸附於下部電極4側。該情形時,選擇電子釋放率較高之氣體種類作為所使用之處理氣體。 As described above, the substrate processing method according to the first embodiment includes a substrate processing step of disposing the wafer substrate 5 in the processing chamber 2 as a processing chamber. Internally, the upper electrode 3 and the lower electrode 4 are independently supplied with electric power, and the processing gas in the processing chamber 2 is plasma-treated to perform substrate processing, and the substrate processing method is performed before the substrate processing step of the plasma etching process. The processing gas pressure adjusting step (stabilizing step) for adjusting the pressure of the processing gas supplied into the processing chamber 2 to a specific pressure includes a substrate adsorption step of supplying power only to the upper electrode 3 and supplying it to the processing. The processing gas in the chamber 2 is plasma-charged, and the wafer substrate 5 is charged, and the wafer substrate 5 is electrostatically adsorbed to the lower electrode 4 side. In this case, a gas type having a high electron emission rate is selected as the processing gas to be used.

如此,藉由將電漿蝕刻處理前之穩定步驟兼用作基板吸附步驟,而可避免如先前般另外設置基板吸附步驟而導致多餘之步驟之增加及未預期地進行電漿蝕刻,從而可更有效地進行所需之電漿蝕刻處理等基板處理。 In this way, by using the stabilization step before the plasma etching treatment as the substrate adsorption step, it is possible to avoid an additional step of the substrate adsorption step as before, resulting in an increase in unnecessary steps and an unexpected plasma etching, thereby being more effective. Substrate processing such as plasma etching treatment is performed.

作為處理氣體,使用含有離子化電位為320kcal/mol以下之元素之吸附用氣體。處理氣體作為吸附用氣體,係包含O(氧)及Cl(氯)氣體中之至少任一者之氣體。 As the processing gas, an adsorption gas containing an element having an ionization potential of 320 kcal/mol or less is used. The processing gas is a gas for adsorption, and is a gas containing at least one of O (oxygen) and Cl (chlorine) gases.

基板吸附步驟中,基板係絕緣基板,藉由靜電吸盤(ESC)而靜電吸附絕緣基板之晶圓基板5。 In the substrate adsorption step, the substrate is an insulating substrate, and the wafer substrate 5 of the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).

藉由導入至晶圓基板5之背面上之冷媒而冷卻基板,並且控制基板溫度而進行基板處理。必須確保可確保晶圓基板5之背面冷卻所需之冷媒之壓力之靜電吸附力。作為晶圓基板5之背面冷卻所需之冷媒,使用He氣體。 The substrate is cooled by cooling the substrate introduced onto the back surface of the wafer substrate 5, and the substrate temperature is controlled to perform substrate processing. It is necessary to ensure the electrostatic adsorption force of the pressure of the refrigerant required to ensure the back surface of the wafer substrate 5 to be cooled. He gas is used as a refrigerant required for cooling the back surface of the wafer substrate 5.

作為電漿蝕刻處理(基板處理)之條件,對上部電極3之RF功率(施加電壓)為0.45w/cm2以上且75w/cm2以下或500W以上且2000W以下。更佳為,作為基板處理之條件,RF功率(施加電壓)為500W以上且1200W以下。RF功率1200W~2000W係目前之最大輸出RF功率。 As the plasma etching process (substrate processing) of the condition, the upper electrode 3 to the RF power (applied voltage) is 2 or more and 2 or less, or less than 500W and 2000W 0.45w / cm 75w / cm. More preferably, the RF power (applied voltage) is 500 W or more and 1200 W or less as a condition of substrate processing. The RF power of 1200W~2000W is the current maximum output RF power.

此處,使用藍寶石基板作為晶圓基板5,但亦可為SiC基板或化 合物半導體基板。於晶圓基板5上設置有易帶有來自電漿之電荷之絕緣性膜、且易受電性影響之膜時,靜電吸附力為良好而較佳。作為易受電性影響之膜,有光阻膜等。進而,為了保持靜電吸附力,晶圓基板5上之膜狀態較佳為於基板處理中殘留有光阻膜。 Here, a sapphire substrate is used as the wafer substrate 5, but it may be a SiC substrate or a SiC substrate. Compound semiconductor substrate. When a film which is easily provided with an insulating film derived from a charge of plasma and which is easily affected by electrical properties is provided on the wafer substrate 5, the electrostatic adsorption force is good. As a film which is susceptible to electrical influence, there is a photoresist film or the like. Further, in order to maintain the electrostatic adsorption force, the film state on the wafer substrate 5 is preferably such that a photoresist film remains in the substrate processing.

以上已描述,使用機械夾具等時會使晶圓邊界上之可獲取數目產生損失,因而為了最大限度地有效利用晶圓基板5之表面積而必需使用ESC。基板吸附步驟中,晶圓基板5係絕緣基板,藉由靜電吸盤(ESC)而靜電吸附絕緣基板。 As described above, the use of a mechanical jig or the like causes a loss in the number of available wafer boundaries, and therefore ESC is necessary in order to maximize the effective use of the surface area of the wafer substrate 5. In the substrate adsorption step, the wafer substrate 5 is an insulating substrate, and the insulating substrate is electrostatically adsorbed by an electrostatic chuck (ESC).

晶圓基板5之材質為絕緣體,為難以電性吸附之材質,因而使用靜電吸盤(ESC)後,由於確保吸附力為課題,故為了使晶圓基板5上充分地帶有來自電漿6之電荷,而選擇易電漿化之電子釋放率較高之氣體種類作為處理氣體。所謂易電漿化之電子釋放率較高之氣體種類,係離子化電位較低且氣體之電離電壓Vi亦較低之處理氣體。 The material of the wafer substrate 5 is an insulator and is a material that is difficult to be electrically adsorbed. Therefore, since the electrostatic chuck (ESC) is used, since the adsorption force is ensured, the wafer substrate 5 is sufficiently charged with the electric charge from the plasma 6. And the gas type with high electron emission rate which is easy to be pulverized is selected as the processing gas. The gas type having a high electron emission rate which is easy to be ionized is a processing gas having a low ionization potential and a low ionization voltage Vi of the gas.

為了確保凹凸形狀之縱橫比控制等之製程性能提昇或製程穩定化,即面內均勻性、用以確保容限所需之充分之基板溫度控制之冷卻力,不僅需要晶圓基板5之載置電極溫度,而且為了傳遞該溫度而需要一定程度以上之背面He壓力。 In order to ensure process performance improvement or process stabilization such as aspect ratio control of the uneven shape, that is, in-plane uniformity, sufficient substrate temperature control cooling power required to ensure tolerance, not only the mounting of the wafer substrate 5 is required. The electrode temperature, and a certain amount of back He pressure, is required to transfer this temperature.

此處,對6英吋之晶圓基板5進行各種試驗,而伴隨今後之大口徑化,晶圓基板5之翹曲亦會增大。伴隨該晶圓基板5之翹曲之增大,背面He之密封變得困難,He洩漏量亦會增加。 Here, various tests are performed on the 6-inch wafer substrate 5, and the warpage of the wafer substrate 5 is also increased with the increase in diameter in the future. As the warpage of the wafer substrate 5 increases, the sealing of the back surface He becomes difficult, and the amount of He leakage also increases.

為了確保靜電吸盤(ESC)之吸附力,必需使晶圓基板5之表面上帶有更多之電荷。使晶圓基板5之表面上帶有更多之電荷依存於離子化電位較低且氣體之電離電壓Vi亦較低之元素種。 In order to secure the adsorption force of the electrostatic chuck (ESC), it is necessary to have more charge on the surface of the wafer substrate 5. The charge on the surface of the wafer substrate 5 is more dependent on the element species having a lower ionization potential and a lower ionization voltage Vi of the gas.

(實施形態2) (Embodiment 2)

上述實施形態1中對基板處理裝置及使用其之基板處理方法進行了說明,本實施形態2中,一面參照圖式,一面詳細地說明將包含使 用有該基板處理方法之電漿蝕刻步驟之半導體裝置之製造方法應用於氮化物半導體發光元件之製造方法之情形。 In the first embodiment, the substrate processing apparatus and the substrate processing method using the same are described. In the second embodiment, the details will be described with reference to the drawings. A method of manufacturing a semiconductor device using a plasma etching step of the substrate processing method is applied to a method of manufacturing a nitride semiconductor light-emitting device.

圖10係表示本發明之實施形態2之氮化物半導體發光元件之主要部分構成例之縱剖面圖。 Fig. 10 is a vertical cross-sectional view showing an example of a configuration of a main part of a nitride semiconductor light-emitting device according to a second embodiment of the present invention.

於圖10中,本實施形態2之氮化物半導體發光元件11中,在作為於表面形成有凹凸之厚度為約1300μm之基板之例如藍寶石基板12上,成膜有包含氮化鋁(AlN)之膜厚為約15nm之緩衝層13。於該緩衝層13上成膜有包含非摻雜之GaN之膜厚為約500nm之非摻雜GaN層14。單晶性基板包含該等藍寶石基板12、緩衝層13及非摻雜GaN層14。 In the nitride semiconductor light-emitting device 11 of the second embodiment, for example, on a sapphire substrate 12 having a substrate having a thickness of about 1300 μm on the surface, an aluminum nitride (AlN) film is formed. The buffer layer 13 having a film thickness of about 15 nm. An undoped GaN layer 14 containing undoped GaN having a film thickness of about 500 nm is formed on the buffer layer 13. The single crystal substrate includes the sapphire substrate 12, the buffer layer 13, and the undoped GaN layer 14.

進而,於本實施形態1之氮化物半導體發光元件11中,於該單晶性基板上形成有包含摻雜有1×1018/cm3之矽(Si)之GaN之膜厚為約5μm的n型接觸層15(高載子濃度n+層)。於該n型接觸層15上形成有多重層16,於該多重層16上形成有多重量子井結構之發光層17。 Further, in the nitride semiconductor light-emitting device 11 of the first embodiment, a film thickness of GaN containing bismuth (Si) doped with 1 × 10 18 /cm 3 is formed on the single crystal substrate to be about 5 μm. N-type contact layer 15 (high carrier concentration n + layer). A plurality of layers 16 are formed on the n-type contact layer 15, and a light-emitting layer 17 of a multiple quantum well structure is formed on the multiple layers 16.

該多重層16中,交替積層有複數之包含InxGa1-xN(0<x<0.3)之第1層與包含GaN之第2層。此處,該多重層16中,例如積層有5對之膜厚為3nm之包含In0.03Ga0.97N之第1層、與膜厚為20nm之包含GaN之第2層積層。 In the multiple layer 16, a plurality of layers including In x Ga 1-x N (0 < x < 0.3) and a second layer containing GaN are alternately laminated. Here, in the multiple layer 16, for example, five pairs of a first layer including In 0.03 Ga 0.97 N having a film thickness of 3 nm and a second layer including GaN having a film thickness of 20 nm are laminated.

於該多重層16中之第1層中,添加有作為一導電型雜質之Si,且於其濃度為5×1016cm-3~1×1018cm-3(更佳為1×1017cm-3~1×1018cm-3)之範圍內添加,將發光層17承受之靜電破壞能量(mJ/cm2)設為20以上且40以下(更佳為20以上且35以下)。 In the first layer of the multiple layers 16, Si is added as a conductive impurity, and the concentration thereof is 5 × 10 16 cm -3 to 1 × 10 18 cm -3 (more preferably 1 × 10 17). In the range of cm -3 to 1 × 10 18 cm -3 ), the electrostatic breakdown energy (mJ/cm 2 ) which the luminescent layer 17 receives is 20 or more and 40 or less (more preferably 20 or more and 35 or less).

具體而言,在表示以特定項目之逆向電氣特性(逆向電流)為參數而發光層17承受之靜電破壞能量(mJ/cm2)與多重層16之第1層中之Si濃度之關係的特性曲線中,設定為與靜電破壞能量(mJ/cm2)之極小值對應之Si之濃度。 Specifically, the relationship between the electrostatic breakdown energy (mJ/cm 2 ) received by the light-emitting layer 17 and the Si concentration in the first layer of the multiple layers 16 is represented by the reverse electrical characteristic (reverse current) of the specific item as a parameter. In the curve, the concentration of Si corresponding to the minimum value of the electrostatic breakdown energy (mJ/cm 2 ) is set.

多重量子井結構之發光層17之井層包含至少含有In之InyGa1-yN(0≦y<0.3)。如此,此處,多重量子井結構之發光層17中,例如積層有3對之膜厚為3nm之包含In0.2Ga0.8N之井層、與膜厚為20nm之包含GaN之障壁層。 The well layer of the light-emitting layer 17 of the multiple quantum well structure contains In y Ga 1-y N (0 ≦ y < 0.3) containing at least In. As described above, in the light-emitting layer 17 of the multiple quantum well structure, for example, three pairs of well layers including In 0.2 Ga 0.8 N having a film thickness of 3 nm and a barrier layer containing GaN having a film thickness of 20 nm are laminated.

進而,於本實施形態2之氮化物半導體發光元件11中,於該發光層17上,形成有摻雜有2×1019/cm3之Mg之膜厚為25nm之包含p型Al0.15Ga0.85N的p型層即電子阻擋層18。於該電子阻擋層18上,形成有摻雜有8×1019之Mg之膜厚為100nm之包含p型GaN的p型接觸層19。 Further, in the nitride semiconductor light-emitting device 11 of the second embodiment, p-type Al 0.15 Ga 0.85 including a film doped with 2 × 10 19 /cm 3 of Mg and having a film thickness of 25 nm is formed on the light-emitting layer 17 . The p-type layer of N is the electron blocking layer 18. On the electron blocking layer 18, a p-type contact layer 19 containing p-type GaN doped with 8 × 10 19 Mg and having a film thickness of 100 nm was formed.

於該p型接觸層19上,形成有由金屬蒸鍍而產生之透光性薄膜電極20(ITO,Indium Tin Oxide,氧化銦錫)。於透光性薄膜電極20之一部分上形成有p電極21。 On the p-type contact layer 19, a light-transmissive thin film electrode 20 (ITO, Indium Tin Oxide, indium tin oxide) which is formed by metal deposition is formed. A p-electrode 21 is formed on a portion of the translucent thin film electrode 20.

另一方面,使n型接觸層15之端部至中途為止露出,且於其上形成有n電極22。於p電極21及n電極22上之最上部,形成有包含作為SixOy膜之SiO2膜之耐濕度用等之保護膜23。 On the other hand, the end portion of the n-type contact layer 15 is exposed to the middle, and the n-electrode 22 is formed thereon. On the uppermost portion of the p-electrode 21 and the n-electrode 22, a protective film 23 containing a SiO 2 film as a Si x O y film for humidity resistance or the like is formed.

保護膜23係形成於透光性薄膜電極20、p電極21、n電極22及n型接觸層15之露出表面上,進而形成於至n型接觸層15之端部中途為止之多重層16、發光層17、電子阻擋層18、p型接觸層19及透光性薄膜電極20(ITO)之蝕刻去除側面上。 The protective film 23 is formed on the exposed surfaces of the translucent film electrode 20, the p-electrode 21, the n-electrode 22, and the n-type contact layer 15, and is formed on the plurality of layers 16 to the end of the end portion of the n-type contact layer 15, The luminescent layer 17, the electron blocking layer 18, the p-type contact layer 19, and the translucent thin film electrode 20 (ITO) are etched away on the side surface.

如此,保護膜23係覆蓋p電極21、n電極22及元件表面而進行保護者。保護膜23可為SiO2膜之單層構造,亦可為作為SixNy膜之SiN膜、與其上之作為SixOy膜之SiO2膜之2層構造。又,亦可上下顛倒,為作為SixOy膜之SiO2膜、與其上之作為SixNy膜之SiN膜之2層構造。於該等之情形時,SiN膜係作為鈍化膜而發揮功能。 In this manner, the protective film 23 covers the p-electrode 21, the n-electrode 22, and the surface of the element for protection. Protective film 23 may be a single layer structure of SiO 2 film, it may also be used as SiN Si x N y film of the film, on which the two-layer structure as membrane 2 Si x O SiO y of the film. Further, also upside down, as a Si x O SiO y film of the film 2, on which the two-layer structure as SiN Si x N y film of the film. In such cases, the SiN film functions as a passivation film.

總之,保護膜23包含SixOy膜、SixNy膜及SixOyNz膜中之至少SixOy膜。 In short, the protective film 23 contains at least a Si x O y film of a Si x O y film, a Si x N y film, and a Si x O y N z film.

其次,對上述構成之氮化物半導體發光元件11之製造方法進行說 明。 Next, a method of manufacturing the nitride semiconductor light-emitting device 11 having the above configuration will be described. Bright.

如圖10所示,本實施形態2之氮化物半導體發光元件11之製造方法包含:藍寶石基板12之基板收容步驟,其係將藍寶石基板12收容於特定位置;表面凹凸加工步驟,其係於藍寶石基板12之表面以特定之縱橫比而形成凹凸;MOCVD(Metal Organic Chemical Vapor Deposition,金屬有機化學氣相沈積)步驟,其係藉由MOCVD法,於藍寶石基板12之表面凹凸加工面上,依序形成緩衝層13、非摻雜GaN層14、n型接觸層15、多重層16、多重量子井結構之發光層17、電子阻擋層18及p型接觸層19;透明性電極形成步驟,其係於p型接觸層19上形成透光性薄膜電極20;p電極21及n電極22之電極形成步驟,其係將基板端部蝕刻去除至n型接觸層15之中途為止而使n型接觸層15之端部於中途露出,於n型接觸層15之端部表面上形成n電極22,並且於透光性薄膜電極20之一部分表面上形成p電極21;保護膜形成步驟,其係於透光性薄膜電極20、p電極21、n電極22及n型接觸層15之露出表面、進而於蝕刻去除側面上形成用於耐濕度用等之保護膜23;及電極開口部步驟,其係使p電極21及n電極22上之保護膜23分別開口。 As shown in FIG. 10, the method for manufacturing the nitride semiconductor light-emitting device 11 of the second embodiment includes a substrate housing step of the sapphire substrate 12, wherein the sapphire substrate 12 is housed at a specific position, and a surface unevenness processing step is performed on the sapphire. The surface of the substrate 12 is formed with irregularities at a specific aspect ratio; a MOCVD (Metal Organic Chemical Vapor Deposition) step is performed on the surface of the sapphire substrate 12 by the MOCVD method, in order Forming a buffer layer 13, an undoped GaN layer 14, an n-type contact layer 15, a multiple layer 16, a light-emitting layer 17 of a multiple quantum well structure, an electron blocking layer 18, and a p-type contact layer 19; a transparent electrode forming step A transparent thin film electrode 20 is formed on the p-type contact layer 19; an electrode forming step of the p-electrode 21 and the n-electrode 22 is performed by etching the end portion of the substrate to the middle of the n-type contact layer 15 to form an n-type contact layer. The end portion of the 15 is exposed halfway, an n-electrode 22 is formed on the end surface of the n-type contact layer 15, and a p-electrode 21 is formed on a surface of a portion of the translucent thin film electrode 20; a protective film forming step a protective film 23 for moisture resistance or the like is formed on the exposed surfaces of the transparent thin film electrode 20, the p-electrode 21, the n-electrode 22, and the n-type contact layer 15, and further, an electrode opening portion is formed on the etching removal side surface; The protective film 23 on the p electrode 21 and the n electrode 22 is opened, respectively.

於作為半導體裝置之製造方法之氮化物半導體發光元件11之製造方法中,於在藍寶石基板12之表面形成凹凸之表面凹凸加工步驟、及將基板端部蝕刻去除至n型接觸層15之中途為止而使n型接觸層15之端部於中途露出之蝕刻步驟中,使用上述實施形態1之基板處理方法正確地進行更為良好之電漿蝕刻處理。如此,氮化物半導體發光元件11之製造方法中,於將供給至處理腔室2內之處理氣體之壓力調整為特定壓力之處理氣體壓力調整步驟內,包含使用有上述實施形態1之基板處理方法之電漿蝕刻步驟,上述實施形態1之基板處理方法係僅對上部電極3供給電力而將供給至處理腔室2內之處理氣體電漿化,使晶圓基板5帶有電荷,並使晶圓基板5靜電吸附於下部電極4側。 In the method of manufacturing the nitride semiconductor light-emitting device 11 as a method of manufacturing a semiconductor device, the surface unevenness processing step of forming the unevenness on the surface of the sapphire substrate 12 and the etching of the substrate end portion to the n-type contact layer 15 are performed. In the etching step in which the end portion of the n-type contact layer 15 is exposed in the middle, the substrate processing method according to the first embodiment described above is used to accurately perform a more excellent plasma etching treatment. In the manufacturing method of the nitride semiconductor light-emitting device 11, the substrate processing method using the above-described first embodiment is included in the processing gas pressure adjusting step of adjusting the pressure of the processing gas supplied into the processing chamber 2 to a specific pressure. In the plasma etching step, in the substrate processing method according to the first embodiment, only the electric power supplied to the processing chamber 2 is plasma-charged to the upper electrode 3, and the wafer substrate 5 is charged and the crystal is charged. The circular substrate 5 is electrostatically adsorbed to the lower electrode 4 side.

因此,藉由本實施形態2之氮化物半導體發光元件11之製造方法,於電漿蝕刻步驟中,亦可最大限度地有效利用絕緣體基板上之面積而使每1塊基板之晶片可獲取數目提高,並且不再另外需要吸附構件便可有效地進行製造,從而使製造成本效益提昇。 Therefore, in the method of manufacturing the nitride semiconductor light-emitting device 11 of the second embodiment, in the plasma etching step, the area on the insulator substrate can be utilized to the maximum extent, and the number of wafers that can be obtained per one substrate can be increased. Moreover, the adsorption member can be effectively manufactured without additional need for manufacturing, thereby making the manufacturing cost-effective.

再者,本實施形態2中,對LED(light emitting diode,發光二極體)之氮化物半導體發光元件11之製造方法進行了說明,但並不限於此,只要係包含使用有上述實施形態1之基板處理方法之電漿蝕刻步驟之半導體裝置之製造方法即可。 In the second embodiment, a method of manufacturing the nitride semiconductor light-emitting device 11 of an LED (light emitting diode) has been described. However, the present invention is not limited thereto, and the first embodiment is used as described above. The method of manufacturing the semiconductor device in the plasma etching step of the substrate processing method may be used.

如上般使用本發明之較佳之實施形態1、2而例示了本發明,但本發明不應限定於該實施形態1、2而進行解釋。可理解本發明應僅藉由申請專利範圍而解釋其範圍。本業者根據本發明之具體較佳之實施形態1、2之記載而可理解,可根據本發明之記載及技術常識而實施等價之範圍。關於本說明書中引用之專利、專利申請及文獻,可理解與將其內容本身具體地記載於本說明書中同樣地,應將其內容作為對本說明書之參考而援引。 The present invention has been exemplified as described above using the preferred embodiments 1 and 2 of the present invention, but the present invention is not limited to the first and second embodiments. It is to be understood that the invention is to be construed as limited only by the scope of the claims. The present invention can be understood from the description of the preferred embodiments 1 and 2 of the present invention, and equivalents can be made according to the description of the present invention and the technical knowledge. The patents, patent applications, and documents cited in the present specification are to be understood as being specifically described in the specification.

[產業上之可利用性] [Industrial availability]

本發明於將被處理基板靜電吸附並固定,並且對被處理基板進行電漿乾式蝕刻等特定之處理時所使用之基板處理裝置、及使用其之基板處理方法、使用其之半導體裝置之製造方法之領域內,於將供給至處理室內之處理氣體之壓力調整為特定壓力之處理氣體壓力調整步驟內,僅對上部電極供給電力而將供給至處理室內之處理氣體電漿化,使基板帶有電荷並使基板靜電吸附於下部電極側,因此可最大限度地有效利用絕緣體基板上之面積而使每1塊基板之晶片可獲取數目提高,並且不再另外需要吸附構件便可有效地進行製造,從而使製造成本效益提昇。 The substrate processing apparatus used for electrostatically adsorbing and fixing a substrate to be processed, and performing specific processing such as plasma dry etching on the substrate to be processed, and a substrate processing method using the same, and a method of manufacturing the semiconductor device using the same In the process gas pressure adjustment step of adjusting the pressure of the processing gas supplied to the processing chamber to a specific pressure, only the electric power is supplied to the upper electrode to plasma the processing gas supplied into the processing chamber, so that the substrate is provided with The electric charge electrostatically adsorbs the substrate to the lower electrode side, so that the area on the insulator substrate can be utilized to the maximum extent, and the number of wafers that can be obtained per one substrate can be increased, and the manufacturing member can be efficiently manufactured without additionally requiring an adsorption member. Thereby making the manufacturing cost-effective.

1‧‧‧基板處理裝置 1‧‧‧Substrate processing unit

2‧‧‧處理腔室 2‧‧‧Processing chamber

3‧‧‧上部電極 3‧‧‧Upper electrode

4‧‧‧下部電極 4‧‧‧ lower electrode

5‧‧‧晶圓基板 5‧‧‧ Wafer Substrate

6‧‧‧電漿 6‧‧‧ Plasma

7‧‧‧ESC電極 7‧‧‧ESC electrode

Claims (6)

一種基板處理方法,其係包含基板處理步驟者,該基板處理步驟係將基板配置於處理室內,對上部電極與下部電極分別獨立地供給電力,將該處理室內之處理氣體電漿化而進行基板處理,且該基板處理方法於該基板處理步驟之前的將供給至該處理室內之該處理氣體之壓力調整為特定壓力之處理氣體壓力調整步驟中包含基板吸附步驟,上述基板吸附步驟係僅對該上部電極供給電力而將供給至該處理室內之處理氣體電漿化,使該基板帶有電荷並使該基板靜電吸附於該下部電極側。 A substrate processing method comprising a substrate processing step of disposing a substrate in a processing chamber, separately supplying electric power to the upper electrode and the lower electrode, and plasma-treating the processing gas in the processing chamber to perform a substrate Processing, and the substrate processing method includes a substrate adsorption step in the process gas pressure adjustment step of adjusting the pressure of the processing gas supplied to the processing chamber to a specific pressure before the substrate processing step, wherein the substrate adsorption step is only The upper electrode supplies electric power, and plasmas the processing gas supplied into the processing chamber, and charges the substrate to electrostatically adsorb the substrate on the lower electrode side. 如請求項1之基板處理方法,其中選擇與惰性氣體相比較易電漿化之電子釋放率較高之氣體種類作為上述處理氣體。 The substrate processing method according to claim 1, wherein a gas species having a higher electron emission rate which is easier to be plasma-pulverized than the inert gas is selected as the processing gas. 如請求項2之基板處理方法,其中上述處理氣體係含有O(氧)及Cl(氯)中之至少任一者之氣體。 The substrate processing method of claim 2, wherein the processing gas system contains a gas of at least one of O (oxygen) and Cl (chlorine). 如請求項1之基板處理方法,其確保靜電吸附力,該靜電吸附力可確保上述基板之背面冷卻所需之冷媒之壓力。 The substrate processing method of claim 1, which secures an electrostatic adsorption force which ensures the pressure of the refrigerant required for cooling the back surface of the substrate. 一種半導體裝置之製造方法,其包含使用如請求項1至4中任一項之基板處理方法之電漿蝕刻步驟。 A method of fabricating a semiconductor device, comprising a plasma etching step using the substrate processing method according to any one of claims 1 to 4. 一種基板處理裝置,其係於處理室內配置基板,對上部電極與下部電極分別獨立地供給電力,將該處理室內之處理氣體電漿化而進行基板處理者,且於如下狀態下可實行該基板處理:僅對該上部電極供給電力,將與惰性氣體相比較易電漿化之電子釋放率較高之供給至該處理室內之處理氣體電漿化,使該基板帶有電荷而使該基板靜電吸附於該下部電極側。 A substrate processing apparatus for arranging a substrate in a processing chamber, supplying electric power independently to the upper electrode and the lower electrode, and plasma-treating the processing gas in the processing chamber to perform substrate processing, and the substrate can be implemented in the following state Processing: only supplying electric power to the upper electrode, and plasma-treating the processing gas supplied to the processing chamber with a higher electron emission rate than the inert gas, so that the substrate is charged and the substrate is electrostatically charged. Adsorbed to the lower electrode side.
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