WO2014045758A1 - Module semi-conducteur de puissance - Google Patents

Module semi-conducteur de puissance Download PDF

Info

Publication number
WO2014045758A1
WO2014045758A1 PCT/JP2013/071762 JP2013071762W WO2014045758A1 WO 2014045758 A1 WO2014045758 A1 WO 2014045758A1 JP 2013071762 W JP2013071762 W JP 2013071762W WO 2014045758 A1 WO2014045758 A1 WO 2014045758A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
heat dissipation
power semiconductor
semiconductor module
fin
Prior art date
Application number
PCT/JP2013/071762
Other languages
English (en)
Japanese (ja)
Inventor
教文 山田
広道 郷原
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Publication of WO2014045758A1 publication Critical patent/WO2014045758A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

  • the present invention relates to a power semiconductor module used in a semiconductor device that controls a large current and a high voltage.
  • Power conversion devices are used for energy saving in devices that use motors such as hybrid vehicles and electric vehicles.
  • a power semiconductor module including a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) is widely used in this power conversion device. Since a power semiconductor element generates heat when controlling a large current, a power semiconductor module including a plurality of fins for cooling the power semiconductor element is known.
  • IGBT Insulated Gate Bipolar Transistor
  • solder is applied to the surface of the circuit layer of the insulating substrate having an insulating layer made of a thin plate of ceramic material, a circuit layer formed on one surface of the insulating layer, and a metal layer formed on the other surface.
  • a power semiconductor module that includes a bonded semiconductor element, a heat dissipation substrate that contacts the metal layer of the insulating substrate, and fins integrated with the heat dissipation substrate (Patent Document 1).
  • the heat dissipation board is generally manufactured from a material mainly composed of aluminum or copper.
  • a power semiconductor module having such a configuration is configured so that a metal substrate for holding fins or heat radiation grease is not interposed between the heat radiation substrate and the fins, that is, an insulating substrate on which a semiconductor element is mounted is used as a cooling body.
  • a metal substrate for holding fins or heat radiation grease is not interposed between the heat radiation substrate and the fins, that is, an insulating substrate on which a semiconductor element is mounted is used as a cooling body.
  • the insulating layer of the insulating substrate is made of a ceramic material, and this ceramic material generally has a linear expansion coefficient of about 3 to 8 ( ⁇ 10 ⁇ 6 / ° C.).
  • the metal layer is copper, it is about 16.5 ( ⁇ 10 ⁇ 6 / ° C.)
  • the thermal expansion substrate (aluminum or aluminum alloy) has a linear expansion coefficient of 22 to 24 ( ⁇ 10 ⁇ 6 / ° C.). )
  • Due to these linear expansion coefficient differences there is a problem in that thermal stress is generated during the thermal cycle, and breakage occurs at the joint between the metal layer and the heat dissipation substrate.
  • the present invention has an object to provide a power semiconductor module that relieves stress concentration generated in the solder layer and hardly generates cracks.
  • the power semiconductor module includes an insulating substrate, a semiconductor element mounted on the insulating substrate, a heat dissipation substrate bonded to a surface of the insulating substrate opposite to the surface on which the semiconductor element is mounted, and the heat dissipation A plurality of fins provided on the substrate and extending, and a metal plate different from a case housing the fins is joined to a tip of the fin extending from the heat dissipation substrate.
  • the metal plate is bonded to the tip portion of the fin extending from the heat dissipation board, warpage of the heat dissipation board is suppressed, thereby causing a crack in the solder layer between the heat dissipation board and the insulating substrate. Can be prevented.
  • FIG. 1 is a schematic cross-sectional view of an embodiment of a power semiconductor module of the present invention.
  • FIG. 2 is a schematic top view of an embodiment of the power semiconductor module of the present invention.
  • FIG. 3 is a schematic cross-sectional view of a conventional fin base integrated power module.
  • FIG. 4 is a graph showing the results of thermal stress simulation in Example 1.
  • FIG. 5 is a graph showing the results of thermal stress simulation in Example 2.
  • a power semiconductor module 10 according to an embodiment of the present invention shown in a sectional view in FIG. 1 has a plurality of circuit element portions 11A and 11B in the illustrated embodiment.
  • the power semiconductor module 10 includes, for example, a three-phase inverter circuit by these circuit element units 11A and 11B and other circuit element units not shown in the drawing.
  • the circuit element portions 11A and 11B each have an insulating substrate 12.
  • the insulating substrate 12 includes an insulating layer 12a made of a thin plate of an electrically insulating material, a circuit layer 12b formed on one surface of the insulating layer 12a, and a metal formed on the other surface of the insulating layer 12a.
  • Layer 12c for the insulating layer 12a of the insulating substrate 12, for example, a ceramic substrate such as aluminum nitride, aluminum oxide, or silicon nitride can be used. More preferably, silicon nitride can be used.
  • the circuit layer 12b and the metal layer 12c of the insulating substrate 12 can be formed using a conductive metal foil (eg, copper foil, aluminum foil) such as copper or aluminum.
  • a circuit pattern is formed on the circuit layer 12b of the insulating substrate 12, and the semiconductor elements 13 and 14 are bonded to the circuit layer 12b via a bonding layer 15 such as solder.
  • the semiconductor elements 13 and 14 are electrically connected directly by the circuit pattern of the circuit layer 12 b or via the wire 16.
  • the exposed surface of the circuit layer 12b and the metal layer 12c of the insulating substrate 12 and the surface of the wire 16 that electrically connects the semiconductor elements 13 and 14 and the circuit layer 12b are stained by nickel plating or the like.
  • a protective layer may be formed for protection from corrosion, external force, and the like.
  • the semiconductor elements 13 and 14 mounted on such an insulating substrate 12 power semiconductor elements are used in the illustrated embodiment.
  • the semiconductor element 13 can be a free wheeling diode (FWD)
  • the other semiconductor element 14 can be an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor: IGBT). 1 shows the semiconductor elements 13 and 14, the power semiconductor module of the present invention is not limited to the case where there are two semiconductor elements, and may be one or three or more.
  • the power semiconductor module of the present invention is not limited to the case where there are two circuit element units.
  • the number of circuit element units can be appropriately changed according to the circuit, application, or function in which the power semiconductor module 10 is used.
  • the power semiconductor module 10 is provided with a resin case 17 so as to surround the circuit element portions 11A and 11B.
  • the insulating substrate 12 on which the semiconductor elements 13 and 14 are mounted is bonded to the heat dissipation substrate 19 via the bonding layer 18 on the metal layer 12c side. In this way, the insulating substrate 12 and the semiconductor elements 13 and 14 are connected to the heat dissipation substrate 19 so as to be able to conduct heat.
  • the heat dissipation substrate 19 is provided with a plurality of fins 20 extending from the heat dissipation substrate 19 on the side opposite to the side bonded to the insulating substrate 12.
  • the fin 20 is used as a heat radiating plate for heat generated from the semiconductor elements 13, 14, in other words, as a heat sink.
  • the fin 20 is, for example, a blade fin in which a plurality of blade-shaped fins are provided in parallel to each other, a corrugated fin formed by folding a single plate at a certain distance, or a plurality of cylindrical or prismatic pins. Pin fins arranged at intervals can also be used.
  • the fin shape of the fin 20 is not limited to a blade fin, a corrugated fin, or a pin fin, and various shapes can be used. However, since the fin 20 has resistance when a coolant as a cooling medium flows through the gaps between the fins 20, it is desirable that the fin 20 has a shape with a small pressure loss with respect to the coolant.
  • the shape and dimensions of the fins 20 are preferably set as appropriate in consideration of the flow conditions of the coolant, the type and nature of the coolant (particularly viscosity), the intended heat removal amount, and the like.
  • the illustrated plurality of fins 20 are integrated with the heat dissipation substrate 19.
  • the means for integrating can be formed, for example, by casting the fin 20 integrally with the heat dissipation substrate 19 by die casting.
  • the fin 20 can also be integrally formed with the heat radiating substrate 19 by brazing the fin 20 or directly joining the heat radiating substrate 19 by various welding methods.
  • the fin base may be bonded to the heat radiating board 19 so that the heat radiating board 19 and the fin 20 are integrated.
  • the convex portion which is a rough outer shape of the fin by die casting or press forging, at the same time as the heat dissipation substrate 19, the convex portion is processed into a desired fin shape by cutting or wire cutting method. It can also be formed. Further, it is possible to integrally form the heat dissipation substrate 19 and the fins 20 only by the press forging method.
  • the outer shape of the heat sink composed of the fins 20 is a substantially rectangular parallelepiped, preferably a rectangular parallelepiped, and may be chamfered or deformed as long as the effects of the present invention are not impaired.
  • the metal plate 21 is bonded to the tip of the fin 20 extending from the heat dissipation board 19.
  • the plane size of the metal plate 21 is approximately the same as the size of the heat sink composed of the fins 20 and is joined to the tips of the fins. But it does not exclude that the fin 20 which is not joined to the metal plate 21 exists partially.
  • the heat dissipation substrate 19 can be deformed relatively freely while the deformation amount is suppressed, and the deformation state becomes gradual. It is possible to prevent cracks from occurring in the bonding layer 18 that bonds the two. If the metal plate 21 is bonded to the tip of the fin 20, the deformation of the heat radiating substrate 19 can be controlled regardless of the thickness of the metal plate 21. In particular, since the thickness of the metal plate 21 is 1.2 mm or more, heat dissipation The deformation of the substrate 19 can be effectively controlled.
  • the heat dissipation substrate 19, the fins 20, and the metal plate 21 are preferably made of a material having high thermal conductivity, and a metal material is particularly preferable. For example, it can be formed using a metal material such as aluminum, aluminum alloy, copper, or copper alloy. More preferably, aluminum or an aluminum alloy can be used.
  • the heat dissipation substrate 19, the fins 20, and the metal plate 21 may be the same type of metal material or different types of metal materials. The same kind of metal material is easy to manufacture.
  • FIG. 2 is a schematic top view of the heat dissipation board 19.
  • the wire 16 and the resin case 17 are not shown for easy understanding of the present invention.
  • the same members as those in FIG. 1 are denoted by the same reference numerals, and description of the members already described is omitted in the following description.
  • a plurality of circuit element portions 11A to 11F are formed on the upper surface of the heat dissipation substrate 19. Further, as indicated by a broken line in FIG. 2, fins 20 are provided on the lower surface of the heat dissipation substrate 19.
  • the region where the fins 20 are provided on the heat dissipation substrate 19 is preferably a planar region of the insulating substrate 12 parallel to the thickness direction of the heat dissipation substrate 19.
  • the projected area is the same as or wider than this projected area.
  • the region where the fins 20 are provided on the heat dissipation substrate 19 includes the region where the insulating substrate 12 is provided on the heat dissipation substrate 19 and this region. It is an area wider than or equal to.
  • the distance L between the contour line of the projected area of the insulating substrate 12 and the contour line of the area where the fins 20 are provided on the heat dissipation substrate 19 is preferably 2 mm or more. The greater the distance between the two contour lines, the wider the fin region than the projection region, so that the stress strain concentration can be effectively alleviated.
  • the fin 20 is accommodated in the case 22.
  • the case 22 has a bottom wall 22a and a side wall 22b provided on the periphery of the bottom wall 22a, and has an opening at the top.
  • the case 22 has a substantially rectangular parallelepiped shape, but is not limited to a substantially rectangular parallelepiped shape.
  • the upper end of the side wall 22b of the case 22 is joined to the heat dissipation board 19 so that the coolant does not leak.
  • the case 22 is provided with an inlet and an outlet for the coolant not shown in the figure.
  • the coolant is introduced from the inlet, and the coolant passes through the gap between the fins 20 accommodated in the case 22. And discharged from the outlet.
  • the fins 20 are cooled by the coolant by the flow of the coolant in the case 22.
  • the discharged cooling liquid is collected, led to the introduction port by a pump, and circulated.
  • the case 22 is preferably made of a material having a high thermal conductivity, like the fins 20 and the heat radiating substrate 19, and a metal material is particularly preferable.
  • a metal material such as aluminum, aluminum alloy, copper, or copper alloy.
  • the case 22 can also use a material containing a carbon filler as a metal material.
  • a ceramic material, a resin material, or the like can be used depending on the type of the coolant, the temperature of the coolant flowing in the case 22, and the like. It is.
  • the coolant water, long life coolant (LLC), or the like can be used.
  • the tips of the fins 20 are joined to the metal plate 21 as described above.
  • the metal plate 21 is a member different from the bottom wall 22 a of the case 22. That is, the fin 20 is not joined to the bottom wall 22 a of the case 22. As shown in FIG. 1, the metal plate 21 is provided at a position in the case 22 that is separated from the bottom wall 22 a by a predetermined distance.
  • the heat dissipation substrate 19 and the fin 20 can be deformed relatively freely while the deformation amount is suppressed by the metal plate 21 in the environment of the thermal cycle. The deformation state is gradual. Since the heat dissipation substrate 19 hardly bends suddenly, the stress on the bonding layer 18 is also small.
  • the heat dissipation board 19 is strongly restrained by the case 22 as compared to the case where the fins 20 are joined to the metal plate 21. If the fin 20 is joined to the bottom wall 22a, the heat dissipation substrate 19 is integrated with the case 22 including the side wall 22b via the fin 20, and cannot be freely deformed. Under a thermal cycle environment, a sharp bent portion is generated in the heat dissipation substrate 19 due to the stress concentrated in the vicinity of the region where the bonding layer 18 is formed, and the stress on the bonding layer 18 increases. Further, as shown in FIG.
  • the tip of the fin 20 is joined to the metal plate 21, so that the surface area of the heat sink is increased by the surface area of the metal plate 21 compared to the case where the fins 20 are joined to the bottom wall 22 a of the case 22. Therefore, the cooling efficiency is high.
  • FIG. 3 shows a schematic cross-sectional view of a conventional power semiconductor module.
  • the power semiconductor module 110 shown in FIG. 3 is different from the power semiconductor module 10 shown in FIG.
  • Such a conventional power semiconductor module 110 may cause deformation of the heat dissipation substrate 19, specifically, warpage, which may cause cracks in the bonding layer 18 that joins the heat dissipation substrate 19 and the insulating substrate 12. there were. Since the deformation of the heat dissipation substrate 19 can be suppressed and cracking of the bonding layer 18 can be prevented, the effect of the power semiconductor module 10 of the present embodiment shown in FIG. 1 is great.
  • the insulating layer 12a of the insulating substrate 12 was made of silicon nitride having a thickness of 0.32 mm.
  • the circuit layer 12b and the metal layer 12c were made of 0.4 mm thick copper.
  • the heat dissipation substrate 19 was made of an aluminum alloy having a thickness of 5 mm.
  • the inside of the resin case 17 was sealed with a sealing resin such as silicone gel or epoxy resin.
  • the clearance between the metal plate 21 and the bottom wall 22a of the case 22 was 1 mm.
  • the relationship between the plastic strain amplitude generated in the bonding layer 18 (Sn—Sb solder) under the insulating substrate 12 and the thickness of the metal plate 21 was analyzed by thermal stress simulation. .
  • FIG. 4 shows the analysis results when the thickness of the metal plate 21 at the tip of the fin was changed to 0 mm (comparative example), 1.2 mm (example), and 1.8 mm (example).
  • the metal plate 21 By installing the metal plate 21, the plastic strain amplitude can be reduced.
  • the metal plate 21 it is considered that the deformation of the heat dissipation substrate 19 is suppressed.
  • the thickness of the metal plate 21 is almost saturated when the thickness is 1.2 mm or more.
  • the plastic strain amplitude can be reduced by about 30%.
  • FIG. 5 shows the thermal stress simulation results.
  • the plastic strain amplitude decreases. It is expected that stress due to warping of the heat dissipation substrate 19 is concentrated at the boundary of the fin region (broken line in FIG. 2), and the plastic strain amplitude can be reduced by separating such a stress concentration location from the bonding layer 18. Conceivable. In particular, when the fin region is expanded to 2 mm or more, it is saturated, and it can be said that the effect of reducing the plastic strain amplitude can be enjoyed more remarkably at 2 mm or more.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention fournit un module semi-conducteur de puissance dans lequel la déformation d'un substrat de dissipation de chaleur par une contrainte thermique est empêchée, et l'apparition de fissures dans une couche de liaison entre ce substrat de dissipation de chaleur et un substrat isolant est inhibée. Ce module semi-conducteur de puissance (10) est équipé : du substrat isolant (12); d'éléments semi-conducteurs (13, 14) installés sur le substrat isolant (12); du substrat de dissipation de chaleur (19) lié au substrat isolant (12); et d'une pluralité d'ailettes (20) se prolongeant de manière à être agencée sur le substrat de dissipation de chaleur (19). Enfin, le module semi-conducteur de puissance (10) présente une plaque métallique distincte d'une enveloppe (22) dans laquelle les ailettes (20) sont admises, qui est liée à des extrémités avant se prolongeant depuis le substrat de dissipation de chaleur (19) au niveau des ailettes (20).
PCT/JP2013/071762 2012-09-19 2013-08-12 Module semi-conducteur de puissance WO2014045758A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-206268 2012-09-19
JP2012206268 2012-09-19

Publications (1)

Publication Number Publication Date
WO2014045758A1 true WO2014045758A1 (fr) 2014-03-27

Family

ID=50341082

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/071762 WO2014045758A1 (fr) 2012-09-19 2013-08-12 Module semi-conducteur de puissance

Country Status (1)

Country Link
WO (1) WO2014045758A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019111751A1 (fr) * 2017-12-05 2019-06-13 昭和電工株式会社 Dispositif de refroidissement de semi-conducteur
JP2020027901A (ja) * 2018-08-15 2020-02-20 昭和電工株式会社 半導体冷却装置
WO2021124704A1 (fr) * 2019-12-19 2021-06-24 富士電機株式会社 Dispositif semi-conducteur

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251932A (ja) * 2007-03-30 2008-10-16 Nichicon Corp パワー半導体モジュール、および該モジュールを搭載したパワー半導体デバイス
JP2012038010A (ja) * 2010-08-05 2012-02-23 Fujitsu Ltd 受熱器、液冷ユニット及び電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251932A (ja) * 2007-03-30 2008-10-16 Nichicon Corp パワー半導体モジュール、および該モジュールを搭載したパワー半導体デバイス
JP2012038010A (ja) * 2010-08-05 2012-02-23 Fujitsu Ltd 受熱器、液冷ユニット及び電子機器

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019111751A1 (fr) * 2017-12-05 2019-06-13 昭和電工株式会社 Dispositif de refroidissement de semi-conducteur
JP2019102677A (ja) * 2017-12-05 2019-06-24 昭和電工株式会社 半導体冷却装置
CN111164748A (zh) * 2017-12-05 2020-05-15 昭和电工株式会社 半导体冷却装置
JP7033443B2 (ja) 2017-12-05 2022-03-10 昭和電工株式会社 半導体冷却装置
CN111164748B (zh) * 2017-12-05 2024-01-02 株式会社力森诺科 半导体冷却装置
JP2020027901A (ja) * 2018-08-15 2020-02-20 昭和電工株式会社 半導体冷却装置
JP7068097B2 (ja) 2018-08-15 2022-05-16 昭和電工株式会社 半導体冷却装置
WO2021124704A1 (fr) * 2019-12-19 2021-06-24 富士電機株式会社 Dispositif semi-conducteur
JPWO2021124704A1 (fr) * 2019-12-19 2021-06-24
JP7160216B2 (ja) 2019-12-19 2022-10-25 富士電機株式会社 半導体装置

Similar Documents

Publication Publication Date Title
JP6168152B2 (ja) 電力用半導体モジュール
WO2014045766A1 (fr) Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
US9881846B2 (en) Semiconductor device
US10064310B2 (en) Power-module device, power conversion device, and method for manufacturing power-module device
JP5895220B2 (ja) 半導体装置の製造方法
JP2009111154A (ja) 電力半導体モジュール
WO2015141284A1 (fr) Unité de module à semi-conducteurs et module à semi-conducteurs
JP7040032B2 (ja) 半導体装置
US9978664B2 (en) Semiconductor module
US20150130042A1 (en) Semiconductor module with radiation fins
JP2015090965A (ja) 半導体装置
KR101461329B1 (ko) 반도체 유닛
WO2014045758A1 (fr) Module semi-conducteur de puissance
JP6150866B2 (ja) 電力半導体装置
JPWO2015194023A1 (ja) パワーモジュール装置及び電力変換装置
JP5957866B2 (ja) 半導体装置
US9960147B2 (en) Power module
JP6183556B2 (ja) 冷却器一体型半導体モジュール
CN112530915A (zh) 半导体装置
JP5840102B2 (ja) 電力用半導体装置
JP5909924B2 (ja) 半導体モジュール
JP5164793B2 (ja) 電力用半導体装置
JP7367418B2 (ja) 半導体モジュールおよび車両
JP6316221B2 (ja) 半導体装置
JP2015126207A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13838188

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13838188

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP