WO2014027535A1 - Dispositif à semi-conducteurs et dispositif électronique - Google Patents

Dispositif à semi-conducteurs et dispositif électronique Download PDF

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Publication number
WO2014027535A1
WO2014027535A1 PCT/JP2013/068840 JP2013068840W WO2014027535A1 WO 2014027535 A1 WO2014027535 A1 WO 2014027535A1 JP 2013068840 W JP2013068840 W JP 2013068840W WO 2014027535 A1 WO2014027535 A1 WO 2014027535A1
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Prior art keywords
semiconductor chip
connection terminal
semiconductor
terminal region
semiconductor substrate
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PCT/JP2013/068840
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English (en)
Japanese (ja)
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下山　健
吉人 長尾
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ソニー株式会社
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Publication of WO2014027535A1 publication Critical patent/WO2014027535A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a connection electrode penetrating a substrate.
  • the present disclosure also relates to an electronic apparatus including the semiconductor device.
  • TSV through silicon via
  • the TSV is a wiring configured by embedding a conductive material in a very small hole penetrating the semiconductor substrate.
  • wirings are provided in a planar direction to connect each circuit.
  • this three-dimensional chip connection technology a plurality of semiconductor chips are stacked, and the semiconductor chips stacked vertically are electrically connected via a TSV, so that a circuit provided in each semiconductor chip can be obtained. Connected.
  • Patent Document 1 discloses a technique for stacking and mounting a semiconductor chip having a TSV on another semiconductor chip.
  • a new standard mobile DRAM called “JESD229 Wide I / O SDR (Single Date Rate)” of the JEDEC standard has been proposed as a semiconductor memory having TSV and capable of three-dimensional mounting.
  • this Wide I / O SDR each memory cell can be independently accessed as an SDRAM of 200 MHz operation with respect to 128-bit ⁇ 4 memory cells using 1200 signal lines.
  • the present disclosure provides a semiconductor device capable of reducing the mounting area.
  • the present disclosure also provides an electronic device using the semiconductor device.
  • the semiconductor device of the present disclosure includes a semiconductor chip including a semiconductor substrate having a desired circuit and a connection terminal region disposed on the semiconductor substrate.
  • the connection terminal region is arranged such that its long side is inclined with respect to a predetermined side of the semiconductor substrate at an angle greater than 0 degree and less than 90 degrees.
  • the connection terminal region includes a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate.
  • connection terminal region is arranged at the center of the semiconductor substrate so that the long side of the connection terminal region is inclined with respect to a predetermined side of the semiconductor substrate.
  • region of a semiconductor substrate can be used effectively for wiring etc.
  • the electronic device of the present disclosure includes the semiconductor device.
  • the peripheral region of the connection terminal region can be effectively used for wiring or the like in the semiconductor substrate constituting the semiconductor device, so that the drive operation can be speeded up.
  • a semiconductor device with a reduced mounting area can be obtained.
  • an electronic device excellent in driving operation can be obtained. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.
  • FIG. 1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 3 is a schematic configuration diagram of a first semiconductor chip configuring the semiconductor device according to the first embodiment of the present disclosure. It is a schematic block diagram of the 2nd semiconductor chip which comprises the semiconductor device concerning a 1st embodiment of this indication. It is a schematic block diagram of the semiconductor device which concerns on a comparative example. It is a schematic block diagram of the 1st semiconductor chip which concerns on a comparative example. It is a schematic diagram at the time of providing the circuit I and the circuit II in the 1st semiconductor chip of a comparative example.
  • FIG. 7A is a schematic configuration diagram of a first semiconductor chip according to a comparative example, and FIG.
  • FIG. 7B is a schematic configuration diagram of a first semiconductor chip used in the first embodiment of the present disclosure.
  • 8A and 8B are diagrams illustrating another example of the connection terminal region applicable to the first embodiment of the present disclosure.
  • FIG. 6 is a schematic configuration diagram of a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 10A is a schematic configuration diagram of a first semiconductor chip configuring a semiconductor device according to the second embodiment of the present disclosure
  • FIG. 10B illustrates a first configuration of the semiconductor device according to the second embodiment of the present disclosure. It is a schematic block diagram of 2 semiconductor chips. In the semiconductor device in which the first semiconductor chip and the second semiconductor chip are stacked, a schematic configuration when the first semiconductor chip protrudes from the second semiconductor chip is shown.
  • FIG. 6 is a schematic configuration diagram of a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 13A is a schematic configuration diagram of a semiconductor device according to the fourth embodiment of the present disclosure, and FIG. 13B is an enlarged view of a main part. It is a figure showing other examples of the connecting terminal field provided in the 1st semiconductor chip of the semiconductor device concerning a 4th embodiment of this indication.
  • First Embodiment Example of using a semiconductor chip in which a long side of a connection terminal region is arranged to be inclined with respect to a side of a semiconductor substrate (part 1) 1-1. Configuration of first semiconductor chip 1-2. Configuration of second semiconductor chip 1-3. 1. Semiconductor device according to comparative example Second Embodiment: Example of using a semiconductor chip in which the long side of the connection terminal region is inclined with respect to the side of the semiconductor substrate (part 2) 2-1. Configuration of first semiconductor chip 2-2. 2. Configuration of second semiconductor chip 3. Third embodiment: Example using a semiconductor chip with a vertex cut off from a rectangular semiconductor substrate Fourth embodiment: an example using a semiconductor chip in which the end in the long side direction of the connection terminal region is triangular.
  • FIG. 1 is a schematic configuration diagram of a semiconductor device according to the first embodiment of the present disclosure.
  • the semiconductor device 1 of this embodiment includes a first semiconductor chip 2 and a second semiconductor chip 6 stacked on the first semiconductor chip 2.
  • the first semiconductor chip 2 is a semiconductor chip unique to the present disclosure, and the second semiconductor chip 6 is assumed to be an existing semiconductor chip.
  • FIG. 2 is a schematic configuration diagram of the first semiconductor chip 2 constituting the semiconductor device 1 of the present embodiment.
  • the first semiconductor chip 2 of the present embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 2).
  • a wiring layer constituting a desired circuit is provided.
  • the length of the diagonal direction of the semiconductor substrate 3 constituting the first semiconductor chip 2 is set shorter than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6 described later.
  • connection terminal region 4 having a plurality of connection terminals 5 is provided in the central portion of the first semiconductor chip 2.
  • the connection terminal 5 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3.
  • TSV through silicon via
  • connection terminal region 4 The shape of the connection terminal region 4 provided with the plurality of connection terminals 5 on the surface of the semiconductor substrate 3 is a rectangle.
  • the plurality of connection terminals 5 are arrayed in a two-dimensional array, and x (x is an arbitrary number) connection terminals 5 are arrayed in the long side direction of the connection terminal region 4.
  • y (y is an arbitrary number smaller than x) connection terminals 5 are arranged. That is, in the connection terminal region 4, the plurality of connection terminals 5 are arranged in the form of x columns ⁇ y rows.
  • the length of each side of the connection terminal region 4 is sufficiently shorter than the length of each side of the semiconductor substrate 3.
  • one diagonal line of the square semiconductor substrate 3 (the diagonal line in the left-right direction in FIG. 2) is parallel to the long side of the connection terminal region 4 and the semiconductor substrate 3
  • the connection terminal region 4 is arranged so that the center coincides with the center of the connection terminal region 4. That is, in the first semiconductor chip 2, the long side of the connection terminal region 4 is arranged to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 3.
  • FIG. 3 is a schematic configuration diagram of the second semiconductor chip 6 constituting the semiconductor device 1 of the present embodiment.
  • the second semiconductor chip 6 is assumed to be an existing semiconductor chip, and the existing semiconductor chip corresponds to, for example, a semiconductor chip corresponding to JEDEC standard JESD229 Wide I / O SDR.
  • the second semiconductor chip 6 is composed of a semiconductor substrate 7 whose outer shape is a square shape (square shape in FIG. 3), and although not shown, a desired circuit is provided on the surface of the semiconductor substrate 7. A wiring layer to be configured is provided. In the present embodiment, the length of one side of the second semiconductor chip 6 is longer than the diagonal length of the first semiconductor chip 2.
  • connection terminal region 8 having a plurality of connection terminals 9 is provided in the central portion of the second semiconductor chip 6.
  • the connection terminal 9 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 7.
  • TSV through silicon via
  • connection terminal region 8 The shape of the connection terminal region 8 provided with the plurality of connection terminals 9 on the surface of the semiconductor substrate 7 is a rectangle.
  • the plurality of connection terminals 9 are two-dimensionally arrayed, and x (x is an arbitrary number) connection terminals 9 are arrayed in the long side direction of the connection terminal region 8.
  • y (y is an arbitrary number smaller than x) connecting terminals 9 are arranged. That is, in the connection terminal region 8, the plurality of connection terminals 9 are arranged in the form of x columns ⁇ y rows.
  • the length of each side of the connection terminal region 8 is sufficiently shorter than the length of each side of the semiconductor substrate 7.
  • the range of the connection terminal region 8, the number of connection terminals 9 provided in the connection terminal region 8, and the interval (pitch) of the connection terminals 9 are the same as those of the first semiconductor chip 2.
  • connection terminal region 8 is arranged so as to coincide with the center of the region 8.
  • the first semiconductor chip 2 is placed on the second semiconductor chip 6 so that the positions of the connection terminal regions 4 and 8 of the first semiconductor chip 2 and the second semiconductor chip 6 coincide at the connection interface between them. Is laminated. Then, the first semiconductor chip 2 and the second semiconductor chip 6 are electrically connected to each other via the connection terminals 5 and 9 provided in the respective connection terminal regions 4 and 8.
  • connection terminal region 4 of the first semiconductor chip 2 is arranged such that the long side is inclined 45 degrees with respect to the side of the semiconductor substrate 3 constituting the first semiconductor chip 2. Yes. Therefore, when the first semiconductor chip 2 is stacked on the second semiconductor chip 6, the side of the first semiconductor chip 2 is inclined 45 degrees with respect to the side of the second semiconductor chip 6 as shown in FIG. 1. It becomes the state.
  • the length of the first semiconductor chip 2 in the diagonal direction is set to be shorter than the length of one side of the second semiconductor chip 6, so that the first semiconductor chip 2 is the second semiconductor. It does not protrude from the chip 6.
  • connection terminal region 4 is arranged so that the side of the connection terminal region 4 is inclined with respect to the side of the semiconductor substrate 3. This makes it easy to secure an area in which circuits and wirings arranged on 3 can be arranged.
  • the semiconductor substrate 3 can be further reduced in size while securing a circuit and wiring arrangementable area. This point will be described below using a semiconductor chip according to a comparative example.
  • FIG. 4 is a schematic configuration diagram of the semiconductor device 10 according to the comparative example.
  • the semiconductor device 10 according to the comparative example is different from the first embodiment in the configuration of the first semiconductor chip. Therefore, in FIG. 4, the same reference numerals are given to the portions corresponding to those in FIG.
  • the semiconductor device 10 of the comparative example includes a first semiconductor chip 11 and a second semiconductor chip 6 stacked on the first semiconductor chip 11.
  • FIG. 5 is a schematic configuration diagram of the first semiconductor chip 11 according to the comparative example.
  • the first semiconductor chip 11 is composed of a semiconductor substrate 12 whose outer shape is a quadrangle (square shape in FIG. 5), and although not shown, a wiring layer constituting a desired circuit is provided on the surface of the semiconductor substrate 12. ing. Further, the length of one side of the semiconductor substrate 12 constituting the first semiconductor chip 11 is set shorter than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6.
  • connection terminal region 13 having a plurality of connection terminals 14 is provided in the central portion of the first semiconductor chip 11.
  • the connection terminal 14 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 12.
  • a circuit provided in the first semiconductor chip 11 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 6 stacked on the first semiconductor chip 11.
  • connection terminal region 13 The shape of the connection terminal region 13 provided with the plurality of connection terminals 14 on the surface of the semiconductor substrate 12 is a rectangle.
  • the plurality of connection terminals 14 are arrayed in a two-dimensional array, and x (x is an arbitrary number) connection terminals 14 are arrayed in the long side direction of the connection terminal region 13.
  • y (y is an arbitrary number smaller than x) connection terminals 14 are arranged. That is, in the connection terminal region 13, the plurality of connection terminals 14 are arranged in the form of x columns ⁇ y rows. Further, each side of the connection terminal region 13 is sufficiently smaller than each side of the semiconductor substrate 12.
  • a predetermined one side (upper or lower in FIG. 3) of the square semiconductor substrate 12 is parallel to the long side of the connection terminal region 13, and the center of the semiconductor substrate 12 is connected.
  • the connection terminal region 13 is arranged so as to coincide with the center of the terminal region 13.
  • the first semiconductor chip 11 is stacked on the second semiconductor chip 6 so that the positions of the connection terminal regions 13 and 8 coincide with each other at the connection interface between them. Then, the first semiconductor chip 11 and the second semiconductor chip 6 are electrically connected to each other via the connection terminals 14 and 9 provided in the respective connection terminal regions 13 and 8.
  • connection terminal region 13 of the first semiconductor chip 11 is provided such that its long side is parallel to a predetermined side of the first semiconductor chip 11. Therefore, the side of the first semiconductor chip 11 is parallel to the side of the second semiconductor chip 6.
  • one side of the first semiconductor chip 11 is set to be equal to or smaller than the width of the connection terminal region 13 in the long side direction. It is not possible.
  • connection terminals In addition, in a semiconductor chip having a plurality of minute connection terminals, a large number of extremely small holes and electrodes are provided. Therefore, as the semiconductor chip is miniaturized, it is physically disposed around the connection terminals. There is a problem that it becomes impossible.
  • connection terminal region in which a plurality of minute connection terminals are arranged, wiring that straddles the connection terminal region cannot be performed. For this reason, the external shape of the connection terminal region is elongated in one direction. As described above, when the connection terminal region where the connection terminal is provided has an elongated shape, there is a possibility that a required circuit arrangement area must be increased.
  • FIG. 6 shows a schematic diagram when the circuit I and the circuit II are provided in the first semiconductor chip 11 of the comparative example.
  • the circuit I is arranged in a substrate region outside one long side of the connection terminal region 13, and the circuit II is arranged on the other long side of the connection terminal region 13.
  • region is demonstrated. That is, an example in which the circuit I and the circuit II are arranged on the semiconductor substrate 12 with the connection terminal region 13 interposed therebetween will be described.
  • FIGS. 7A and 7B show the first semiconductor chip 11 of the comparative example and the first semiconductor chip 2 of the present embodiment side by side.
  • the width A in the long side direction of the connection terminal region 13 of the first semiconductor chip 11 of the comparative example is equal to the connection terminal region 4 of the first semiconductor chip 2 of the present embodiment.
  • the width B of the wiring region (substrate region) outside the short side of the connection terminal region 13 of the first semiconductor chip 11 of the comparative example is the same as that of the connection terminal region 4 of the first semiconductor chip of the present embodiment. .
  • the area of the first semiconductor chip 11 according to the comparative example is (A + 2B) ⁇ (A + 2B), whereas the area of the first semiconductor chip 2 according to the present embodiment is (A + 2B) ⁇ (A + 2B). ⁇ 2.
  • the chip area can be reduced while securing a wiring region having the same width B as that of the first semiconductor chip 11 of the comparative example.
  • the connection terminal region 4 can be enlarged in the first semiconductor chip 2 of the present embodiment. Therefore, the number of connection terminals 5 can be increased.
  • the outer shape of the first semiconductor chip 2 is square, but it may be rectangular. Even in that case, by arranging the connection terminal region 4 so that the long side of the connection terminal region 4 is parallel to one of the diagonal lines of the rectangular semiconductor substrate, the same effect as the present embodiment can be obtained. .
  • connection terminal region 4 has a rectangular shape, and the connection terminals 5 are arranged in a two-dimensional matrix in the rectangular connection terminal region 4.
  • the present invention is not limited to this.
  • FIG. 8A and FIG. 8B show other examples of connection terminal regions applicable to this embodiment.
  • FIG. 8A is an example in which the shape of the connection terminal region 15 in which the plurality of connection terminals 5 are arranged is a polygonal shape extending in one direction.
  • the connecting terminal 5 is provided in the polygonal connecting terminal area
  • connection terminals 5 can be arranged also on the convex portions of the zigzag area of the connection terminal area 5, so that the number of terminals can be increased. Many can be provided.
  • FIG. 8B is an example in which the connection terminals 5 arranged in the rectangular connection terminal region 16 are arranged in a staggered manner.
  • the distance between the adjacent connection terminals 5 is shown to be larger than the example in which the connection terminals 5 are arranged in a two-dimensional matrix as shown in FIG. Since the connection terminals 5 are arranged in a staggered manner, the distance between the connection terminals 5 can be reduced. Accordingly, in the example shown in FIG. 8B, the number of connection terminals 5 can be increased as long as they are within the same area, compared to an example in which the connection terminals 5 are arranged in a two-dimensional matrix.
  • connection terminal region is not limited to the rectangular shape, and an effect similar to that of the present embodiment can be obtained as long as the shape extends in one direction. Furthermore, various modifications can be made to the arrangement of the connection terminals provided in the connection terminal region.
  • connection terminal region 4 is arranged in the central portion of the first semiconductor chip 2, but the present invention is not limited to this. Even when the connection terminal region is disposed at a position slightly deviated from the central portion of the semiconductor chip, the same effect as in the present embodiment can be obtained.
  • FIG. 9 is a schematic configuration diagram of the semiconductor device of the present embodiment.
  • the semiconductor device 20 of this embodiment is different from that of the first embodiment in the stacking relationship between the first semiconductor chip 21 and the second semiconductor chip 25 and the configuration of the connection terminal regions 23 and 27. Therefore, in FIG. 9, the same reference numerals are given to the portions corresponding to FIG.
  • the semiconductor device 20 of the present embodiment includes a first semiconductor chip 21 and a second semiconductor chip 25 stacked on the first semiconductor chip 21.
  • FIG. 10A is a schematic configuration diagram of the first semiconductor chip 21 configuring the semiconductor device 20 according to the present embodiment
  • FIG. 10B is a schematic configuration of the second semiconductor chip 25 configuring the semiconductor device 20 according to the present embodiment.
  • the first semiconductor chip 21 constituting the semiconductor device 20 of this embodiment will be described.
  • the first semiconductor chip 21 of the present embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 10A).
  • a wiring layer constituting a desired circuit is provided.
  • the length of the side of the semiconductor substrate 3 constituting the first semiconductor chip 21 is set smaller than the length of the side of the semiconductor substrate 7 constituting the second semiconductor chip 25 described later.
  • connection terminal region 23 having a plurality of connection terminals 24 is provided in the central portion of the first semiconductor chip 21.
  • the connection terminal 24 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3.
  • a circuit provided in the first semiconductor chip 21 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 25 stacked on the first semiconductor chip 21.
  • connection terminal area 23 provided with a plurality of connection terminals 24 is composed of a first connection terminal area 23a and a second connection terminal area 23b.
  • region 23b is a rectangle.
  • the first connection terminal region 23a and the second connection terminal region 23b are arranged adjacent to each other in the long side direction.
  • connection terminal region 23a and the second connection terminal region 23b a plurality of connection terminals 24 are arrayed in a two-dimensional array. Then, x (x is an arbitrary number) connection terminals 24 are arranged in the long side direction of each of the first connection terminal region 23a and the second connection terminal region 23b, and y ( (wherein y is an arbitrary number smaller than x) of connecting terminals 24 are arranged. That is, in the first connection terminal region 23a and the second connection terminal region 23b, the plurality of connection terminals 24 are each arranged in the form of x columns ⁇ y rows. Each side of the connection terminal region 23 is sufficiently smaller than the length of the diagonal line of the semiconductor substrate 3.
  • the connection terminal region 23 has one diagonal line of the square semiconductor substrate 3 (the diagonal line between the upper left corner and the lower right corner in FIG. 10A) as the length of the connection terminal region 23. It is arranged so as to be parallel to the side. Further, the connection terminal region 23 is arranged so that the center of the semiconductor substrate 3 coincides with the center of the connection terminal region 23. In other words, in the first semiconductor chip 21 in the present embodiment, the long side of the connection terminal region 23 is disposed so as to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 3.
  • the second semiconductor chip 25 constituting the semiconductor device 20 of this embodiment will be described.
  • the second semiconductor chip 25 is configured by a semiconductor substrate 7 having an outer shape of a quadrangle (a square shape in FIG. 10B).
  • a wiring layer to be configured is provided.
  • the length of one side of the second semiconductor chip 25 is longer than that of the first semiconductor chip 21.
  • connection terminal region 27 having a plurality of connection terminals 28 is provided in the central portion of the second semiconductor chip 25.
  • the connection terminal 28 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 7.
  • a circuit provided in the second semiconductor chip 25 is electrically connected to a circuit of another semiconductor chip such as the first semiconductor chip 21 stacked on the second semiconductor chip 25.
  • connection terminal area 27 in which the plurality of connection terminals 28 are provided includes a first connection terminal area 27a and a second connection terminal area 27b.
  • region 27b is a rectangle.
  • the first connection terminal region 27a and the second connection terminal region 27b are arranged adjacent to each other in the long side direction.
  • connection terminal area 27a and the second connection terminal area 27b a plurality of connection terminals 28 are arrayed in a two-dimensional array. Then, x (x is an arbitrary number) connection terminals 28 are arranged in the long side direction of each of the first connection terminal region 27a and the second connection terminal region 27b, and y ( (wherein y is an arbitrary number smaller than x)) connecting terminals 28 are arranged. That is, in the first connection terminal region 27a and the second connection terminal region 27b, the plurality of connection terminals 28 are each arranged in the form of x columns ⁇ y rows. Further, each side of the connection terminal region 27 is sufficiently smaller than the diagonal length of the semiconductor substrate 7.
  • connection terminal region 27 has one diagonal line of the square semiconductor substrate 7 (the diagonal line between the upper left corner and the lower right corner in FIG. 10B) as the length of the connection terminal region 27. It is arranged so as to be parallel to the side. Further, the connection terminal region 27 is arranged so that the center of the semiconductor substrate 7 coincides with the center of the connection terminal region 27. That is, in the second semiconductor chip 25 in the present embodiment, the long side of the connection terminal region 27 is arranged to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 7.
  • the first semiconductor chip 21 and the second semiconductor chip 25 are stacked on each other so that the connection terminal regions 23 and 27 coincide with each other at the interface between them. Then, the first semiconductor chip 21 is electrically connected to the second semiconductor chip 25 through the connection terminals 24 and 28 provided in the connection terminal regions 23 and 27, respectively.
  • the outer shapes of the connection terminal regions 23 and 27 are oblique to the semiconductor substrates 3 and 7 (diagonal lines). (On top).
  • the area of the substrate region located outside the short sides of the connection terminal regions 23 and 27 is secured while reducing the area of the semiconductor substrates 3 and 7, respectively. can do.
  • the same effect as the first embodiment can be obtained.
  • FIG. 11 shows a schematic configuration when a corner portion of the first semiconductor chip 31a protrudes from the second semiconductor chip 6 in the semiconductor device 30a in which the first semiconductor chip 31a is stacked with the second semiconductor chip 6.
  • parts corresponding to those in FIG. 11 are identical to those in FIG.
  • the first semiconductor chip 31 a is configured by a semiconductor substrate 32 a having a quadrangular outer shape (a square shape in FIG. 11), and although not illustrated, a desired circuit is provided on the surface of the semiconductor substrate 32 a.
  • a wiring layer to be configured is provided. Further, the length of the semiconductor substrate 32 a constituting the first semiconductor chip 31 a in the diagonal direction is set to be longer than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6.
  • the width in the diagonal direction of the semiconductor substrate 32a of the first semiconductor chip 31a is longer than the length of one side of the semiconductor substrate 7 of the second semiconductor chip 6. For this reason, when the first semiconductor chip 31a and the second semiconductor chip 6 are stacked such that the connection terminal regions 33 and 8 coincide with each other at the interface between the first semiconductor chip 31a and the second semiconductor chip 6, the corners of the apex region of the first semiconductor chip 31a are Protrudes from the second semiconductor chip 6.
  • FIG. 12 is a schematic configuration diagram of a semiconductor device according to the third embodiment of the present disclosure.
  • the configuration of the first semiconductor chip 31 is partially different from the first semiconductor chip 31a of the semiconductor device 30a shown in FIG. Therefore, in FIG. 12, the same reference numerals are given to the portions corresponding to those in FIG.
  • the semiconductor device 30 of this embodiment includes a first semiconductor chip 31 and a second semiconductor chip 6 stacked on the first semiconductor chip 31.
  • the first semiconductor chip 31 is composed of a semiconductor substrate 32 having an octagonal outer shape. Although not shown, a wiring layer constituting a desired circuit is provided on the surface of the semiconductor substrate 32.
  • the semiconductor substrate 32 constituting the first semiconductor chip 31 is the semiconductor substrate 7 constituting the second semiconductor chip 6 when the first semiconductor chip 31 is stacked on the second semiconductor chip 6. The size is set so as not to protrude.
  • the first semiconductor chip 31 is a semiconductor chip having a shape obtained by cutting off the apex portion (corner portion) protruding from the second semiconductor chip 6 of the first semiconductor chip 31a shown in FIG.
  • the first semiconductor chip 31 is configured by the semiconductor substrate 32 from which excess vertex portions are cut off, whereby the chip area can be further reduced.
  • the same effects as those of the first embodiment can be obtained in this embodiment.
  • the outer shape of the first semiconductor chip 31 is an octagonal shape, but the shape of the first semiconductor chip 31 may be an octagonal shape as long as it does not protrude from the second semiconductor chip 6. There is no need.
  • the second semiconductor chip 6 has a rectangular shape and only a pair of opposing apexes of the first semiconductor chip 31 a protrude from the second semiconductor chip 6, the first semiconductor chip 6 By adopting a square shape, the same effect as in the present embodiment can be obtained.
  • FIG. 13A is a schematic configuration diagram of the semiconductor device 40 of the present embodiment
  • FIG. 13B is an enlarged view of a main part.
  • the configuration of the connection terminal region 41 in the first semiconductor chip 43 is different from that of the first semiconductor chip 2 in the first embodiment. Therefore, in FIG. 13A, the same reference numerals are given to the portions corresponding to FIG.
  • the first semiconductor chip 43 of this embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 13A).
  • a connection terminal area 41 having a connection terminal 42 is provided.
  • the connection terminal 42 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3.
  • TSV through silicon via
  • the shape of the connection terminal region 41 is a hexagon, and has a shape extending along a diagonal line between a pair of opposing vertices.
  • the angle of the vertex is formed at about 90 degrees. That is, the connection terminal area 41 corresponds to the apex among the connection terminals 5 located near each short side among the connection terminals 5 arranged in the connection terminal area 4 having the rectangular outer shape shown in FIG. The shape is such that only the connection terminal 5 remains.
  • connection terminal region 41 has one diagonal line of the square semiconductor substrate 3 (the diagonal line in the horizontal direction in FIG. 13) parallel to the long side of the connection terminal region 41. It is arranged to be. Further, the connection terminal region 41 is arranged so that the center of the semiconductor substrate 3 coincides with the center of the connection terminal region 41.
  • the shape of the end portion including the apex of the connection terminal region 41 is a triangular shape having an apex angle of approximately 90 degrees, so that the semiconductor substrate extends from the end portion of the connection terminal region 41 as shown in FIG. 13A.
  • the distances w1 and w2 to the corresponding side of 3 can be made substantially constant. As a result, it is possible to efficiently arrange the wiring and the circuit provided so as to bypass the connection terminal 42.
  • the same effect as the first embodiment can be obtained.
  • FIG. 14 shows another example of the connection terminal region 41 provided in the first semiconductor chip 43.
  • the connection terminal 42a located near the corner may not be used for the connection between the chips.
  • the end shape including the apex of the connection terminal region 41 actually used for connection can be a triangular shape.
  • the connection terminal 42a not used for connection can be configured by not burying a conductive material in the through hole. Even when the configuration shown in FIG. 14 is adopted, the same effect as that of the present embodiment can be obtained.
  • connection terminal region 41 has a hexagonal shape extending along a diagonal line between a pair of opposing vertices.
  • examples in which the effect of the present embodiment can be exhibited are limited thereto. It is not a thing.
  • connection terminal region has a polygonal shape extending in one direction and the width in the short axis direction of the connection terminal region is formed so as to decrease toward the end side in the long axis direction of the connection terminal region. The effect similar to this embodiment can be acquired.
  • the connection terminal region is provided in the semiconductor substrate so that the long side thereof is parallel to one diagonal line of the semiconductor substrate.
  • the present invention is not limited to this.
  • the connection terminal region is provided on the semiconductor substrate so that the long side of the connection terminal region is inclined at an angle larger than 0 degree and smaller than 90 degrees with respect to a predetermined side of the semiconductor substrate. The effect of can be obtained.
  • the connection terminal region is positioned outside the end side of the connection terminal region. It is possible to secure a wider area of the substrate region.
  • the semiconductor device has a structure in which the first semiconductor chip and the second semiconductor chip are stacked.
  • the semiconductor device also has a structure in which two or more semiconductor chips are stacked.
  • the technology of the present disclosure can be applied.
  • at least one of the stacked semiconductor chips has the configuration of the first semiconductor chip in the first to fourth embodiments, so that the same effect as in the first to fourth embodiments can be obtained. Can do.
  • the semiconductor device described above can be applied to various electronic devices such as an imaging device, a computer, and an image display device.
  • the driving speed can be reduced. Improvement is achieved.
  • this indication can also take the following structures.
  • a semiconductor substrate having a desired circuit and a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate, and a connection terminal region disposed in the semiconductor substrate, the connection terminals
  • the semiconductor is provided with a semiconductor chip which is formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees apparatus.
  • the semiconductor substrate is square or rectangular, The semiconductor device according to (1) or (2), wherein the connection terminal region is arranged on the semiconductor substrate such that a long side of the connection terminal region is parallel to one diagonal line of the semiconductor substrate.
  • the semiconductor chip and the other semiconductor chip are stacked such that the outer side of the semiconductor chip is tilted with respect to the outer side of the other semiconductor chip (1) to (4) A semiconductor device according to 1.
  • connection terminal region has a polygonal shape extending in one direction, and is formed so that the width in the minor axis direction of the connection terminal region decreases toward the end side in the major axis direction of the connection terminal region.
  • the semiconductor chip and the other semiconductor chip are stacked so that the outer side of the semiconductor chip is parallel to the outer side of the other semiconductor chip.
  • the semiconductor includes a semiconductor chip formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees Electronic equipment equipped with the device.
  • SYMBOLS 1,10,20,30,40 ... Semiconductor device, 2, 11, 21, 31, 43 ... 1st semiconductor chip, 3, 7, 12, 32 ... Semiconductor substrate, 4, 8, 13 , 23, 27, 33, 41 ... connection terminal region, 5, 9, 14, 24, 28, 34, 42 ... connection terminals, 6, 25 ... second semiconductor chip.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention porte sur un dispositif à semi-conducteurs qui comporte une puce à semi-conducteurs qui comprend un substrat de semi-conducteur ayant un circuit souhaité et une région de borne de connexion qui est disposée dans la partie centrale du substrat de semi-conducteur. La région de borne de connexion est disposée de telle sorte que le côté long de celle-ci est incliné vers un côté prédéterminé du substrat de semi-conducteur à un angle supérieur à 0° mais inférieur à 90°. De plus, la région de borne de connexion a une pluralité de bornes de connexion qui sont formées par remplissage de trous traversants, qui ont été formés dans le substrat de semi-conducteur, avec un matériau conducteur. En conséquence, le dispositif à semi-conducteurs peut être réduit dans la zone de montage.
PCT/JP2013/068840 2012-08-13 2013-07-10 Dispositif à semi-conducteurs et dispositif électronique WO2014027535A1 (fr)

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JP2012179184A JP2015181139A (ja) 2012-08-13 2012-08-13 半導体装置及び電子機器
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653272A (ja) * 1992-07-28 1994-02-25 Nippon Steel Corp 半導体チップ及びｔａｂ方式半導体装置
JP2010245267A (ja) * 2009-04-06 2010-10-28 Mitsubishi Electric Corp 半導体装置
JP2011166026A (ja) * 2010-02-12 2011-08-25 Elpida Memory Inc 半導体装置
JP2012119368A (ja) * 2010-11-29 2012-06-21 Elpida Memory Inc 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653272A (ja) * 1992-07-28 1994-02-25 Nippon Steel Corp 半導体チップ及びｔａｂ方式半導体装置
JP2010245267A (ja) * 2009-04-06 2010-10-28 Mitsubishi Electric Corp 半導体装置
JP2011166026A (ja) * 2010-02-12 2011-08-25 Elpida Memory Inc 半導体装置
JP2012119368A (ja) * 2010-11-29 2012-06-21 Elpida Memory Inc 半導体装置の製造方法

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