WO2014027535A1 - Semiconductor device and electronic device - Google Patents

Semiconductor device and electronic device Download PDF

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Publication number
WO2014027535A1
WO2014027535A1 PCT/JP2013/068840 JP2013068840W WO2014027535A1 WO 2014027535 A1 WO2014027535 A1 WO 2014027535A1 JP 2013068840 W JP2013068840 W JP 2013068840W WO 2014027535 A1 WO2014027535 A1 WO 2014027535A1
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WIPO (PCT)
Prior art keywords
semiconductor chip
connection terminal
semiconductor
terminal region
semiconductor substrate
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Application number
PCT/JP2013/068840
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French (fr)
Japanese (ja)
Inventor
下山　健
吉人 長尾
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ソニー株式会社
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Publication of WO2014027535A1 publication Critical patent/WO2014027535A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a connection electrode penetrating a substrate.
  • the present disclosure also relates to an electronic apparatus including the semiconductor device.
  • TSV through silicon via
  • the TSV is a wiring configured by embedding a conductive material in a very small hole penetrating the semiconductor substrate.
  • wirings are provided in a planar direction to connect each circuit.
  • this three-dimensional chip connection technology a plurality of semiconductor chips are stacked, and the semiconductor chips stacked vertically are electrically connected via a TSV, so that a circuit provided in each semiconductor chip can be obtained. Connected.
  • Patent Document 1 discloses a technique for stacking and mounting a semiconductor chip having a TSV on another semiconductor chip.
  • a new standard mobile DRAM called “JESD229 Wide I / O SDR (Single Date Rate)” of the JEDEC standard has been proposed as a semiconductor memory having TSV and capable of three-dimensional mounting.
  • this Wide I / O SDR each memory cell can be independently accessed as an SDRAM of 200 MHz operation with respect to 128-bit ⁇ 4 memory cells using 1200 signal lines.
  • the present disclosure provides a semiconductor device capable of reducing the mounting area.
  • the present disclosure also provides an electronic device using the semiconductor device.
  • the semiconductor device of the present disclosure includes a semiconductor chip including a semiconductor substrate having a desired circuit and a connection terminal region disposed on the semiconductor substrate.
  • the connection terminal region is arranged such that its long side is inclined with respect to a predetermined side of the semiconductor substrate at an angle greater than 0 degree and less than 90 degrees.
  • the connection terminal region includes a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate.
  • connection terminal region is arranged at the center of the semiconductor substrate so that the long side of the connection terminal region is inclined with respect to a predetermined side of the semiconductor substrate.
  • region of a semiconductor substrate can be used effectively for wiring etc.
  • the electronic device of the present disclosure includes the semiconductor device.
  • the peripheral region of the connection terminal region can be effectively used for wiring or the like in the semiconductor substrate constituting the semiconductor device, so that the drive operation can be speeded up.
  • a semiconductor device with a reduced mounting area can be obtained.
  • an electronic device excellent in driving operation can be obtained. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.
  • FIG. 1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 3 is a schematic configuration diagram of a first semiconductor chip configuring the semiconductor device according to the first embodiment of the present disclosure. It is a schematic block diagram of the 2nd semiconductor chip which comprises the semiconductor device concerning a 1st embodiment of this indication. It is a schematic block diagram of the semiconductor device which concerns on a comparative example. It is a schematic block diagram of the 1st semiconductor chip which concerns on a comparative example. It is a schematic diagram at the time of providing the circuit I and the circuit II in the 1st semiconductor chip of a comparative example.
  • FIG. 7A is a schematic configuration diagram of a first semiconductor chip according to a comparative example, and FIG.
  • FIG. 7B is a schematic configuration diagram of a first semiconductor chip used in the first embodiment of the present disclosure.
  • 8A and 8B are diagrams illustrating another example of the connection terminal region applicable to the first embodiment of the present disclosure.
  • FIG. 6 is a schematic configuration diagram of a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 10A is a schematic configuration diagram of a first semiconductor chip configuring a semiconductor device according to the second embodiment of the present disclosure
  • FIG. 10B illustrates a first configuration of the semiconductor device according to the second embodiment of the present disclosure. It is a schematic block diagram of 2 semiconductor chips. In the semiconductor device in which the first semiconductor chip and the second semiconductor chip are stacked, a schematic configuration when the first semiconductor chip protrudes from the second semiconductor chip is shown.
  • FIG. 6 is a schematic configuration diagram of a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 13A is a schematic configuration diagram of a semiconductor device according to the fourth embodiment of the present disclosure, and FIG. 13B is an enlarged view of a main part. It is a figure showing other examples of the connecting terminal field provided in the 1st semiconductor chip of the semiconductor device concerning a 4th embodiment of this indication.
  • First Embodiment Example of using a semiconductor chip in which a long side of a connection terminal region is arranged to be inclined with respect to a side of a semiconductor substrate (part 1) 1-1. Configuration of first semiconductor chip 1-2. Configuration of second semiconductor chip 1-3. 1. Semiconductor device according to comparative example Second Embodiment: Example of using a semiconductor chip in which the long side of the connection terminal region is inclined with respect to the side of the semiconductor substrate (part 2) 2-1. Configuration of first semiconductor chip 2-2. 2. Configuration of second semiconductor chip 3. Third embodiment: Example using a semiconductor chip with a vertex cut off from a rectangular semiconductor substrate Fourth embodiment: an example using a semiconductor chip in which the end in the long side direction of the connection terminal region is triangular.
  • FIG. 1 is a schematic configuration diagram of a semiconductor device according to the first embodiment of the present disclosure.
  • the semiconductor device 1 of this embodiment includes a first semiconductor chip 2 and a second semiconductor chip 6 stacked on the first semiconductor chip 2.
  • the first semiconductor chip 2 is a semiconductor chip unique to the present disclosure, and the second semiconductor chip 6 is assumed to be an existing semiconductor chip.
  • FIG. 2 is a schematic configuration diagram of the first semiconductor chip 2 constituting the semiconductor device 1 of the present embodiment.
  • the first semiconductor chip 2 of the present embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 2).
  • a wiring layer constituting a desired circuit is provided.
  • the length of the diagonal direction of the semiconductor substrate 3 constituting the first semiconductor chip 2 is set shorter than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6 described later.
  • connection terminal region 4 having a plurality of connection terminals 5 is provided in the central portion of the first semiconductor chip 2.
  • the connection terminal 5 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3.
  • TSV through silicon via
  • connection terminal region 4 The shape of the connection terminal region 4 provided with the plurality of connection terminals 5 on the surface of the semiconductor substrate 3 is a rectangle.
  • the plurality of connection terminals 5 are arrayed in a two-dimensional array, and x (x is an arbitrary number) connection terminals 5 are arrayed in the long side direction of the connection terminal region 4.
  • y (y is an arbitrary number smaller than x) connection terminals 5 are arranged. That is, in the connection terminal region 4, the plurality of connection terminals 5 are arranged in the form of x columns ⁇ y rows.
  • the length of each side of the connection terminal region 4 is sufficiently shorter than the length of each side of the semiconductor substrate 3.
  • one diagonal line of the square semiconductor substrate 3 (the diagonal line in the left-right direction in FIG. 2) is parallel to the long side of the connection terminal region 4 and the semiconductor substrate 3
  • the connection terminal region 4 is arranged so that the center coincides with the center of the connection terminal region 4. That is, in the first semiconductor chip 2, the long side of the connection terminal region 4 is arranged to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 3.
  • FIG. 3 is a schematic configuration diagram of the second semiconductor chip 6 constituting the semiconductor device 1 of the present embodiment.
  • the second semiconductor chip 6 is assumed to be an existing semiconductor chip, and the existing semiconductor chip corresponds to, for example, a semiconductor chip corresponding to JEDEC standard JESD229 Wide I / O SDR.
  • the second semiconductor chip 6 is composed of a semiconductor substrate 7 whose outer shape is a square shape (square shape in FIG. 3), and although not shown, a desired circuit is provided on the surface of the semiconductor substrate 7. A wiring layer to be configured is provided. In the present embodiment, the length of one side of the second semiconductor chip 6 is longer than the diagonal length of the first semiconductor chip 2.
  • connection terminal region 8 having a plurality of connection terminals 9 is provided in the central portion of the second semiconductor chip 6.
  • the connection terminal 9 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 7.
  • TSV through silicon via
  • connection terminal region 8 The shape of the connection terminal region 8 provided with the plurality of connection terminals 9 on the surface of the semiconductor substrate 7 is a rectangle.
  • the plurality of connection terminals 9 are two-dimensionally arrayed, and x (x is an arbitrary number) connection terminals 9 are arrayed in the long side direction of the connection terminal region 8.
  • y (y is an arbitrary number smaller than x) connecting terminals 9 are arranged. That is, in the connection terminal region 8, the plurality of connection terminals 9 are arranged in the form of x columns ⁇ y rows.
  • the length of each side of the connection terminal region 8 is sufficiently shorter than the length of each side of the semiconductor substrate 7.
  • the range of the connection terminal region 8, the number of connection terminals 9 provided in the connection terminal region 8, and the interval (pitch) of the connection terminals 9 are the same as those of the first semiconductor chip 2.
  • connection terminal region 8 is arranged so as to coincide with the center of the region 8.
  • the first semiconductor chip 2 is placed on the second semiconductor chip 6 so that the positions of the connection terminal regions 4 and 8 of the first semiconductor chip 2 and the second semiconductor chip 6 coincide at the connection interface between them. Is laminated. Then, the first semiconductor chip 2 and the second semiconductor chip 6 are electrically connected to each other via the connection terminals 5 and 9 provided in the respective connection terminal regions 4 and 8.
  • connection terminal region 4 of the first semiconductor chip 2 is arranged such that the long side is inclined 45 degrees with respect to the side of the semiconductor substrate 3 constituting the first semiconductor chip 2. Yes. Therefore, when the first semiconductor chip 2 is stacked on the second semiconductor chip 6, the side of the first semiconductor chip 2 is inclined 45 degrees with respect to the side of the second semiconductor chip 6 as shown in FIG. 1. It becomes the state.
  • the length of the first semiconductor chip 2 in the diagonal direction is set to be shorter than the length of one side of the second semiconductor chip 6, so that the first semiconductor chip 2 is the second semiconductor. It does not protrude from the chip 6.
  • connection terminal region 4 is arranged so that the side of the connection terminal region 4 is inclined with respect to the side of the semiconductor substrate 3. This makes it easy to secure an area in which circuits and wirings arranged on 3 can be arranged.
  • the semiconductor substrate 3 can be further reduced in size while securing a circuit and wiring arrangementable area. This point will be described below using a semiconductor chip according to a comparative example.
  • FIG. 4 is a schematic configuration diagram of the semiconductor device 10 according to the comparative example.
  • the semiconductor device 10 according to the comparative example is different from the first embodiment in the configuration of the first semiconductor chip. Therefore, in FIG. 4, the same reference numerals are given to the portions corresponding to those in FIG.
  • the semiconductor device 10 of the comparative example includes a first semiconductor chip 11 and a second semiconductor chip 6 stacked on the first semiconductor chip 11.
  • FIG. 5 is a schematic configuration diagram of the first semiconductor chip 11 according to the comparative example.
  • the first semiconductor chip 11 is composed of a semiconductor substrate 12 whose outer shape is a quadrangle (square shape in FIG. 5), and although not shown, a wiring layer constituting a desired circuit is provided on the surface of the semiconductor substrate 12. ing. Further, the length of one side of the semiconductor substrate 12 constituting the first semiconductor chip 11 is set shorter than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6.
  • connection terminal region 13 having a plurality of connection terminals 14 is provided in the central portion of the first semiconductor chip 11.
  • the connection terminal 14 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 12.
  • a circuit provided in the first semiconductor chip 11 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 6 stacked on the first semiconductor chip 11.
  • connection terminal region 13 The shape of the connection terminal region 13 provided with the plurality of connection terminals 14 on the surface of the semiconductor substrate 12 is a rectangle.
  • the plurality of connection terminals 14 are arrayed in a two-dimensional array, and x (x is an arbitrary number) connection terminals 14 are arrayed in the long side direction of the connection terminal region 13.
  • y (y is an arbitrary number smaller than x) connection terminals 14 are arranged. That is, in the connection terminal region 13, the plurality of connection terminals 14 are arranged in the form of x columns ⁇ y rows. Further, each side of the connection terminal region 13 is sufficiently smaller than each side of the semiconductor substrate 12.
  • a predetermined one side (upper or lower in FIG. 3) of the square semiconductor substrate 12 is parallel to the long side of the connection terminal region 13, and the center of the semiconductor substrate 12 is connected.
  • the connection terminal region 13 is arranged so as to coincide with the center of the terminal region 13.
  • the first semiconductor chip 11 is stacked on the second semiconductor chip 6 so that the positions of the connection terminal regions 13 and 8 coincide with each other at the connection interface between them. Then, the first semiconductor chip 11 and the second semiconductor chip 6 are electrically connected to each other via the connection terminals 14 and 9 provided in the respective connection terminal regions 13 and 8.
  • connection terminal region 13 of the first semiconductor chip 11 is provided such that its long side is parallel to a predetermined side of the first semiconductor chip 11. Therefore, the side of the first semiconductor chip 11 is parallel to the side of the second semiconductor chip 6.
  • one side of the first semiconductor chip 11 is set to be equal to or smaller than the width of the connection terminal region 13 in the long side direction. It is not possible.
  • connection terminals In addition, in a semiconductor chip having a plurality of minute connection terminals, a large number of extremely small holes and electrodes are provided. Therefore, as the semiconductor chip is miniaturized, it is physically disposed around the connection terminals. There is a problem that it becomes impossible.
  • connection terminal region in which a plurality of minute connection terminals are arranged, wiring that straddles the connection terminal region cannot be performed. For this reason, the external shape of the connection terminal region is elongated in one direction. As described above, when the connection terminal region where the connection terminal is provided has an elongated shape, there is a possibility that a required circuit arrangement area must be increased.
  • FIG. 6 shows a schematic diagram when the circuit I and the circuit II are provided in the first semiconductor chip 11 of the comparative example.
  • the circuit I is arranged in a substrate region outside one long side of the connection terminal region 13, and the circuit II is arranged on the other long side of the connection terminal region 13.
  • region is demonstrated. That is, an example in which the circuit I and the circuit II are arranged on the semiconductor substrate 12 with the connection terminal region 13 interposed therebetween will be described.
  • FIGS. 7A and 7B show the first semiconductor chip 11 of the comparative example and the first semiconductor chip 2 of the present embodiment side by side.
  • the width A in the long side direction of the connection terminal region 13 of the first semiconductor chip 11 of the comparative example is equal to the connection terminal region 4 of the first semiconductor chip 2 of the present embodiment.
  • the width B of the wiring region (substrate region) outside the short side of the connection terminal region 13 of the first semiconductor chip 11 of the comparative example is the same as that of the connection terminal region 4 of the first semiconductor chip of the present embodiment. .
  • the area of the first semiconductor chip 11 according to the comparative example is (A + 2B) ⁇ (A + 2B), whereas the area of the first semiconductor chip 2 according to the present embodiment is (A + 2B) ⁇ (A + 2B). ⁇ 2.
  • the chip area can be reduced while securing a wiring region having the same width B as that of the first semiconductor chip 11 of the comparative example.
  • the connection terminal region 4 can be enlarged in the first semiconductor chip 2 of the present embodiment. Therefore, the number of connection terminals 5 can be increased.
  • the outer shape of the first semiconductor chip 2 is square, but it may be rectangular. Even in that case, by arranging the connection terminal region 4 so that the long side of the connection terminal region 4 is parallel to one of the diagonal lines of the rectangular semiconductor substrate, the same effect as the present embodiment can be obtained. .
  • connection terminal region 4 has a rectangular shape, and the connection terminals 5 are arranged in a two-dimensional matrix in the rectangular connection terminal region 4.
  • the present invention is not limited to this.
  • FIG. 8A and FIG. 8B show other examples of connection terminal regions applicable to this embodiment.
  • FIG. 8A is an example in which the shape of the connection terminal region 15 in which the plurality of connection terminals 5 are arranged is a polygonal shape extending in one direction.
  • the connecting terminal 5 is provided in the polygonal connecting terminal area
  • connection terminals 5 can be arranged also on the convex portions of the zigzag area of the connection terminal area 5, so that the number of terminals can be increased. Many can be provided.
  • FIG. 8B is an example in which the connection terminals 5 arranged in the rectangular connection terminal region 16 are arranged in a staggered manner.
  • the distance between the adjacent connection terminals 5 is shown to be larger than the example in which the connection terminals 5 are arranged in a two-dimensional matrix as shown in FIG. Since the connection terminals 5 are arranged in a staggered manner, the distance between the connection terminals 5 can be reduced. Accordingly, in the example shown in FIG. 8B, the number of connection terminals 5 can be increased as long as they are within the same area, compared to an example in which the connection terminals 5 are arranged in a two-dimensional matrix.
  • connection terminal region is not limited to the rectangular shape, and an effect similar to that of the present embodiment can be obtained as long as the shape extends in one direction. Furthermore, various modifications can be made to the arrangement of the connection terminals provided in the connection terminal region.
  • connection terminal region 4 is arranged in the central portion of the first semiconductor chip 2, but the present invention is not limited to this. Even when the connection terminal region is disposed at a position slightly deviated from the central portion of the semiconductor chip, the same effect as in the present embodiment can be obtained.
  • FIG. 9 is a schematic configuration diagram of the semiconductor device of the present embodiment.
  • the semiconductor device 20 of this embodiment is different from that of the first embodiment in the stacking relationship between the first semiconductor chip 21 and the second semiconductor chip 25 and the configuration of the connection terminal regions 23 and 27. Therefore, in FIG. 9, the same reference numerals are given to the portions corresponding to FIG.
  • the semiconductor device 20 of the present embodiment includes a first semiconductor chip 21 and a second semiconductor chip 25 stacked on the first semiconductor chip 21.
  • FIG. 10A is a schematic configuration diagram of the first semiconductor chip 21 configuring the semiconductor device 20 according to the present embodiment
  • FIG. 10B is a schematic configuration of the second semiconductor chip 25 configuring the semiconductor device 20 according to the present embodiment.
  • the first semiconductor chip 21 constituting the semiconductor device 20 of this embodiment will be described.
  • the first semiconductor chip 21 of the present embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 10A).
  • a wiring layer constituting a desired circuit is provided.
  • the length of the side of the semiconductor substrate 3 constituting the first semiconductor chip 21 is set smaller than the length of the side of the semiconductor substrate 7 constituting the second semiconductor chip 25 described later.
  • connection terminal region 23 having a plurality of connection terminals 24 is provided in the central portion of the first semiconductor chip 21.
  • the connection terminal 24 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3.
  • a circuit provided in the first semiconductor chip 21 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 25 stacked on the first semiconductor chip 21.
  • connection terminal area 23 provided with a plurality of connection terminals 24 is composed of a first connection terminal area 23a and a second connection terminal area 23b.
  • region 23b is a rectangle.
  • the first connection terminal region 23a and the second connection terminal region 23b are arranged adjacent to each other in the long side direction.
  • connection terminal region 23a and the second connection terminal region 23b a plurality of connection terminals 24 are arrayed in a two-dimensional array. Then, x (x is an arbitrary number) connection terminals 24 are arranged in the long side direction of each of the first connection terminal region 23a and the second connection terminal region 23b, and y ( (wherein y is an arbitrary number smaller than x) of connecting terminals 24 are arranged. That is, in the first connection terminal region 23a and the second connection terminal region 23b, the plurality of connection terminals 24 are each arranged in the form of x columns ⁇ y rows. Each side of the connection terminal region 23 is sufficiently smaller than the length of the diagonal line of the semiconductor substrate 3.
  • the connection terminal region 23 has one diagonal line of the square semiconductor substrate 3 (the diagonal line between the upper left corner and the lower right corner in FIG. 10A) as the length of the connection terminal region 23. It is arranged so as to be parallel to the side. Further, the connection terminal region 23 is arranged so that the center of the semiconductor substrate 3 coincides with the center of the connection terminal region 23. In other words, in the first semiconductor chip 21 in the present embodiment, the long side of the connection terminal region 23 is disposed so as to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 3.
  • the second semiconductor chip 25 constituting the semiconductor device 20 of this embodiment will be described.
  • the second semiconductor chip 25 is configured by a semiconductor substrate 7 having an outer shape of a quadrangle (a square shape in FIG. 10B).
  • a wiring layer to be configured is provided.
  • the length of one side of the second semiconductor chip 25 is longer than that of the first semiconductor chip 21.
  • connection terminal region 27 having a plurality of connection terminals 28 is provided in the central portion of the second semiconductor chip 25.
  • the connection terminal 28 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 7.
  • a circuit provided in the second semiconductor chip 25 is electrically connected to a circuit of another semiconductor chip such as the first semiconductor chip 21 stacked on the second semiconductor chip 25.
  • connection terminal area 27 in which the plurality of connection terminals 28 are provided includes a first connection terminal area 27a and a second connection terminal area 27b.
  • region 27b is a rectangle.
  • the first connection terminal region 27a and the second connection terminal region 27b are arranged adjacent to each other in the long side direction.
  • connection terminal area 27a and the second connection terminal area 27b a plurality of connection terminals 28 are arrayed in a two-dimensional array. Then, x (x is an arbitrary number) connection terminals 28 are arranged in the long side direction of each of the first connection terminal region 27a and the second connection terminal region 27b, and y ( (wherein y is an arbitrary number smaller than x)) connecting terminals 28 are arranged. That is, in the first connection terminal region 27a and the second connection terminal region 27b, the plurality of connection terminals 28 are each arranged in the form of x columns ⁇ y rows. Further, each side of the connection terminal region 27 is sufficiently smaller than the diagonal length of the semiconductor substrate 7.
  • connection terminal region 27 has one diagonal line of the square semiconductor substrate 7 (the diagonal line between the upper left corner and the lower right corner in FIG. 10B) as the length of the connection terminal region 27. It is arranged so as to be parallel to the side. Further, the connection terminal region 27 is arranged so that the center of the semiconductor substrate 7 coincides with the center of the connection terminal region 27. That is, in the second semiconductor chip 25 in the present embodiment, the long side of the connection terminal region 27 is arranged to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 7.
  • the first semiconductor chip 21 and the second semiconductor chip 25 are stacked on each other so that the connection terminal regions 23 and 27 coincide with each other at the interface between them. Then, the first semiconductor chip 21 is electrically connected to the second semiconductor chip 25 through the connection terminals 24 and 28 provided in the connection terminal regions 23 and 27, respectively.
  • the outer shapes of the connection terminal regions 23 and 27 are oblique to the semiconductor substrates 3 and 7 (diagonal lines). (On top).
  • the area of the substrate region located outside the short sides of the connection terminal regions 23 and 27 is secured while reducing the area of the semiconductor substrates 3 and 7, respectively. can do.
  • the same effect as the first embodiment can be obtained.
  • FIG. 11 shows a schematic configuration when a corner portion of the first semiconductor chip 31a protrudes from the second semiconductor chip 6 in the semiconductor device 30a in which the first semiconductor chip 31a is stacked with the second semiconductor chip 6.
  • parts corresponding to those in FIG. 11 are identical to those in FIG.
  • the first semiconductor chip 31 a is configured by a semiconductor substrate 32 a having a quadrangular outer shape (a square shape in FIG. 11), and although not illustrated, a desired circuit is provided on the surface of the semiconductor substrate 32 a.
  • a wiring layer to be configured is provided. Further, the length of the semiconductor substrate 32 a constituting the first semiconductor chip 31 a in the diagonal direction is set to be longer than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6.
  • the width in the diagonal direction of the semiconductor substrate 32a of the first semiconductor chip 31a is longer than the length of one side of the semiconductor substrate 7 of the second semiconductor chip 6. For this reason, when the first semiconductor chip 31a and the second semiconductor chip 6 are stacked such that the connection terminal regions 33 and 8 coincide with each other at the interface between the first semiconductor chip 31a and the second semiconductor chip 6, the corners of the apex region of the first semiconductor chip 31a are Protrudes from the second semiconductor chip 6.
  • FIG. 12 is a schematic configuration diagram of a semiconductor device according to the third embodiment of the present disclosure.
  • the configuration of the first semiconductor chip 31 is partially different from the first semiconductor chip 31a of the semiconductor device 30a shown in FIG. Therefore, in FIG. 12, the same reference numerals are given to the portions corresponding to those in FIG.
  • the semiconductor device 30 of this embodiment includes a first semiconductor chip 31 and a second semiconductor chip 6 stacked on the first semiconductor chip 31.
  • the first semiconductor chip 31 is composed of a semiconductor substrate 32 having an octagonal outer shape. Although not shown, a wiring layer constituting a desired circuit is provided on the surface of the semiconductor substrate 32.
  • the semiconductor substrate 32 constituting the first semiconductor chip 31 is the semiconductor substrate 7 constituting the second semiconductor chip 6 when the first semiconductor chip 31 is stacked on the second semiconductor chip 6. The size is set so as not to protrude.
  • the first semiconductor chip 31 is a semiconductor chip having a shape obtained by cutting off the apex portion (corner portion) protruding from the second semiconductor chip 6 of the first semiconductor chip 31a shown in FIG.
  • the first semiconductor chip 31 is configured by the semiconductor substrate 32 from which excess vertex portions are cut off, whereby the chip area can be further reduced.
  • the same effects as those of the first embodiment can be obtained in this embodiment.
  • the outer shape of the first semiconductor chip 31 is an octagonal shape, but the shape of the first semiconductor chip 31 may be an octagonal shape as long as it does not protrude from the second semiconductor chip 6. There is no need.
  • the second semiconductor chip 6 has a rectangular shape and only a pair of opposing apexes of the first semiconductor chip 31 a protrude from the second semiconductor chip 6, the first semiconductor chip 6 By adopting a square shape, the same effect as in the present embodiment can be obtained.
  • FIG. 13A is a schematic configuration diagram of the semiconductor device 40 of the present embodiment
  • FIG. 13B is an enlarged view of a main part.
  • the configuration of the connection terminal region 41 in the first semiconductor chip 43 is different from that of the first semiconductor chip 2 in the first embodiment. Therefore, in FIG. 13A, the same reference numerals are given to the portions corresponding to FIG.
  • the first semiconductor chip 43 of this embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 13A).
  • a connection terminal area 41 having a connection terminal 42 is provided.
  • the connection terminal 42 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3.
  • TSV through silicon via
  • the shape of the connection terminal region 41 is a hexagon, and has a shape extending along a diagonal line between a pair of opposing vertices.
  • the angle of the vertex is formed at about 90 degrees. That is, the connection terminal area 41 corresponds to the apex among the connection terminals 5 located near each short side among the connection terminals 5 arranged in the connection terminal area 4 having the rectangular outer shape shown in FIG. The shape is such that only the connection terminal 5 remains.
  • connection terminal region 41 has one diagonal line of the square semiconductor substrate 3 (the diagonal line in the horizontal direction in FIG. 13) parallel to the long side of the connection terminal region 41. It is arranged to be. Further, the connection terminal region 41 is arranged so that the center of the semiconductor substrate 3 coincides with the center of the connection terminal region 41.
  • the shape of the end portion including the apex of the connection terminal region 41 is a triangular shape having an apex angle of approximately 90 degrees, so that the semiconductor substrate extends from the end portion of the connection terminal region 41 as shown in FIG. 13A.
  • the distances w1 and w2 to the corresponding side of 3 can be made substantially constant. As a result, it is possible to efficiently arrange the wiring and the circuit provided so as to bypass the connection terminal 42.
  • the same effect as the first embodiment can be obtained.
  • FIG. 14 shows another example of the connection terminal region 41 provided in the first semiconductor chip 43.
  • the connection terminal 42a located near the corner may not be used for the connection between the chips.
  • the end shape including the apex of the connection terminal region 41 actually used for connection can be a triangular shape.
  • the connection terminal 42a not used for connection can be configured by not burying a conductive material in the through hole. Even when the configuration shown in FIG. 14 is adopted, the same effect as that of the present embodiment can be obtained.
  • connection terminal region 41 has a hexagonal shape extending along a diagonal line between a pair of opposing vertices.
  • examples in which the effect of the present embodiment can be exhibited are limited thereto. It is not a thing.
  • connection terminal region has a polygonal shape extending in one direction and the width in the short axis direction of the connection terminal region is formed so as to decrease toward the end side in the long axis direction of the connection terminal region. The effect similar to this embodiment can be acquired.
  • the connection terminal region is provided in the semiconductor substrate so that the long side thereof is parallel to one diagonal line of the semiconductor substrate.
  • the present invention is not limited to this.
  • the connection terminal region is provided on the semiconductor substrate so that the long side of the connection terminal region is inclined at an angle larger than 0 degree and smaller than 90 degrees with respect to a predetermined side of the semiconductor substrate. The effect of can be obtained.
  • the connection terminal region is positioned outside the end side of the connection terminal region. It is possible to secure a wider area of the substrate region.
  • the semiconductor device has a structure in which the first semiconductor chip and the second semiconductor chip are stacked.
  • the semiconductor device also has a structure in which two or more semiconductor chips are stacked.
  • the technology of the present disclosure can be applied.
  • at least one of the stacked semiconductor chips has the configuration of the first semiconductor chip in the first to fourth embodiments, so that the same effect as in the first to fourth embodiments can be obtained. Can do.
  • the semiconductor device described above can be applied to various electronic devices such as an imaging device, a computer, and an image display device.
  • the driving speed can be reduced. Improvement is achieved.
  • this indication can also take the following structures.
  • a semiconductor substrate having a desired circuit and a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate, and a connection terminal region disposed in the semiconductor substrate, the connection terminals
  • the semiconductor is provided with a semiconductor chip which is formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees apparatus.
  • the semiconductor substrate is square or rectangular, The semiconductor device according to (1) or (2), wherein the connection terminal region is arranged on the semiconductor substrate such that a long side of the connection terminal region is parallel to one diagonal line of the semiconductor substrate.
  • the semiconductor chip and the other semiconductor chip are stacked such that the outer side of the semiconductor chip is tilted with respect to the outer side of the other semiconductor chip (1) to (4) A semiconductor device according to 1.
  • connection terminal region has a polygonal shape extending in one direction, and is formed so that the width in the minor axis direction of the connection terminal region decreases toward the end side in the major axis direction of the connection terminal region.
  • the semiconductor chip and the other semiconductor chip are stacked so that the outer side of the semiconductor chip is parallel to the outer side of the other semiconductor chip.
  • the semiconductor includes a semiconductor chip formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees Electronic equipment equipped with the device.
  • SYMBOLS 1,10,20,30,40 ... Semiconductor device, 2, 11, 21, 31, 43 ... 1st semiconductor chip, 3, 7, 12, 32 ... Semiconductor substrate, 4, 8, 13 , 23, 27, 33, 41 ... connection terminal region, 5, 9, 14, 24, 28, 34, 42 ... connection terminals, 6, 25 ... second semiconductor chip.

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Abstract

This semiconductor device is provided with a semiconductor chip that comprises a semiconductor substrate having a desired circuit and a connection terminal region that is arranged in the central part of the semiconductor substrate. The connection terminal region is arranged such that the long side thereof is inclined to a predetermined side of the semiconductor substrate at an angle larger than 0° but smaller than 90°. In addition, the connection terminal region has a plurality of connection terminals that are formed by filling through holes, which have been formed in the semiconductor substrate, with a conductive material. Consequently, this semiconductor device can be reduced in the mounting area.

Description

半導体装置及び電子機器Semiconductor device and electronic equipment
　本開示は、半導体装置に関し、特に、基板を貫通する接続電極を有する半導体装置に関する。また、本開示は、その半導体装置を備える電子機器に関する。 The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a connection electrode penetrating a substrate. The present disclosure also relates to an electronic apparatus including the semiconductor device.
　近年、デジタルカメラ、ビデオレコーダ、携帯電話、タブレット端末、ネットワーク端末などの様々なデジタル機器で、より高精細な画像処理や、高音質・高機能な音声処理や、複雑なデータ処理などが求められている。このような信号処理及びソフトウエアの実行の為、大容量で広帯域のメモリが組み込まれた半導体基板と所望の回路が組み込まれた半導体基板とを互いに接続する技術や、所望の回路が組み込まれた２つ以上の半導体基板を互いに接続する技術などが求められている。 In recent years, various digital devices such as digital cameras, video recorders, mobile phones, tablet terminals, network terminals, etc. have been demanded for higher-definition image processing, higher sound quality / higher performance voice processing, and more complicated data processing. ing. For such signal processing and software execution, a technology for connecting a semiconductor substrate incorporating a large-capacity, wide-band memory and a semiconductor substrate incorporating a desired circuit, and a desired circuit are incorporated. There is a demand for a technique for connecting two or more semiconductor substrates to each other.
　これを実現する技術の一つとして、スルーシリコンビア（ＴＳＶ：Through Silicon Via）を利用した３次元のチップ接続技術（チップ積層技術）がある。ＴＳＶは、半導体基板を貫通する極小の孔に導電材料を埋め込むことによって構成される配線である。従来、半導体装置の内部では、平面方向に配線を設けて各回路を接続していた。これに対し、この３次元のチップ接続技術では、複数の半導体チップを積層し、上下に積層した半導体チップ間をＴＳＶを介して電気的に接続することで、各半導体チップに設けられた回路が接続される。 One of the technologies for realizing this is a three-dimensional chip connection technology (chip stacking technology) using a through silicon via (TSV). The TSV is a wiring configured by embedding a conductive material in a very small hole penetrating the semiconductor substrate. Conventionally, in a semiconductor device, wirings are provided in a planar direction to connect each circuit. On the other hand, in this three-dimensional chip connection technology, a plurality of semiconductor chips are stacked, and the semiconductor chips stacked vertically are electrically connected via a TSV, so that a circuit provided in each semiconductor chip can be obtained. Connected.
　特許文献１では、ＴＳＶを有する半導体チップを、他の半導体チップに積層して搭載する技術が開示されている。また、近年、ＴＳＶを有し、３次元実装が可能な半導体メモリとして、ＪＥＤＥＣ規格の「ＪＥＳＤ２２９　Ｗｉｄｅ　Ｉ／Ｏ　ＳＤＲ（Single Date Rate）」と呼ばれる新規格のモバイルＤＲＡＭが提唱されている。このＷｉｄｅ　Ｉ／Ｏ　ＳＤＲでは、１２００本の信号線を使って、１２８ｂｉｔ×４系統のメモリセルに対し、各メモリセルを２００ＭＨｚ動作のＳＤＲＡＭとしてそれぞれ独立にアクセスすることができる。 Patent Document 1 discloses a technique for stacking and mounting a semiconductor chip having a TSV on another semiconductor chip. In recent years, a new standard mobile DRAM called “JESD229 Wide I / O SDR (Single Date Rate)” of the JEDEC standard has been proposed as a semiconductor memory having TSV and capable of three-dimensional mounting. In this Wide I / O SDR, each memory cell can be independently accessed as an SDRAM of 200 MHz operation with respect to 128-bit × 4 memory cells using 1200 signal lines.
特開２０１０－５０３１２号公報JP 2010-50312 A
　このような、複数の半導体チップを積層し、ＴＳＶを用いて積層した半導体チップ間を電気的に接続した構造を有する半導体装置において、実装面積の更なる縮小化が望まれている。 In such a semiconductor device having a structure in which a plurality of semiconductor chips are stacked and the semiconductor chips stacked using TSV are electrically connected, further reduction in mounting area is desired.
　上述の点に鑑み、本開示は、実装面積を縮小できる半導体装置を提供する。また、本開示は、その半導体装置を用いた電子機器を提供する。 In view of the above points, the present disclosure provides a semiconductor device capable of reducing the mounting area. The present disclosure also provides an electronic device using the semiconductor device.
　本開示の半導体装置は、所望の回路を有する半導体基板と、半導体基板に配置された接続端子領域とを含む半導体チップを備える。接続端子領域は、その長辺が、半導体基板の所定の辺に対して０度よりも大きく９０度よりも小さい角度で傾くように配置されている。また、接続端子領域は、半導体基板に設けられた貫通孔に導電材料が埋め込まれた複数の接続端子を有する。 The semiconductor device of the present disclosure includes a semiconductor chip including a semiconductor substrate having a desired circuit and a connection terminal region disposed on the semiconductor substrate. The connection terminal region is arranged such that its long side is inclined with respect to a predetermined side of the semiconductor substrate at an angle greater than 0 degree and less than 90 degrees. The connection terminal region includes a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate.
　本開示の半導体装置では、接続端子領域の長辺が半導体基板の所定の辺に対して傾くように接続端子領域が半導体基板の中央部に配置されている。これにより、半導体基板の接続端子領域の周辺領域を、配線等に有効に用いることができる。 In the semiconductor device of the present disclosure, the connection terminal region is arranged at the center of the semiconductor substrate so that the long side of the connection terminal region is inclined with respect to a predetermined side of the semiconductor substrate. Thereby, the peripheral area | region of the connection terminal area | region of a semiconductor substrate can be used effectively for wiring etc.
　本開示の電子機器は、上記半導体装置を有する。 The electronic device of the present disclosure includes the semiconductor device.
　本開示の電子機器では、半導体装置を構成する半導体基板において、接続端子領域の周辺領域を、配線等に有効に用いることができるため、駆動動作の高速化が図られる。 In the electronic device of the present disclosure, the peripheral region of the connection terminal region can be effectively used for wiring or the like in the semiconductor substrate constituting the semiconductor device, so that the drive operation can be speeded up.
　本開示によれば、実装面積が縮小された半導体装置が得られる。また、その半導体装置を用いることにより、駆動動作に優れた電子機器が得られる。なお、本明細書に記載された効果はあくまで例示であって限定されるものでは無く、また付加的な効果があってもよい。 According to the present disclosure, a semiconductor device with a reduced mounting area can be obtained. In addition, by using the semiconductor device, an electronic device excellent in driving operation can be obtained. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.
本開示の第１の実施形態に係る半導体装置の概略構成図である。1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present disclosure. 本開示の第１の実施形態に係る半導体装置を構成する第１半導体チップの概略構成図である。FIG. 3 is a schematic configuration diagram of a first semiconductor chip configuring the semiconductor device according to the first embodiment of the present disclosure. 本開示の第１の実施形態に係る半導体装置を構成する第２半導体チップの概略構成図である。It is a schematic block diagram of the 2nd semiconductor chip which comprises the semiconductor device concerning a 1st embodiment of this indication. 比較例に係る半導体装置の概略構成図である。It is a schematic block diagram of the semiconductor device which concerns on a comparative example. 比較例に係る第１半導体チップの概略構成図である。It is a schematic block diagram of the 1st semiconductor chip which concerns on a comparative example. 比較例の第１半導体チップに、回路Ｉと回路ＩＩとを設けた場合の模式図である。It is a schematic diagram at the time of providing the circuit I and the circuit II in the 1st semiconductor chip of a comparative example. 図７Ａは、比較例に係る第１半導体チップの概略構成図であり、図７Ｂは、本開示の第１の実施形態で用いられる第１半導体チップの概略構成図である。FIG. 7A is a schematic configuration diagram of a first semiconductor chip according to a comparative example, and FIG. 7B is a schematic configuration diagram of a first semiconductor chip used in the first embodiment of the present disclosure. 図８Ａ及び図８Ｂは、本開示の第１の実施形態に適用可能な接続端子領域の他の例を示した図である。8A and 8B are diagrams illustrating another example of the connection terminal region applicable to the first embodiment of the present disclosure. 本開示の第２の実施形態に係る半導体装置の概略構成図である。FIG. 6 is a schematic configuration diagram of a semiconductor device according to a second embodiment of the present disclosure. 図１０Ａは、本開示の第２の実施形態に係る半導体装置を構成する第１半導体チップの概略構成図であり、図１０Ｂは、本開示の第２の実施形態に係る半導体装置を構成する第２半導体チップの概略構成図である。FIG. 10A is a schematic configuration diagram of a first semiconductor chip configuring a semiconductor device according to the second embodiment of the present disclosure, and FIG. 10B illustrates a first configuration of the semiconductor device according to the second embodiment of the present disclosure. It is a schematic block diagram of 2 semiconductor chips. 第１半導体チップと第２半導体チップとが積層された半導体装置において、第１半導体チップが第２半導体チップからはみ出た場合の概略構成を示す。In the semiconductor device in which the first semiconductor chip and the second semiconductor chip are stacked, a schematic configuration when the first semiconductor chip protrudes from the second semiconductor chip is shown. 本開示の第３の実施形態に係る半導体装置の概略構成図である。FIG. 6 is a schematic configuration diagram of a semiconductor device according to a third embodiment of the present disclosure. 図１３Ａは、本開示の第４の実施形態に係る半導体装置の概略構成図であり、図１３Ｂは、要部の拡大図である。FIG. 13A is a schematic configuration diagram of a semiconductor device according to the fourth embodiment of the present disclosure, and FIG. 13B is an enlarged view of a main part. 本開示の第４の実施形態に係る半導体装置の第１半導体チップに設けられる接続端子領域の他の例を示した図である。It is a figure showing other examples of the connecting terminal field provided in the 1st semiconductor chip of the semiconductor device concerning a 4th embodiment of this indication.
　以下に、本開示の実施形態に係る半導体装置の一例を、図面を参照しながら説明する。本開示の実施形態は以下の順で説明する。なお、本開示の技術は、以下の例に限定されるものではない。
１．第１の実施形態：接続端子領域の長辺が半導体基板の辺に対して傾いて配置された半導体チップを用いる例（その１）
　１－１．第１半導体チップの構成
　１－２．第２半導体チップの構成
　１－３．比較例に係る半導体装置
２．第２の実施形態：接続端子領域の長辺が半導体基板の辺に対して傾いて配置された半導体チップを用いる例（その２）
　２－１．第１半導体チップの構成
　２－２．第２半導体チップの構成
３．第３の実施形態：四角形状の半導体基板の頂点を切り取られた半導体チップを用いる例
４．第４の実施形態：接続端子領域の長辺方向の端部が三角形状である半導体チップを用いる例 Hereinafter, an example of a semiconductor device according to an embodiment of the present disclosure will be described with reference to the drawings. Embodiments of the present disclosure will be described in the following order. Note that the technology of the present disclosure is not limited to the following example.
1. First Embodiment: Example of using a semiconductor chip in which a long side of a connection terminal region is arranged to be inclined with respect to a side of a semiconductor substrate (part 1)
1-1. Configuration of first semiconductor chip 1-2. Configuration of second semiconductor chip 1-3. 1. Semiconductor device according to comparative example Second Embodiment: Example of using a semiconductor chip in which the long side of the connection terminal region is inclined with respect to the side of the semiconductor substrate (part 2)
2-1. Configuration of first semiconductor chip 2-2. 2. Configuration of second semiconductor chip 3. Third embodiment: Example using a semiconductor chip with a vertex cut off from a rectangular semiconductor substrate Fourth embodiment: an example using a semiconductor chip in which the end in the long side direction of the connection terminal region is triangular.
　〈１．第１の実施形態：接続端子領域の長辺が半導体基板の辺に対して傾いて配置された半導体チップを用いる例（その１）〉
　図１は、本開示の第１の実施形態に係る半導体装置の概略構成図である。図１に示すように、本実施形態の半導体装置１は、第１半導体チップ２と、第１半導体チップ２に積層された第２半導体チップ６とを有する。第１半導体チップ２は、本開示に特有の半導体チップであり、第２半導体チップ６は、既存の半導体チップを想定している。 <1. First Embodiment: Example (Part 1) Using a Semiconductor Chip Arranged with the Long Side of the Connection Terminal Region Inclined with respect to the Side of the Semiconductor Substrate>
FIG. 1 is a schematic configuration diagram of a semiconductor device according to the first embodiment of the present disclosure. As shown in FIG. 1, the semiconductor device 1 of this embodiment includes a first semiconductor chip 2 and a second semiconductor chip 6 stacked on the first semiconductor chip 2. The first semiconductor chip 2 is a semiconductor chip unique to the present disclosure, and the second semiconductor chip 6 is assumed to be an existing semiconductor chip.
　［１－１．第１半導体チップの構成］
　まず、本実施形態の半導体装置１を構成する第１半導体チップ２について説明する。図２は、本実施形態の半導体装置１を構成する第１半導体チップ２の概略構成図である。 [1-1. Configuration of first semiconductor chip]
First, the first semiconductor chip 2 constituting the semiconductor device 1 of this embodiment will be described. FIG. 2 is a schematic configuration diagram of the first semiconductor chip 2 constituting the semiconductor device 1 of the present embodiment.
　図２に示すように、本実施形態の第１半導体チップ２は、外形が四角形状（図２では正方形状）の半導体基板３で構成され、図示を省略するが、半導体基板３の表面には所望の回路を構成する配線層が設けられている。また、第１半導体チップ２を構成する半導体基板３の対角方向の長さは、後述する第２半導体チップ６を構成する半導体基板７の一辺の長さよりも短く設定されている。 As shown in FIG. 2, the first semiconductor chip 2 of the present embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 2). A wiring layer constituting a desired circuit is provided. Further, the length of the diagonal direction of the semiconductor substrate 3 constituting the first semiconductor chip 2 is set shorter than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6 described later.
　また、第１半導体チップ２の中央部分には、複数の接続端子５を有する接続端子領域４が設けられている。接続端子５は、半導体基板３を貫通する貫通孔に導電材料が埋め込まれた、いわゆるスルーシリコンビア（ＴＳＶ）である。この接続端子５によって、第１半導体チップ２に設けられた回路が、第１半導体チップ２に積層された第２半導体チップ６等、他の半導体チップの回路と電気的に接続される。 Further, a connection terminal region 4 having a plurality of connection terminals 5 is provided in the central portion of the first semiconductor chip 2. The connection terminal 5 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3. With this connection terminal 5, a circuit provided in the first semiconductor chip 2 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 6 stacked on the first semiconductor chip 2.
　複数の接続端子５が設けられる接続端子領域４の半導体基板３の面における形状は長方形である。そして、接続端子領域４内において、複数の接続端子５は２次元状にアレイ配列されており、接続端子領域４の長辺方向にはｘ個（ｘは任意の数）の接続端子５が配列され、短辺方向にはｙ個（ｙはｘよりも小さい任意の数）の接続端子５が配列されている。すなわち、接続端子領域４内において、複数の接続端子５は、ｘ列×ｙ行の形態で配列される。また、接続端子領域４の各辺の長さは、半導体基板３の各辺の長さよりも十分に短い。 The shape of the connection terminal region 4 provided with the plurality of connection terminals 5 on the surface of the semiconductor substrate 3 is a rectangle. In the connection terminal region 4, the plurality of connection terminals 5 are arrayed in a two-dimensional array, and x (x is an arbitrary number) connection terminals 5 are arrayed in the long side direction of the connection terminal region 4. In the short side direction, y (y is an arbitrary number smaller than x) connection terminals 5 are arranged. That is, in the connection terminal region 4, the plurality of connection terminals 5 are arranged in the form of x columns × y rows. The length of each side of the connection terminal region 4 is sufficiently shorter than the length of each side of the semiconductor substrate 3.
　そして、本実施形態の第１半導体チップ２では、正方形状の半導体基板３の一方の対角線（図２では左右方向の対角線）が接続端子領域４の長辺と平行となり、かつ、半導体基板３の中心が接続端子領域４の中心と一致するように接続端子領域４が配置されている。すなわち、第１半導体チップ２では、接続端子領域４の長辺が半導体基板３の辺に対して約４５度傾くように配置されている。 In the first semiconductor chip 2 of the present embodiment, one diagonal line of the square semiconductor substrate 3 (the diagonal line in the left-right direction in FIG. 2) is parallel to the long side of the connection terminal region 4 and the semiconductor substrate 3 The connection terminal region 4 is arranged so that the center coincides with the center of the connection terminal region 4. That is, in the first semiconductor chip 2, the long side of the connection terminal region 4 is arranged to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 3.
　［１－２．第２半導体チップの構成］
　次に、本実施形態の半導体装置１を構成する第２半導体チップ６について説明する。図３は、本実施形態の半導体装置１を構成する第２半導体チップ６の概略構成図である。なお、第２半導体チップ６は、既存の半導体チップを想定しており、この既存の半導体チップとしては、例えば、ＪＥＤＥＣ規格のＪＥＳＤ２２９　Ｗｉｄｅ　Ｉ／Ｏ　ＳＤＲに対応する半導体チップが該当する。 [1-2. Configuration of second semiconductor chip]
Next, the second semiconductor chip 6 constituting the semiconductor device 1 of the present embodiment will be described. FIG. 3 is a schematic configuration diagram of the second semiconductor chip 6 constituting the semiconductor device 1 of the present embodiment. The second semiconductor chip 6 is assumed to be an existing semiconductor chip, and the existing semiconductor chip corresponds to, for example, a semiconductor chip corresponding to JEDEC standard JESD229 Wide I / O SDR.
　図３に示すように、第２半導体チップ６は、外形が四角形状（図３では正方形状）の半導体基板７で構成され、図示を省略するが、半導体基板７の表面には所望の回路を構成する配線層が設けられている。また、本実施形態では、第２半導体チップ６の一辺の長さは、第１半導体チップ２の対角方向の長さよりも長い。 As shown in FIG. 3, the second semiconductor chip 6 is composed of a semiconductor substrate 7 whose outer shape is a square shape (square shape in FIG. 3), and although not shown, a desired circuit is provided on the surface of the semiconductor substrate 7. A wiring layer to be configured is provided. In the present embodiment, the length of one side of the second semiconductor chip 6 is longer than the diagonal length of the first semiconductor chip 2.
　また、第２半導体チップ６の中央部分には、複数の接続端子９を有する接続端子領域８が設けられている。接続端子９は、半導体基板７を貫通する貫通孔に導電材料が埋め込まれた、いわゆるスルーシリコンビア（ＴＳＶ）である。この接続端子９によって、第２半導体チップ６に設けられた回路が、第２半導体チップ６に積層される第１半導体チップ２等、他の半導体チップの回路と電気的に接続される。 Further, a connection terminal region 8 having a plurality of connection terminals 9 is provided in the central portion of the second semiconductor chip 6. The connection terminal 9 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 7. With this connection terminal 9, a circuit provided in the second semiconductor chip 6 is electrically connected to a circuit of another semiconductor chip such as the first semiconductor chip 2 stacked on the second semiconductor chip 6.
　複数の接続端子９が設けられる接続端子領域８の半導体基板７の面における形状は長方形である。そして、接続端子領域８内において、複数の接続端子９は２次元状にアレイ配列されており、接続端子領域８の長辺方向にはｘ個（ｘは任意の数）の接続端子９が配列され、短辺方向にはｙ個（ｙはｘよりも小さい任意の数）の接続端子９が配列されている。すなわち、接続端子領域８内において、複数の接続端子９は、ｘ列×ｙ行の形態で配列される。また、接続端子領域８の各辺の長さは、半導体基板７の各辺の長さよりも十分に短い。この接続端子領域８の範囲、接続端子領域８に設けられる接続端子９の数、及び、接続端子９の間隔（ピッチ）は、第１半導体チップ２のそれらと同じである。 The shape of the connection terminal region 8 provided with the plurality of connection terminals 9 on the surface of the semiconductor substrate 7 is a rectangle. In the connection terminal region 8, the plurality of connection terminals 9 are two-dimensionally arrayed, and x (x is an arbitrary number) connection terminals 9 are arrayed in the long side direction of the connection terminal region 8. In the short side direction, y (y is an arbitrary number smaller than x) connecting terminals 9 are arranged. That is, in the connection terminal region 8, the plurality of connection terminals 9 are arranged in the form of x columns × y rows. In addition, the length of each side of the connection terminal region 8 is sufficiently shorter than the length of each side of the semiconductor substrate 7. The range of the connection terminal region 8, the number of connection terminals 9 provided in the connection terminal region 8, and the interval (pitch) of the connection terminals 9 are the same as those of the first semiconductor chip 2.
　そして、第２半導体チップ６では、正方形状の半導体基板７の所定の一辺（図３では上辺又は下辺）が、接続端子領域８の長辺と平行となり、かつ、半導体基板７の中心が接続端子領域８の中心と一致するように、接続端子領域８が配置されている。 In the second semiconductor chip 6, a predetermined one side (the upper side or the lower side in FIG. 3) of the square semiconductor substrate 7 is parallel to the long side of the connection terminal region 8, and the center of the semiconductor substrate 7 is the connection terminal. The connection terminal region 8 is arranged so as to coincide with the center of the region 8.
　本実施形態では、第１半導体チップ２及び第２半導体チップ６のそれぞれの接続端子領域４，８の位置が両者の接続界面で一致するように、第１半導体チップ２が第２半導体チップ６上に積層される。そして、それぞれの接続端子領域４，８に設けられた接続端子５，９を介して、第１半導体チップ２と第２半導体チップ６とが互いに電気的に接続される。 In the present embodiment, the first semiconductor chip 2 is placed on the second semiconductor chip 6 so that the positions of the connection terminal regions 4 and 8 of the first semiconductor chip 2 and the second semiconductor chip 6 coincide at the connection interface between them. Is laminated. Then, the first semiconductor chip 2 and the second semiconductor chip 6 are electrically connected to each other via the connection terminals 5 and 9 provided in the respective connection terminal regions 4 and 8.
　本実施形態の半導体装置１では、第１半導体チップ２の接続端子領域４は、その長辺が、第１半導体チップ２を構成する半導体基板３の辺に対して４５度傾くように配置されている。このため、第１半導体チップ２を第２半導体チップ６上に積層した場合に、図１に示すように、第１半導体チップ２の辺は、第２半導体チップ６の辺に対して４５度傾いた状態となる。 In the semiconductor device 1 of the present embodiment, the connection terminal region 4 of the first semiconductor chip 2 is arranged such that the long side is inclined 45 degrees with respect to the side of the semiconductor substrate 3 constituting the first semiconductor chip 2. Yes. Therefore, when the first semiconductor chip 2 is stacked on the second semiconductor chip 6, the side of the first semiconductor chip 2 is inclined 45 degrees with respect to the side of the second semiconductor chip 6 as shown in FIG. 1. It becomes the state.
　本実施形態の半導体装置１では、第１半導体チップ２の対角方向の長さが、第２半導体チップ６の一辺の長さよりも短く設定されているため、第１半導体チップ２が第２半導体チップ６からはみ出ることがない。 In the semiconductor device 1 of the present embodiment, the length of the first semiconductor chip 2 in the diagonal direction is set to be shorter than the length of one side of the second semiconductor chip 6, so that the first semiconductor chip 2 is the second semiconductor. It does not protrude from the chip 6.
　そして、本実施形態の半導体装置１に用いた第１半導体チップ２では、半導体基板３の辺に対して、接続端子領域４の辺が傾くように接続端子領域４を配置することにより、半導体基板３上に配置する回路や配線の配置可能領域を確保しやすくなる。本実施形態の半導体装置１に用いた第１半導体チップ２では、さらに、回路や配線の配置可能領域を確保した上で、半導体基板３の小型化を図ることができる。この点について、以下に、比較例に係る半導体チップを用いて説明する。 In the first semiconductor chip 2 used in the semiconductor device 1 of the present embodiment, the connection terminal region 4 is arranged so that the side of the connection terminal region 4 is inclined with respect to the side of the semiconductor substrate 3. This makes it easy to secure an area in which circuits and wirings arranged on 3 can be arranged. In the first semiconductor chip 2 used in the semiconductor device 1 of the present embodiment, the semiconductor substrate 3 can be further reduced in size while securing a circuit and wiring arrangementable area. This point will be described below using a semiconductor chip according to a comparative example.
　［１－３．比較例に係る半導体装置］
　図４は、比較例に係る半導体装置１０の概略構成図である。比較例に係る半導体装置１０は、第１半導体チップの構成が第１の実施形態と異なる。したがって、図４において、図１に対応する部分には同一符号を付し重複説明を省略する。 [1-3. Semiconductor device according to comparative example]
FIG. 4 is a schematic configuration diagram of the semiconductor device 10 according to the comparative example. The semiconductor device 10 according to the comparative example is different from the first embodiment in the configuration of the first semiconductor chip. Therefore, in FIG. 4, the same reference numerals are given to the portions corresponding to those in FIG.
　図４に示すように、比較例の半導体装置１０は、第１半導体チップ１１と、第１半導体チップ１１に積層された第２半導体チップ６とを有する。図５は、比較例に係る第１半導体チップ１１の概略構成図である。 As shown in FIG. 4, the semiconductor device 10 of the comparative example includes a first semiconductor chip 11 and a second semiconductor chip 6 stacked on the first semiconductor chip 11. FIG. 5 is a schematic configuration diagram of the first semiconductor chip 11 according to the comparative example.
　第１半導体チップ１１は、外形が四角形状（図５では正方形状）の半導体基板１２で構成され、図示を省略するが、半導体基板１２の表面には所望の回路を構成する配線層が設けられている。また、第１半導体チップ１１を構成する半導体基板１２の一辺の長さは、第２半導体チップ６を構成する半導体基板７の一辺の長さよりも短く設定されている。 The first semiconductor chip 11 is composed of a semiconductor substrate 12 whose outer shape is a quadrangle (square shape in FIG. 5), and although not shown, a wiring layer constituting a desired circuit is provided on the surface of the semiconductor substrate 12. ing. Further, the length of one side of the semiconductor substrate 12 constituting the first semiconductor chip 11 is set shorter than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6.
　また、第１半導体チップ１１の中央部分には、複数の接続端子１４を有する接続端子領域１３が設けられている。接続端子１４は、半導体基板１２を貫通する貫通孔に導電材料が埋め込まれた、いわゆるスルーシリコンビアである。この接続端子１４により、第１半導体チップ１１に設けられた回路が、第１半導体チップ１１に積層された第２半導体チップ６等、他の半導体チップの回路と電気的に接続される。 Further, a connection terminal region 13 having a plurality of connection terminals 14 is provided in the central portion of the first semiconductor chip 11. The connection terminal 14 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 12. With this connection terminal 14, a circuit provided in the first semiconductor chip 11 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 6 stacked on the first semiconductor chip 11.
　複数の接続端子１４が設けられる接続端子領域１３の半導体基板１２の面における形状は長方形である。そして、接続端子領域１３内において、複数の接続端子１４は２次元状にアレイ配列されており、接続端子領域１３の長辺方向にはｘ個（ｘは任意の数）の接続端子１４が配列され、短辺方向にはｙ個（ｙはｘよりも小さい任意の数）の接続端子１４が配列されている。すなわち、接続端子領域１３内において、複数の接続端子１４は、ｘ列×ｙ行の形態で配列される。また、接続端子領域１３の各辺は半導体基板１２の各辺よりも十分に小さい。 The shape of the connection terminal region 13 provided with the plurality of connection terminals 14 on the surface of the semiconductor substrate 12 is a rectangle. In the connection terminal region 13, the plurality of connection terminals 14 are arrayed in a two-dimensional array, and x (x is an arbitrary number) connection terminals 14 are arrayed in the long side direction of the connection terminal region 13. In the short side direction, y (y is an arbitrary number smaller than x) connection terminals 14 are arranged. That is, in the connection terminal region 13, the plurality of connection terminals 14 are arranged in the form of x columns × y rows. Further, each side of the connection terminal region 13 is sufficiently smaller than each side of the semiconductor substrate 12.
　比較例に係る第１半導体チップ１１では、正方形状の半導体基板１２の所定の一辺（図３では上方又は下方）が接続端子領域１３の長辺と平行となり、かつ、半導体基板１２の中心が接続端子領域１３の中心と一致するように接続端子領域１３が配置されている。 In the first semiconductor chip 11 according to the comparative example, a predetermined one side (upper or lower in FIG. 3) of the square semiconductor substrate 12 is parallel to the long side of the connection terminal region 13, and the center of the semiconductor substrate 12 is connected. The connection terminal region 13 is arranged so as to coincide with the center of the terminal region 13.
　比較例に係る半導体装置１０においても、第１半導体チップ１１が第２半導体チップ６上に、それぞれの接続端子領域１３，８の位置が両者の接続界面で一致するように積層される。そして、それぞれの接続端子領域１３，８に設けられた接続端子１４，９を介して、第１半導体チップ１１と第２半導体チップ６とが互いに電気的に接続される。 Also in the semiconductor device 10 according to the comparative example, the first semiconductor chip 11 is stacked on the second semiconductor chip 6 so that the positions of the connection terminal regions 13 and 8 coincide with each other at the connection interface between them. Then, the first semiconductor chip 11 and the second semiconductor chip 6 are electrically connected to each other via the connection terminals 14 and 9 provided in the respective connection terminal regions 13 and 8.
　比較例に係る半導体装置１０では、第１半導体チップ１１の接続端子領域１３は、その長辺が、第１半導体チップ１１の所定の辺に平行となるように設けられている。したがって、第１半導体チップ１１の辺は、第２半導体チップ６の辺と平行となる。 In the semiconductor device 10 according to the comparative example, the connection terminal region 13 of the first semiconductor chip 11 is provided such that its long side is parallel to a predetermined side of the first semiconductor chip 11. Therefore, the side of the first semiconductor chip 11 is parallel to the side of the second semiconductor chip 6.
　ところで、図４に示したように、第２半導体チップ６に接続する第１半導体チップ１１を作製する場合、第１半導体チップ１１の一辺は、接続端子領域１３の長辺方向の幅以下にすることはできない。 Incidentally, as shown in FIG. 4, when the first semiconductor chip 11 connected to the second semiconductor chip 6 is manufactured, one side of the first semiconductor chip 11 is set to be equal to or smaller than the width of the connection terminal region 13 in the long side direction. It is not possible.
　また、複数の微小な接続端子を有する半導体チップでは、多数の極小の孔及び電極を設けるため、半導体チップが小型化するにつれて、接続端子の周辺に、配線や回路等を配置することが物理的に不可能になるという問題がある。 In addition, in a semiconductor chip having a plurality of minute connection terminals, a large number of extremely small holes and electrodes are provided. Therefore, as the semiconductor chip is miniaturized, it is physically disposed around the connection terminals. There is a problem that it becomes impossible.
　さらに、微小な接続端子が複数配列される接続端子領域を有する半導体チップでは、接続端子領域を跨ぐような配線はできない。このため、接続端子領域の外形は、一方の方向に細長い形状となる。このように、接続端子が設けられる接続端子領域が細長い形状である場合、必要な回路配置面積を大きくしなければならない可能性がある。 Furthermore, in a semiconductor chip having a connection terminal region in which a plurality of minute connection terminals are arranged, wiring that straddles the connection terminal region cannot be performed. For this reason, the external shape of the connection terminal region is elongated in one direction. As described above, when the connection terminal region where the connection terminal is provided has an elongated shape, there is a possibility that a required circuit arrangement area must be increased.
　図６に、比較例の第１半導体チップ１１に、回路Ｉと回路ＩＩとを設けた場合の模式図を示す。ここでは、図６に示すように、半導体基板１２上において、回路Ｉが接続端子領域１３の一方の長辺の外側の基板領域に配置され、回路ＩＩが接続端子領域１３の他方の長辺の外側の基板領域に配置された例を説明する。すなわち、半導体基板１２上において、回路Ｉ及び回路ＩＩが間に接続端子領域１３を挟んで配置されている例を説明する。 FIG. 6 shows a schematic diagram when the circuit I and the circuit II are provided in the first semiconductor chip 11 of the comparative example. Here, as shown in FIG. 6, on the semiconductor substrate 12, the circuit I is arranged in a substrate region outside one long side of the connection terminal region 13, and the circuit II is arranged on the other long side of the connection terminal region 13. The example arrange | positioned in the outer side board | substrate area | region is demonstrated. That is, an example in which the circuit I and the circuit II are arranged on the semiconductor substrate 12 with the connection terminal region 13 interposed therebetween will be described.
　回路Ｉを回路ＩＩと、第１半導体チップ１１内において接続する場合、回路Ｉと回路ＩＩとを接続する配線を半導体基板１２上に設ける必要がある。しかしながら、同一の半導体チップ内で、複数の回路を電気的に接続する場合、接続端子領域１３を跨いで配線（図６中の破線矢印）を配置することはできない。このため、図６の矢印ａに示すように、接続端子１４が形成された領域を避けるように、配線を設けなければならないという要請がある。 When the circuit I is connected to the circuit II in the first semiconductor chip 11, it is necessary to provide wiring on the semiconductor substrate 12 for connecting the circuit I and the circuit II. However, when a plurality of circuits are electrically connected in the same semiconductor chip, wiring (broken arrows in FIG. 6) cannot be arranged across the connection terminal region 13. For this reason, there is a demand that wiring should be provided so as to avoid the region where the connection terminal 14 is formed, as indicated by an arrow a in FIG.
　この場合、比較例の半導体装置１０では、配線経路が長くなり、駆動のタイミングが合わなくなるため、高速駆動できなくなるという問題がある。また、図６の矢印ａに示すように配線を設ける場合、接続端子領域１３の短辺の外側に位置する基板領域の面積が狭いと配線密度が高くなり、所望数の配線を形成することが難しくなる。このため、必要とする配線分だけ、接続端子領域１３の短辺の外側に位置する基板領域の面積を確保する必要がある。そうすると、最終的に、実装面積の増加によりコストが高くなるという可能性がある。 In this case, in the semiconductor device 10 of the comparative example, there is a problem that the wiring path becomes long and the driving timing is not matched, so that high-speed driving cannot be performed. Further, when wiring is provided as shown by an arrow a in FIG. 6, if the area of the substrate region located outside the short side of the connection terminal region 13 is small, the wiring density increases, and a desired number of wirings can be formed. It becomes difficult. For this reason, it is necessary to secure the area of the substrate region located outside the short side of the connection terminal region 13 for the required wiring. As a result, the cost may eventually increase due to an increase in the mounting area.
　図７Ａ及び図７Ｂに、比較例の第１半導体チップ１１と、本実施形態の第１半導体チップ２とを並べて図示する。ここでは、図７Ａ及び図７Ｂに示すように、比較例の第１半導体チップ１１の接続端子領域１３の長辺方向の幅Ａは、本実施形態の第１半導体チップ２の接続端子領域４とのそれと同じとする。また、比較例の第１半導体チップ１１の接続端子領域１３の短辺の外側の配線領域（基板領域）の幅Ｂが、本実施形態の第１半導体チップの接続端子領域４のそれと同じである。この場合、比較例に係る第１半導体チップ１１の面積は、（Ａ＋２Ｂ）×（Ａ＋２Ｂ）であるのに対し、本実施形態に係る第１半導体チップ２の面積は、（Ａ＋２Ｂ）×（Ａ＋２Ｂ）÷２となる。 7A and 7B show the first semiconductor chip 11 of the comparative example and the first semiconductor chip 2 of the present embodiment side by side. Here, as shown in FIGS. 7A and 7B, the width A in the long side direction of the connection terminal region 13 of the first semiconductor chip 11 of the comparative example is equal to the connection terminal region 4 of the first semiconductor chip 2 of the present embodiment. The same as that. Further, the width B of the wiring region (substrate region) outside the short side of the connection terminal region 13 of the first semiconductor chip 11 of the comparative example is the same as that of the connection terminal region 4 of the first semiconductor chip of the present embodiment. . In this case, the area of the first semiconductor chip 11 according to the comparative example is (A + 2B) × (A + 2B), whereas the area of the first semiconductor chip 2 according to the present embodiment is (A + 2B) × (A + 2B). ÷ 2.
　したがって、本実施形態の第１半導体チップ２では、比較例の第１半導体チップ１１と同じ幅Ｂの配線領域を確保しながらも、チップ面積の縮小化を図ることができる。また、本実施形態の第１半導体チップ２を比較例の第１半導体チップ１１と同じ面積とした場合には、本実施形態の第１半導体チップ２において、接続端子領域４を拡大することができるため、接続端子５の本数を増やすこともできる。 Therefore, in the first semiconductor chip 2 of the present embodiment, the chip area can be reduced while securing a wiring region having the same width B as that of the first semiconductor chip 11 of the comparative example. Further, when the first semiconductor chip 2 of the present embodiment has the same area as the first semiconductor chip 11 of the comparative example, the connection terminal region 4 can be enlarged in the first semiconductor chip 2 of the present embodiment. Therefore, the number of connection terminals 5 can be increased.
　本実施形態では、第１半導体チップ２の外形を正方形状としたが、長方形状としてもよい。その場合にも、接続端子領域４の長辺が長方形状の半導体基板の一方の対角線と平行となるように接続端子領域４を配置することで、本実施形態と同様の効果を得ることができる。 In the present embodiment, the outer shape of the first semiconductor chip 2 is square, but it may be rectangular. Even in that case, by arranging the connection terminal region 4 so that the long side of the connection terminal region 4 is parallel to one of the diagonal lines of the rectangular semiconductor substrate, the same effect as the present embodiment can be obtained. .
　なお、本実施形態では、接続端子領域４を長方形状とし、その長方形状の接続端子領域４内に接続端子５を二次元マトリクス状に配列する例としたが、これに限られるものではない。図８Ａ及び図８Ｂに、本実施形態に適用可能な接続端子領域の他の例を示す。 In the present embodiment, the connection terminal region 4 has a rectangular shape, and the connection terminals 5 are arranged in a two-dimensional matrix in the rectangular connection terminal region 4. However, the present invention is not limited to this. FIG. 8A and FIG. 8B show other examples of connection terminal regions applicable to this embodiment.
　図８Ａは、複数の接続端子５が配列される接続端子領域１５の形状を、一方の方向に延在する多角形状とした例である。この例では、特に、長軸方向に延在する２つの辺がジグザグ状に設けられている。そして、一方の方向に延在する多角形状の接続端子領域１５内に、接続端子５が設けられている。 FIG. 8A is an example in which the shape of the connection terminal region 15 in which the plurality of connection terminals 5 are arranged is a polygonal shape extending in one direction. In this example, in particular, two sides extending in the major axis direction are provided in a zigzag shape. And the connecting terminal 5 is provided in the polygonal connecting terminal area | region 15 extended in one direction.
　図８Ａに示すように、接続端子領域１５の辺をジグザグ状に設けることにより、接続端子領域５のジグザグ状の領域の凸部分にも接続端子５を配置することができるため、端子数をより多く設けることができる。 As shown in FIG. 8A, by providing the sides of the connection terminal area 15 in a zigzag shape, the connection terminals 5 can be arranged also on the convex portions of the zigzag area of the connection terminal area 5, so that the number of terminals can be increased. Many can be provided.
　図８Ｂは、長方形状の接続端子領域１６内に配列される接続端子５を、千鳥状に配置する例である。図８Ｂでは、図面の関係上、隣り合う接続端子５間の距離が、図８Ａのように、接続端子５を二次元マトリクス状に配列する例に比較して大きく図示されているが、実際には、接続端子５を千鳥状に配列することで、接続端子５間の距離を小さくすることができる。これにより、図８Ｂに示す例では、同じ面積内であれば、二次元マトリクス状に接続端子５を配列する例に比較して、接続端子５の数を増やすことができる。 FIG. 8B is an example in which the connection terminals 5 arranged in the rectangular connection terminal region 16 are arranged in a staggered manner. In FIG. 8B, the distance between the adjacent connection terminals 5 is shown to be larger than the example in which the connection terminals 5 are arranged in a two-dimensional matrix as shown in FIG. Since the connection terminals 5 are arranged in a staggered manner, the distance between the connection terminals 5 can be reduced. Accordingly, in the example shown in FIG. 8B, the number of connection terminals 5 can be increased as long as they are within the same area, compared to an example in which the connection terminals 5 are arranged in a two-dimensional matrix.
　以上のように、接続端子領域の形状は長方形状に限られるものではなく、一方の方向に延在する形状であれば、本実施形態と同様の効果を得ることができる。さらに、接続端子領域内に設けられる接続端子の配列についても、種々の変形が可能である。 As described above, the shape of the connection terminal region is not limited to the rectangular shape, and an effect similar to that of the present embodiment can be obtained as long as the shape extends in one direction. Furthermore, various modifications can be made to the arrangement of the connection terminals provided in the connection terminal region.
　また、本実施形態では、接続端子領域４は、第１半導体チップ２の中央部分に配置される例としたが、これに限られるものではない。接続端子領域が半導体チップの中央部分から多少ずれた位置に配置される場合でも、本実施形態と同様の効果を得ることができる。 In the present embodiment, the connection terminal region 4 is arranged in the central portion of the first semiconductor chip 2, but the present invention is not limited to this. Even when the connection terminal region is disposed at a position slightly deviated from the central portion of the semiconductor chip, the same effect as in the present embodiment can be obtained.
　〈２．第２の実施形態：接続端子領域の長辺が半導体基板の辺に対して傾いて配置された半導体チップを用いる例（その２）〉
　次に、本開示の第２の実施形態に係る半導体装置について説明する。図９は、本実施形態の半導体装置の概略構成図である。本実施形態の半導体装置２０は、第１半導体チップ２１及び第２半導体チップ２５の積層関係、及び、それぞれの接続端子領域２３，２７の構成が第１の実施形態のそれと異なる。したがって、図９において、図１に対応する部分には同一符号を付し、重複説明を省略する。 <2. Second Embodiment: Example (Part 2) Using a Semiconductor Chip Arranged with the Long Side of the Connection Terminal Region Inclined with respect to the Side of the Semiconductor Substrate>
Next, a semiconductor device according to the second embodiment of the present disclosure will be described. FIG. 9 is a schematic configuration diagram of the semiconductor device of the present embodiment. The semiconductor device 20 of this embodiment is different from that of the first embodiment in the stacking relationship between the first semiconductor chip 21 and the second semiconductor chip 25 and the configuration of the connection terminal regions 23 and 27. Therefore, in FIG. 9, the same reference numerals are given to the portions corresponding to FIG.
　図９に示すように、本実施形態の半導体装置２０は、第１半導体チップ２１と、第１半導体チップ２１に積層される第２半導体チップ２５とを有する。図１０Ａは、本実施形態に係る半導体装置２０を構成する第１半導体チップ２１の概略構成図であり、図１０Ｂは、本実施形態に係る半導体装置２０を構成する第２半導体チップ２５の概略構成図である。 As shown in FIG. 9, the semiconductor device 20 of the present embodiment includes a first semiconductor chip 21 and a second semiconductor chip 25 stacked on the first semiconductor chip 21. FIG. 10A is a schematic configuration diagram of the first semiconductor chip 21 configuring the semiconductor device 20 according to the present embodiment, and FIG. 10B is a schematic configuration of the second semiconductor chip 25 configuring the semiconductor device 20 according to the present embodiment. FIG.
　［２－１．第１半導体チップの構成］
　まず、本実施形態の半導体装置２０を構成する第１半導体チップ２１について説明する。図１０Ａに示すように、本実施形態の第１半導体チップ２１は、外形が四角形状（図１０Ａでは正方形状）の半導体基板３で構成され、図示を省略するが、半導体基板３の表面には所望の回路を構成する配線層が設けられている。また、第１半導体チップ２１を構成する半導体基板３の辺の長さは、後述する第２半導体チップ２５を構成する半導体基板７の辺の長さよりも小さく設定されている。 [2-1. Configuration of first semiconductor chip]
First, the first semiconductor chip 21 constituting the semiconductor device 20 of this embodiment will be described. As shown in FIG. 10A, the first semiconductor chip 21 of the present embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 10A). A wiring layer constituting a desired circuit is provided. Further, the length of the side of the semiconductor substrate 3 constituting the first semiconductor chip 21 is set smaller than the length of the side of the semiconductor substrate 7 constituting the second semiconductor chip 25 described later.
　また、第１半導体チップ２１の中央部分には、複数の接続端子２４を有する接続端子領域２３が設けられている。接続端子２４は、半導体基板３を貫通する貫通孔に導電材料が埋め込まれた、いわゆるスルーシリコンビアである。この接続端子２４により、第１半導体チップ２１に設けられた回路が、第１半導体チップ２１に積層される第２半導体チップ２５等、他の半導体チップの回路と電気的に接続される。 Further, a connection terminal region 23 having a plurality of connection terminals 24 is provided in the central portion of the first semiconductor chip 21. The connection terminal 24 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3. With this connection terminal 24, a circuit provided in the first semiconductor chip 21 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 25 stacked on the first semiconductor chip 21.
　複数の接続端子２４が設けられる接続端子領域２３は、第１接続端子領域２３ａと第２接続端子領域２３ｂとで構成されている。第１接続端子領域２３ａ及び第２接続端子領域２３ｂの半導体基板３の面におけるそれぞれの形状は長方形である。そして、接続端子領域２３では、それらの第１接続端子領域２３ａ及び第２接続端子領域２３ｂがそれぞれの長辺方向に隣り合って配置されている。 The connection terminal area 23 provided with a plurality of connection terminals 24 is composed of a first connection terminal area 23a and a second connection terminal area 23b. Each shape in the surface of the semiconductor substrate 3 of the 1st connection terminal area | region 23a and the 2nd connection terminal area | region 23b is a rectangle. In the connection terminal region 23, the first connection terminal region 23a and the second connection terminal region 23b are arranged adjacent to each other in the long side direction.
　第１接続端子領域２３ａ内、及び、第２接続端子領域２３ｂ内においては、それぞれ、複数の接続端子２４が２次元状にアレイ配列されている。そして、第１接続端子領域２３ａ及び第２接続端子領域２３ｂのそれぞれの長辺方向にはｘ個（ｘは任意の数）の接続端子２４が配列され、それぞれの短辺方向にはｙ個（ｙはｘよりも小さい任意の数）の接続端子２４が配列されている。すなわち、第１接続端子領域２３ａ及び第２接続端子領域２３ｂ内において、複数の接続端子２４は、それぞれ、ｘ列×ｙ行の形態で配列される。また、接続端子領域２３の各辺は半導体基板３の対角線の長さよりも十分に小さい。 In the first connection terminal region 23a and the second connection terminal region 23b, a plurality of connection terminals 24 are arrayed in a two-dimensional array. Then, x (x is an arbitrary number) connection terminals 24 are arranged in the long side direction of each of the first connection terminal region 23a and the second connection terminal region 23b, and y ( (wherein y is an arbitrary number smaller than x) of connecting terminals 24 are arranged. That is, in the first connection terminal region 23a and the second connection terminal region 23b, the plurality of connection terminals 24 are each arranged in the form of x columns × y rows. Each side of the connection terminal region 23 is sufficiently smaller than the length of the diagonal line of the semiconductor substrate 3.
　そして、本実施形態の第１半導体チップ２１では、接続端子領域２３は、正方形状の半導体基板３の一方の対角線（図１０Ａでは左上角及び右下角間の対角線）が、接続端子領域２３の長辺と平行となるように配置されている。さらに、接続端子領域２３は、半導体基板３の中心が接続端子領域２３の中心と一致するように配置されている。すなわち、本実施形態における第１半導体チップ２１では、接続端子領域２３の長辺が半導体基板３の辺に対して約４５度傾くように配置されている。 In the first semiconductor chip 21 of the present embodiment, the connection terminal region 23 has one diagonal line of the square semiconductor substrate 3 (the diagonal line between the upper left corner and the lower right corner in FIG. 10A) as the length of the connection terminal region 23. It is arranged so as to be parallel to the side. Further, the connection terminal region 23 is arranged so that the center of the semiconductor substrate 3 coincides with the center of the connection terminal region 23. In other words, in the first semiconductor chip 21 in the present embodiment, the long side of the connection terminal region 23 is disposed so as to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 3.
　［２－２．第２半導体チップの構成］
　次に、本実施形態の半導体装置２０を構成する第２半導体チップ２５について説明する。図１０Ｂに示すように、第２半導体チップ２５は、外形が四角形状（図１０Ｂでは正方形状）の半導体基板７で構成され、図示を省略するが、半導体基板７の表面には所望の回路を構成する配線層が設けられている。また、本実施形態では、第２半導体チップ２５の一辺の長さは、第１半導体チップ２１のそれよりも長く構成されている。 [2-2. Configuration of second semiconductor chip]
Next, the second semiconductor chip 25 constituting the semiconductor device 20 of this embodiment will be described. As shown in FIG. 10B, the second semiconductor chip 25 is configured by a semiconductor substrate 7 having an outer shape of a quadrangle (a square shape in FIG. 10B). A wiring layer to be configured is provided. In the present embodiment, the length of one side of the second semiconductor chip 25 is longer than that of the first semiconductor chip 21.
　また、第２半導体チップ２５の中央部分には、複数の接続端子２８を有する接続端子領域２７が設けられている。接続端子２８は、半導体基板７を貫通する貫通孔に導電材料が埋め込まれた、いわゆるスルーシリコンビアである。この接続端子２８により、第２半導体チップ２５に設けられた回路が、第２半導体チップ２５に積層される第１半導体チップ２１等、他の半導体チップの回路と電気的に接続される。 Further, a connection terminal region 27 having a plurality of connection terminals 28 is provided in the central portion of the second semiconductor chip 25. The connection terminal 28 is a so-called through silicon via in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 7. With this connection terminal 28, a circuit provided in the second semiconductor chip 25 is electrically connected to a circuit of another semiconductor chip such as the first semiconductor chip 21 stacked on the second semiconductor chip 25.
　複数の接続端子２８が設けられる接続端子領域２７は、第１接続端子領域２７ａと第２接続端子領域２７ｂとで構成されている。第１接続端子領域２７ａ及び第２接続端子領域２７ｂの半導体基板７の面におけるそれぞれの形状は長方形である。そして、接続端子領域２７では、それらの第１接続端子領域２７ａ及び第２接続端子領域２７ｂがそれぞれの長辺方向に隣り合って配置されている。 The connection terminal area 27 in which the plurality of connection terminals 28 are provided includes a first connection terminal area 27a and a second connection terminal area 27b. Each shape in the surface of the semiconductor substrate 7 of the 1st connection terminal area | region 27a and the 2nd connection terminal area | region 27b is a rectangle. In the connection terminal region 27, the first connection terminal region 27a and the second connection terminal region 27b are arranged adjacent to each other in the long side direction.
　第１接続端子領域２７ａ内、及び、第２接続端子領域２７ｂ内においては、それぞれ、複数の接続端子２８が２次元状にアレイ配列されている。そして、第１接続端子領域２７ａ及び第２接続端子領域２７ｂのそれぞれの長辺方向にはｘ個（ｘは任意の数）の接続端子２８が配列され、それぞれの短辺方向にはｙ個（ｙはｘよりも小さい任意の数）の接続端子２８が配列されている。すなわち、第１接続端子領域２７ａ及び第２接続端子領域２７ｂ内において、複数の接続端子２８は、それぞれ、ｘ列×ｙ行の形態で配列される。また、接続端子領域２７の各辺は半導体基板７の対角線の長さよりも十分に小さい。 In the first connection terminal area 27a and the second connection terminal area 27b, a plurality of connection terminals 28 are arrayed in a two-dimensional array. Then, x (x is an arbitrary number) connection terminals 28 are arranged in the long side direction of each of the first connection terminal region 27a and the second connection terminal region 27b, and y ( (wherein y is an arbitrary number smaller than x)) connecting terminals 28 are arranged. That is, in the first connection terminal region 27a and the second connection terminal region 27b, the plurality of connection terminals 28 are each arranged in the form of x columns × y rows. Further, each side of the connection terminal region 27 is sufficiently smaller than the diagonal length of the semiconductor substrate 7.
　そして、本実施形態の第２半導体チップ２５では、接続端子領域２７は、正方形状の半導体基板７の一方の対角線（図１０Ｂでは左上角及び右下角間の対角線）が、接続端子領域２７の長辺と平行となるように配置されている。さらに、接続端子領域２７は、半導体基板７の中心が接続端子領域２７の中心と一致するように配置されている。すなわち、本実施形態における第２半導体チップ２５では、接続端子領域２７の長辺が半導体基板７の辺に対して約４５度傾くように配置されている。 In the second semiconductor chip 25 of the present embodiment, the connection terminal region 27 has one diagonal line of the square semiconductor substrate 7 (the diagonal line between the upper left corner and the lower right corner in FIG. 10B) as the length of the connection terminal region 27. It is arranged so as to be parallel to the side. Further, the connection terminal region 27 is arranged so that the center of the semiconductor substrate 7 coincides with the center of the connection terminal region 27. That is, in the second semiconductor chip 25 in the present embodiment, the long side of the connection terminal region 27 is arranged to be inclined by about 45 degrees with respect to the side of the semiconductor substrate 7.
　そして、本実施形態の半導体装置２０では、第１半導体チップ２１と第２半導体チップ２５とは、それぞれの接続端子領域２３，２７が両者の界面で一致するように互いに積層される。そして、それぞれの接続端子領域２３，２７に設けられた接続端子２４，２８を介して、第１半導体チップ２１が第２半導体チップ２５と電気的に接続される。 In the semiconductor device 20 of the present embodiment, the first semiconductor chip 21 and the second semiconductor chip 25 are stacked on each other so that the connection terminal regions 23 and 27 coincide with each other at the interface between them. Then, the first semiconductor chip 21 is electrically connected to the second semiconductor chip 25 through the connection terminals 24 and 28 provided in the connection terminal regions 23 and 27, respectively.
　このように、本実施形態では、積層する第１半導体チップ２１と第２半導体チップ２５との両方において、接続端子領域２３，２７の外形を、それぞれ半導体基板３，７に対して斜めに（対角線上に）配置する。これにより、第１半導体チップ２１及び第２半導体チップでは、それぞれ、半導体基板３，７の面積を縮小しながらも、接続端子領域２３，２７の短辺の外側に位置する基板領域の面積を確保することができる。その他、本実施形態においても、第１の実施形態と同様の効果を得ることができる。 As described above, in this embodiment, in both the first semiconductor chip 21 and the second semiconductor chip 25 to be stacked, the outer shapes of the connection terminal regions 23 and 27 are oblique to the semiconductor substrates 3 and 7 (diagonal lines). (On top). Thereby, in the first semiconductor chip 21 and the second semiconductor chip, the area of the substrate region located outside the short sides of the connection terminal regions 23 and 27 is secured while reducing the area of the semiconductor substrates 3 and 7, respectively. can do. In addition, also in this embodiment, the same effect as the first embodiment can be obtained.
　〈３．第３の実施形態：四角形状の半導体基板の頂点を切り取られた半導体チップを用いる例〉
　ところで、第１の実施形態の半導体装置１のように、第１半導体チップ２をベースとなる第２半導体チップ６に対して回転させて積層させる場合、第１半導体チップ２の面積が大きくなると、第１半導体チップ２の角部が第２半導体チップ６からはみ出る場合がある。 <3. Third Embodiment: Example Using Semiconductor Chip Cut from Vertex of Rectangular Semiconductor Substrate>
By the way, when the first semiconductor chip 2 is rotated and stacked with respect to the second semiconductor chip 6 serving as a base as in the semiconductor device 1 of the first embodiment, when the area of the first semiconductor chip 2 increases, The corner of the first semiconductor chip 2 may protrude from the second semiconductor chip 6 in some cases.
　図１１に、第１半導体チップ３１ａが第２半導体チップ６と積層された半導体装置３０ａにおいて、第１半導体チップ３１ａの角部が第２半導体チップ６からはみ出た場合の概略構成を示す。図１１において、図１に対応する部分には同一符号を付し重複説明を省略する。 FIG. 11 shows a schematic configuration when a corner portion of the first semiconductor chip 31a protrudes from the second semiconductor chip 6 in the semiconductor device 30a in which the first semiconductor chip 31a is stacked with the second semiconductor chip 6. In FIG. 11, parts corresponding to those in FIG.
　図１１に示すように、第１半導体チップ３１ａは、外形が四角形状（図１１では正方形状）の半導体基板３２ａで構成され、図示を省略するが、半導体基板３２ａの表面には所望の回路を構成する配線層が設けられている。また、第１半導体チップ３１ａを構成する半導体基板３２ａの対角方向の長さは、第２半導体チップ６を構成する半導体基板７の一辺の長さよりも長く設定されている。 As shown in FIG. 11, the first semiconductor chip 31 a is configured by a semiconductor substrate 32 a having a quadrangular outer shape (a square shape in FIG. 11), and although not illustrated, a desired circuit is provided on the surface of the semiconductor substrate 32 a. A wiring layer to be configured is provided. Further, the length of the semiconductor substrate 32 a constituting the first semiconductor chip 31 a in the diagonal direction is set to be longer than the length of one side of the semiconductor substrate 7 constituting the second semiconductor chip 6.
　図１１に示す半導体装置３０ａでは、第１半導体チップ３１ａの半導体基板３２ａの対角方向の幅が、第２半導体チップ６の半導体基板７の一辺の長さよりも長い。このため、第１半導体チップ３１ａと第２半導体チップ６とをそれぞれの接続端子領域３３，８が両者の界面で互いに一致するように積層した場合、第１半導体チップ３１ａの頂点領域の角部が、第２半導体チップ６からはみ出る。 In the semiconductor device 30a shown in FIG. 11, the width in the diagonal direction of the semiconductor substrate 32a of the first semiconductor chip 31a is longer than the length of one side of the semiconductor substrate 7 of the second semiconductor chip 6. For this reason, when the first semiconductor chip 31a and the second semiconductor chip 6 are stacked such that the connection terminal regions 33 and 8 coincide with each other at the interface between the first semiconductor chip 31a and the second semiconductor chip 6, the corners of the apex region of the first semiconductor chip 31a are Protrudes from the second semiconductor chip 6.
　以下に、本開示の第３の実施形態として、第１半導体チップが第２半導体チップからはみ出ることなく、第２半導体チップ上に積層される例を説明する。 Hereinafter, an example in which the first semiconductor chip is stacked on the second semiconductor chip without protruding from the second semiconductor chip will be described as a third embodiment of the present disclosure.
　図１２は、本開示の第３の実施形態に係る半導体装置の概略構成図である。本実施形態の半導体装置３０では、第１半導体チップ３１の構成が、図１１に示した半導体装置３０ａの第１半導体チップ３１ａと一部異なる。したがって、図１２において、図１１に対応する部分には同一符号を付し、重複説明を省略する。 FIG. 12 is a schematic configuration diagram of a semiconductor device according to the third embodiment of the present disclosure. In the semiconductor device 30 of this embodiment, the configuration of the first semiconductor chip 31 is partially different from the first semiconductor chip 31a of the semiconductor device 30a shown in FIG. Therefore, in FIG. 12, the same reference numerals are given to the portions corresponding to those in FIG.
　図１２に示すように、本実施形態の半導体装置３０は、第１半導体チップ３１と、第１半導体チップ３１に積層される第２半導体チップ６とを有する。 As shown in FIG. 12, the semiconductor device 30 of this embodiment includes a first semiconductor chip 31 and a second semiconductor chip 6 stacked on the first semiconductor chip 31.
　第１半導体チップ３１は、外形が八角形状の半導体基板３２で構成され、図示を省略するが、半導体基板３２の表面には所望の回路を構成する配線層が設けられている。また、第１半導体チップ３１を構成する半導体基板３２は、第１半導体チップ３１を第２半導体チップ６上に積層したときに、第１半導体チップ３１が第２半導体チップ６を構成する半導体基板７からはみ出さない大きさに設定されている。この第１半導体チップ３１は、図１１に示した第１半導体チップ３１ａの第２半導体チップ６からはみ出た頂点部分（角部）を切り取った形状の半導体チップである。
The first semiconductor chip 31 is composed of a semiconductor substrate 32 having an octagonal outer shape. Although not shown, a wiring layer constituting a desired circuit is provided on the surface of the semiconductor substrate 32. The semiconductor substrate 32 constituting the first semiconductor chip 31 is the semiconductor substrate 7 constituting the second semiconductor chip 6 when the first semiconductor chip 31 is stacked on the second semiconductor chip 6. The size is set so as not to protrude. The first semiconductor chip 31 is a semiconductor chip having a shape obtained by cutting off the apex portion (corner portion) protruding from the second semiconductor chip 6 of the first semiconductor chip 31a shown in FIG.
　図１１に示すように、第１半導体チップ３１ａの頂点部分が第２半導体チップ６からはみ出る場合には、その第１半導体チップ３１ａの頂点部分に回路や配線等を設けないことにより、必要に応じて切り取ることができる。本実施形態の半導体装置３０のように、第１半導体チップ３１を、余分な頂点部分を切り落とした半導体基板３２で構成することにより、チップ面積をより小さくすることができる。その他、本実施形態においても第１の実施形態と同様の効果を得ることができる。 As shown in FIG. 11, when the apex portion of the first semiconductor chip 31 a protrudes from the second semiconductor chip 6, if necessary, by not providing a circuit, wiring, or the like at the apex portion of the first semiconductor chip 31 a. Can be cut off. As in the semiconductor device 30 of the present embodiment, the first semiconductor chip 31 is configured by the semiconductor substrate 32 from which excess vertex portions are cut off, whereby the chip area can be further reduced. In addition, the same effects as those of the first embodiment can be obtained in this embodiment.
　なお、本実施形態では、第１半導体チップ３１の外形は八角形状としたが、第１半導体チップ３１の形状は、第２半導体チップ６からはみ出ない形状であればよいため、必ずしも八角形状である必要はない。例えば、図１１において、第２半導体チップ６が長方形状であり、第１半導体チップ３１ａの対向する一対の頂点部分のみが第２半導体チップ６からはみ出るような場合には、第１半導体チップを６角形状とすることで、本実施形態と同様の効果をえることができる。 In the present embodiment, the outer shape of the first semiconductor chip 31 is an octagonal shape, but the shape of the first semiconductor chip 31 may be an octagonal shape as long as it does not protrude from the second semiconductor chip 6. There is no need. For example, in FIG. 11, when the second semiconductor chip 6 has a rectangular shape and only a pair of opposing apexes of the first semiconductor chip 31 a protrude from the second semiconductor chip 6, the first semiconductor chip 6 By adopting a square shape, the same effect as in the present embodiment can be obtained.
　〈４．第４の実施形態：接続端子領域の長辺方向の端部が三角形状である半導体チップを用いる例〉
　次に、本開示の第４の実施形態に係る半導体装置について説明する。図１３Ａは、本実施形態の半導体装置４０の概略構成図であり、図１３Ｂは、要部の拡大図である。本実施形態の半導体装置４０は、第１半導体チップ４３における接続端子領域４１の構成が、第１の実施形態における第１半導体チップ２のそれと異なる。したがって、図１３Ａにおいて、図１に対応する部分には同一符号を付し、重複説明を省略する。 <4. Fourth Embodiment: Example of Using a Semiconductor Chip whose End in the Long Side Direction of the Connection Terminal Area is Triangular>
Next, a semiconductor device according to the fourth embodiment of the present disclosure will be described. FIG. 13A is a schematic configuration diagram of the semiconductor device 40 of the present embodiment, and FIG. 13B is an enlarged view of a main part. In the semiconductor device 40 of this embodiment, the configuration of the connection terminal region 41 in the first semiconductor chip 43 is different from that of the first semiconductor chip 2 in the first embodiment. Therefore, in FIG. 13A, the same reference numerals are given to the portions corresponding to FIG.
　図１３Ａに示すように、本実施形態の第１半導体チップ４３は、外形が四角形状（図１３Ａでは正方形状）の半導体基板３で構成され、第１半導体チップ４３の中央部分には、複数の接続端子４２を有する接続端子領域４１が設けられている。接続端子４２は、半導体基板３を貫通する貫通孔に導電材料が埋め込まれた、いわゆるスルーシリコンビア（ＴＳＶ）である。この接続端子４２により、第１半導体チップ４３に設けられた回路が、第１半導体チップ４３に積層される第２半導体チップ６等、他の半導体チップの回路と電気的に接続される。 As shown in FIG. 13A, the first semiconductor chip 43 of this embodiment is configured by a semiconductor substrate 3 having an outer shape of a square shape (a square shape in FIG. 13A). A connection terminal area 41 having a connection terminal 42 is provided. The connection terminal 42 is a so-called through silicon via (TSV) in which a conductive material is embedded in a through hole penetrating the semiconductor substrate 3. With this connection terminal 42, a circuit provided in the first semiconductor chip 43 is electrically connected to a circuit of another semiconductor chip such as the second semiconductor chip 6 stacked on the first semiconductor chip 43.
　図１３Ｂに示すように、本実施形態の第１半導体チップ４３では、接続端子領域４１の形状は六角形であり、そのうち一組の対向する頂点間の対角線に沿って延在した形状を有し、その頂点の角度は、約９０度に形成されている。すなわち、接続端子領域４１は、図１に示した外形が長方形状の接続端子領域４内に配列された接続端子５のうち、各短辺付近に位置する接続端子５のうち、頂点に対応する接続端子５のみを残した形状である。 As shown in FIG. 13B, in the first semiconductor chip 43 of the present embodiment, the shape of the connection terminal region 41 is a hexagon, and has a shape extending along a diagonal line between a pair of opposing vertices. The angle of the vertex is formed at about 90 degrees. That is, the connection terminal area 41 corresponds to the apex among the connection terminals 5 located near each short side among the connection terminals 5 arranged in the connection terminal area 4 having the rectangular outer shape shown in FIG. The shape is such that only the connection terminal 5 remains.
　そして、本実施形態の第１半導体チップ４３では、接続端子領域４１は、正方形状の半導体基板３の一方の対角線（図１３では左右方向の対角線）が、接続端子領域４１の長辺と平行となるように配置されている。さらに、接続端子領域４１は、半導体基板３の中心が接続端子領域４１の中心と一致するように、接続端子領域４１が配置されている。 In the first semiconductor chip 43 of the present embodiment, the connection terminal region 41 has one diagonal line of the square semiconductor substrate 3 (the diagonal line in the horizontal direction in FIG. 13) parallel to the long side of the connection terminal region 41. It is arranged to be. Further, the connection terminal region 41 is arranged so that the center of the semiconductor substrate 3 coincides with the center of the connection terminal region 41.
　本実施形態では、接続端子領域４１の頂点を含む端部の形状を、頂角がほぼ９０度の三角形状とすることで、図１３Ａに示すように、接続端子領域４１の端部から半導体基板３の対応する辺までの距離ｗ１，ｗ２をほぼ一定とすることができる。これにより、接続端子４２を迂回するように設けられる配線や、回路の配置を効率よく行うことができる。その他、本実施形態においても、第１の実施形態と同様の効果を得ることができる。 In the present embodiment, the shape of the end portion including the apex of the connection terminal region 41 is a triangular shape having an apex angle of approximately 90 degrees, so that the semiconductor substrate extends from the end portion of the connection terminal region 41 as shown in FIG. 13A. The distances w1 and w2 to the corresponding side of 3 can be made substantially constant. As a result, it is possible to efficiently arrange the wiring and the circuit provided so as to bypass the connection terminal 42. In addition, also in this embodiment, the same effect as the first embodiment can be obtained.
　図１４に、第１半導体チップ４３に設けられる接続端子領域４１の他の例を示す。図１４に示すように、長方形状の領域内に配列された接続端子４２のうち、角部付近に位置する接続端子４２ａをチップ間の接続に用いないようにしてもよい。この場合にも、実際に接続に用いられる接続端子領域４１の頂点を含む端部形状を三角形状とすることができる。接続に用いない接続端子４２ａは、貫通孔に導電材料を埋め込まないことで構成することができる。図１４に示す構成とした場合でも、本実施形態と同様の効果を得ることができる。 FIG. 14 shows another example of the connection terminal region 41 provided in the first semiconductor chip 43. As shown in FIG. 14, out of the connection terminals 42 arranged in the rectangular region, the connection terminal 42a located near the corner may not be used for the connection between the chips. Also in this case, the end shape including the apex of the connection terminal region 41 actually used for connection can be a triangular shape. The connection terminal 42a not used for connection can be configured by not burying a conductive material in the through hole. Even when the configuration shown in FIG. 14 is adopted, the same effect as that of the present embodiment can be obtained.
　本実施形態では、接続端子領域４１が、一組の対向する頂点間の対角線に沿って延在した六角形状である例を説明したが、本実施形態の効果を発揮できる例はこれに限られるものではない。接続端子領域が、一方の方向に延在する多角形状であり、接続端子領域の短軸方向の幅が接続端子領域の長軸方向の端部側にかけて小さくなるように形成されている場合においては、本実施形態と同様の効果を得ることができる。 In the present embodiment, the example in which the connection terminal region 41 has a hexagonal shape extending along a diagonal line between a pair of opposing vertices has been described. However, examples in which the effect of the present embodiment can be exhibited are limited thereto. It is not a thing. In the case where the connection terminal region has a polygonal shape extending in one direction and the width in the short axis direction of the connection terminal region is formed so as to decrease toward the end side in the long axis direction of the connection terminal region. The effect similar to this embodiment can be acquired.
　以上、第１～第４の実施形態では、接続端子領域を、その長辺が、半導体基板の一方の対角線と平行になるように半導体基板に設ける構成としたが、これに限られるものではない。接続端子領域の長辺が、半導体基板の所定の辺に対して０度より大きく９０度よりも小さい角度で傾くように接続端子領域を半導体基板上に設けることで、第１の実施形態と同様の効果を得ることができる。第１～第４の実施形態のように、接続端子領域を、その長辺が、半導体基板の一方の対角線と平行になるように設けた場合には、接続端子領域の端辺の外側に位置する基板領域の面積をより広く確保することができる。 As described above, in the first to fourth embodiments, the connection terminal region is provided in the semiconductor substrate so that the long side thereof is parallel to one diagonal line of the semiconductor substrate. However, the present invention is not limited to this. . Similar to the first embodiment, the connection terminal region is provided on the semiconductor substrate so that the long side of the connection terminal region is inclined at an angle larger than 0 degree and smaller than 90 degrees with respect to a predetermined side of the semiconductor substrate. The effect of can be obtained. As in the first to fourth embodiments, when the connection terminal region is provided so that its long side is parallel to one diagonal line of the semiconductor substrate, the connection terminal region is positioned outside the end side of the connection terminal region. It is possible to secure a wider area of the substrate region.
　第１～第４の実施形態に係る半導体装置は、第１半導体チップと第２半導体チップとを積層した構造としたが、２つ以上の複数の半導体チップを積層する構造を有する半導体装置にも本開示の技術を適用することができる。その場合は、積層される半導体チップの少なくとも１つを、第１～第４の実施形態における第１半導体チップの構成とすることで、第１～第４の実施形態と同様の効果を得ることができる。 The semiconductor device according to the first to fourth embodiments has a structure in which the first semiconductor chip and the second semiconductor chip are stacked. However, the semiconductor device also has a structure in which two or more semiconductor chips are stacked. The technology of the present disclosure can be applied. In that case, at least one of the stacked semiconductor chips has the configuration of the first semiconductor chip in the first to fourth embodiments, so that the same effect as in the first to fourth embodiments can be obtained. Can do.
　以上、第１～第４の実施形態に本開示の実施形態を示したが、本開示は上述の例に限られるものではなく、趣旨を逸脱しない範囲内において種々の変更が可能である。また、第１～第４の実施形態に係る構成を組み合わせて構成することも可能である。 As mentioned above, although the embodiments of the present disclosure have been shown in the first to fourth embodiments, the present disclosure is not limited to the above-described examples, and various modifications can be made without departing from the spirit of the present disclosure. It is also possible to combine the configurations according to the first to fourth embodiments.
　また、以上で説明した半導体装置は、撮像装置、コンピュータ、画像表示装置等、様々な電子機器に適用することができ、本開示の半導体チップが組み込まれた半導体装置を用いることで、駆動速度の向上が図られる。 In addition, the semiconductor device described above can be applied to various electronic devices such as an imaging device, a computer, and an image display device. By using the semiconductor device in which the semiconductor chip of the present disclosure is incorporated, the driving speed can be reduced. Improvement is achieved.
　なお、本開示は、以下のような構成を取ることもできる。
（１）
　所望の回路を有する半導体基板と、前記半導体基板に設けられた貫通孔に導電材料が埋め込まれた複数の接続端子を有し、前記半導体基板に配置された接続端子領域とを含み、　前記接続端子領域は、所定方向に延在して形成され、その長辺が前記半導体基板の所定の辺に対して０度よりも大きく９０度よりも小さい角度で傾くように配置された半導体チップ
　を備える半導体装置。
（２）
　前記接続端子領域は、長方形状である
　（１）に記載の半導体装置。
（３）
　前記半導体基板は、正方形状又は長方形状であり、
　前記接続端子領域は、前記接続端子領域の長辺が前記半導体基板の一方の対角線に平行になるように、前記半導体基板に配置されている
　（１）又は（２）に記載の半導体装置。
（４）
　前記半導体チップに積層され、前記接続端子を介して前記半導体チップと電気的に接続された他の半導体チップを備える
　（１）～（３）のいずれかに記載の半導体装置。
（５）
　前記半導体チップと前記他の半導体チップとは、前記半導体チップの外形の辺が、前記他の半導体チップの外形の辺に対して傾くように積層されている
　（１）～（４）のいずれかに記載の半導体装置。
（６）
　前記接続端子領域は一方の方向に延在する多角形状であり、前記接続端子領域の短軸方向の幅が前記接続端子領域の長軸方向の端部側にかけて小さくなるように形成されている　（１）～（５）のいずれかに記載の半導体装置。
（７）
　前記半導体チップと前記他の半導体チップとは、前記半導体チップの外形の辺が、前記他の半導体チップの外形の辺に対して平行となるように積層されている
　（１）～（４）のいずれかに記載の半導体装置。
（８）
　所望の回路を有する半導体基板と、前記半導体基板に設けられた貫通孔に導電材料が埋め込まれた複数の接続端子を有し、前記半導体基板に配置された接続端子領域とを含み、　前記接続端子領域は、所定方向に延在して形成され、その長辺が前記半導体基板の所定の辺に対して０度よりも大きく９０度よりも小さい角度で傾くように配置された半導体チップを有する半導体装置
　を備える電子機器。 In addition, this indication can also take the following structures.
(1)
A semiconductor substrate having a desired circuit; and a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate, and a connection terminal region disposed in the semiconductor substrate, the connection terminals The semiconductor is provided with a semiconductor chip which is formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees apparatus.
(2)
The semiconductor device according to (1), wherein the connection terminal region has a rectangular shape.
(3)
The semiconductor substrate is square or rectangular,
The semiconductor device according to (1) or (2), wherein the connection terminal region is arranged on the semiconductor substrate such that a long side of the connection terminal region is parallel to one diagonal line of the semiconductor substrate.
(4)
The semiconductor device according to any one of (1) to (3), further including another semiconductor chip stacked on the semiconductor chip and electrically connected to the semiconductor chip via the connection terminal.
(5)
The semiconductor chip and the other semiconductor chip are stacked such that the outer side of the semiconductor chip is tilted with respect to the outer side of the other semiconductor chip (1) to (4) A semiconductor device according to 1.
(6)
The connection terminal region has a polygonal shape extending in one direction, and is formed so that the width in the minor axis direction of the connection terminal region decreases toward the end side in the major axis direction of the connection terminal region. 1) The semiconductor device according to any one of (5).
(7)
The semiconductor chip and the other semiconductor chip are stacked so that the outer side of the semiconductor chip is parallel to the outer side of the other semiconductor chip. (1) to (4) The semiconductor device according to any one of the above.
(8)
A semiconductor substrate having a desired circuit; and a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate, and a connection terminal region disposed in the semiconductor substrate, the connection terminals The semiconductor includes a semiconductor chip formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees Electronic equipment equipped with the device.
　１，１０，２０，３０，４０・・・半導体装置、２，１１，２１，３１，４３・・・第１半導体チップ、３，７，１２，３２・・・半導体基板、４，８，１３，２３，２７，３３，４１・・・接続端子領域、５，９，１４，２４，２８，３４，４２・・・接続端子、６，２５・・・第２半導体チップ DESCRIPTION OF SYMBOLS 1,10,20,30,40 ... Semiconductor device, 2, 11, 21, 31, 43 ... 1st semiconductor chip, 3, 7, 12, 32 ... Semiconductor substrate, 4, 8, 13 , 23, 27, 33, 41 ... connection terminal region, 5, 9, 14, 24, 28, 34, 42 ... connection terminals, 6, 25 ... second semiconductor chip.

Claims (8)

  1. 　所望の回路を有する半導体基板と、前記半導体基板に設けられた貫通孔に導電材料が埋め込まれた複数の接続端子を有し、前記半導体基板に配置された接続端子領域とを含み、　前記接続端子領域は、所定方向に延在して形成され、その長辺が前記半導体基板の所定の辺に対して０度よりも大きく９０度よりも小さい角度で傾くように配置された半導体チップ
    　を備える半導体装置。     A semiconductor substrate having a desired circuit; and a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate, and a connection terminal region disposed in the semiconductor substrate, the connection terminals The semiconductor is provided with a semiconductor chip which is formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees apparatus.
  2. 　前記接続端子領域は、長方形状である
    　請求項１に記載の半導体装置。     The semiconductor device according to claim 1, wherein the connection terminal region has a rectangular shape.
  3. 　前記半導体基板は、正方形状又は長方形状であり、
    　前記接続端子領域は、前記接続端子領域の長辺が前記半導体基板の一方の対角線に平行になるように、前記半導体基板に配置されている
    　請求項２に記載の半導体装置。     The semiconductor substrate is square or rectangular,
    The semiconductor device according to claim 2, wherein the connection terminal region is arranged on the semiconductor substrate such that a long side of the connection terminal region is parallel to one diagonal line of the semiconductor substrate.
  4. 　前記半導体チップに積層され、前記接続端子を介して前記半導体チップと電気的に接続された他の半導体チップを備える
    　請求項３に記載の半導体装置。     The semiconductor device according to claim 3, further comprising another semiconductor chip stacked on the semiconductor chip and electrically connected to the semiconductor chip via the connection terminal.
  5. 　前記半導体チップと前記他の半導体チップとは、前記半導体チップの外形の辺が、前記他の半導体チップの外形の辺に対して傾くように積層されている
    　請求項４に記載の半導体装置。     The semiconductor device according to claim 4, wherein the semiconductor chip and the other semiconductor chip are stacked such that an outer side of the semiconductor chip is inclined with respect to an outer side of the other semiconductor chip.
  6. 　前記接続端子領域は一方の方向に延在する多角形状であり、前記接続端子領域の短軸方向の幅が前記接続端子領域の長軸方向の端部側にかけて小さくなるように形成されている　請求項１に記載の半導体装置。 The connection terminal region has a polygonal shape extending in one direction, and is formed so that the width in the short axis direction of the connection terminal region decreases toward the end of the connection terminal region in the long axis direction. Item 14. The semiconductor device according to Item 1.
  7. 　前記半導体チップと前記他の半導体チップとは、前記半導体チップの外形の辺が、前記他の半導体チップの外形の辺に対して平行となるように積層されている
    　請求項４に記載の半導体装置。     The semiconductor device according to claim 4, wherein the semiconductor chip and the other semiconductor chip are stacked so that an outer side of the semiconductor chip is parallel to an outer side of the other semiconductor chip. .
  8. 　所望の回路を有する半導体基板と、前記半導体基板に設けられた貫通孔に導電材料が埋め込まれた複数の接続端子を有し、前記半導体基板に配置された接続端子領域とを含み、　前記接続端子領域は、所定方向に延在して形成され、その長辺が前記半導体基板の所定の辺に対して０度よりも大きく９０度よりも小さい角度で傾くように配置された半導体チップを有する半導体装置
    　を備える電子機器。     A semiconductor substrate having a desired circuit; and a plurality of connection terminals in which a conductive material is embedded in a through hole provided in the semiconductor substrate, and a connection terminal region disposed in the semiconductor substrate, the connection terminals The semiconductor includes a semiconductor chip formed so as to extend in a predetermined direction and whose long side is inclined with respect to the predetermined side of the semiconductor substrate at an angle larger than 0 degree and smaller than 90 degrees Electronic equipment equipped with the device.
PCT/JP2013/068840 2012-08-13 2013-07-10 Semiconductor device and electronic device WO2014027535A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653272A (en) * 1992-07-28 1994-02-25 Nippon Steel Corp Semiconductor chip and tab-type semiconductor device
JP2010245267A (en) * 2009-04-06 2010-10-28 Mitsubishi Electric Corp Semiconductor device
JP2011166026A (en) * 2010-02-12 2011-08-25 Elpida Memory Inc Semiconductor device
JP2012119368A (en) * 2010-11-29 2012-06-21 Elpida Memory Inc Method for manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653272A (en) * 1992-07-28 1994-02-25 Nippon Steel Corp Semiconductor chip and tab-type semiconductor device
JP2010245267A (en) * 2009-04-06 2010-10-28 Mitsubishi Electric Corp Semiconductor device
JP2011166026A (en) * 2010-02-12 2011-08-25 Elpida Memory Inc Semiconductor device
JP2012119368A (en) * 2010-11-29 2012-06-21 Elpida Memory Inc Method for manufacturing semiconductor device

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