JP2007088329A - Multi-chip package semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-chip package semiconductor device that can manage the mount conditions of multiple semiconductor chips. <P>SOLUTION: This multi-chip package semiconductor device is mounted on a module substrate 10, a first semiconductor chip 15, a second semiconductor chip 25, and a nonvolatile memory 35 which is mounted on the module substrate 10 and is electrically writable and readable. This nonvolatile memory chip 35 stores mount management data indicating the mount conditions of the first semiconductor chip 15 and second semiconductor chip 25, production management data indicating a production history, and procurement management data indicating a procurement history. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multichip package type semiconductor device.

  In recent years, small digital devices such as mobile phones are required to be multi-functional and compact, and multi-chip package type semiconductor devices in which a plurality of semiconductor chips having specific circuit functions are mounted on a module substrate are used. Yes.

  However, due to the demand for miniaturization and miniaturization of small digital devices, with the miniaturization of circuit elements in semiconductor chips and the complexity of circuits, multichip package type semiconductor devices have been returned after their production and shipment. It tends to increase. Therefore, manufacturing management after manufacturing and shipping of the multichip package type semiconductor device is becoming important.

  For this reason, for example, manufacturing management data such as manufacturing lots, slice coordinates and manufacturing history is attached to the semiconductor chip in the form of a chip ID to perform management after manufacturing and shipping (for example, Patent Document 1). reference.).

However, in the above-described prior art, the mounting state such as the connection between the semiconductor chip and the module substrate or between the semiconductor chips is not considered at all, and there is a problem that the mounting state cannot be managed.
JP 2000-171525 A

  An object of the present invention is to provide a multichip package type semiconductor device capable of managing the mounting state of a semiconductor chip.

  In order to achieve the above object, a multi-chip package semiconductor device according to one embodiment of the present invention is provided with a module substrate, a plurality of semiconductor chips mounted on the module substrate, and mounted and writable on the module substrate. And a non-volatile memory chip that can be electrically read, and mounting management data of the plurality of semiconductor chips is stored in the non-volatile memory chip.

  In the multichip package type semiconductor device of the present invention, the mounting state of the semiconductor chip can be managed.

  Embodiments according to the present invention will be described below with reference to the drawings.

Example 1
A stacked multi-chip package semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

  In this embodiment, an example of a multi-chip package type semiconductor device having a three-layer structure in which first and second semiconductor chips each having a chip ID and a nonvolatile memory chip are stacked is shown.

  FIG. 1 is a plan view of a multi-chip package type semiconductor device having a three-layer structure according to a first embodiment of the present invention with the package removed, and FIG. 2 is cut along the line AA ′ in FIG. FIG.

  As shown in FIGS. 1 and 2, the multi-package semiconductor device of this embodiment includes a module substrate 10, a first semiconductor chip 15, a first spacer 20, a second semiconductor chip 25, and a second spacer 30. A nonvolatile memory chip 35 and a package 45.

  The module substrate 10 has a pad group 11 for connecting bonding wires to the peripheral portion of the upper surface. In addition, a solder ball group 12 as an external terminal electrically connected to the pad group 11 is provided on the lower surface. The solder ball group 12 is arranged in a grid on the lower surface of the module substrate 10.

  FIG. 3 is a plan view of the first semiconductor chip 15.

The first semiconductor chip 15 is mounted on the module substrate 10 and fixed to the upper surface of the module substrate 10 using an epoxy resin underfill material 14.

  The first semiconductor chip 15 has the largest dimension among the plurality of semiconductor chips mounted in the package 45, and the first circuit 16, the first pad group 17, and the first pad are formed on the upper surface of the first semiconductor chip 15. Each having one chip ID 18.

  The first circuit 16 is provided inside the upper surface center of the first semiconductor chip 15 and has a predetermined circuit function such as an arbitrary logic circuit, memory, or analog interface circuit.

  The first pad group 17 is provided on the peripheral portion of the upper surface of the first semiconductor chip 15 and is electrically connected to the first circuit 16. The first pad group 17 is electrically connected to the pad group 11 of the module substrate 10 via the first bonding wire 50.

  The first chip ID 18 indicates manufacturing management data of the first semiconductor chip 15. In this embodiment, the first chip ID 18 is provided in a barcode format by printing on the upper surface of the first semiconductor chip 15. The manufacturing management data is data indicating the manufacturing history of the first semiconductor chip 15, for example, data such as a data manufacturing line, a manufacturing date, a manufacturing lot, or coordinates indicating a position on the wafer.

  The first spacer 20 is made of an insulating member and is provided between the first semiconductor chip 15 and the second semiconductor chip 25, and electrically connects the first semiconductor chip 15 and the second semiconductor chip 25. Insulated.

  The first spacer 20 is fixed to the first semiconductor chip 15 and the second semiconductor chip 25 with an epoxy resin-based underfill material 14.

  The first spacer 20 is smaller than the first semiconductor chip 15, larger than the second semiconductor chip 25, and has a size such that the first pad group 17 is not hidden.

  FIG. 4 is a plan view of the second semiconductor chip 25.

The second semiconductor chip 25 has a large dimension next to the first semiconductor chip 15 among the plurality of semiconductor chips to be mounted. That is, it has a size smaller than that of the first semiconductor chip 15 and larger than that of the nonvolatile memory 35 described later.

  The second semiconductor chip 25 has a second circuit 26, a second pad group 27, and a second chip ID 28 on its upper surface.

  The second circuit 26 is provided inside the upper surface center of the second semiconductor chip 25 and has a predetermined circuit function such as an arbitrary logic circuit, memory, or analog interface circuit.

  The second pad group 27 is provided on the peripheral portion of the upper surface of the second semiconductor chip 25 and is electrically connected to the second circuit 26. The second pad group 27 is electrically connected to the pad group 11 of the module substrate 10 via the second bonding wire 51.

  Like the first chip ID 18, the second chip ID 28 indicates manufacturing management data of the second semiconductor chip 25. The second chip ID 28 is printed on the upper surface of the second semiconductor chip 25 in a barcode format. Yes.

  The manufacturing management data is data indicating the manufacturing history of the semiconductor chip, and is, for example, data such as a data manufacturing line, a manufacturing date, a manufacturing lot, or coordinates indicating a position on the wafer.

  The second spacer 30 is made of an insulating member like the first spacer 20, and is provided between the second semiconductor chip 25 and the nonvolatile memory chip 35. The second semiconductor chip 25 and the nonvolatile memory are provided. The chip 35 is electrically insulated.

  The second spacer 30 is fixed to the second semiconductor chip 25 and the nonvolatile memory chip 35 by an epoxy resin-based underfill material 14.

  The second spacer 30 is smaller than the second semiconductor chip 25, larger than the nonvolatile memory chip 35, and has a size such that the second pad group 27 is not hidden.

  FIG. 5 is a plan view of the nonvolatile memory chip 35.

The non-volatile memory chip 35 has the smallest dimension among a plurality of mounted semiconductor chips, and has a flash memory portion 36, a third pad group 41, and a third chip ID 42 on the upper surface thereof.

  The flash memory unit 36 is composed of a flash memory array and is formed inside the upper surface center of the nonvolatile memory chip 35.

  The third pad group 41 is provided at the peripheral portion of the upper surface of the nonvolatile memory chip 35 and is electrically connected to the flash memory unit 36. The third pad group 41 is electrically connected to the pad group 11 of the module substrate 10 through the third bonding wire 52.

  Similar to the first and second chip IDs 18 and 28, the third chip ID 42 indicates manufacturing management data of the nonvolatile memory chip 35, and is printed on the upper surface of the nonvolatile memory chip 35 in a barcode format. Is provided.

  The manufacturing management data is data indicating the manufacturing history of the semiconductor chip, and is, for example, data such as a data manufacturing line, a manufacturing date, a manufacturing lot, or coordinates indicating a position on the wafer.

  The flash memory unit 36 has a first storage area 37, a second storage area 38, a third storage area 39, and a fourth storage area 40.

  The first storage area 37 is an area for storing and holding manufacturing management data of the first and second semiconductor chips 15 and 25 and the nonvolatile memory chip 35. The first storage area 37 can be arbitrarily changed according to the amount of data stored.

  The second storage area 38 is an area for storing purchase management data of the first and second semiconductor chips 15 and 25 and the nonvolatile memory chip 35. The purchase management data is, for example, data indicating a purchase history such as a purchase source company name and purchase date and time. Unlike the production management data, this purchase management data is not recorded or stored as a chip ID in the semiconductor chip itself. Therefore, the data is required to prepare the multichip package type semiconductor device of this embodiment by the manufacturer. Similarly to the first storage area 37, the second storage area 38 can be arbitrarily changed according to the amount of data to be stored.

  The third storage area 39 is an area for storing and holding the mounting management data. The mounting management data includes, for example, the types of semiconductor chips constituting the multichip package type semiconductor device of this embodiment, the connection state between the semiconductor chip and the module substrate, the connection state between the semiconductor chips, and the multichip of this embodiment. This is data such as a manufacturing line, a manufacturing lot, and an inspection result of the package type semiconductor device itself. This mounting management data is data that needs to be newly prepared by the manufacturer when the multichip package semiconductor device of this embodiment is manufactured. The third storage area 39 can be arbitrarily changed according to the amount of data stored.

  The fourth storage area 40 is the remaining area excluding the first storage area 37, the second storage area 38, and the third storage area 39 in the storage area of the flash memory unit 36. The fourth storage area 40 is an area in which arbitrary data can be written, but is not necessarily required.

  The first and second semiconductor chips 15 and 25 and the nonvolatile memory chip 35 are electrically connected to each other via the module substrate 10 and electrically connected to an external circuit via the solder ball group 12. Connection is possible.

  The package 45 is made of, for example, mold resin, and hermetically seals the chips 15, 25, 35 on the module substrate 10, the spacers 20, 30, and the bonding wires 50, 51, 52.

  Next, writing and reading of data to and from the first storage area 37, the second storage area 38, and the third storage area 39 of the nonvolatile memory chip 35 in the multichip package type semiconductor device of this embodiment. Will be described with reference to FIG. FIG. 6 is a diagram schematically showing the configuration of the data read / write tool.

As shown in FIG. 6, the data read / write tool includes a personal computer (PC) 60, a barcode reader 61, and a flash memory data read / write device 63.

  The barcode reader 61 and the flash memory data read / write device 63 are each connected to the PC 60 via a connection cable 62.

  The PC 60 executes data read / write software and controls the barcode reader 61 and the flash memory data read / write device 63 to read / write data in the flash memory. Further, the PC 60 temporarily stores barcode data read from an arbitrary barcode via the barcode reader 61, data input via a keyboard, or data read via an arbitrary storage medium. To remember.

  The flash memory data read / write device 63 has a flash memory pad 64, and in addition to the BGA type flash memory, other shapes of flash memory can be placed.

  The writing of data to the nonvolatile memory chip 35 of the multichip package semiconductor device of this embodiment is performed using a data read / write tool shown in FIG. Done in The procedure is as follows.

  First, the PC 60 is caused to execute data read / write software.

Next, manufacturing management is performed from the first chip ID 18, the second chip ID 28, and the third chip ID 42 of the first and second semiconductor chips 15 and 25 and the nonvolatile memory chip 35 using the barcode reader 61. The data is read out, and the read management data is temporarily stored in the PC 60.

  Next, purchase management data of the first semiconductor chips 15 and 25 and the nonvolatile memory chip 35 are prepared in advance on the manufacturing side, and are temporarily stored in the PC 60 via an arbitrary storage medium.

  In addition, the mounting management data is prepared in advance by the manufacturer and is temporarily stored in the PC 60 via an arbitrary storage medium.

  Next, the first storage area 37, the second storage area 38, and the third storage area of the non-volatile memory chip 35 in order of the manufacturing management data, purchase management data, and mounting management data temporarily stored in the PC 60 Write to 39 respectively. Thus, the data writing procedure to the nonvolatile memory chip 35 is completed.

  Next, when the multi-chip package type semiconductor device of this embodiment is manufactured and shipped, for example, when it is returned to the manufacturer for inspection due to some malfunction, it is described in the nonvolatile memory chip 35 for malfunction analysis. Management data is read out. The procedure is as follows.

  First, the returned multi-chip package semiconductor device is mounted on the data read / write device 63 for flash memory.

  Next, the PC 60 is caused to execute data read / write software, and the PC 60 issues a data read command to the flash memory data read / write device 63.

  Based on this data read command, the flash memory data read / write device 63 reads the management data from the flash memory unit 36 and sends it to the PC 60.

  Next, the PC 60 temporarily stores the management data sent from the flash memory data read / write device 63 and displays it on the screen of the PC 60. The PC 60 can also write the temporarily stored management data to an arbitrary storage medium. Thus, the data reading procedure from the nonvolatile memory chip 35 is completed.

  As described above, according to the multi-chip package semiconductor device of this embodiment, in addition to the manufacturing management data indicating the manufacturing history of the semiconductor chip, the purchase management data indicating the purchase history of the semiconductor chip, and the mounting of the semiconductor chip Mounting management data indicating the state is stored in the nonvolatile memory chip.

  Therefore, when the multi-chip package type semiconductor device is returned, for example, due to some malfunction after manufacturing and shipment, the management data of the nonvolatile memory chip 35 is electrically read without destroying the package, You can grasp the purchase history and implementation status.

  In the conventional multi-chip package type semiconductor device, when the chip ID is in the barcode format, it is necessary to destroy the package in order to read the manufacturing management data held in the chip ID. In the package type semiconductor device, it is possible to read the manufacturing management data written in the nonvolatile memory chip without destroying the package.

  Further, for example, if it is found that only a semiconductor chip of a specific manufacturing lot is defective among the first semiconductor chips, the manufacturing management data of the nonvolatile memory chip is read without destroying the package. Thus, it becomes possible to find a multi-chip package type semiconductor device on which the first semiconductor chip with the defective lot is mounted.

(Example 2)
A multi-chip package semiconductor device having a three-layer structure according to Embodiment 2 of the present invention will be described with reference to FIG. The present embodiment is different from the first embodiment in that the nonvolatile memory chip 35 further includes a third circuit 70, and other configurations are the same as those of the first embodiment. Accordingly, the following description will be made on differences from the first embodiment.

  FIG. 7 is a plan view of the nonvolatile memory chip 35 in the multichip package semiconductor device according to the second embodiment.

  The non-volatile memory chip 35 has a third circuit 70 in addition to the flash memory unit 36 in a region surrounded by the third pad group 41 on the peripheral portion of the upper surface thereof.

  The third circuit 70 is provided in parallel with the flash memory unit 36 and has a circuit function such as an arbitrary logic circuit, memory, or analog interface circuit. The third circuit 70 is electrically connected to the third pad group 41.

  Since the configuration and electrical connection of the flash memory unit 50, the third pad group 41, and the third chip ID 42 other than the third circuit 70 are the same as those in the first embodiment, the description thereof is omitted.

  As described above, the multi-chip package type semiconductor device according to the present embodiment is provided with an arbitrary circuit in addition to the flash memory portion in the nonvolatile memory chip 35 in addition to the effects of the first embodiment. Compared with the first embodiment, more circuit functions can be realized with the same number of semiconductor chips and mounting area.

(Example 3)
A multi-chip package semiconductor device having a three-layer structure according to Embodiment 3 of the present invention will be described with reference to FIG. This embodiment is an example in which a third semiconductor chip 75 having no chip ID is mounted in place of the second semiconductor chip 25 of the first embodiment or the second embodiment. Other configurations are the same as those in the first embodiment or the second embodiment.

  FIG. 8 is a plan view of the third semiconductor chip 75 in the multichip package semiconductor device according to the third embodiment.

  The third semiconductor chip 75 has the second circuit 26 and the second pad group 27 on its upper surface, but the second chip ID 28 of the second semiconductor chip 25 in the first embodiment, that is, the manufacturing history is recorded. Does not have manufacturing management data to show.

  Since the second circuit 26 and the second pad group 27 are the same as those in the first embodiment or the second embodiment, description thereof is omitted.

  In the multi-chip package type semiconductor device of this embodiment, the management data held in the first storage area 37 of the nonvolatile memory chip 35 is different from the first embodiment or the second embodiment, and the first semiconductor chip 15 manufacturing management data and non-volatile memory chip 35 manufacturing management data. The management data held in the second storage area 38 and the third storage area 39 are purchase management data and mounting management data, respectively, as in the first embodiment or the second embodiment.

As described above, the multi-chip package type semiconductor device according to the present embodiment uses purchase management data and mounting management data even for a semiconductor chip to which the chip ID indicating the manufacturing management data of the second semiconductor chip 75 is not attached. Therefore, it is possible to manage the purchase history and the implementation status at least.
Example 4
A multi-chip package semiconductor device having a three-layer structure according to a fourth embodiment of the present invention will be described with reference to FIGS. The present embodiment is an example where the first spacer 20 and the second spacer 30 of the first embodiment are omitted. Other configurations are the same as in the first embodiment.
FIG. 9 is a plan view of the multichip package type semiconductor device according to the present embodiment with the package removed. 10 is a cross-sectional view taken along the line BB ′ in FIG. 9 and viewed in the direction of the arrow.

  As shown in FIGS. 9 and 10, in the multichip package type semiconductor device of this embodiment, the first semiconductor chip 15 is directly fixed to the upper surface of the module substrate 10 by an epoxy resin-based underfill material 14. The second semiconductor chip 25 is directly fixed to the upper surface of the first semiconductor chip 15 by the epoxy resin-based underfill material 14, and the nonvolatile memory chip 35 is bonded to the upper surface of the second semiconductor chip 7 by the epoxy resin-based underfill material 14. It is directly fixed by the fill material 14. Other configurations and data writing to and reading from the nonvolatile memory chip 35 are the same as those in the first embodiment, and a description thereof will be omitted.

  In the multichip package type semiconductor device of the present embodiment described above, the two spacers are omitted in addition to the same effects as in the first embodiment. Is low and thin.

(Example 5)
A planar multi-chip package semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. This embodiment is different from the first embodiment in that the first semiconductor chip 15, the second semiconductor chip 25, and the nonvolatile memory chip 35 are mounted side by side on the upper surface of the module substrate 10.

  FIG. 11 is a plan view of the multichip package type semiconductor device according to the fifth embodiment viewed from above with the package removed. 12 is a cross-sectional view taken along the line C-C ′ of FIG. 10 and viewed in the direction of the arrow.

  As shown in FIGS. 11 and 12, in the multi-chip package type semiconductor device of the present embodiment, the module substrate 10, the first semiconductor chip 15, the second semiconductor chip 25, the nonvolatile memory chip 35, and the package 45 Have On the upper surface of the module substrate 10, chip mounting regions 15a, 25a, and 35a for mounting the first semiconductor chip 15, the second semiconductor chip 25, and the nonvolatile memory chip 35, respectively, are provided.

  Pad groups 11 are provided in the peripheral portions of the chip mounting areas 15 a, 25 a, and 35 a of the module substrate 10, respectively. Are electrically connected to each other.

  The first semiconductor chip 15 has a first circuit (not shown), a first pad group 17, and a first chip ID (not shown) on its upper surface, as in the first embodiment. The module substrate 10 is fixed to the chip mounting region 15 a of the module substrate 10 with an epoxy resin underfill material 14. The first pad group 17 of the first semiconductor chip 15 is electrically connected to the pad group 11 of the module substrate 10 through the first bonding wire 50.

  The second semiconductor chip 25 has a second circuit (not shown), a second pad group 27, and a second chip ID (not shown) on its upper surface, as in the first embodiment. The module substrate 10 is fixed to the chip mounting region 25a of the module substrate 10 with an epoxy resin-based underfill material 14. The second pad group 27 of the second semiconductor chip 25 is electrically connected to the pad group 11 of the module substrate 10 through the second bonding wire 51.

  As in the first embodiment, the nonvolatile memory chip 35 includes a flash memory unit (not shown) having first to third storage areas, a third pad group 41, and a third chip ID (not shown). Are fixed to the chip mounting area 35a of the module substrate 10 by an epoxy resin-based underfill material (not shown). Then, the third pad group 41 of the nonvolatile memory chip 35 is electrically connected to the pad group 11 of the module substrate 10 via the third bonding wire 52.

  The package 45 is made of, for example, a mold resin, and hermetically seals the chips 15, 25, 35 and the bonding wires 50, 51, 52 on the module substrate 10. Note that data writing to and reading from the nonvolatile memory chip 35 in the multi-chip package type semiconductor device having a planar structure according to the present embodiment is the same as in the first embodiment, and a description thereof is omitted.

  In the multichip package type semiconductor device of the present embodiment described above, in addition to the same effects as in the first embodiment, the semiconductor chip and the nonvolatile memory chip are arranged side by side on the module substrate. Compared to the example, it is possible to reduce the thickness.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention.

For example, in each of the above embodiments, the nonvolatile memory chip has a flash memory unit, but instead of the flash memory unit, for example, a fuse chip, an anti-fuse chip, or another type of electrical data is stored. A configuration using a readable / writable nonvolatile memory is also possible. Further, a configuration in which a flash memory, a fuse chip, an antifuse chip, and other types of nonvolatile memories are combined is also possible.

  Further, in each of the above-described embodiments, the chip ID is an example of a barcode format, but for example, a fuse chip, an antifuse chip, or other formats can also be used. In this case, the reading tool may be changed according to the format of the chip ID. Furthermore, when the data of the chip ID is electrically readable such as a fuse chip or an antifuse chip, in addition to electrically reading data from the flash memory unit 36 as in the above embodiments, Data can be electrically read from the chip ID 18, the second chip ID 28, and the third chip ID 42 without destroying the package.

  In each of the above-described embodiments, an example in which the manufacturing management data of the chip ID can be read has been described. However, a chip ID that cannot be read according to the format of the manufacturing management data can be used. In this case, the manufacturing management data cannot be managed, but the purchase history and the mounting status can be managed at least by using the purchase history data and the mounting management data.

  In each of the above embodiments, a multi-chip package type semiconductor device having a BGA structure is shown. However, for example, a structure capable of electrically exchanging signals with the outside such as SOP and QFP is also possible.

  In each of the above embodiments, the semiconductor chip and the module substrate are connected via the bonding wire. However, for example, the internal chip is connected by means of internal vias, bump connection, or other means capable of exchanging signals. A structure is also possible.

  In each of the above embodiments, the semiconductor chips and the semiconductor chip and the module substrate are fixed to each other using an epoxy resin-based underfill material. However, a structure using other insulating adhesive is also possible. It is.

  In each of the above embodiments, the case where three semiconductor chips are mounted has been described. However, the number of semiconductor chips to be mounted is not limited as long as it has a multichip package structure.

  In each of the above-described embodiments, an example in which one arbitrary electric circuit is mounted on the first, second, and third semiconductor chips is shown. However, a configuration in which one or more arbitrary electric circuits are mounted is also possible. Is possible.

  In the first to third embodiments, the first and second spacers may have any size as long as they have the same function.

  In the third embodiment, an example is shown in which one semiconductor chip having no chip ID is mounted. However, the mounting position and the number of the semiconductor chips can be arbitrarily changed.

  Moreover, although the example which does not use a spacer was shown in the said Example 4, according to the semiconductor chip to mount, the example using only one piece and other arbitrary number structures are also possible.

The top view of the state which removed the package of the multichip package type semiconductor device which concerns on Example 1 of this invention. Sectional drawing cut | disconnected along the A-A 'line | wire of FIG. 1, and looked at the arrow direction. FIG. 3 is a plan view of a first semiconductor chip in the multichip package semiconductor device according to the first embodiment. FIG. 3 is a plan view of a second semiconductor chip in the multichip package semiconductor device according to the first embodiment. 1 is a plan view of a nonvolatile memory chip in a multichip package type semiconductor device according to Embodiment 1. FIG. The figure which showed the structure of the data read / write tool. The top view of the non-volatile memory chip in the multichip package type semiconductor device which concerns on Example 2 of this invention. The top view of the 3rd semiconductor chip in the multichip package type semiconductor device concerning Example 3 of the present invention. The top view in the multichip package type semiconductor device concerning Example 4 of the present invention. Sectional drawing cut | disconnected along the B-B 'line | wire of FIG. 9, and looked at the arrow direction. FIG. 9 is a plan view of a multichip package semiconductor device according to a fifth embodiment of the present invention. Sectional drawing cut | disconnected along the C-C 'line | wire of FIG. 11, and looked at the arrow direction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Module board | substrate 11 Pad group 12 Solder ball group 14 Underfill material 15 1st semiconductor chip 15a Chip mounting area 16 1st circuit 17 1st pad group 18 1st chip ID
20 First Spacer 25 Second Semiconductor Chip 25a Chip Mounting Area 26 Second Circuit 27 Second Pad Group 28 Second Chip ID
30 Second spacer 35 Nonvolatile memory chip 35a Chip mounting area 36 Flash memory section 37 First storage area 38 Second storage area 39 Third storage area 40 Fourth storage area 41 Third pad group 42 Second 3 chip ID
45 Package 50 First bonding wire 51 Second bonding wire 52 Third bonding wire 60 PC
61 Bar code reader 62 Connection cable 63 Flash memory data read / write tool 64 Flash memory pad 70 Third circuit 75 Third semiconductor chip

Claims (4)

A module board;
A plurality of semiconductor chips mounted on the module substrate;
A nonvolatile memory chip that is mounted on the module substrate and is writable and electrically readable;
A multi-chip package type semiconductor device, wherein the non-volatile memory chip stores mounting management data of the plurality of semiconductor chips.   2. The multi-chip package type semiconductor device according to claim 1, wherein manufacturing control data of the plurality of semiconductor chips is further stored in the nonvolatile memory chip.   3. The multichip package semiconductor device according to claim 1, wherein purchase history data of the plurality of semiconductor chips is further stored in the nonvolatile memory chip.   The semiconductor device according to claim 1, wherein the nonvolatile memory chip includes an arbitrary electric circuit.

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