JP6023866B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a package structure in which a memory chip and a controller chip are stacked on a wiring board.

  In recent years, various semiconductor devices in which a plurality of memory chips are stacked on a wiring substrate have been developed in order to increase the capacity of the semiconductor memory and reduce the size of the device.

  Japanese Patent Laying-Open No. 2006-351664 (Patent Document 1) discloses a SIP (System In Package) in which a plurality of memory chips and a microcomputer chip are stacked on a wiring board. In this SIP, a plurality of memory chips and a microcomputer chip are stacked on the surface of a wiring board, and an interposer chip made of a silicon substrate is disposed on the surface of the memory chip adjacent to the microcomputer chip. Further, the pads of the microcomputer chip are connected to the pads of the wiring board via the interposer chip and bonding wires.

  Japanese Patent Laid-Open No. 2002-33442 (Patent Document 2), Japanese Patent Laid-Open No. 2002-217356 (Patent Document 3), and Japanese Patent Laid-Open No. 2007-59541 (Patent Document 4) have a plurality of bonding pads formed on one side. A semiconductor device in which a semiconductor chip is stacked on a wiring board is disclosed. Each of the semiconductor chips is arranged such that one side on which the bonding pad is formed faces in the opposite direction, and is stacked in a state of being alternately shifted in a direction perpendicular to the one side.

  Japanese Patent Laying-Open No. 2006-86149 (Patent Document 5) discloses a semiconductor device having a stacked multichip package structure in which a plurality of semiconductor chips and rewiring elements (interposers) are stacked and mounted on a wiring board. Yes. The rewiring element has wiring for connecting between a plurality of semiconductor chips or between a wiring substrate and a semiconductor chip. Interconnection between a plurality of semiconductor chips, rearrangement of pads of a semiconductor chip, etc. Has been implemented.

  Japanese Patent Laying-Open No. 2005-244143 (Patent Document 6) discloses a semiconductor device in which an interface chip is stacked on a plurality of stacked semiconductor chips. An Si interposer and a resin interposer are disposed under the plurality of semiconductor chips. The Si interposer is disposed between the resin interposer and the plurality of semiconductor chips, is thicker than the semiconductor chip, and smaller than the linear expansion coefficient of the resin interposer, and is greater than the linear expansion coefficient of the plurality of semiconductor chips. have.

  Japanese Patent Laying-Open No. 2007-66922 (Patent Document 7) discloses a semiconductor integrated circuit device provided with a package having a stacked structure. This semiconductor integrated circuit device has a stacked structure in which a plurality of semiconductor chips are stacked on a printed wiring board, and an interface circuit is provided on the semiconductor chip mounted at the bottom. This interface circuit includes a buffer, an electrostatic protection circuit, and the like, and all signals input / output to / from a plurality of semiconductor chips are input / output via this interface circuit.

  Japanese Patent Laying-Open No. 2007-128953 (Patent Document 8) discloses a semiconductor device in which first and second semiconductor chips each having a long-side one-side pad structure are stacked and mounted on a wiring board having connection pads. doing. The second semiconductor chip is smaller than the first semiconductor chip and has an elongated shape. The first and second semiconductor chips are electrically connected to the wiring board 2 connection pads via bonding wires, and the second semiconductor chip has a long side with respect to the ultrasonic wave application direction X during wire bonding. It arrange | positions so that L may become parallel.

  Japanese Patent Laying-Open No. 2007-96071 (Patent Document 9) discloses a semiconductor memory card capable of mounting a large-capacity nonvolatile memory chip. The semiconductor memory card is placed on a rectangular circuit board and a circuit board, and a plurality of first bonding pads are formed along only the first side. A rectangular nonvolatile memory chip wire-bonded to a plurality of first substrate terminals formed in the vicinity of the first side, and the direction and length of the second side of the nonvolatile memory chip adjacent to the first side It is mounted on the nonvolatile memory chip so that the direction of the side is substantially parallel. In addition, a plurality of second bonding pads are formed in the direction of the long side, and the second bonding pads and a plurality of second substrate terminals formed on the circuit board in proximity to the long side are wires. And a bonded rectangular controller chip.

  Japanese Patent Laying-Open No. 2004-63579 (Patent Document 10) discloses a semiconductor device in which two semiconductor chips each having bonding pads formed on two sides orthogonal to each other are stacked. The second semiconductor chip stacked on the first semiconductor chip is stacked in a state shifted in the X and Y directions so that the bonding pads on the two sides of the first semiconductor chip are exposed.

  Japanese Patent Laid-Open No. 2005-339496 (Patent Document 11) has a plurality of flash memory chips stacked and mounted on a main surface of a wiring board, and a controller chip and a security controller on the uppermost flash memory chip. A multi-function memory card on which the IC card microcomputer chip is mounted is disclosed. Each of the plurality of flash memory chips has a bonding pad formed on one short side, and is laminated with a predetermined distance shifted in the long side direction so that the bonding pad is exposed.

JP 2006-351664 A JP 2002-33442 A JP 2002-217356 A JP 2007-59541 A JP 2006-86149 A JP-A-2005-244143 JP 2007-66922 A JP 2007-128953 A JP 2007-96071 A JP 2004-63579 A JP-A-2005-339496

  Memory cards are used as recording media for various portable electronic devices such as mobile phones, digital cameras, and digital audio players.

  The general configuration of the memory card is such that a plurality of flash memory chips are stacked and mounted on the main surface of the wiring board, and a controller chip is mounted on the uppermost flash memory chip as in Patent Document 11 described above. Is. Each of the plurality of flash memory chips is stacked while being shifted by a predetermined distance in a direction orthogonal to the one side so that the bonding pad formed on one side of the chip is exposed.

  In recent years, with an increase in storage capacity required for recording media of various portable electronic devices such as mobile phones, the number of stacked flash memory chips mounted on a memory card has increased, and the size of the flash memory chip has increased. It has become. On the other hand, since various portable electronic devices are becoming smaller and thinner, memory cards are also required to be smaller and thinner.

  For this reason, since the size of the flash memory chip is close to the size of the wiring board of the memory card, when a plurality of flash memory chips are mounted on the wiring board, the flash memory chip is mounted as described in Patent Document 11. In the method of stacking by shifting in one direction, the flash memory chip cannot be accommodated in the memory card.

  In addition, the memory card is equipped with a controller chip for controlling the flash memory on the uppermost layer of the stacked flash memory chips, and the flash memory chip and the controller chip are electrically connected via wiring formed on the wiring board and Au wires. Connected. However, when the size of the flash memory chip approaches the size of the wiring board of the memory card, there is no space for arranging the bonding pads for connecting the memory chip and the bonding pads for connecting the controller chip on the surface of the wiring board.

  An object of the present invention is to provide a technique capable of increasing the number of memory chips stacked and mounted on a wiring board in a semiconductor device having a package structure in which a memory chip and a controller chip are stacked on the wiring board. There is.

  Another object of the present invention is to provide a technique capable of improving the degree of freedom of wiring for connecting a memory chip and a controller chip in a semiconductor device having a package structure in which a memory chip and a controller chip are stacked on a wiring board. It is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) A wiring board having a main surface and a back surface and having external connection terminals formed on the back surface, a memory chip mounted on the main surface of the wiring board, and the memory chip mounted on the memory chip A semiconductor device having a controller chip for controlling a memory chip and an interposer mounted on the memory chip and electrically connected to the controller chip,
A first terminal is formed on a first side of the memory chip, and the interposer is disposed between the first side of the memory chip and the controller chip, and a first terminal of the interposer is provided. A second terminal is formed on the side, a third terminal is formed on the second side orthogonal to the first side, and a fourth terminal is formed on the third side opposite to the first side. The second terminal formed on the first side of the interposer is electrically connected to the first terminal formed on the first side of the memory chip, and the interposer The third terminal formed on the second side is electrically connected to the external connection terminal via a fifth terminal provided on one side of the main surface of the wiring board, and the interposer The fourth terminal formed on the third side is Serial are those controller chip electrically connected.
(2) A wiring board having a main surface and a back surface and having external connection terminals formed on the back surface, a memory chip mounted on the main surface of the wiring board, and a controller mounted on the memory chip A semiconductor device having a chip,
A first terminal is formed on the first side of the memory chip, a second terminal is formed on the first side of the controller chip, and a second side orthogonal to the first side is formed on the second side. A third terminal is formed, and the second terminal formed on the first side of the controller chip is electrically connected to the first terminal formed on the first side of the memory chip. And the third terminal formed on the second side of the controller chip is a second terminal on the main surface of the wiring board provided on the second side orthogonal to the first side of the memory chip. It is electrically connected to the external connection terminal via four terminals, and mounted on the main surface of the wiring board in a state where a plurality of the memory chips are stacked, and the plurality of memory chips are The first terminal provided on each of the first sides is exposed. As described above, the first and second memory chips of the plurality of memory chips are stacked so as to be shifted in a direction orthogonal to the first side. Are stacked in a state of being shifted by 180 degrees in the main surface of the wiring substrate so that the sides of the wiring substrate are directed in opposite directions, and the first terminal of the lowermost memory chip is connected to the fourth terminal. Electrically connected to the controller chip via the wiring of the wiring board, and the first terminal of the other memory chip is electrically connected to the second terminal of the controller chip It is.
(3) A semiconductor device mounted in a state where a plurality of memory chips are stacked on a main surface of a wiring board,
A first terminal is formed on a first side of each of the plurality of memory chips, and the first plurality of memory chips are exposed such that a first terminal on each of the first sides is exposed. The plurality of memory chips are stacked so as to be shifted in a direction perpendicular to the side, and the first side of the lowermost memory chip among the plurality of memory chips is arranged to be aligned with the first side of the wiring board, When the number of memory chips is n (n is 4 or more), the number of memory chips continuously shifted in the same direction is (n / 2) or less and 2 or more. Of the plurality of memory chip groups that are successively shifted in the same direction except for the uppermost memory chip of the memory chips, the uppermost memory chip is connected to the other memory chips in the group. Are stacked with the sides shifted 180 degrees. It is intended.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a semiconductor device having a package structure in which a memory chip and a controller chip are stacked on a wiring board, the number of memory chips stacked and mounted on the wiring board can be increased.

  In a semiconductor device having a package structure in which a memory chip and a controller chip are stacked on a wiring board, the degree of freedom of wiring for connecting the memory chip and the controller chip can be improved.

It is a schematic plan view which shows the internal structure of the memory card which is one embodiment of this invention. It is a top view which shows the external appearance of the back surface of the memory card which is one embodiment of this invention. It is the sectional view on the AA line of FIG. (A), (b) is sectional drawing of the memory card which changed the lamination | stacking method of the memory chip. In the memory card which is one embodiment of this invention, it is a schematic plan view which shows the connection relationship of a controller chip, an interposer, a memory chip, and a wiring board. In the memory card which is one embodiment of this invention, it is a block diagram which shows the connection relation of a controller chip, an interposer, a memory chip, and a wiring board. It is a block diagram which shows the connection relation between each chip | tip, without showing an interposer. (A) is an enlarged plan view of the connection portion between the chip select pad of the interposer and the chip select pad of the memory chip, and (b) is the memory specific control pad of the controller chip and the chip select pad of the memory chip. It is the top view to which the connection part with was expanded. It is sectional drawing which shows another example of the lamination | stacking method of a memory chip. It is sectional drawing which shows another example of the lamination | stacking method of a memory chip. It is sectional drawing which shows another example of the lamination | stacking method of a memory chip. It is sectional drawing of the memory card which is other embodiment of this invention. It is the schematic which shows the lamination | stacking method of a comparative example. It is a schematic plan view which shows the internal structure of the memory card which is other embodiment of this invention. (A) is a plan view showing the appearance (front side) of a memory card according to another embodiment of the present invention, (b) is a side view of this memory card, and (c) is the appearance of this memory card. It is a top view which shows (back side). FIG. 16 is a plan view showing a wiring board of the memory card shown in FIG. 15. FIG. 16 is a cross-sectional view showing a wiring board of the memory card shown in FIG. 15. FIG. 16 is a circuit diagram schematically showing a connection relationship among a wiring board, a memory chip, a controller chip, and an interposer of the memory card shown in FIG. 15. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. It is sectional drawing which shows the wiring board of the memory card which is other embodiment of this invention. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. It is sectional drawing which shows the wiring board of the memory card which is other embodiment of this invention. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. It is sectional drawing which shows the wiring board of the memory card which is other embodiment of this invention. It is a top view of the map board | substrate used for preparation of an interposer. FIG. 26 is a plan view showing a method for producing an interposer from the map substrate shown in FIG. 25. FIG. 26 is a plan view showing a method for producing an interposer from the map substrate shown in FIG. 25. FIG. 26 is a plan view showing a method for assembling a memory card using an interposer obtained from the map board shown in FIG. 25. FIG. 26 is a plan view showing a method for assembling a memory card using an interposer obtained from the map board shown in FIG. 25. FIG. 26 is a plan view showing a method for assembling a memory card using an interposer obtained from the map board shown in FIG. 25. FIG. 26 is a plan view showing another example of a method for assembling a memory card using an interposer obtained from the map board shown in FIG. 25. FIG. 26 is a plan view showing another example of a method for assembling a memory card using an interposer obtained from the map board shown in FIG. 25. FIG. 26 is a plan view showing another example of a method for assembling a memory card using an interposer obtained from the map board shown in FIG. 25. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. FIG. 37 is a cross-sectional view showing a wiring board of the memory card shown in FIG. 36. FIG. 37 is a circuit diagram schematically showing a connection relationship among a wiring board, a memory chip, a controller chip, and an interposer of the memory card shown in FIG. 36. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. It is a top view which shows the wiring board of the memory card which is other embodiment of this invention. It is sectional drawing which shows the system in package of the ball grid array structure which is other embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The present embodiment is applied to a memory card used as a mobile phone recording medium.
<Outline of laminated structure>
1 is a schematic plan view showing the internal structure of the memory card according to the present embodiment, FIG. 2 is a plan view showing the appearance of the back surface of the memory card, and FIG. 3 is a cross-sectional view taken along line AA in FIG. is there.

  The memory card 1A of the present embodiment is used by being inserted into a card slot of a mobile phone, and the outer dimensions thereof are, for example, long side × short side 15 mm × 12.5 mm, and thickness is 1.2 mm. It is. The memory card 1A includes a wiring board 2 mainly composed of glass epoxy resin, four memory chips M1, M2, M3, and M4 stacked on the main surface (front surface), and an uppermost memory chip. A controller chip 3 and an interposer 4 mounted on the surface of M4 are provided. Here, the memory chips M1, M2, M3, and M4 have substantially the same shape and the same size.

  The wiring board 2 and the memory chips M1 to M4 are fixed to each other with an adhesive or the like. Further, the controller chip 3 and the interposer 4 are respectively fixed to the surface of the memory chip M4 with an adhesive or the like.

  The surface side of the wiring board 2 is covered with a mold resin 5 that seals the memory chips M1 to M4, the controller chip 3, and the interposer 4. The mold resin 5 is made of, for example, a thermosetting epoxy resin containing a quartz filler. Although not shown, an insulating label describing the product name, manufacturer, storage capacity, etc. is affixed to the surface of the mold resin 5 corresponding to the surface of the memory card 1A. Further, the above contents can be directly printed on the surface of the mold resin 5 in place of such a label.

  As shown in FIG. 3, one side of the mold resin 5 (right end portion in the figure), that is, one side (point indicated by an arrow) that becomes the tip portion (right end portion in the figure) when the memory card 1A is inserted into the card slot of the cellular phone. Is tapered so that the thickness of the tip is thinner than other parts. By forming the tip portion in such a shape, smooth insertion is possible even when the insertion angle is slightly shifted in the vertical direction when the memory card 1A is inserted into the card slot. On the other hand, a groove 5A is provided in the mold resin 5 near one side (short side) that becomes the rear end (left end in the figure) when the memory card 1A is inserted into the card slot of the mobile phone. The concave groove 5A is a guide groove that prevents the front end and the rear end of the memory card 1A from being reversed when the memory card 1A is inserted into the card slot of the mobile phone. Further, by providing the concave groove 5A, the memory card 1A can be easily removed from the card slot.

  Each of the memory chips M1 to M4 is made of a rectangular silicon chip having a thickness of about 0.09 mm, and its main surface (front surface) has an 8-gigabit storage capacity here, and is electrically erased and written. Possible non-volatile memory (flash memory) is formed. Accordingly, the memory card 1A of the present embodiment on which the four memory chips M1 to M4 are mounted has a storage capacity of 8 gigabits × 4 = 32 gigabits (4 gigabytes). As the flash memory, for example, a NAND flash memory is used, but an AG-AND (Assist Gate-AND) flash memory, a NOR flash memory, or the like may be used. In the vicinity of one side (short side) of each surface of the memory chips M1 to M4, a plurality of pads (terminals) 6 are formed concentrated in the short side direction. For simplification of the drawing, only a part of the pad 6 is shown in FIG.

Each of the memory chips M <b> 1 to M <b> 4 is stacked on the surface of the wiring board 2 so that the long side faces the same direction as the long side of the wiring board 2. The wiring board 2 is arranged such that its long side faces the same direction as the long side of the memory card 1A.
<Controller chip>
The controller chip 3 is a rectangular silicon chip having a smaller area than the memory chips M1 to M4. The thickness of the controller chip 3 is about 0.1 mm. On the main surface (front surface) of the controller chip 3, an interface circuit for exchanging data between the memory chips M1 to M4 and the outside is formed, and an external interface operation is performed in a control manner according to an instruction from the outside. The memory interface operation for the memory chips M1 to M4 is controlled. A row of a plurality of pads (terminals) 7 is formed in the vicinity of one side (long side) of the surface of the controller chip 3.

The interface circuit formed in the controller chip 3 has a plurality of interface control modes, and controls the external interface operation and the memory interface operations for the memory chips M1 to M4 in a control mode according to an instruction from the outside. The memory card interface mode conforms to the interface specifications of various single memory cards. For example, the interface controller realizes the function of the memory card controller that supports the interface specifications of these memory cards by program control. It is also possible to support a predetermined memory card interface specification later by adding a control program, that is, firmware, to the interface controller by downloading via a network or the like. Further, if execution of a predetermined control program is prohibited by license information obtained via a network, it is possible to disable a predetermined memory card interface specification later.
<Interposer>
The interposer 4 is a rectangular resin substrate whose long side is slightly shorter than the short sides of the memory chips M1 to M4, and has a thickness of about 0.13 mm. The interposer 4 is mounted in the vicinity of the controller chip 3 with its long side directed in the same direction as the short side of the wiring board 2. The interposer 4 is used as a relay board when the controller chip 3 is connected to the memory chips M1 to M4 and the wiring board 2, and a plurality of pads (terminals) 8 are formed in a row near the three sides of the surface. Yes.

  Here, a controller chip connection pad is arranged on one of the two long sides facing each other, and a memory chip connection pad is arranged on the other side. Further, a connection pad is disposed on the wiring board on one short side.

  A plurality of layers of wiring are formed in the interposer 4. Here, it is composed of a resin substrate having wirings formed on the front surface and the back surface. Although the interposer 4 is described as a resin substrate, the interposer 4 may be configured by, for example, a silicon chip on which wiring is formed. Further, when the connection with the wiring board, the memory chip, and the controller chip is not complicated, the wiring board, the memory chip, and the controller chip may be formed with a single layer wiring instead of a plurality of layers.

  As shown in FIG. 1, the interposer 4 and the controller chip 3 are electrically connected by an Au wire 10. The interposer 4 and the memory chips M2, M3, and M4 and the memory chips M2 to M4 are electrically connected to each other by Au wires 11, respectively. Further, the interposer 4 and the wiring board 2 are electrically connected by an Au wire 12. A pad (terminal) 9 on the wiring board 2 side to which one end of the Au wire 12 is connected is formed along one long side of the wiring board 2.

  Since the interposer 4 is provided between the controller chip 3, the memory chips M2 to M4, and the wiring board 2, the order of signals input to and output from the interposer 4 can be changed by changing the pad 8 and wiring layout of the interposer 4. Can be replaced, and the pad pitch can be changed. For this reason, the freedom degree of wiring design improves compared with the case where the controller chip 3, the memory chips M-M4, and the wiring board 2 are connected directly. In particular, the degree of freedom of wiring can be increased.

  In the present embodiment, the long side of the interposer 4 is closer to the short side of the memory chips M1 to M4 than the long side of the controller chip 3. For this reason, the connection between the pads 6 of the memory chips M1 to M4 and the pads 8 of the interposer 4 can be reduced and shortened by adjusting the wiring in the interposer 4.

  In addition, since the long side of the interposer 4 approaches the length of the short side of the memory chips M1 to M4, the pad 8 and the wiring board 2 provided on the short side of the interposer 4 are compared with those that match the size of the controller chip 3. The distance from the upper pad 9 can be shortened. Therefore, the wire length between pads can be shortened. In particular, since the level difference is severe in this structure, reducing the wire length has a great effect of stabilizing the wire connection.

Furthermore, although the external dimensions of the memory chips M1 to M4 and the layout of the pads 6 are different depending on the semiconductor manufacturer, even when the memory chips M1 to M4 of different semiconductor manufacturers are mounted, by changing the specifications of the interposer 4, Since it is not necessary to change the specifications of the controller chip 3, the versatility of the controller chip 3 is improved.
<Wiring board>
The wiring substrate 2 is a rectangular resin substrate having a thickness of about 0.2 mm, and includes a front surface wiring 20, a back surface wiring 21, and a via hole 22 that connects them, although not shown in FIGS. . In addition to the memory chips M1 to M4, a small passive element (not shown) such as a chip capacitor is mounted on the main surface (front surface) of the wiring board 2 as necessary.

  The back surface of the wiring board 2 is not covered with the mold resin 5 and is exposed on the back surface side of the memory card 1A. As shown in FIG. 2, a plurality of external connection terminals 23 are formed on the back surface of the wiring board 2. The external connection terminal 23 includes a power supply terminal (Vcc), a ground terminal (Vss), and a data input / output terminal. As will be described later, the controller chip is connected via the back surface wiring 21, the via hole 22, the front surface wiring 20, and the like. 3 is connected.

The external connection terminal 23 is formed in the vicinity of one side (short side) which becomes the tip when the memory card 1A is inserted into the card slot of the mobile phone, and is arranged in the short side direction. Therefore, when the memory card 1A is inserted into the card slot of the mobile phone, the connector terminal built in the card slot and the external connection terminal 23 come into contact with each other, and exchange of signals and power supply between the memory card 1A and the mobile phone are made. Supply is made. The memory card of this embodiment is designed to operate with a single power supply (for example, 3.3V), but can be operated with a plurality of power supplies (for example, 1.8V and 3.3V). In this case, a power control chip is separately mounted on the surface of the uppermost memory chip M4.
<Laminated cross-sectional structure>
As described above, each of the memory chips M <b> 1 to M <b> 4 is stacked on the surface of the wiring board 2 with its long side directed in the same direction as the long side of the wiring board 2. As shown in FIG. 3, the lowermost memory chip M1 has a short side on the side where the pad 6 is formed at the rear end of the memory card 1A (the rear end when the memory card 1A is inserted into the card slot of the mobile phone). Part). A plurality of pads 9 are formed in the vicinity of one side (short side) of the wiring board 2 located at the rear end portion of the memory card 1A. These pads 9 and the pads 6 of the memory chip M1 are connected by Au wires 13. Electrically connected. That is, the lowermost memory chip M1 is mounted on the wiring board 2 in a state shifted by a predetermined distance in the direction of the front end of the memory card 1A so as not to overlap the pad 9 of the wiring board 2.

  On the other hand, in the three memory chips M2 to M4 stacked on the memory chip M1, the short side on the side where the pad 6 is formed is positioned at the tip of the memory card 1A, contrary to the memory chip M1. Is arranged. The memory chip M2 is mounted on the memory chip M1 in a state shifted by a predetermined distance in the direction of the front end of the memory card 1A so that the pad 6 of the lower-layer memory chip M1 is exposed. Similarly, the memory chips M3 and M4 are stacked in a state shifted by a predetermined distance in the direction of the rear end of the memory card 1A so that the pads 6 of the memory chip M2 and the pads 6 of the memory chip M3 are respectively exposed. .

  When the memory chips M1 to M4 are stacked as described above, one end of each of the memory chips M1, M2, and M3 (one end on the front end side of the memory card 1A) protrudes outside the end portion of the wiring board 2. become. However, as described above, the tip end side of the memory card 1A is taper-processed on the mold resin 5, and the central portion in the thickness direction of the mold resin 5 projects laterally from the upper and lower portions. Even if the end portions of the memory chips M1, M2, and M3 protrude from the end portions of the wiring substrate 2, they are not exposed to the outside of the mold resin 5.

  4A and 4B show a memory card in which four memory chips M1 to M4 are stacked by a method different from the above and sealed with a mold resin 5 having the same dimensions as the mold resin 5 of the memory card 1A. A cross section is shown.

  4A shows an example in which the memory chips M1 and M3 and the memory chips M2 and M4 are arranged in opposite directions, and the memory chips M1 to M4 are alternately shifted in the long side direction of the wiring board 2 and stacked. . In this case, since it is necessary to provide the pads 9 on the front end side and the rear end side of the memory card 1A on the wiring board 2A, the dimension in the long side direction is longer than that of the wiring board 2 of the present embodiment. Thus, it is exposed to the outside of the mold resin 5.

  In FIG. 4B, the four memory chips M1 to M4 are arranged in the same direction, and are shifted by a predetermined distance toward the rear end of the memory card so that the respective pads 6 of the memory chips M2 to M4 are exposed. This is an example of stacking. In this case, the wiring board 2B may have the same dimensions as the wiring board 2 of the present embodiment, but from one end of the lowermost memory chip M1 (the front end side of the memory card) to the other end of the uppermost memory chip M4 ( Since the distance to the rear end side of the memory card becomes longer, the memory chips M1 to M4 are exposed to the outside of the mold resin 5.

  On the other hand, in the present embodiment, the lowermost memory chip M1 is connected to the pad 9 provided on one short side of the wiring board 2, and the memory chips M2 to M4 above the lowermost layer are connected to the wiring board. 2 is not connected to the pad 9 on the short side. That is, the memory chips M2 to M4 above the lowermost layer are connected via the pad 9 provided on one long side of the wiring board 2 and the interposer 4 provided on the memory chip M4. Thereby, compared with the case where the pads 9 are provided on the two short sides of the wiring board 2, the pad area for one side can be reduced. Further, by providing the pad 9 on the long side of one side of the wiring board 2, it is possible to connect to the memory chips M2 to M4 above the lowermost layer.

  Also, by providing the pads 9 on one short side and one long side of the wiring board 2, compared to the case where the pads are provided on the two short sides, the same degree on the short side and the long side. Thus, it is possible to make the size of the wiring board 2 and the memory chips M1 to M4 close to each other with sufficient dimensional margin.

  In the present embodiment, the pads 6 of the lowermost memory chip M1 are arranged on one short side of the wiring board 2, and the pads 6 of the memory chips M2 to M4 other than the lowermost layer are arranged on the wiring board 2. The other short side is laminated. Further, when viewed from the wiring board 2, the first and second layer memory chips M1 and M2 are sequentially shifted in the right direction in FIG. 3 from the bottom, and the third and fourth layer memory chips M3. , M4 is shifted to the opposite side (left direction in FIG. 3). By stacking the four memory chips M1 to M4 in this way, the length in the long side direction of the stacked structure of the four memory chips M1 to M4 can be reduced. As a result, even when the chip size increases as the capacity of the flash memory formed in the memory chips M1 to M4 increases, the four memory chips M1 to M4 can be stacked and accommodated in the memory card 1A. As a result, the capacity of the memory card 1A can be increased.

In the present embodiment, as shown in FIG. 3, the outer shape of the side surface of the memory card 1A is not symmetrical. That is, the right side surface of FIG. 3 has a tapered portion, and the upper layer memory chip M2 extends to the tapered portion. On the other hand, the left side surface (the portion without the taper) in FIG. 3 does not extend as on the right side. As described above, since the memory chip M2 can be arranged in the tapered portion, it is possible to absorb the influence of the length expansion due to the shift in stacking.
<Connection with interposer>
FIG. 5 is a schematic plan view showing the connection relationship among the controller chip 3, the interposer 4, the memory chips M1 to M4, and the wiring board 2 in more detail than FIG.

  FIG. 6 is a block diagram showing a connection relationship among the controller chip 3, the interposer 4, the memory chips M1 to M4, and the wiring board 2. For simplification of the drawings, only a part of the pads (6 to 9) and signal wirings connected thereto are shown. For the sake of simplicity, only one of Vcc and Vss is illustrated as the external connection terminal 23V for power supply, but in reality, two of Vcc and Vss are provided. In addition, “memory common” shown in the figure means that each memory chip is given in common, and “memory unique” means that it is given to one of a plurality of memory chips. doing.

  FIG. 7 shows the connection relationship between the chips without showing the interposer 4. Vcc and GND (Vss) are commonly supplied to the controller chip 3 and the memory chips M1 to M4. I / Obs used for command signals, address signals, and data signals with the controller chip 3 are connected to the memory chips M1 to M4 and the controller chip 3. One of the memory chips M1 to M4 is selected by a Select signal (1 to 4) from the controller chip 3. Here, the I / Ob corresponds to the “memory common”, and the Select corresponds to the “memory unique”.

  Next, the above connection relationship will be described with reference to FIG. The memory chips M1 to M4 and the controller chip 3 are supplied with power (Vcc, Vss) via the interposer 4. That is, the power supply pad 7a1 of the controller chip 3 and the power supply pad 6a1 of the memory chips M2 to M4 are connected by the surface wiring 15a1 of the interposer 4.

  The front surface wiring 15a1 is connected to the back surface wiring 16a1 and the front surface wiring 15a2 through the via hole 17, and further connected to the front surface wiring 20a of the wiring board 2 through the Au wire 12 or the like. The front surface wiring 20a is connected to the power supply pad 9a1 of the memory chip M1, and is further connected to the external connection terminal 23 (power supply terminal) on the back surface of the wiring substrate 2 shown in FIG.

  Each of the memory chips M1 to M4 includes a memory common signal pad 6a2 used for a command signal, an address signal, and a data signal, and a chip select pad (memory specific signal pad) 6b used for a chip selection signal. In the vicinity of one long side of the interposer 4, a memory common signal pad 8a2 and a chip select pad (memory specific signal pad) 8b are arranged.

  Among the four memory chips M1 to M4, the memory common signal pads 6a2 of the memory chips M2 to M4 other than the lowermost memory chip M1 are connected to each other through the Au wire 11, and the memory of the interposer 4 is common. The signal is connected to the memory common control pad 7a2 of the controller chip 3 through the signal pad 8a2. Further, each chip select pad 6b of the memory chips M2 to M4 is connected to the memory specific control pad 7b of the controller chip 3 via the Au wire 11 and the chip select pad 8b of the interposer 4.

  On the other hand, the memory common signal pad 6 a of the memory chip M 1 is connected to the Au wires 12 and 13, the memory common signal pad 9 a 2 of the wiring board 2, and the surface wiring 20 formed along the long side of the wiring board 2. It is connected to the memory common signal pad 8a3 of the interposer 4. The memory common signal pad 8a3 is arranged in the vicinity of one short side of the interposer 4 and the memory common signal pad 8a2 and the memory common control of the controller chip 3 via the front surface wiring 15, the via hole 17 and the back surface wiring 16. It is connected to the pad 7a.

  The chip select pad 6b of the memory chip M1 includes Au wires 12 and 13, a chip select pad (memory specific signal pad) 9b of the wiring board 2, and a surface formed along the long side of the wiring board 2. It is connected to the chip select pad 8 b of the interposer 4 through the wiring 20. The chip select pad 8b is disposed near one short side of the interposer 4 and is connected to the memory specific control pad 7b of the controller chip 3 through the surface wiring 15.

  In the vicinity of one short side of the interposer 4, an external input / output pad 8c is formed together with a memory common signal pad 8a3 and a chip select pad 8b connected to the memory chip M1. The external input / output pad 7c of the controller chip 3 is connected to the external connection terminal 23 via the external input / output pad 8c of the interposer 4, the front surface wiring 20, the via hole 22 and the back surface wiring 21 of the wiring board 2. .

  As described above, in the present embodiment, one side of the long side of the interposer 4 is used for connection to the second or higher layered memory chips M2 to M4, and the other side of the long side of the interposer 4 is used as the controller chip 3. Used to connect to. Further, one side of the short side of the interposer 4 is used for connection to the wiring board. More specifically, the interposer is connected to the connection between the first-layer memory chip M1 and the controller chip 3, the power supply connection between the controller chip 3 and the memory chips M2 to M4, and the connection to the external connection terminal 23 on the back surface of the wiring board 2. One side of the short side is used.

Thus, the interposer 4 is effectively used by dividing each side of the interposer 4 to each connection partner. Further, the side (in this case, the short side) of the interposer 4 on which pads used for connection to the wiring board 2 are arranged is made closer to the side of the corresponding memory chip than the other side where the pads are provided. doing. As a result, the length of the wire connecting the interposer 4 having a large step and the wiring board 2 can be shortened, so that the connection can be stabilized.
<Interposer and chip select>
FIG. 8A is an enlarged plan view of a connection portion between the chip select pad 8b of the interposer 4 and the chip select pads 6b of the memory chips M2 to M4. As described above, when the interposer 4 is provided between the controller chip 3 and the memory chips M to M4, the pitch and layout of the pads 8 of the interposer 4 can be appropriately changed.

  Therefore, for example, as shown in FIG. 8A, the chip select pad 8b connected to the memory chip M4 is arranged in the middle, and the chip select pads 8b connected to the memory chips M2 and M3 are arranged on both sides thereof. Then, since the pitch between the Au wires 11 is widened, short-circuiting between them can be suppressed.

  On the other hand, as shown in FIG. 8B, when the memory specific control pad 7b of the controller chip 3 and the chip select pads 6b of the memory chips M2 to M4 are directly connected, the memory specific control pads 7b Since the pitch is narrow and the layout thereof cannot be changed, the pitch between the Au wires 11 is narrowed, and a short circuit is likely to occur. Thus, providing the interposer 4 between the controller chip 3 and the memory chips M2 to M4 is effective in preventing a short circuit between the Au wires 11.

(Embodiment 2)
<Memory chip stacking method>
In this embodiment, a method of stacking four memory chips different from that in Embodiment 1 is shown.
Even when the memory chips M1 to M4 are arranged and stacked as shown in FIG. 9, FIG. 10, or FIG. 11, the length of the four memory chips M1 to M4 in the long side direction can be reduced.
<Laminated structure of FIG. 9>
In the stacking method shown in FIG. 9, the memory chips M1 and M3 are arranged so that the short side on the side where the pad 6 is formed is located at the rear end of the memory card 1A. The short side on the side where the pad 6 is formed is arranged so as to be located at the tip of the memory card 1A.

  Further, the memory chips M1 and M2 are stacked on the right side of the drawing with respect to the wiring board 2. The memory chip M3 is stacked on the left side of the figure so as to substantially overlap the wiring board 2, and the memory chip M4 is stacked on the right side of the figure with respect to the memory chip M3.

  The memory chip M <b> 1 is connected to the wiring substrate 2 via the wire 13. The memory chips M2 and M4 are connected to the interposer 4 on the right side of the figure, and the memory chip M3 is connected to the interposer 4 on the left side of the figure. The interposer 4 is connected via a wire 12 on the long side of the wiring board 2.

  In this case, in order to shorten the length of the Au wire 11 connecting the memory chips M1, M3 and the interposer 4, and the length of the Au wire 11 connecting the memory chips M2, M4 and the interposer 4, respectively, the memory chip M1 The length of the interposer 4 along the long side direction of M4 is made longer than that of the first embodiment.

In this case, since the area of the interposer 4 is increased, the controller chip 3 is mounted on the surface of the interposer 4. In this laminated structure, the wires 11 can be dispersed on both the left and right sides of the figure.
<Laminated structure of FIG. 10>
In FIG. 10, the memory chip M <b> 1 and the wiring board 2 are arranged so as to substantially overlap. The memory chip M2 is connected to the interposer 4 via the memory chip M1, and the memory chips M3 and M4 are connected to the interposer 4 on the side opposite to the memory chips M1 and M2. Other parts similar to those in the stacked structure in FIG. 9 are not described.

In this stacked structure, since the memory chip M1 and the wiring substrate 2 are not directly connected, it is not necessary to provide a pad directly connected to the memory chip M1 on the short side of the wiring substrate 2.
<Laminated structure of FIG. 11>
In FIG. 11, the memory chips M1 and M2 are connected to the wiring board 2 on the left side of the figure, and the memory chips M3 and M4 are connected to the interposer 4 on the right side of the figure.

  In this stacked structure, since the two memory chips M1 and M2 are directly connected to the wiring board 2, the connection of the interposer 4 is not complicated compared to the structure in which the interposer 4 and three or more memory chips are connected.

  The common point of the stacking method of the present embodiment and the stacking method shown in FIGS. 9 to 11 is that two or three of the memory chips M2 to M4 are separated by a predetermined distance in the long side direction of the lowermost memory chip M1. They are stacked in a shifted state, and some memory chips M3 and M4 are connected to the wiring board 2 via the interposer 4. 9 and 10 are connected to the interposer 4 from the left and right sides of the figure.

(Embodiment 3)
FIG. 12 is a cross-sectional view showing the memory card of the present embodiment. In the memory card 1B, eight memory chips M1 to M8 are stacked on the surface of the wiring board 2 in the order of M1 to M8 from the lower layer.

  In each of the memory chips M1 to M8, a plurality of pads 6 are formed in the vicinity of one side (short side). The interposer 4 is mounted on the surface of the uppermost memory chip M8, and the controller chip 3 is mounted on the surface of the interposer 4. A plurality of pads 8 are formed in the vicinity of the two short sides of the interposer 4, and these pads 8 and the pads 6 of the memory chips M <b> 3 to M <b> 8 are connected by Au wires 11.

  On the other hand, the lowermost memory chip M1 and the memory chip M2 thereabove are connected to the surface wiring (not shown) of the wiring board 2 via the Au wires 13. The surface wiring is formed along one long side of the wiring substrate 2, connected to a pad (not shown) of the interposer 4 through the Au wire 12, and further connected to the controller chip 3 through the Au wire 10. It is connected to the. Although not shown, the pad of the interposer 4 to which one end of the Au wire 12 is connected is formed along the long side of the interposer 4.

  Further, a part of the pad formed along the long side of the interposer 4 is connected to the surface wiring (not shown) of the wiring board 2 through the Au wire 12, and further, this surface wiring and via holes (not shown) It is connected to the external connection terminal 23 via the back surface wiring.

  In the example shown in FIG. 12, the lower two memory chips M1 and M2 are connected to the interposer 4 through the surface wiring of the wiring board 2, and the upper memory chips M3 to M8 are not connected to the interposer 4 via the surface wiring. However, the lower three memory chips M1 to M3 are connected to the interposer 4 through the surface wiring of the wiring board 2, and the upper memory chips M4 to M8 are connected to the interposer 4 without going through the surface wiring. May be.

  Here, the stacking method in the case where the eight memory chips M1 to M8 are stacked on the surface of the wiring board 2 has been described, but in general, when a plurality of memory chips are stacked on the surface of the wiring board, the number of memory chips Is n (where n is 4 or more), the number of memory chips that are continuously shifted in the same direction is (n / 2) or less, and two or more memory chips are stacked. The length can be reduced.

  For example, when eight memory chips M1 to M8 are stacked on the surface of the wiring board 2 as in the present embodiment, the number of memory chips that are continuously shifted in the same direction is less than four and two. That is all. In the example shown in the figure, the three memory chips M1 to M3 are shifted in the direction of the front end of the memory card 1B, and the three upper memory chips M4 to M6 are shifted in the direction of the rear end of the memory card 1B. Further, the two upper memory chips M7 and M8 are arranged so as to be shifted toward the front end of the memory card 1B. In addition, the uppermost memory chip (within a group) among the memory chips that are successively shifted by a plurality of pieces has the side where the pad (within the group) is provided is opposite to the other memory chips. That is, the sides of the pads of the memory chip M3 and the memory chips M1 and M2 are reversed, and the sides of the pads of the memory chip M6 and the memory chips M4 and M5 are also reversed.

  Note that the uppermost memory chip among all the memory chips and the memory chip closest to the interposer 4 may or may not be reversed. In the example shown in the figure, the memory chip M8 and the memory chip M7 are not reversed.

  For example, as shown in FIG. 13, in the stacking method in which the memory chips M1 to M4 are alternately shifted one by one, the two upper memory chips M3 overlap above the pads 6 of the memory chip M1, so that the pads 6 of the memory chip M1 overlap. The memory chip M3 cannot be stacked until after the Au wire 13 is bonded to the substrate. On the other hand, if the number of memory chips shifted continuously in the same direction is more than (n / 2), the length of the stacked memory chips becomes long.

  As described above, the stacked structure using the interposer 4 can shorten the length when the memory chips are stacked.

(Embodiment 4)
In recent years, memory cards for mobile phones have been pursued to be smaller and thinner as represented by a micro SD card. However, on the other hand, since the memory chip accommodated in the memory card is pursued to have a large capacity, the size of the memory chip is as close as possible to the size of the wiring board of the memory card, and a plurality of memories The capacity is increased by stacking chips. On the other hand, the controller chip accommodated in the memory card tends to have a smaller chip size in order to increase the number of sheets that can be obtained from one semiconductor wafer, and the dimensional difference from the memory chip is gradually increasing. In addition, since the controller chip has a larger number of pads (bonding pads) than the memory chip, when the chip size is reduced, the pads that are conventionally arranged along one or two sides of the chip are replaced with 3 chips of the chip. It will have to be arranged along the sides or four sides.

  For this reason, in a small and thin memory card such as a micro SD card, the space for arranging the wire bonding pads on the wiring board becomes extremely narrow, and the controller chip and the wiring board are connected by wires. Has become difficult.

  In addition, when pads are arranged along three or four sides of the controller chip, when connecting the controller chip and other components (wiring board or memory card) with wires, the positions of the pads of the other components In some cases, it becomes difficult to route the wire. Even if the controller chip and other parts can be connected with a wire, the wire length becomes long, so that the problem of bonding becomes unstable and the loop height of the wire cannot be lowered. Therefore, there arises a problem that it is difficult to reduce the thickness of the memory card.

  The present embodiment and subsequent embodiments are made to solve these problems. Hereinafter, embodiments applied to the micro SD card will be described in detail. FIG. 15A is a plan view showing the appearance (front side) of the memory card of the present embodiment, FIG. 15B is a side view of the memory card, and FIG. FIG. 16 is a plan view showing the appearance (back side), FIG. 16 is a plan view showing the wiring board of the memory card, and FIG. 17 is a cross-sectional view showing the wiring board of the memory card.

  The memory card 1B of the present embodiment is composed of a synthetic resin cap 30 and a wiring board 2C accommodated in the cap 30, and the outer dimensions of the long side x short side are 15 mm x 11 mm, The thickness is 1.0 mm excluding the portion where the protrusion 31 is formed. Although not shown, the product name, manufacturer, storage capacity, and the like are printed on the surface of the cap 30 which is the surface of the memory card 1B. The protrusion 31 is provided along one side (short side) of the cap 30 that becomes the rear end when the memory card 1B is inserted into the card slot of the mobile phone. By providing the protrusions 31, it becomes easy to insert the memory card 1 </ b> B into the card slot or remove it from the card slot.

  The wiring board 2C accommodated in the cap 30 is mainly composed of glass epoxy resin, and on its main surface (front surface), there are two memory chips M1, M2, one controller chip 3, and One interposer 4 is mounted. A small passive element such as a chip capacitor 24 is mounted on the main surface of the wiring board 2C as necessary.

  As shown in FIG. 17, the main surface of the wiring substrate 2 </ b> C is covered with a mold resin 5 that seals the memory chips M <b> 1 and M <b> 2, the controller chip 3, and the interposer 4. The mold resin 5 is made of, for example, a thermosetting epoxy resin to which a quartz filler is added. The thickness of the wiring board 2C is about 0.2 mm, and the combined thickness of the wiring board 2C and the mold resin 5 is about 0.7 mm.

  The back surface of the wiring board 2C is not covered with the cap 30, and is exposed on the back surface side of the memory card 1B. As shown in FIG. 15C, eight external connection terminals 23 are formed on the back surface of the wiring board 2C. These external connection terminals 23 include, for example, one power supply terminal (Vdd), one ground terminal (Vss), one command terminal (CMD), one clock terminal (CLK), and four data. It consists of input / output terminals (I / O). These external connection terminals 23 are connected to the interposer 4 through backside wiring, via holes, front surface wiring and the like (not shown) formed on the wiring board 2C, similarly to the memory card 1A of the first embodiment. Further, it is electrically connected to the controller chip 3 and the memory chips M1 and M2. In addition, these external connection terminals 23, like the external connection terminals 23 formed on the memory card 1A of the first embodiment, have one side (short side) that becomes the tip when the memory card 1B is inserted into the card slot of the mobile phone. ). Accordingly, when the memory card 1B is inserted into the card slot of the mobile phone, the connector terminal built in the card slot and the external connection terminal 23 come into contact with each other, and exchange of signals and power supply between the memory card 1B and the mobile phone are made. Supply is made.

  As shown in FIG. 16, the two memory chips M1 and M2 mounted on the main surface of the wiring board 2C have the long side facing the same direction as the long side of the wiring board 2C. The wiring board 2C is mounted on the board so that the long side thereof faces the same direction as the long side of the memory card 1B. In the vicinity of one side (short side) of each main surface of each of the memory chips M1 and M2, a plurality of pads (terminals) 6 connected to the memory cell (circuit) portion in the chip are formed. Each of M2 is arranged so that the short side on the side where these pads 6 are formed is located at the tip of the memory card 1B. Therefore, the memory chip M2 stacked on the memory chip M1 is such that the pad 6 of the lower memory chip M1 is exposed, and the rear end of the memory chip M1 does not exceed the rear end of the memory card 1B. Are mounted on the memory chip M1 in a state of being shifted toward the rear end of the memory card 1B.

  For example, an electrically erasable and writable nonvolatile memory (flash memory) having a storage capacity of 8 gigabits is formed on each main surface of the memory chips M1 and M2. Therefore, the memory card 1B of the present embodiment on which the two memory chips M1 and M2 are mounted has a storage capacity of 8 gigabits × 2 = 16 gigabits (2 gigabytes).

  An interposer 4 is mounted on the upper memory chip M2. The interposer 4 is made of, for example, a glass epoxy resin substrate having a thickness of about 0.09 mm on which two layers of wiring are formed. The interposer 4 has a long side that is slightly shorter than the short sides of the memory chips M1 and M2. The interposer 4 is arranged on the memory chip M2 so that one of the long sides is located in the vicinity of the pad 6 of the memory chip M2. Has been implemented. A plurality of pads 8 are formed in a row near the long side of the interposer 4, and these pads 8 and the pads 6 of the memory chip M 2 are electrically connected via Au wires 11. Further, the pad 6 of the lower layer memory chip M1 and the pad 6 of the upper layer memory chip M2 are electrically connected via an Au wire 11. That is, the two memory chips M <b> 1 and M <b> 2 are electrically connected to each other via the Au wire 11 and electrically connected to the interposer 4. When the memory chips M1 and M2 and the interposer 4 are electrically connected by the Au wire 11, the length of the Au wire 11 can be increased by arranging the pad 8 of the interposer 4 in the vicinity of the pad 6 of the memory chip M2 as described above. Therefore, the loop height of the Au wire 11 can be reduced.

  A controller chip 3 is mounted on the interposer 4. The controller chip 3 is made of a rectangular silicon chip, and its thickness is about 0.1 mm. A plurality of pads 7 are formed on the controller chip 3 along three sides of the main surface. On the other hand, the interposer 4 is formed with a plurality of pads 8 along the plurality of pads 7 of the controller chip 3, and these pads 8 and the pads 7 of the controller chip 3 are electrically connected via Au wires 10. It is connected.

  When the controller chip 3 and the interposer 4 are electrically connected by the Au wire 10, the controller chip 3 is mounted on the interposer 4 and the pads 8 of the interposer 4 are disposed in the vicinity of the controller chip 3 as described above. Thus, the length of the Au wire 10 that electrically connects the controller chip 3 having the plurality of pads 7 formed along the three sides and the interposer 4 can be shortened. Can be lowered.

  A plurality of pads 9 are formed along one of the long sides of the main surface of the wiring board 2C. Although not shown, these pads 9 are connected to the external connection terminals 23 through the front surface wirings, via holes and back surface wirings formed on the wiring board 2C as in the memory card 1A of the first embodiment. On the other hand, a plurality of pads 8 are formed in the vicinity of these pads 9 in the interposer 4, and these pads 8 and the pads 9 on the wiring board 2 </ b> C are electrically connected via Au wires 12. . When the wiring board 2C and the interposer 4 are electrically connected by the Au wire 12, the length of the Au wire 12 is reduced by arranging the pad 8 of the interposer 4 in the vicinity of the pad 9 of the wiring board 2C as described above. Since it can be shortened, the loop height of the Au wire 12 can be lowered.

  As shown in FIG. 16, a slight protrusion is provided on one of the long sides of the wiring board 2C. Further, since most of the main surface of the wiring board 2C is occupied by the memory chips M1 and M2, there is no spacer for arranging the pads 9 in the area excluding the protruding portion. Therefore, the memory card 1B according to the present embodiment uses a slight protruding portion provided on one of the long sides of the wiring board 2C, and the pad 9 and a small passive element (chip capacitor 24) are arranged there. Yes. The pad 8 of the interposer 4 is disposed in the vicinity of the pad 9 and the pad 9 and the pad 8 are electrically connected via the Au wire 12.

  FIG. 18 is a circuit diagram schematically showing a connection relationship among the wiring board 2C, the memory chips M1 and M2, the controller chip 3, and the interposer 4.

  In the interposer 4, two layers of wirings 15 and 16 are formed as in the interposer 4 of the first embodiment. The memory chips M1 and M2, the controller chip 3 and the wiring board 2C are electrically connected to each other via the wirings 15 and 16 of the interposer 4. Therefore, as with the memory card 1A of the first embodiment, by changing the layout of the pads 8 and the wirings 15 and 16 of the interposer 4, the order of signals inputted to and outputted from the interposer 4 can be changed and the pad pitch can be changed. You can do it. As a result, the degree of freedom in wiring design is improved as compared with the case where the memory chips M1 and M2, the controller chip 3 and the wiring board 2C are connected to each other via the wiring formed on the wiring board 2C. Large area memory chips M1 and M2 can be mounted on the wiring board 2C.

  Further, as described above, the controller chip 3 is mounted on the interposer 4 and the pads 8 of the interposer 4 are disposed in the vicinity of the controller chip 3 so that the pads 7 are formed along the three sides. The length of the Au wire 10 that electrically connects the interposer 4 and the interposer 4 can be shortened. As a result, the memory chips M1 and M2, the controller chip 3, and the interposer 4 can be stacked and mounted on the extremely thin wiring board 2C having a thickness combined with the mold resin 5 of about 0.7 mm.

  In addition to the glass epoxy resin substrate on which the two-layer wiring is formed, the interposer 4 can be constituted by, for example, a silicon chip or a flexible resin substrate on which the two-layer wiring is formed. In addition, when the interconnection of the wiring board 2C, the memory chips M1 and M2, and the controller chip 3 is not complicated, an interposer having a single-layer wiring structure can be used.

  In the present embodiment, the case where the controller chip 3 in which the plurality of pads 7 are formed along the three sides is mounted has been described. However, the controller chip 3 in which the plurality of pads 7 are formed along the four sides is described. It can also be applied to mounting. That is, as shown in FIGS. 19 and 20, the controller chip 3 having a plurality of pads 7 formed along the four sides is mounted on the interposer 4, and the pads 8 of the interposer 4 are connected to the pads 7 of the controller chip 3. By arranging in the vicinity, the same effects as those described above can be obtained.

  In the memory card 1B of the present embodiment, the memory chips M1 and M2 and the controller chip 3 are connected in a closed area inside the interposer 4. Therefore, the number of pads 9 on the wiring board 2C connected to the interposer 4 is eight (one power supply terminal (Vdd), one ground terminal (Vss), one command terminal (CMD), one piece The number of clock terminals (CLK) and four data input / output terminals (I / O) can be reduced. As a result, the pad 9 can be disposed on the protruding portion of a small area provided on one of the long sides of the wiring board 2C.

  Further, when the manufacturers of the memory chips M1 and M2 and the controller chip 3 are changed according to the type of the memory card 1B or when there are a plurality of manufacturers, the chip size and the pad arrangement also differ. However, even in such a case, according to the configuration of the present embodiment described above, it is possible to cope with the type by simply changing the specifications of the interposer 4, and the wiring board 2C can be used in common even if the type is changed. can do.

(Embodiment 5)
The present embodiment is applied to a micro SD card as in the fourth embodiment. FIG. 21 is a plan view showing a wiring board of the memory card, and FIG. 22 is a cross-sectional view showing the wiring board of the memory card.

  In the memory card 1B of the fourth embodiment, the controller chip 3 is mounted on the interposer 4, but in the memory card of the present embodiment, the controller chip 3 and the interposer 4 are mounted side by side on the memory chip M2. There is a special feature.

  As shown in FIG. 21, the interposer 4 has a U-shaped planar shape, and the controller chip 3 is arranged inside a region surrounded by the U-shape of the interposer 4 and mounted side by side with the interposer 4. Has been. Similar to the interposer 4 of the fourth embodiment, the interposer 4 is formed of, for example, a glass epoxy resin substrate having a thickness of about 0.09 mm on which two layers of wiring are formed.

  The interposer 4 has a long side slightly shorter than the short sides of the memory chips M1 and M2, and is mounted on the memory chip M2 so that the long side is located in the vicinity of the pad 6 of the memory chip M2. ing. A plurality of pads 8 are formed in a row near the long side of the interposer 4, and these pads 8 and the pads 6 of the memory chip M 2 are electrically connected via Au wires 11. Further, the pad 6 of the lower layer memory chip M1 and the pad 6 of the upper layer memory chip M2 are electrically connected via an Au wire 11. That is, the two memory chips M <b> 1 and M <b> 2 are electrically connected to each other via the Au wire 11 and electrically connected to the interposer 4. When the memory chips M1 and M2 and the interposer 4 are electrically connected by the Au wire 11, the length of the Au wire 11 can be increased by arranging the pad 8 of the interposer 4 in the vicinity of the pad 6 of the memory chip M2 as described above. Therefore, the loop height of the Au wire 11 can be reduced.

  The controller chip 3 arranged inside the area surrounded by the U-shape of the interposer 4 is made of a rectangular silicon chip, and its thickness is about 0.1 mm. The controller chip 3 has a plurality of pads 7 formed along three sides of the main surface. On the other hand, the interposer 4 is formed with a plurality of pads 8 along the plurality of pads 7 of the controller chip 3, and these pads 8 and the pads 7 of the controller chip 3 are electrically connected via Au wires 10. It is connected. When the controller chip 3 and the interposer 4 are electrically connected by the Au wire 10, as described above, the controller chip 3 is disposed inside the area surrounded by the U-shape of the interposer 4, and the pad 8 of the interposer 4 is disposed. By arranging in the vicinity of the controller chip 3, the length of the Au wire 10 that electrically connects the controller chip 3 having the plurality of pads 7 formed along the three sides and the interposer 4 can be shortened. The loop height of the Au wire 10 can be reduced.

  A plurality of pads 9 are formed along one of the long sides of the main surface of the wiring board 2C. Although not shown, these pads 9 are connected to the external connection terminals 23 through the front surface wiring, via holes and back surface wiring formed on the wiring substrate 2C, as in the memory card 1B of the fourth embodiment. On the other hand, a plurality of pads 8 are formed in the vicinity of these pads 9 in the interposer 4, and these pads 8 and the pads 9 on the wiring board 2 </ b> C are electrically connected via Au wires 12. . When the wiring board 2C and the interposer 4 are electrically connected by the Au wire 12, the length of the Au wire 12 is reduced by arranging the pad 8 of the interposer 4 in the vicinity of the pad 9 of the wiring board 2C as described above. Since it can be shortened, the loop height of the Au wire 12 can be lowered.

  Although illustration is omitted, the interposer 4 is formed with two layers of wiring as in the case of the interposer 4 of the fourth embodiment. The memory chips M1 and M2, the controller chip 3, and the wiring board 2C are electrically connected to each other through the wiring of the interposer 4. Therefore, like the memory card 1B of the fourth embodiment, the order of signals input to and output from the interposer 4 is changed and the pad pitch is changed by changing the layout of the pads 8 and wiring of the interposer 4. be able to. As a result, the degree of freedom in wiring design is improved as compared with the case where the memory chips M1 and M2, the controller chip 3 and the wiring board 2C are connected to each other via the wiring formed on the wiring board 2C. Large area memory chips M1 and M2 can be mounted on the wiring board 2C.

  Further, as described above, the interposer 4 has a U-shaped planar shape, and the controller chip 3 is arranged inside the area surrounded by the U-shaped, thereby forming a plurality of pads 7 along the three sides. Thus, the loop height of the Au wire 10 connecting the controller chip 3 and the interposer 4 can be reduced. Further, unlike the fourth embodiment in which the controller chip 3 is mounted on the interposer 4, the controller chip 3 and the interposer 4 are mounted side by side on the memory chip M2, so that the main surface of the wiring board 2C is Au. The height to the top of the loop of the wire 10 can be reduced. This makes it easy to stack and mount the memory chips M1, M2, the controller chip 3, and the interposer 4 on the extremely thin wiring board 2C having a combined thickness of about 0.7 mm with the mold resin 5.

  In the present embodiment, the case where the controller chip 3 in which the plurality of pads 7 are formed along the three sides is mounted has been described. However, the controller chip 3 in which the plurality of pads 7 are formed along the four sides is described. It can also be applied to mounting. In this case, as shown in FIGS. 23 and 24, an interposer 4 having a square planar shape is used. That is, a rectangular opening slightly larger than the controller chip 3 is provided inside the interposer 4, the controller chip 3 is arranged inside the opening, and the pads 8 are arranged along the opening, thereby making the above-described case. An effect similar to the effect can be obtained.

  The interposer 4 having a U-shaped planar shape can be manufactured by the following method as an example. FIG. 25 is a plan view of the map substrate 33 used for manufacturing the interposer 4. The map substrate 33 is a glass epoxy resin substrate having a larger area than the interposer 4, and a plurality of units of pads 8 and wirings are formed along the horizontal and vertical directions in the figure. A region indicated by a two-dot chain line in the figure indicates a region (one unit) to be one interposer 4. On this map substrate 33, for example, 10 units of pads 8 and wirings are formed in the horizontal direction and 4 units in the vertical direction. Therefore, 10 × 4 = 40 interposers 4 can be acquired from the map substrate 33.

  In order to fabricate the interposer 4 from the map substrate 33, first, as shown in FIG. 26, a double-sided adhesive tape 34 having a thickness of 10 μm to 20 μm called a die attach film is attached to the back surface of the map substrate 33. The double-sided adhesive tape 34 is a tape that becomes sticky when heated. The double-sided adhesive tape 34 is attached to the back surface of the map substrate 33 by heating the double-sided adhesive tape 34 under the map substrate 33. be able to.

  Next, in this state, the map substrate 33 is irradiated with a laser beam from above, and each unit is cut into a U-shape. At this time, the double-sided adhesive tape 34 attached to the back surface of the map substrate 33 may be cut at the same time, but here, only the map substrate 33 is cut by adjusting the energy of the laser beam, and the double-sided adhesive on the back surface. The tape 34 is not cut.

  Next, as shown in FIG. 27, the map substrate 33 is cut linearly in the horizontal direction and the vertical direction along the boundary portion of each unit. When the map substrate 33 is cut linearly, a dicing blade having a cutting speed faster than the laser beam is used, and the double-sided adhesive tape 34 attached to the back surface of the map substrate 33 is also cut simultaneously. The map substrate 33 may be cut in a straight line with a dicing blade and then cut in a U-shape with a laser beam. However, when the map substrate 33 is cut in a straight line, the units are separated from each other and are restored to their original shapes. Since it shifts from the position, it can be cut with high accuracy when it is cut into a U-shape and then cut into a straight line. Through the steps so far, a plurality of interposers 4 having the double-sided adhesive tape 34 attached to the back surface can be produced.

  Further, a laser beam may be used when cutting the map substrate 33 in a straight line, and in this case, only one type of apparatus for cutting the map substrate 33 is sufficient. In this case as well, when cutting each unit into a U-shape, the energy of the laser beam is lowered to cut only the map substrate 33, and when cutting each unit linearly, the energy is increased and the double-sided adhesive tape 34 is also simultaneously cut. Disconnect.

  Next, as shown in FIG. 28, after the interposer 4 is positioned on the memory chips M1 and M2 mounted on the wiring board 2C, the wiring board 2C is heated, thereby the memory via the double-sided adhesive tape 34. The interposer 4 is mounted on the chip M2. At this time, the double-sided adhesive tape 34 is exposed inside the area surrounded by the U-shape of the interposer 4.

  Next, as shown in FIG. 29, the controller chip 3 is positioned on the double-sided adhesive tape 34, and then the wiring board 2C is heated, whereby the controller chip 3 is placed on the memory chip M2 via the double-sided adhesive tape 34. 3 can be implemented. As described above, when the interposer 4 is manufactured by dividing the map substrate 33 into individual pieces, the process of mounting the controller chip 3 by leaving the double-sided adhesive tape 34 inside the area surrounded by the U-shape. It can be simplified.

  Thereafter, as shown in FIG. 30, the wiring board 2C is transported to the wire bonding process, and the pad 8 of the interposer 4, the pad 7 of the controller chip 3, the pad 6 of the memory chips M1 and M2, and the pad 9 of the wiring board 2C Are electrically connected by Au wires 10, 11 and 12, respectively.

  Here, the manufacturing method of the interposer 4 having a U-shaped planar shape has been described. However, the interposer 4 having a rectangular-shaped planar shape as shown in FIG. 23 is also manufactured by the same method as described above. Can do.

  Here, the case where the double-sided adhesive tape 34 is attached to the back surface of the map substrate 33 when the map substrate 33 is cut with a dicing blade or a laser beam has been described. However, in this case, when the interposer 4 obtained from the map substrate 33 is inspected and a defect is found in a part thereof, the defective interposer 4 and the double-sided adhesive tape 34 adhered to the back surface thereof must be discarded together. Therefore, the double-sided adhesive tape 34 is wasted. Therefore, after the map substrate 33 is cut without attaching the double-sided adhesive tape 34 to the back surface, an adhesive may be applied to the back surface of the interposer 4 and mounted on the memory chip M2.

  As yet another method, as shown in FIG. 31, a rectangular double-sided adhesive tape 34 is previously bonded onto the memory chip M2, and then the map substrate 33 is cut as shown in FIG. The interposer 4 obtained in this manner is bonded onto the double-sided adhesive tape 34, and as shown in FIG. 33, the double-sided adhesive tape 34 that is exposed inside the area surrounded by the U-shape of the interposer 4 is attached. Alternatively, the controller chip 3 may be bonded. By doing in this way, it can prevent that the double-sided adhesive tape 34 is consumed wastefully.

  Here, an example in which the interposer 4 having a U-shaped planar shape is used has been described. However, even when the interposer 4 having a rectangular-shaped planar shape as shown in FIG. 23 is used, the memory chip M2 is used in advance. By adhering the double-sided adhesive tape 34 on top, it is possible to prevent the double-sided adhesive tape 34 from being wasted.

  In FIG. 34, the interposer 4 having a U-shaped planar shape is not used, but the three interposers 4a, 4b, and 4c having a rectangular planar shape are mounted on the memory chip M2 in a U-shaped combination. Then, the controller chip 3 is arranged inside the area surrounded by the U-shape. In this case, since the three interposers 4a, 4b, and 4c are different from each other in the number and arrangement of pads and the wiring pattern, three types of interposers 4a, 4b, and 4c are produced from three types of map substrates. In this case, since the planar shapes of the interposers 4a, 4b, and 4c are all rectangular, when the map substrate is cut, it is only necessary to cut it straight with a dicing blade. It can be simplified.

  Also, when mounting the controller chip 3 in which a plurality of pads 7 are formed along the four sides, the interposer 4 having a square-shaped planar shape as shown in FIG. 23 is not used. As shown in FIG. 35, after four interposers 4d, 4e, 4f, and 4g having a rectangular planar shape are combined in a square shape and mounted on the memory chip M2, the inside of the region surrounded by the square shape Alternatively, the controller chip 3 may be disposed.

(Embodiment 6)
36 is a plan view showing the wiring board of the memory card of the present embodiment, FIG. 37 is a cross-sectional view showing the wiring board of the memory card, and FIG. 38 is a wiring board, memory chip, and controller chip of the memory card. FIG. 3 is a circuit diagram schematically showing a connection relationship between the interposer and the interposer.

  For example, even if the generation of the wafer process advances and the memory chip has the same storage capacity, if the chip size becomes smaller than the previous generation, not only the long side of the wiring board 2C of the memory card but also the pad on the short side 9 can be arranged, so that the following mounting structure is possible.

  A plurality of pads 9 are respectively formed on one of the long sides and one of the short sides of the wiring board 2C. Two memory chips M1 and M2 are mounted on the main surface of the wiring board 2C, and the memory chip M2 is stacked on the memory chip M1. An interposer 4 is mounted on the upper memory chip M2, and a controller chip 3 is mounted on the interposer 4.

  The memory chips M1 and M2, the interposer 4 and the controller chip 3 have a rectangular planar shape, and are arranged so that the long sides thereof face the same direction. The interposer 4 and the controller chip 3 have their long sides. Are stacked so as to overlap one of the long sides of the memory chips M1 and M2.

  The pad 6 formed along the short side of each of the two memory chips M1 and M2 is electrically connected to the short side pad 9 of the wiring board 2C via the Au wire 11.

  Pads 7 are formed on the main surface of the controller chip 3 along its three sides (one long side and two short sides). The pad 7 formed along the long side of the controller chip 3 is electrically connected to the long side pad 9 of the wiring board 2 </ b> C via the Au wire 14. The pads 7 formed along the two short sides of the controller chip 3 are electrically connected to the pads 8 of the interposer 4 through Au wires 10. These pads 8 are connected to one end of the wiring 18 of the interposer 4 for converting the short side pad 7 of the controller chip 3 by 90 degrees, and the pad 8 formed at the other end of the wiring 18 and the pad 8. It is electrically connected to the pad 9 on the long side of the wiring board 2C through the Au wire 12 connected to the wiring board 2C.

  According to the present embodiment configured as described above, it is possible to simplify the routing of wiring while reducing the size of the interposer 4.

(Embodiment 7)
FIG. 39 is a plan view showing a wiring board of the memory card of the present embodiment. The memory card of the present embodiment is mounted in a state where four memory chips M1, M2, M3, and M4 are stacked on the main surface of the wiring board 2C. Two controller chips 3 are mounted on the uppermost memory chip M4. As described above, when the number of memory chips mounted on the main surface of the wiring board 2C increases, in order to prevent a decrease in access speed between the memory chip and the controller chip, the two controller chips 3 on the memory chip M4. Is required to be implemented.

  As shown in FIG. 39, in the memory card of the present embodiment, two interposers 4 having a U-shaped planar shape are mounted on the uppermost memory chip M4, and each interposer 4 has a U-shaped configuration. The controller chip 3 is arranged inside the enclosed area. One interposer 4 and the other interposer 4 are electrically connected via an Au wire 19.

  According to the present embodiment configured as described above, the same effect as in the fifth embodiment can be obtained, so that two controller chips 3 can be mounted on the memory chip M4.

  Further, instead of using two interposers 4 having a U-shaped planar shape, as shown in FIG. 40, three interposers 4a, 4b, 4c having a rectangular planar shape and three interposers 4h, 4i. 4j can be combined in a U-shape and mounted on the memory chip M4, and the same effect can be obtained even when the controller chip 3 is arranged inside the area surrounded by the U-shape.

  Here, the case where two controller chips 3 each having the pads 7 formed on the three sides are mounted has been described. However, when two controller chips 3 each having the pads 7 formed on the four sides are mounted, FIG. By using two interposers 4 having a square shape as shown in the figure, two controller chips 3 can be mounted on the memory chip M4.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the flash memory chip provided with the pad on one of the short sides is stacked, but the present invention can also be applied to the case where the flash memory chip provided with the pad on one of the long sides is stacked. Further, the present invention can also be applied to a case where rewiring is formed on a flash memory chip having pads on two opposite sides and the pads are concentrated on one side.

  In the fourth to seventh embodiments, the case where two or four memory chips are stacked has been described. However, the present invention can be applied to a memory card in which more memory chips are stacked. In that case, by adopting the various stacking methods described in the first to third embodiments, it is possible to stack a large number of memory chips on a wiring board having a limited size.

  Further, when the flash memory chip is stacked on the wiring board, a spacer chip may be provided between the wiring board and the flash memory chip, or between the lower flash memory chip and the upper flash memory chip.

  In the above-described embodiment, the case where the present invention is applied to a memory card has been described. For example, as shown in FIG. 41, a plurality of memory chips M1, M2 are provided on a wiring substrate 2C having a large number of bump electrodes 40 connected to the lower surface. Further, the present invention can be applied to a semiconductor device having a package form other than a memory card, such as a system in package (SIP) having a ball grid array (BGA) structure in which a controller chip 3 is stacked.

  Further, the memory chip is not limited to the flash memory chip, and can be applied when other memory chips such as DRAM are mounted. The number of memory chips mounted on the wiring board may be one or more.

  In the first to third embodiments, when the controller chip 3 is custom designed in accordance with the specifications of the memory chips M2 to M4, and the controller chip 3 is directly connected to the memory chips M2 to M4 and the wiring board 2. The interposer 4 can be dispensed with. In this case, as shown in FIG. 14, a pad 7 for connecting to the memory chips M2 to M4 is arranged on one side of the controller chip 3, and one side orthogonal to the one side (parallel to the long side of the memory chips M2 to M4). A pad 7 for connecting to the wiring board 2 is arranged on the side. Thereby, the number of parts and the number of assembly steps of the memory card 1A can be reduced.

  The present invention can be applied to a semiconductor device in which a memory chip and a controller chip are stacked on a wiring board.

1A, 1B Memory card 2, 2A, 2B, 2C Wiring board 3 Controller chip 4, 4a-4j Interposer 5 Mold resin 5A Concave groove 6 Pad 6a Memory common signal pad 6b Chip select pad 7 Pad 7a Memory common control pad 7b Memory specific control pad 7c External input / output pad 8 Pad 8a Memory common signal pad 8b Chip select pad (memory specific signal pad)
8c External input / output pad 9 Pad 9a Memory common signal pad 9b Chip select pad (memory specific signal pad)
10, 11, 12, 13, 14, 19 Au wires 15, 15a1 Front wiring 16 Back wiring 17 Via hole 18 Wiring 20 Front wiring 21 Back wiring 22 Via hole 23 External connection terminal 24 Chip capacitor 30 Cap 31 Protrusion 33 Map substrate 34 Double-sided adhesion Tape 40 Bump electrodes M1 to M8 Memory chip

Claims (10)

The main surface has a back surface opposite to the main surface, the main surface intersecting the first long side, the second long side opposite to the first long side, and the first and second long sides. A wiring board including a first short side and a second short side opposite to the first short side, wherein the first long side includes a straight portion and a protruding portion, and an external connection terminal is formed on the back surface When,
Mounted on the main surface of the wiring board, and arranged to face the first long side, the second long side, the first short side, and the second short side of the wiring board in plan view, respectively. A memory chip having one long side, a second long side, a first short side and a second short side;
A controller chip for controlling the memory chip mounted on the memory chip;
With
On the main surface of the wiring board, a first terminal and a second terminal are formed between a first long side of the memory chip and a protruding portion of the wiring board,
A third terminal and a fourth terminal are formed on the controller chip along the first long side of the memory chip,
A fifth terminal is formed on the main surface of the wiring board between the first short side of the memory chip and the first short side of the wiring board.
A sixth terminal is formed on the memory chip closer to the first short side of the memory chip than the second short side of the memory chip;
The first terminal formed on the main surface of the wiring board is electrically connected to the third terminal formed on the controller chip via a first wire;
The second terminal formed on the main surface of the wiring board is electrically connected to the fourth terminal formed on the controller chip via a second wire;
The fifth terminal formed on the main surface of the wiring board is electrically connected to the sixth terminal formed on the memory chip via a third wire,
The fifth terminal is electrically connected to the first terminal;
The external connection terminal is electrically connected to the second terminal;
The first long side of the memory chip is close to the first long side in the straight portion of the wiring board,
A second long side of the memory chip is close to a second long side of the wiring board; a second short side of the memory chip is close to a second short side of the wiring board;
Between the first long side of the memory chip and the first long side of the straight portion of the wiring board, between the second long side of the memory chip and the second long side of the wiring board, and the first of the memory chip. A semiconductor device in which a terminal on the wiring board is not formed between two short sides and the second short side of the wiring board.   2. The semiconductor according to claim 1, wherein a passive element is disposed on the main surface of the wiring board between a first long side of the memory chip and a first long side of a protruding portion of the wiring board. apparatus.   The semiconductor device according to claim 2, wherein the passive element is a chip capacitor.   The semiconductor device according to claim 2, wherein the plurality of first terminals are disposed between a first long side of the memory chip and the passive element.   The semiconductor device according to claim 1, wherein the sixth terminal is disposed to face the first short side of the memory chip and faces the fifth terminal in a plan view. On the memory chip, a further memory chip having a terminal arrangement equal to the memory chip is stacked,
The semiconductor device according to claim 1, wherein the further memory chip is stacked while being shifted in the extending direction of the second long side of the memory chip so that the sixth terminal is exposed.   The semiconductor device according to claim 1, wherein the main surface of the wiring board, the memory chip, and the controller chip are sealed with resin. The protruding portion of the wiring board includes a first protruding portion and a second protruding portion,
The first projecting portion is disposed between the first short side of the wiring board and the second short side of the wiring board in a plan view.
The semiconductor device according to claim 1, wherein the second protruding portion is disposed between a second short side of the wiring board and the first protruding portion in plan view.   The passive element is disposed on the main surface of the wiring board between the first long side of the memory chip and the first long side of the second protruding portion of the wiring board. The semiconductor device described.   The semiconductor device according to claim 1, wherein an outer dimension of the wiring board is the same as an outer dimension of the wiring board of the micro SD card.