KR100688581B1 - Semiconductor chip card and manufacturing method the same - Google Patents

Semiconductor chip card and manufacturing method the same Download PDF

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Publication number
KR100688581B1
KR100688581B1 KR1020050125457A KR20050125457A KR100688581B1 KR 100688581 B1 KR100688581 B1 KR 100688581B1 KR 1020050125457 A KR1020050125457 A KR 1020050125457A KR 20050125457 A KR20050125457 A KR 20050125457A KR 100688581 B1 KR100688581 B1 KR 100688581B1
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South Korea
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semiconductor chip
printed circuit
circuit board
bonding
chip card
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KR1020050125457A
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Korean (ko)
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황태회
정종욱
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor chip card and a manufacturing method of the same are provided to increase capacity of a memory within a limited area by using a reverse bonding method. A printed circuit board(60) is used for a semiconductor chip card. A first semiconductor chip(10) is loaded on one end of the printed circuit board. A first bonding wire(63) is used for connecting electrically a bonding pad of the first semiconductor chip and an electrode pad of the printed circuit board. A second semiconductor chip(20) is loaded on the other end of the printed circuit board. A plurality of bonding pads are disposed at one side of the semiconductor chip. A second bonding wire(64) is bonded reversely from the bonding pad of the second semiconductor chip across the second semiconductor chip.

Description

반도체 칩 카드 및 그 제조방법{Semiconductor chip card and manufacturing method the same}Semiconductor chip card and manufacturing method the same

도 1은 종래 기술에 의한 반도체 칩 카드를 설명하기 위한 평면도이다.1 is a plan view for explaining a semiconductor chip card according to the prior art.

도 2는 종래 기술에 의한 다른 반도체 칩 카드를 설명하기 위한 평면도이다.2 is a plan view for explaining another semiconductor chip card according to the prior art.

도 3은 몰딩(molding) 공정이 완료된 상태의 도2의 단면도이다.FIG. 3 is a cross-sectional view of FIG. 2 with a molding process completed. FIG.

도 4는 본 발명의 일 실시예에 의한 반도체 칩 카드를 설명하기 위한 평면도이다.4 is a plan view illustrating a semiconductor chip card according to an embodiment of the present invention.

도 5는 몰딩(molding) 공정이 완료된 상태의 도 4의 단면도이다.FIG. 5 is a cross-sectional view of FIG. 4 with a molding process completed. FIG.

도 6은 도 4의 "A" 부분에 대한 확대 평면도이다.6 is an enlarged plan view of a portion “A” of FIG. 4.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10: 메모리 칩, 20:컨트롤러 칩 10: memory chip, 20: controller chip

22: 본딩 패드22: bonding pads

40, 50, 60: 인쇄회로기판, 42, 52, 62: 전극 패드40, 50, 60: printed circuit board, 42, 52, 62: electrode pad

53, 54, 63, 64: 본딩 와이어53, 54, 63, 64: bonding wire

100, 200, 300: 반도체 칩 카드, 100, 200, 300: semiconductor chip card,

본 발명은 반도체 칩 카드 및 그 제조방법에 관한 것으로, 더욱 상세하게는 메모리 칩과 컨트롤러 칩의 배치 및 전기적 연결이 개선된 반도체 칩 카드 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip card and a method of manufacturing the same, and more particularly, to a semiconductor chip card having improved arrangement and electrical connection of a memory chip and a controller chip, and a method of manufacturing the same.

현재 반도체 칩 카드는 모바일 폰(Mobile phone), 디지털 카메라, 휴대용 디지털 제품(PDA) 등에 장착되는 기록 매체로써 음악, 화상 등의 정보를 넣어 복수의 전자기기 사이에서 정보를 교환 할 수 있다. 반도체 칩 카드의 발전방향은, 다른 기능을 갖는 반도체 칩들을 효율적으로 실장하고, 고 부가가치의 패키징(Packaging)이 가능한 것에 중점을 두고 지속적으로 발전해가고 있다. 반도체 칩 카드에는 기록 기능을 갖는 메모리 칩과 이를 제어하는 컨트롤러 칩이 내장되어 있다. Currently, a semiconductor chip card is a recording medium mounted on a mobile phone, a digital camera, a portable digital product (PDA), and the like, and can exchange information between a plurality of electronic devices by inserting information such as music and images. The development direction of the semiconductor chip card is continuously developing with the emphasis on the efficient mounting of semiconductor chips having different functions and the high value-added packaging. The semiconductor chip card includes a memory chip having a write function and a controller chip for controlling the same.

도 1은 종래 기술에 의한 반도체 칩 카드를 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a semiconductor chip card according to the prior art.

도 1을 참조하면, 메모리 칩(10)과 컨트롤러로 사용되는 시스템 LSI 칩(20)이 인쇄회로기판(40)에 실장된 형태의 반도체 칩 카드(100)이다. 반도체 칩 카드(100)를 제조하기 위한 인쇄회로기판(40)의 일 표면에는 메모리 칩(10)과 컨트롤러 칩(20)을 연결하기 위한 전극 패드(41, 42)가 각각 형성되어 있다. 이러한 메모리 칩(10)과 컨트롤러 칩(20)의 배치는 인쇄회로기판(40)의 크기가 충분히 큰 경우에 주로 사용되는 경우이다.Referring to FIG. 1, a system LSI chip 20 used as a memory chip 10 and a controller is a semiconductor chip card 100 mounted on a printed circuit board 40. Electrode pads 41 and 42 for connecting the memory chip 10 and the controller chip 20 are formed on one surface of the printed circuit board 40 for manufacturing the semiconductor chip card 100. The arrangement of the memory chip 10 and the controller chip 20 is mainly used when the size of the printed circuit board 40 is large enough.

도 2는 종래 기술에 의한 다른 반도체 칩 카드를 설명하기 위한 평면도이다.2 is a plan view for explaining another semiconductor chip card according to the prior art.

도 2를 참조하면, 반도체 칩 카드(200)는, 인쇄회로기판(50) 위에서 최소한 두 개 이상의 메모리 칩(10)들이 적층된 상태로 탑재되고, 본딩 와이어(53)를 통해 상기 인쇄회로기판(50)의 전극 패드(51)와 전기적으로 연결된다. 그리고 컨트롤러 칩(20)이 상기 메모리 칩(10) 위에 다시 적층되고, 다른 본딩 와이어(54)를 통해 상기 인쇄회로기판(50)의 다른 전극 패드(52)와 전기적으로 서로 연결된다. Referring to FIG. 2, the semiconductor chip card 200 is mounted in a state in which at least two or more memory chips 10 are stacked on a printed circuit board 50, and is bonded to the printed circuit board through a bonding wire 53. It is electrically connected to the electrode pad 51 of 50. The controller chip 20 is again stacked on the memory chip 10, and is electrically connected to another electrode pad 52 of the printed circuit board 50 through another bonding wire 54.

도 3은 몰딩공정이 완료된 상태의 도 2의 단면도이다.3 is a cross-sectional view of FIG. 2 with a molding process completed.

도 3을 참조하면, 반도체 칩 카드(200)는, 0.87㎜이라는 제한된 높이 내에서 복수의 메모리 칩(10)과 컨트롤러 칩(20)을 수직 방향으로 적층되어 있다. 그러나 이러한 설계 방식은 제한된 높이와 면적내에서 메모리 칩(10)을 4개 이상 적층하여 고밀도 실장을 위해서는 높이 제한이 따른다. 도면에서 반도체 칩 카드(200)의 높이 0.87mm가 예시적으로 나타나 있다. 도면에서 참조부호 53은 상기 메모리 칩(10)을 상기 인쇄회로기판(50)과 연결하는 본딩 와이어이고, 54는 컨트롤러 칩(20)을 상기 인쇄회로기판(50)과 연결하는 다른 본딩 와이어이다.Referring to FIG. 3, the semiconductor chip card 200 has a plurality of memory chips 10 and controller chips 20 stacked in a vertical direction within a limited height of 0.87 mm. However, this design method has a height limit for high density mounting by stacking four or more memory chips 10 within a limited height and area. 0.87 mm in height of the semiconductor chip card 200 is illustrated in the drawing. In the drawing, reference numeral 53 is a bonding wire for connecting the memory chip 10 to the printed circuit board 50, and 54 is another bonding wire for connecting the controller chip 20 with the printed circuit board 50.

상세히 설명하면, 반도체 칩 카드(200)는 0.87㎜ 높이일 때, 2개의 메모리 칩(10)과 컨트롤러 칩(20)이 적층되어 탑재하는 것이 가능하다. 그러나 메모리 용량을 증가시키기 위하여 4개의 메모리 칩(10)을 적층할 수는 없다. 왜냐하면 반도체 칩 카드(200)의 높이 제한이 있기 때문이다. 따라서 메모리 칩(10)의 용량이 1기가 낸드 플래시 메모리(NAND Flash Memory)라면, 반도체 칩 카드(200)에 2기가 낸드 플래시 메모리까지는 설계가 가능하지만, 4기가 낸드 플래시 메모리는 높이 제한으로 설계가 불가능하다.In detail, when the semiconductor chip card 200 is 0.87 mm high, two memory chips 10 and a controller chip 20 may be stacked and mounted. However, four memory chips 10 may not be stacked in order to increase memory capacity. This is because there is a height limitation of the semiconductor chip card 200. Therefore, if the memory chip 10 has a capacity of 1 Gigabyte NAND Flash memory, it is possible to design up to 2 Gigabyte NAND flash memory in the semiconductor chip card 200, but the 4 Gigabyte NAND flash memory can be designed with a height limitation. impossible.

따라서 종래의 반도체 칩 카드는 제한된 크기 및 높이에 비해 메모리 칩의 용 량이 증가함에 따라 컨트롤러 칩을 실장하는데 제약이 따르는 문제점을 안고 있다.Therefore, the conventional semiconductor chip card has a problem that there is a limitation in mounting the controller chip as the capacity of the memory chip increases compared to the limited size and height.

본 발명이 이루고자 하는 기술적 과제는 상술한 문제점들을 해결할 수 있도록 컨트롤러 칩의 본딩 패드와 인쇄회로기판 상에 형성된 대응하는 전극 패드와의 사이를 연결하는 본딩 와이어를 컨트롤러 칩을 가로질러 역(Reverse)방향으로 본딩 되는 반도체 칩 카드를 제공하는데 있다.The technical problem to be solved by the present invention is to reverse the bonding wires across the controller chip to connect the bonding pads of the controller chip and the corresponding electrode pad formed on the printed circuit board to solve the above problems. To provide a semiconductor chip card that is bonded by.

본 발명이 이루고자 하는 다른 기술적 과제는 상기 반도체 칩 카드의 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing the semiconductor chip card.

상기 기술적 과제를 달성하기 위해 본 발명에 의한 반도체 칩 카드는, 반도체 칩 카드용 인쇄회로기판과, 상기 인쇄회로기판의 일단에 탑재된 제 1 반도체 칩과, 상기 제1 반도체 칩의 본딩패드와 상기 인쇄회로기판의 전극패드를 상하방향에서 서로 전기적으로 연결하는 제1 본딩와이어와, 상기 인쇄회로기판의 타단에 탑재되고, 일 측면에 다수의 본딩 패드가 배치된 제 2 반도체 칩과, 상기 제 2 반도체 칩의 본딩 패드로부터 상기 제 2 반도체 칩을 가로질러 역(Reverse)방향으로 본딩 되는 제2 본딩와이어를 구비하는 것을 특징으로 한다.In order to achieve the above technical problem, a semiconductor chip card according to the present invention includes a printed circuit board for a semiconductor chip card, a first semiconductor chip mounted on one end of the printed circuit board, a bonding pad of the first semiconductor chip, and A first bonding wire electrically connecting the electrode pads of the printed circuit board to each other in a vertical direction, a second semiconductor chip mounted on the other end of the printed circuit board, and having a plurality of bonding pads disposed on one side thereof, and the second And a second bonding wire bonded in a reverse direction from the bonding pad of the semiconductor chip to the second semiconductor chip.

본 발명의 바람직한 실시예에 의하면, 상기 반도체 칩 카드에서 상기 제1 반도체 칩은 메모리이고, 제2 반도체 칩은 컨트롤러 칩인 것이 적합하다.According to a preferred embodiment of the present invention, in the semiconductor chip card, the first semiconductor chip is a memory, and the second semiconductor chip is a controller chip.

또한 본 발명의 바람직한 실시예에 의하면, 상기 반도체 칩 카드에서 상기 인쇄회로기판 상에 형성된 상기 전극 패드는 방사형으로 배치된 것이 바람직하다.In addition, according to a preferred embodiment of the present invention, the electrode pad formed on the printed circuit board in the semiconductor chip card is preferably arranged radially.

상기 다른 기술적 과제를 달성하기 위한 본 발명에 의한 반도체 칩 카드의 제조방법은, 반도체 칩 카드용 인쇄회로기판을 준비하는 단계와, 상기 인쇄회로기판의 일단에 제1 반도체 칩을 탑재하고 제1 본딩와이어로 전기적으로 연결하는 단계와, 상기 인쇄회로기판의 타단에 상기 인쇄회로기판과 전기적으로 연결되고, 일 측면에 다수의 본딩 패드가 배치된 제 2 반도체 칩을 탑재하는 단계와, 상기 제2 반도체 칩의 본딩 패드와 상기 인쇄회로기판에 형성된 전극패드를 제2 본딩 와이어로 연결하되 상기 제2 본딩 와이어는 상기 제2 반도체 칩을 가로질러 역방향으로 본딩 하는 단계를 구비하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor chip card, including preparing a printed circuit board for a semiconductor chip card, mounting a first semiconductor chip on one end of the printed circuit board, and bonding the first bond to the printed circuit board. Electrically connecting a wire, mounting a second semiconductor chip electrically connected to the printed circuit board at the other end of the printed circuit board, and having a plurality of bonding pads disposed on one side thereof, and the second semiconductor. Connecting a bonding pad of the chip and an electrode pad formed on the printed circuit board with a second bonding wire, wherein the second bonding wire is bonded in a reverse direction across the second semiconductor chip.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다. 그러나, 아래의 상세한 설명에서 개시되는 실시 예는 본 발명을 한정하려는 의미가 아니라, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게, 본 발명의 개시가 실시 가능한 형태로 완전해지도록 발명의 범주를 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments disclosed in the following detailed description are not meant to limit the present invention, but to those skilled in the art to which the present invention pertains, the disclosure of the present invention may be completed in a form that can be implemented. It is provided to inform the category.

도 4는 본 발명의 일 실시예에 의한 반도체 칩 카드를 설명하기 위한 평면도이다.4 is a plan view illustrating a semiconductor chip card according to an embodiment of the present invention.

도 4를 참조하면, 본 발명에 의한 반도체 칩 카드(300)는, 인쇄회로기판(60) 위에서 최소한 두 개 이상의 제1 반도체 칩, 예컨대 메모리 칩(10)이 제1 본딩 와이어(63)를 통해 상기 인쇄회로기판(60)의 전극 패드(61)와 전기적으로 연결된다. 그리고 제2 반도체 칩인 컨트롤러 칩(20)이 제2 본딩 와이어(64)를 통해 상기 인쇄회로기판(60)의 대응하는 전극 패드(62)와 전기적으로 연결된다. Referring to FIG. 4, in the semiconductor chip card 300 according to the present invention, at least two or more first semiconductor chips, for example, the memory chip 10, are mounted on the printed circuit board 60 through the first bonding wire 63. The electrode pad 61 of the printed circuit board 60 is electrically connected to the electrode pad 61. The controller chip 20, which is a second semiconductor chip, is electrically connected to the corresponding electrode pad 62 of the printed circuit board 60 through the second bonding wire 64.

이러한 전극 패드(61, 62)는 상기 인쇄회로기판(60) 위에서 포토 솔더 레지스트(PSR: Photo Solder Resist)의 오프닝(opening)에 의해 형성된다. The electrode pads 61 and 62 are formed by opening a photo solder resist (PSR) on the printed circuit board 60.

상기 메모리 칩(10)은 플래시(Flash) 메모리, SDRAM, SRAM등 일 수 있으며, 이들의 적층과 조합된 적층 구조일 수 있다. 본 발명에 의하면, 상기 컨트롤러 칩(20)의 본딩패드와 전기적으로 연결되는 전극 패드(62)는 인쇄회로 기판(60)상에 메모리 칩(10)과 컨트롤러 칩(20)의 사이에서 일정한 길이로 방사형으로 배치된다.The memory chip 10 may be a flash memory, an SDRAM, an SRAM, or the like, and may have a stacked structure combined with a stack thereof. According to the present invention, the electrode pad 62 electrically connected to the bonding pad of the controller chip 20 has a predetermined length between the memory chip 10 and the controller chip 20 on the printed circuit board 60. Arranged radially.

이때 인쇄회로기판(60)은 폴리이미드 재질의 휘어질 수 있는 기판(flexible substrate) 혹은 FR4 수지, BT 수지(resin) 및 재질의 고형의 기판(rigid substrate)을 선택적으로 사용할 수 있다. In this case, the printed circuit board 60 may selectively use a flexible substrate made of polyimide or a rigid substrate made of FR4 resin, BT resin, and material.

도 4에는, 제1 반도체 칩인 메모리 칩(10) 4개가 수직으로 적층되면서, 제1 본딩 와이어(63)를 통해 인쇄회로기판(60)의 전극 패드(미도시)들과 연결도어 있다. 그리고 컨트롤러 칩(20)이 그 옆으로 탑재되고 제2 본딩와이어(64)를 통해 상기 인쇄회로기판(60)과 전기적으로 연결된 것을 보여준다.In FIG. 4, four memory chips 10, which are first semiconductor chips, are vertically stacked and connected to electrode pads (not shown) of the printed circuit board 60 through the first bonding wire 63. And it shows that the controller chip 20 is mounted to the side and electrically connected to the printed circuit board 60 through the second bonding wire (64).

본 발명은 인쇄회로기판(60)의 메모리 칩(10)이 실장된 영역 외에서 컨트롤러 칩(20)의 효율적인 실장이 가능하며 전극 패드(62)를 방사형으로 배치함으로써 거의 동일한 제2 본딩 와이어 길이를 제공한다. According to the present invention, the controller chip 20 can be efficiently mounted outside the region in which the memory chip 10 of the printed circuit board 60 is mounted, and the electrode pads 62 are radially disposed to provide almost the same second bonding wire length. do.

도 5는 몰딩(molding) 공정이 완료된 상태의 도 4의 단면도이다.FIG. 5 is a cross-sectional view of FIG. 4 with a molding process completed. FIG.

도 5를 참조하면, 본 발명에 의한 반도체 칩 카드(300)는, 제한된 높이 내에서 복수의 제1 반도체 칩, 예컨대 메모리 칩(10)을 수직 방향으로 적층한다. 그리고 제2 반도체 칩인 컨트롤러 칩(20)이 제한된 크기 내에서 수평 방향으로 실장된 다. 도 5에는 반도체 칩 카드(300)의 높이 0,87mm로 예시적으로 나타나 있다. Referring to FIG. 5, the semiconductor chip card 300 according to the present invention stacks a plurality of first semiconductor chips, for example, memory chips 10 in a vertical direction within a limited height. The controller chip 20, which is the second semiconductor chip, is mounted in a horizontal direction within a limited size. 5 exemplarily shows a height of 0,87 mm of the semiconductor chip card 300.

이렇게 메모리 칩과 컨트롤러 칩을 반도체 칩 카드의 제한된 높이와 크기 내에서 효율적으로 실장하는 것은, 인쇄회로기판(60) 상에 제1 및 제2 반도체 칩(10, 20)의 배치 및 제2 본딩와이어(64)의 역방향 본딩에 의하여 구현되고, 이것은 본 발명의 목적을 달성하는데 있어서 중대한(critical) 의미를 갖는다. The efficient mounting of the memory chip and the controller chip within the limited height and size of the semiconductor chip card may include disposing the first and second semiconductor chips 10 and 20 on the printed circuit board 60 and the second bonding wires. Implemented by reverse bonding of 64, this has a critical meaning in achieving the object of the present invention.

도 6은 도 4의 "A" 부분에 대한 확대 평면도이다.6 is an enlarged plan view of a portion “A” of FIG. 4.

도 6을 참조하면, 본 발명에 의한 반도체 칩 카드(300)는, 컨트롤러 칩(20)의 본딩 패드(22)와 전기적으로 연결되는 전극 패드(62)는 인쇄회로 기판(60)상의 메모리 칩(10)과 컨트롤러 칩(20) 사이의 인접한 영역에 방사형으로 배치된다. Referring to FIG. 6, in the semiconductor chip card 300 according to the present invention, the electrode pad 62 electrically connected to the bonding pad 22 of the controller chip 20 may include a memory chip on the printed circuit board 60. Radially disposed in an adjacent area between the 10 and the controller chip 20.

도 6에서, 컨트롤러 칩(20)의 본딩 패드(22)는 일 측면에 배치되고, 컨트롤러 칩(20)을 가로질러 역 본딩 되어 이에 대응하는 전극 패드(62)와 전기적으로 연결된다. In FIG. 6, the bonding pads 22 of the controller chip 20 are disposed on one side, reverse bonded across the controller chip 20, and electrically connected to the corresponding electrode pads 62.

도 6에는, 컨트롤러 칩(20)의 본딩 패드(22)와 이에 대응하는 전극 패드(62)를 전기적으로 연결하는 본딩 와이어(64)의 길이(Length)가 3.46mm로 예시적으로 나타나 있다. In FIG. 6, the length of the bonding wire 64 that electrically connects the bonding pad 22 of the controller chip 20 and the electrode pad 62 corresponding thereto is illustrated as 3.46 mm.

본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

따라서, 상술한 본 발명에 따르면, 메모리 칩의 적층 및 컨트롤러 칩에 대한 역방향 본딩을 활용하여 제한된 면적의 인쇄회로기판에서 반도체 칩 카드의 메모리 용량을 증가시킬 수 있다. Therefore, according to the present invention described above, it is possible to increase the memory capacity of the semiconductor chip card in a limited area printed circuit board by utilizing the stacking of the memory chip and the reverse bonding to the controller chip.

Claims (9)

반도체 칩 카드용 인쇄회로기판;       Printed circuit boards for semiconductor chip cards; 상기 인쇄회로기판의 일단에 탑재된 제 1 반도체 칩;A first semiconductor chip mounted on one end of the printed circuit board; 상기 제1 반도체 칩의 본딩패드와 상기 인쇄회로기판의 전극패드를 상하방향에서 서로 전기적으로 연결하는 제1 본딩와이어;A first bonding wire electrically connecting the bonding pad of the first semiconductor chip and the electrode pad of the printed circuit board to each other in an up and down direction; 상기 인쇄회로기판의 타단에 탑재되고, 일 측면에 다수의 본딩 패드가 배치된 제 2 반도체 칩; 및A second semiconductor chip mounted on the other end of the printed circuit board and having a plurality of bonding pads disposed on one side thereof; And 상기 제 2 반도체 칩의 본딩 패드로부터 상기 제 2 반도체 칩을 가로질러 역(Reverse)방향으로 본딩 되는 제2 본딩와이어를 구비하는 것을 특징으로 하는 반도체 칩 카드.And a second bonding wire bonded in a reverse direction across the second semiconductor chip from the bonding pad of the second semiconductor chip. 제1항에 있어서, The method of claim 1, 상기 제 1 반도체 칩은 복수 개의 반도체 칩들이 수직으로 적층된 것을 특징으로 하는 반도체 칩 카드.The first semiconductor chip is a semiconductor chip card, characterized in that a plurality of semiconductor chips are stacked vertically. 제1항에 있어서, The method of claim 1, 상기 제 1 반도체 칩은 플래시(Flash) 메모리 칩인 것을 특징으로 하는 반도체 칩 카드. And the first semiconductor chip is a flash memory chip. 제1항에 있어서, The method of claim 1, 상기 제 2 반도체 칩은 컨트롤러(Controller) 칩인 것을 특징으로 하는 반도체 칩 카드. And the second semiconductor chip is a controller chip. 제1항에 있어서, The method of claim 1, 상기 제2 반도체 칩을 전기적으로 연결하기 위하여 상기 인쇄회로기판 상에 형성된 상기 전극패드는 방사형으로 배치된 것을 특징으로 하는 반도체 칩 카드.And the electrode pad formed on the printed circuit board in a radial manner to electrically connect the second semiconductor chip. 반도체 칩 카드용 인쇄회로기판을 준비하는 단계;Preparing a printed circuit board for a semiconductor chip card; 상기 인쇄회로기판의 일단에 제1 반도체 칩을 탑재하고 제1 본딩와이어로 전기적으로 연결하는 단계;Mounting a first semiconductor chip on one end of the printed circuit board and electrically connecting the first semiconductor wire with a first bonding wire; 상기 인쇄회로기판의 타단에 상기 인쇄회로기판과 전기적으로 연결되고, 일 측면에 다수의 본딩 패드가 배치된 제 2 반도체 칩을 탑재하는 단계; Mounting a second semiconductor chip electrically connected to the printed circuit board at the other end of the printed circuit board and having a plurality of bonding pads disposed on one side thereof; 상기 제2 반도체 칩의 본딩 패드와 상기 인쇄회로기판에 형성된 전극패드를 제2 본딩 와이어로 연결하되 상기 제2 본딩 와이어는 상기 제2 반도체 칩을 가로질러 역방향으로 본딩 하는 단계를 구비하는 것을 특징으로 하는 반도체 칩 카드 제조방법.Connecting a bonding pad of the second semiconductor chip and an electrode pad formed on the printed circuit board with a second bonding wire, wherein the second bonding wire is bonded in a reverse direction across the second semiconductor chip. A semiconductor chip card manufacturing method. 제6항에 있어서, The method of claim 6, 상기 제 1 반도체 칩은 복수 개의 반도체 칩이 수직으로 적층된 것을 특징으로 하는 반도체 칩 카드 제조 방법.The first semiconductor chip is a semiconductor chip card manufacturing method, characterized in that a plurality of semiconductor chips are stacked vertically. 제6항에 있어서, The method of claim 6, 상기 인쇄회로기판 상에 형성된 상기 전극패드는 방사형으로 배치된 것을 특징으로 하는 반도체 칩 카드 제조 방법.The electrode pad formed on the printed circuit board is a semiconductor chip card manufacturing method, characterized in that arranged radially. 제6항에 있어서, The method of claim 6, 상기 제2 본딩 와이어는 상기 제 2 반도체 칩을 가로질러 상기 인쇄회로기판 상에 방사형으로 배치된 대응하는 상기 전극패드에 역(Reverse) 본딩 되는 것을 특징으로 하는 반도체 칩 카드 제조 방법. And wherein the second bonding wire is reverse bonded to a corresponding electrode pad disposed radially on the printed circuit board across the second semiconductor chip.
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US9496216B2 (en) 2011-12-22 2016-11-15 Samsung Electronics Co., Ltd. Semiconductor package including stacked semiconductor chips and a redistribution layer

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JPH04350990A (en) * 1991-05-29 1992-12-04 Fuji Electric Co Ltd Hybrid integrated circuit
JPH07297218A (en) * 1994-04-28 1995-11-10 Toshiba Corp Semiconductor device
KR20020009482A (en) * 2000-07-25 2002-02-01 니시가키 코지 Semiconductor device

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JPH04350990A (en) * 1991-05-29 1992-12-04 Fuji Electric Co Ltd Hybrid integrated circuit
JPH07297218A (en) * 1994-04-28 1995-11-10 Toshiba Corp Semiconductor device
KR20020009482A (en) * 2000-07-25 2002-02-01 니시가키 코지 Semiconductor device

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