KR200251183Y1 - Ultra-Thin Stack Package Device and Ultra-Thin Memory Card Employing Such Package Device - Google Patents

Abstract

The present invention discloses an ultra-thin stacked package device having an increased memory capacity and a very thin thickness, and a memory card including the same. The laminated package element includes a substrate having a through opening having a larger size than a plurality of individual package elements to be mounted and having a top surface and a bottom surface, a package body accommodated in the opening of the substrate, and protruding from the package body. An upper individual package element having a plurality of leads connected to an upper surface of a substrate, a lower individual having a package body accommodated in an opening of the substrate and a plurality of leads protruding from the package body and connected to a lower surface of the substrate It includes a package element. The upper and lower individual package elements may be a single chip package or a dual chip package, and may be stacked in plural. The leads of the individual package elements may extend in a straight line from the package body, or may be curved toward the upper and lower surfaces of the substrate. It may be directly connected to or connected to the leads of the individual elements stacked directly below. In a memory card including such a stacked package element, the card substrate includes a plurality of via holes electrically connected to the wiring pattern, and upper and lower individual memory elements each include a chip select lead, and each of the lead pairs except the chip select lead is The via holes are commonly connected to upper and lower individual memory elements.

Description

Ultra-Thin Stack Package Device and Ultra-Thin Memory Card Employing Such Package Device

The present invention relates to an ultra-thin laminated package device having a very thin thickness and a memory card including the same, and more particularly, to an ultra-thin laminated package device using a substrate having a through opening through which the body of an individual package can be accommodated. Relates to a memory card.

As digital communication devices, electronic devices for processing image data, and music data are widely used, memory cards for storing digital data have been provided in various forms. The memory card is mainly implemented in the form of a card using flash memory, currently SmartMedia (Toshiba, Japan), Memory Stick (Sony), Sony (Japan), SanDisk (USA) SanDisk's CompactFlash, MultiMedia Card and Secure Digital Card, developed jointly by SanDisk and Siemens, are standardized. These memory cards are recording media used in various portable electronic devices such as digital cameras, MP3 players, handheld personal computers (HPC), personal digital assistants (PDAs), mobile phones, etc. Increasingly, their applications are expanding. In recent years, moving and storing digital data between home digital devices has become easier, further accelerating the digitization and networking of consumer electronics.

The semiconductor device used in such a memory card must have a particularly thin thickness and a large data storage capacity. To this end, it is common to use a memory having a stacked package element as shown in Figs.

1 is a cross-sectional view illustrating a structure of a multilayer package device 10 using a conventional dual die package (DDP) technique. In the multilayer package device 10 of FIG. 1, semiconductor chips are mounted on both surfaces of a lead frame in order to increase chip mounting density. Referring to FIG. 1, a conventional semiconductor package 10 of the related art has a lead frame 15 composed of a die pad 13 and a plurality of leads 14. The semiconductor integrated circuit chip 11 is physically bonded to the die pad 13 by an adhesive 12, and is electrically connected to the lead 14 by a bonding wire 16. The semiconductor chip 11 and the bonding wire 16 and the like are sealed in a package molded body 17 formed of a molding resin such as epoxy and protected from the outside. Outer leads protruding outward from each lead 14, i.e., outside the package molded body 17, are processed into a form suitable for mounting on a substrate 18 (e.g., a memory card substrate).

2 is a cross-sectional view illustrating a structure of a multilayer package device 20 to which a conventional chip-on-chip technology is applied. The lower semiconductor chip 21 is attached to the substrate 28 with the adhesive 23, and the upper semiconductor chip 23 is attached onto the lower semiconductor chip 21 through the adhesive 24. The upper and lower semiconductor chips 21 and 23 are electrically connected to the substrate through the bonding wire 25, and the chips 21 and 23 and the bonding wire 25 are protected by the package body 27.

The conventional multilayer package device 10 and 20 having the above structure has a limitation in reducing the overall thickness because the chip is mounted on the substrate, or the size of the upper and lower semiconductor chips must be different. In order to reduce the thickness of the multilayer package device, there is a method of reducing the thickness of the semiconductor chip itself or thinning the lead frame. While semiconductor chips can reduce wafer thickness, for example, by back-lapping wafers to a range of 100-150 μm, reducing the thickness of the chip makes wafer handling difficult and increases the likelihood of wafer breakage or chip breakage. There are disadvantages. On the other hand, if the thickness of the lead frame is too thin, the lead frame may be easily broken during the assembly process, and the productivity of the assembly process may be reduced. At present, it is known that the thickness of the lead frame is 100 占 퐉 in consideration of the handleability of the lead frame, the formability of the external lead, and the like. It is also possible to use new assembly techniques, such as chip scale package (CSP) techniques, to reduce the thickness of the package elements, but this entails an increase in costs such as the need to replace plastic package assembly equipment already in use.

Therefore, the object of the present invention is to significantly reduce the thickness of the laminated package device while applying the plastic assembly technology as it is without special processing on the chip or lead frame.

Another object of the present invention is to provide a memory card having a very thin thickness while ensuring sufficient memory capacity.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a structure of a laminated package device using a conventional dual die package (DDP) technique.

2 is a cross-sectional view illustrating a structure of a multilayer package device to which a conventional chip-on-chip technology is applied.

3 is a cross-sectional view showing the structure of a laminated package device according to the present invention.

4 is a plan view illustrating an example of a memory card to which a multilayer package device according to the present invention is applied.

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4. FIG.

6 is a cross-sectional view showing a structure of a multilayer package device according to another embodiment of the present invention.

7 is a cross-sectional view showing the structure of a multilayer package device according to another embodiment of the present invention.

8 is a cross-sectional view showing the structure of a multilayer package device according to another embodiment of the present invention.

9 is a cross-sectional view showing the structure of a multilayer package device according to another embodiment of the present invention.

10 is a plan view showing another embodiment of a memory card to which the stacked package device according to the present invention is applied.

FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 10.

<Description of Major Symbols in Drawing>

30: laminated package 31: substrate

32, 34: upper and lower package 33, 35: lead

37: solder joint 38: substrate opening

40: memory card 42: external connection terminal

44: controller 46: component

48: switch

The laminated package device according to the present invention is a substrate having a through opening having a larger size than a plurality of individual package elements to be mounted and having an upper surface and a lower surface, a package body accommodated in the opening of the substrate, and the package body. An upper individual package element having a plurality of leads protruding from and connected to an upper surface of the substrate, a package body accommodated in an opening of the substrate and a plurality of leads protruding from the package body and connected to a lower surface of the substrate It includes a lower individual package element having a. Individual package elements are single chip packages or dual chip packages. The upper and lower individual package elements may be stacked in plurality, and the leads of the individual package elements may extend in a straight line from the package body or may be bent toward the upper and lower surfaces of the substrate, and may be directly connected to or directly stacked on the upper and lower surfaces of the substrate. It can be connected to the lead of the device. Individual package elements are stacked such that semiconductor chip active surfaces disposed close to the package top surface are disposed in the same direction.

A memory card according to the present invention includes a card substrate having a top surface and a bottom surface having a wiring pattern formed therethrough, a package body accommodated in the through opening portion of the card substrate, and a protruding portion from the package body and an upper portion of the substrate. An upper individual memory element having a plurality of leads connected to a surface thereof, a lower body individual memory element having a package body accommodated in an opening of the card substrate and a plurality of leads protruding from the package body and connected to a lower surface of the substrate; And a control element for controlling the operation of the upper and lower individual memory elements and the operation of the memory card. The card substrate may include a plurality of via holes electrically connected to the wiring pattern, and each of the upper and lower individual memory elements may include chip select leads, and each of the pairs of leads except for the chip select leads may be separated from each other through the via holes. Common connections are made to the memory elements.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3 is a cross-sectional view showing the structure of a multilayer package device according to an embodiment of the present invention.

The stacked package device 30 of FIG. 3 includes a substrate 31, an upper individual package element 32, and a lower individual package element 34. The substrate 31 is a printed circuit board (PCB), for example, an epoxy-glass substrate such as Fireretardant epoxy resin / glass cloth laminate (FR-4). The substrate 31 has an upper surface and a lower surface on which circuit wiring patterns (not shown) are formed. Here, the upper and lower portions refer to the upper and lower surfaces of the substrate shown in the drawings, wherein the active surface (the surface on which the on-chip circuit is formed) of the semiconductor chip included in the package body of the individual elements is disposed. Direction is the upper direction. If two semiconductor chips are included in the individual package device, it means that the active surface side of the upper semiconductor chip disposed closer to the upper surface of the package body among the two semiconductor chips is the upper portion. It is also possible to comprise a multilayer so that a wiring pattern exists in the inner layer of the board | substrate 31. FIG.

Individual package elements 32, 34 are mounted on the substrate 31, with openings 38 formed in the substrate 31 that are larger in size (eg, 0.5 mm larger than the package body) than the individual package elements to be mounted. It is. The opening 38 penetrates completely through the substrate 31.

The individual package elements 32, 34 comprise a package body and a plurality of leads 33, 35 protruding from the body. The package body is sealed with a semiconductor chip, for example a memory chip, which is electrically connected to the leads. The package body may include one semiconductor chip or two or more semiconductor chips. An individual package device including one semiconductor chip is called a single chip package device, and a device including two semiconductor chips is called a dual chip package device. The chip structure of the individual package device and the connection structure between the leads are easily understood by those skilled in the art to which the present invention pertains, and thus detailed descriptions thereof will be omitted.

The upper individual package element 32 is mounted on the upper surface of the substrate 31 so that the package body is inserted into and received in the opening 38 of the substrate. The lead 33 protruding from the package body of the upper individual package element 32 is electrically connected to the upper surface of the substrate 31 by the substrate wiring pattern and the connecting portion 37. The connecting portion 37 is, for example, a solder joint.

The lower individual package element 34 is mounted on the lower surface of the substrate 31 so that the package body is inserted into and received in the opening 38. The leads 35 protruding from the package body of the lower individual package element 34 are electrically connected by the substrate wiring pattern and the solder joint 37 at the lower surface of the substrate 31.

The upper and lower individual package elements 32 and 34 are mounted on the substrate 31 in the same direction. That is, the active surface of the semiconductor chip disposed close to the upper surface of the package inside the individual package elements 32 and 34 is mounted in the same direction. Accordingly, the upper and lower individual package elements 32 and 34 may be connected to each other through the substrate wiring pattern and the via hole facing each other having the same function without having one as a mirror chip.

On the other hand, it is preferable to mount on the board | substrate 31 so that the upper and lower individual package elements 32 and 34 may be symmetrical about the opening part 38 of the board | substrate 31. As shown in FIG. Thus, for example, when using a wide small outline package (WSOP) having a thickness t3 of 0.58 mm as the upper and lower individual package elements 32 and 34 and a substrate 31 having a thickness t1 of 0.4 mm, the upper and lower individual package elements 32 , 34 so that the same distance from the side of the opening 38, the bottom of the upper individual package element 32 and the upper surface of the lower individual package element 34 in the vertical space of the laminated package structure 30 To be almost centered. According to this example, the distance t2 between the leads 33 and 35 of the individual package and the upper or lower surface of the substrate is 0.05 mm, and the interval t4 of the upper and lower individual package elements 32 and 34 is 0.02 mm, and the laminated package element 30 ) Has a total thickness of 1.18 mm.

On the other hand, when the TSOP having a thickness t3 of 1.0 mm is used as the upper and lower individual package elements 32 and 34 and the substrate 31 having a thickness t1 of 0.7 mm is used, the leads 33 and 35 of the individual package and the upper surface of the substrate are used. Alternatively, the distance t2 of the lower surface is 0.09 mm, the interval t4 of the upper and lower individual package elements 32 and 34 is 0.04 mm, and the total thickness of the laminated package element 30 is 2.04 mm.

However, the structure shown in FIG. 3 and the numerical examples given above are for illustration only and are not intended to limit the protection scope of the present invention. Accordingly, the lead structure and numerical values may be variously modified or modified without departing from the technical spirit of the present invention. That is, the structure or dimensions of the multilayer package may be changed according to the type or standard of the electronic component using the multilayer package, for example, a memory card. An embodiment thereof will be described later with reference to FIGS. 6 to 9.

4 is a plan view illustrating an example of a memory card to which a stacked package device according to the present invention is applied, and FIG. 5 is a cross-sectional view taken along line IV-IV of FIG. 4.

The memory card 40 shown in Figs. 4 and 5 is a secure digital card having a width, a length, and a thickness of 24 mm, 32 mm, and 2.1 mm, respectively. The card 40 comprises a substrate 31, individual package elements 32, 34, external connection terminals 42, a controller 44, a controller 46, a switch 48. The external connection terminal 42 is an electrical path between the security digital card 40 and an external device. For example, four data input / output terminals DATA0 to 3, a command signal terminal, a clock signal terminal, and a power terminal (V _DD ) and the ground power supply terminal (V _SS ). The control element 44 is a logic element that controls the operation of the memory card 40 and the operation of the memory package elements 32 and 34. Component 46 includes passive elements such as resistors and capacitors required for the operation of the memory card and active elements such as transistors and diodes. The switch 48 serves to prevent overwriting of the memory card 40. The via hole 31 and the wiring patterns 53, 55, 57 are formed in the substrate 31. The via hole 31 electrically connects the wiring pattern of the upper surface of the substrate and the wiring pattern of the lower surface of the substrate.

The memory elements 32 and 34 shown in this embodiment are, for example, 64M x 8-bit NAND type flash memory elements, and unconnected leads are denoted as NC (No Connection), and electrical signals with the remaining control elements 44 are shown. Leads are exchanged with symbols representing each function and marked with black in the drawings so that they can be easily distinguished. Here, I / O _{0 to 7} are data input / output reads, CLE is command latch enable, ALE is address latch enable lead, and CE is chip enable. Is a lead for selecting the upper and lower individual memory elements 32 and 34 as. In addition, RE is read enable, WE is write enable, WP is write protect, R / B is ready / busy output, Vcc is power, Vss means ground lead respectively.

Since all leads except the CE leads and NC leads are connected to the respective wiring patterns 53, all leads except the CE leads of the upper memory element 32 and the lower memory element 34 are connected to the via hole 51. It is connected in common, and is therefore controlled in common by the control element 44. However, the CE leads are not commonly connected to the upper and lower memory elements, but are individually connected to the respective memory elements as shown in the cross-sectional view of FIG. That is, the CE lead for the upper memory element 32 is connected to the control element 44 through the wiring pattern 55, and the CE lead for the lower memory element 34 is connected to the control element (the wiring pattern 57). 44, the CE leads for each individual element 32, 34 are separated from each other.

The stacked package device and the memory card including the same according to the present invention can implement various stacked structures of individual package devices. 6-9 illustrate the structure of stacked package devices in accordance with these various embodiments.

For example, as shown in FIG. 6, the upper package element includes a first individual upper package element 64a, a second individual upper package element 66a, and a third individual upper package element 68a, and the lower package element. The device includes a first individual bottom package element 64b, a second individual bottom package element 66b, and a third individual bottom package element 68b. The leads 63a and 63b of the first individual package elements 64a and 64b protrude in a straight line from the package body and are connected to the upper and lower surfaces of the substrate 62, respectively. Meanwhile, the second individual package elements 66a and 66b and the third individual package elements 68a and 68b protrude from the package body to be bent toward upper and lower surfaces of the substrate, so-called Gull-Wings. Shaped leads 65a, 65b; 69a, 69b, respectively. In this example, the leads 69a and 69b of the third individual package element are also directly connected to the upper and lower surfaces of the substrate 62.

On the other hand, it is also possible to shorten the lead length of the individual elements to be stacked. For example, as illustrated in FIG. 7, in the state in which the plurality of upper individual package elements 74a, 76a, and 78a and the lower individual package elements 74b, 76b, and 78b are stacked, the individual elements 78a and 78b that are stacked on the upper and lowermost parts. ) Leads 79a and 79b to the leads 76a and 76b of the individual elements 76a and 76b stacked below them, and is not directly connected to the upper or lower surfaces of the substrate 72. It is also possible to reduce the length of.

As shown in FIG. 8, the lead structure of the individual package elements to be stacked is bent in a hook-like manner to the leads 83 of the upper individual package elements 84 of the stacked package element 80 to form a top surface of the substrate 82. The lead 85 of the lower individual package element 86 can be connected to the lower surface of the substrate 82 in a straight line. Alternatively, as shown in FIG. 9, all of the leads 93 and 95 of the upper and lower individual package elements 94 and 96 of the stacked package element 90 are bent into a hook-wing shape to form the upper and lower surfaces of the substrate 92. It is also possible to connect to the surface. In the structure of FIG. 9, the leads 93, 95 are bent to one-half the thickness of the substrate 92. That is, when bending at least one of the individual package elements stacked as in the embodiment shown in FIGS. 8 and 9 without bending a straight line, a stacked element and a memory card may be implemented using a thinner substrate. It is possible.

The multilayer package device according to the present invention can be applied to various types of memory cards. For example, as shown in FIGS. 10 and 11, the multilayer package device according to the present invention may be applied to a memory stick card to realize an ultra-thin memory card having a thinner memory capacity.

10 and 11, the memory stick card 100 has a width, a length, and a thickness of 21.5 mm, 50 mm, and 2.8 mm, respectively, and an external connection terminal 102 and an overwrite lock switch 104. , Control element 106, individual memory package elements 110, 120, and card substrate 130. The control element 106 controls the operation of the memory stick card 100 and the operation of the memory package elements 110 and 120, for example, a 64-LGA-0909 (0.7T) controller or 64-TQFP-12 × 12 ( 1.2T) controller. The individual memory elements 110, 120 are, for example, 64M x 8-bit NAND type TSOP flash memory elements. Since the lead pin configurations of the memory devices 110 and 120 are the same as those of the memory device of the card implementation described with reference to FIGS. 4 and 5, a detailed description of each read function is omitted.

A through opening 138 is formed in the card substrate 130, and the individual memory elements 110 and 120 are accommodated in the opening 138. The wiring pattern 153 is formed on the substrate 130, and the wiring pattern connected to the lead 112 of the upper memory element 110 may include the wiring pattern and the via hole 151 connected to the lead 122 of the lower memory element 120. Is electrically connected via Meanwhile, similar to the card implementation described with reference to FIGS. 4 and 5, the wiring pattern 155 connected to the CE lead used to select the upper memory element and the wiring pattern connected to the CE lead for selecting the lower memory element are shown. 157 are electrically separated from each other. Therefore, the control element 106 may control the selective operation of the upper and lower memory elements 110 and 120.

In this embodiment, the leads 112 of the upper memory element 110 are bent into a hooked wing shape and connected to the upper surface of the substrate 130, while the leads 122 of the lower memory element 120 are straight. It protrudes from the package body in a shape and is connected to the lower surface of the substrate 130. Therefore, the upper and lower memory elements 110 and 120 are asymmetrically disposed with respect to the center line of the substrate 130 with respect to the vertical direction of the cross-sectional view of FIG. 11. The bending of the lead 112 of the upper memory element 110 is to reduce the thickness of the substrate 130 and to properly accommodate the stacked package element in the memory stick card. It is of course also possible to configure the bent lead in the lower memory element 120.

In this embodiment, the total thickness t1 of the memory stick card 100 is 2.8 mm, the distance from the bottom of the substrate 130 to the bottom of the card is 0.4 mm and the distance t3 from the top surface of the laminated package element to the card top surface is 0.4 mm, the distance t4 between the center of the upper memory element and the center of the lower memory element is 2 mm.

The upper memory element 110 and the lower memory element 120 are mounted on the substrate 130 in the same direction with respect to the vertical direction. That is, the active surface of the semiconductor chip accommodated in the package body of the upper memory device 110 and the active surface of the semiconductor chip accommodated in the package body of the lower memory device 120 are disposed in the same direction, for example, the upper surface of the stacked package device. . Meanwhile, when two memory chips are accommodated in the package bodies of the upper and lower memory devices 110 and 120, the active surface of the upper memory chip is disposed on the upper surface of the multilayer package device.

According to the present invention, since the individual package body is accommodated in the through opening of the substrate, it is possible to improve the stacking density of the individual package elements and to reduce the overall thickness of the stacked package element, thus increasing the memory capacity. It is possible to implement

In addition, according to the present invention, it is possible to significantly reduce the thickness of the package element and the memory card including the same while utilizing the plastic package assembly technology widely used in the semiconductor assembly process.

Claims (10)

As a laminated package element, A substrate having a through opening having a larger size than a plurality of individual package elements to be mounted and having an upper surface and a lower surface, An upper individual package element having a package body accommodated in an opening of the substrate and a plurality of leads protruding from the package body and connected to an upper surface of the substrate; And a lower individual package element having a package body accommodated in an opening of the substrate and a plurality of leads protruding from the package body and connected to the lower surface of the substrate. The multilayer package device of claim 1, wherein the individual package device is a single chip package device or a dual chip package device. The stack package device of claim 1, wherein the leads of the individual package elements extend in a straight line from each package body. 4. The multilayer package device of claim 3, wherein the individual package elements further comprise first individual package elements having a first plurality of leads protruding from the package body and bent toward the upper or lower surface of the substrate. The stack package device of claim 1, wherein at least one of the individual package elements has a lead protruding from the package body and bent toward the upper or lower surface of the substrate. The multilayer package device of claim 1, wherein the upper individual package element and the lower individual package element have semiconductor chip active surfaces disposed close to the upper surface of each package element in the same direction. As a memory card, A card substrate having an upper surface and a lower surface on which wiring patterns are formed and having a through opening; An upper individual memory element having a package body accommodated in the through opening of the card substrate and a plurality of leads protruding from the package body and connected to an upper surface of the substrate; A lower individual memory element having a package body accommodated in an opening of the card substrate and a plurality of leads protruding from the package body and connected to a lower surface of the substrate; And a control element for controlling the operation of the upper and lower individual memory elements and the operation of the memory card. The method of claim 7, wherein the card substrate includes a plurality of via holes electrically connected to the wiring pattern, and the upper and lower individual memory elements each include a chip select lead, and each of the lead pairs excluding the chip select lead each have the via hole. And a common connection for the upper and lower individual memory elements. 8. The memory card of claim 7, wherein the upper individual memory elements and the lower individual memory elements have semiconductor chip active surfaces disposed close to the upper surface of each package body in the same direction. 8. The memory card of claim 7, wherein the individual memory elements comprise leads that extend or bend in a straight line from each package body.