KR0156332B1 - Stack semiconductor leadframe and semiconductor package using it - Google Patents

Stack semiconductor leadframe and semiconductor package using it

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Publication number
KR0156332B1
KR0156332B1 KR1019950039735A KR19950039735A KR0156332B1 KR 0156332 B1 KR0156332 B1 KR 0156332B1 KR 1019950039735 A KR1019950039735 A KR 1019950039735A KR 19950039735 A KR19950039735 A KR 19950039735A KR 0156332 B1 KR0156332 B1 KR 0156332B1
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South Korea
Prior art keywords
semiconductor chip
semiconductor
package
inner lead
lead
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Application number
KR1019950039735A
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Korean (ko)
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KR970030725A (en
Inventor
안민철
Original Assignee
김광호
삼성전자주식회사
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Priority to KR1019950039735A priority Critical patent/KR0156332B1/en
Publication of KR970030725A publication Critical patent/KR970030725A/en
Application granted granted Critical
Publication of KR0156332B1 publication Critical patent/KR0156332B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 중앙부에 캐비티 영역을 가지며 실장되는 반도체 칩 본딩패드를 중심으로 대향되는 다수의 내부리드를 갖는 리드 프레임의 상/하면으로 반도체 칩을 앙면 실장하여 더블 본딩에 의해 외부리드와 전기적으로 접속하며 에폭시 수지로 본딩 하여 패키지 몸체를 형성시킴으로써, 접속되지 않는 내부리드를 이용하여 각각의 반도체 칩내의 신호의 전송을 분리 전송함으로써 메모리 용량의 확장이 가능하도록 한 적층형 반도체 패키지에 관한 것이다.According to the present invention, the semiconductor chip is face-mounted to the upper and lower surfaces of a lead frame having a plurality of inner leads facing the center of the semiconductor chip bonding pads having a cavity area at the center thereof, and electrically connected to the external leads by double bonding. By forming a package body by bonding with epoxy resin, the present invention relates to a stacked semiconductor package that allows memory capacity to be expanded by separating and transmitting a signal transmission in each semiconductor chip using an unconnected internal lead.

Description

적층형 반도체 리드 프레임 및 그를 이용한 반도체 패키지Stacked Semiconductor Lead Frames and Semiconductor Packages Using the Same

제1도는 종래기술에 따른 적층형 반도체 패키지의 일 실시예를 나타낸 단면도.1 is a cross-sectional view showing an embodiment of a stacked semiconductor package according to the prior art.

제2도는 종래기술에 따른 적층형 반도체 패키지의 다른 실시예를 나타낸 단면도.2 is a cross-sectional view showing another embodiment of a stacked semiconductor package according to the prior art.

제3a도는 본 발명의 적층형 반도체 패키지에 적용되는 리드 프레임의 평면도.3A is a plan view of a lead frame applied to the stacked semiconductor package of the present invention.

제3b도는 본 발명의 적층형 반도체 패키지에 적용되는 리드 프레임의 부분 확대 사시도.3B is a partially enlarged perspective view of a lead frame applied to the stacked semiconductor package of the present invention.

제4도는 본 발명의 적층형 반도체 패키지의 일 실시예를 나타낸 단면도.4 is a cross-sectional view showing an embodiment of a stacked semiconductor package of the present invention.

제5도는 본 발명의 적층형 반도체 패키지의 다른 실시예를 나타낸 단면도.5 is a cross-sectional view showing another embodiment of the stacked semiconductor package of the present invention.

제6도는 이 발명의 적층형 반도체 패키지의 또다른 실시예를 나타낸 단면도.6 is a cross-sectional view showing yet another embodiment of the stacked semiconductor package of the present invention.

제7도는 제4도 내지 제6도에 적용되는 반도체 패키지의 회로적인 블록도이다.7 is a circuit block diagram of a semiconductor package applied to FIGS. 4 to 6.

본 발명은 적층형 반도체 리드 프레임 및 그를 이용한 반도체 패키지에 관한 것으로서, 더욱 상세하게는 전기적으로 접속되지 않는(No Connection: 이하, NC라 약칭함) 내부리드를 전기적 연결에 사용할 수 있도록 갈고리 형상을 갖게 하여 복수 개의 반도체 칩을 실장할 수 있는 적층형 반도체 리드 프레임 및 그를 이용한 반도체 패키지에 관한 것이다.The present invention relates to a laminated semiconductor lead frame and a semiconductor package using the same. More particularly, the present invention provides a hooked shape to enable an internal lead that is not electrically connected (hereinafter abbreviated as NC) to be used for electrical connection. The present invention relates to a stacked semiconductor lead frame capable of mounting a plurality of semiconductor chips and a semiconductor package using the same.

최근들어 각종 전자기기들의 편이성에 대한 사용자의 요구가 증대함에 따라 이러한 요구들을 충족시켜주기 위한 하나의 방법으로 전자기기들의 소형화, 박형화, 고기능화 추세가 끊임없이 이루어지고 있는 추세에 있다. 이를 위해서는 핵심소자인 반도체 패키지의 고밀도 실장화가 매우 중요하다. 특히 컴퓨터의 경우 기억용량 증가를 위해서 랜덤 억세스 메모리 또는 플레쉬 메모리 등과 같은 반도체 칩의 크기는 증가하지만, 반도체 패키지는 고밀도 실장화를 위해서 그 크기가 매우 작아져야 한다.Recently, as the user's demand for convenience of various electronic devices increases, there is a trend of miniaturization, thinning, and high functionalization of electronic devices as a way to satisfy these demands. For this purpose, high-density mounting of the semiconductor package, which is a core device, is very important. In particular, in the case of a computer, the size of a semiconductor chip such as a random access memory or a flash memory is increased to increase a memory capacity, but a semiconductor package must be very small for a high density mounting.

그러나, 반도체 패키지의 크기를 줄이기 위해 지금까지 제안되어온 여러가지 방법이 주로 2차원적인 방법이었으므로 반도체 패키지의 크기를 줄이는 데는 여전히 한계가 있었다.However, there have been limitations in reducing the size of the semiconductor package since various methods proposed up to now have been mainly two-dimensional methods for reducing the size of the semiconductor package.

종래의 플레쉬 메모리의 일반적인 반도체 패키지는 반도체 칩의 본딩패드들과 내부리드가 본딩 와이어에 의해 전기적으로 연결되어 있고, 반도체 칩은 외부의 기계적, 화학적 환경으로부터 보호할 수 있도록 성형수지로 봉지되어 있다. 이와 같은 구조를 갖는 반도체 패키지는 현재까지도 통상적으로 사용되고 있지만, 보다 고밀도화를 요구함과 동시에 소형화를 요구하는 시스템에 적용하는 데는 부적합하다.In a typical semiconductor package of a conventional flash memory, bonding pads and an inner lead of a semiconductor chip are electrically connected by a bonding wire, and the semiconductor chip is encapsulated with a molding resin so as to protect it from external mechanical and chemical environments. Although a semiconductor package having such a structure is still commonly used until now, it is not suitable for application to a system requiring a higher density and a smaller size.

그러므로 상기한 한계를 극복하기 위해 동일한 기억용량의 반도체 칩 또는 반도체 패키지를 3차원적(3-Dimensional)으로 다수개 적층한 반도체 패키징 기술이 제안된 바 이에 대한 일 실시예가 제1도 및 제2도에 도시되어 있다.Therefore, in order to overcome the above limitations, a semiconductor packaging technology in which a plurality of three-dimensionally stacked semiconductor chips or semiconductor packages having the same memory capacity is proposed, an embodiment thereof is illustrated in FIGS. 1 and 2. Is shown.

제1도 및 제2도는 종래기술에 따른 적층형 반도체 패키지의 일 실시예들을 나타낸 것이다.1 and 2 illustrate one embodiment of a stacked semiconductor package according to the prior art.

먼저, 제1도는 적층된 베어 다이(stacked bare die) 반도체 패키지(10)를 나타낸 것으로 다수의 층간 구조를 이루는 내부리드(12)의 하면에 다수개의 반도체 칩(11)이 전기적으로 접속되도록 베어 다이 본딩되어 있으며, 내부리드(12)의 끝단은 외부리드(13)와 연결되어 있고, 상술한 구조는 EMC(Epoxy Molding Compound)로 몰딩(molding)되어 패키지 몸체(14)가 형성되어 있다.First, FIG. 1 illustrates a stacked bare die semiconductor package 10, in which a plurality of semiconductor chips 11 are electrically connected to a lower surface of an inner lead 12 forming a plurality of interlayer structures. Bonded, the end of the inner lead 12 is connected to the outer lead 13, the above-described structure is molded with an epoxy molding compound (EMC) to form a package body (14).

이러한 구조를 갖는 종래의 반도체 패키지(10)는 패키징 공정을 단순화할 수 있는 이점이 있으나, 적층에 따른 패키지의 높이가 높아져 패키지 크기가 증가되는 단점이 있다.Conventional semiconductor package 10 having such a structure has the advantage of simplifying the packaging process, but has the disadvantage that the package size is increased by increasing the height of the package according to the stack.

다음, 제2도는 적층되어 패키징된 반도체 패키지(20)를 나타낸 것으로, 일반적인 리드 프레임의 다이패드(25) 상에 반도체 칩(21)을 다이본딩하고, 반도체 칩(21)의 본딩패드와 내부리드(22)와의 전기적 접속을 위해 와이어(26)로 본딩하며, 다이본딩과 와이어본딩이 완료된 반도체 칩(21)을 외부 환경으로부터 보호하기 위하여 EMC로 봉지하여 패키징된 반도체 패키지를 적어도 2개 이상 수직으로 적층시킨 후, 외부리드(23)를 전기적으로 상호 연결시키고, 재차 EMC로 봉지 함으로써 적층되어 패키징된 반도체 패키지(20)가 얻어진다.Next, FIG. 2 illustrates a stacked and packaged semiconductor package 20. The semiconductor chip 21 is die-bonded on a die pad 25 of a general lead frame, and the bonding pad and the inner lead of the semiconductor chip 21 are formed. Vertically bond at least two semiconductor packages packaged with EMC to bond the wires 26 for electrical connection with the wires 22 and to protect the die-bonded and wire-bonded semiconductor chips 21 from the external environment. After the lamination, the outer leads 23 are electrically interconnected and again sealed with EMC to obtain the laminated and packaged semiconductor package 20.

그러나, 이러한 구조를 갖는 반도체 패키지(20)는 내부 리드 본딩( ILB; lnner Lead Bonding)과 외부 리드 본딩(OLB; Outer Lead Bonding)을 각각 수행하기 때문에 공정이 복잡해지고 다이실장에 대한 신뢰도가 저하되는 문제점이 있다. 또 제1도의 구조에서와 같이 적층에 따른 패키지의 높이가 증가되어 반도체 패키지의 크기가 증가되는 문제점이 있다.However, since the semiconductor package 20 having such a structure performs inner lead bonding (ILB) and outer lead bonding (OLB), the process is complicated and reliability of die mounting is reduced. There is a problem. In addition, as in the structure of FIG. 1, there is a problem in that the height of the package is increased by stacking, thereby increasing the size of the semiconductor package.

또한, 도면에 도시하지 않았으나, 히다치사의 3D 메모리 적층형 패키지는 탭 (TAB; Tape Automated Bonding) 방식을 이용한 TCP(Tape Carrier Package)를 적층하는 것으로, 글라스 에폭시 프레임에 적층되는 패키지가 디바이스 셀렉터 신호를 선택적으로 전송하기 위한 칩 선택 패턴을 별도로 구비하여야 하고, TCP 리드에 홀을 뚫어 솔더 결합을 해야하는 등 패키지 제조 공정이 복잡한 단점이 있다.In addition, although not shown in the drawing, Hitachi's 3D memory stacked package stacks a Tape Carrier Package (TCP) using a tape automated bonding (TAB) method, and a package stacked on a glass epoxy frame selectively selects a device selector signal. The chip selection pattern must be provided separately for transmission, and the package manufacturing process has to be complicated, such as soldering through holes in the TCP lead.

따라서, 본 발명은 상기한 종래기술에서 제시된 제반 문제점들을 해소하기 위하여 발명한 것으로서, 본 발명의 목적은 다수의 내부리드를 갖는 리드 프레임의 상/하면으로 양면실장이 가능한 적층형 반도체 리드 프레임을 제공함에 있다.Accordingly, the present invention has been invented to solve the above-mentioned problems in the prior art, and an object of the present invention is to provide a stacked semiconductor lead frame that can be double-sided mounted on the upper and lower surfaces of a lead frame having a plurality of internal leads. have.

또한, 본 발명의 다른 목적은 양면 실장이 가능한 반도체 리드 프레임을 이용하여 적어도 하나 이상의 반도체 칩을 실장한 후, 본딩에 의해 외부리드와 전기적으로 접속하여 에폭시 수지로 몰딩하여 패키지 몸체를 형성시킴으로써, 크기가 감소된 적층형 반도체 패키지를 제공함에 있다.In addition, another object of the present invention is to mount the package body by mounting at least one semiconductor chip using a semiconductor lead frame capable of double-side mounting, then electrically connected to the external lead by bonding and molding with an epoxy resin to form a package body To provide a reduced stacked semiconductor package.

또한, 본 발명의 또다른 목적은 개별 패키지 소자에 적용할 경우에는 전기적 접속이 이루어지지 않는 내부리드를 이용하여 복수의 반도체 칩을 리드 프레임에 상/하로 실장하고 각각와 반도체 칩과의 신호의 전송을 분리함으로써 메모리 용량의 확장이 가능하도록 한 적층형 반도체 패키지를 제공함에 있다.In addition, another object of the present invention is to mount a plurality of semiconductor chips in the lead frame up and down by using an internal lead that does not make electrical connection when applied to the individual package element and to transmit the signal between each and the semiconductor chip. The present invention provides a stacked semiconductor package capable of expanding memory capacity by separating.

상기한 목적들을 달성하기 위한 본 발명에 따른 적층형 반도체 리드 프레임의 특징은, 반도체 칩이 실장되고 갈고리 형상을 갖는 제1내부리드와, 제1내부리드의 외측에 배열되어 있는 앵커 형상을 갖는 제2내부리드를 포함하는 것이다.A feature of the stacked semiconductor lead frame according to the present invention for achieving the above objects is a first inner lead in which the semiconductor chip is mounted and having a hook shape, and a second having an anchor shape arranged outside the first inner lead. It includes internal leads.

또한, 본 발명에 따른 적층형 반도체 패키지의 특징은, 복수 개의 제1 및 제2 내부리드중 제1 내부리드상에 복수 개의 상부/하부 반도체 칩이 다이본딩 되고, 상부 반도체 칩의 본딩패드와 제2 내부리드가 와이어 본딩되며, 하부 반도체 칩의 본딩패드와 제1 내부리드가 와이어 본딩되고, 반도체 칩을 외부 환경으로 부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸체가 형성된 점에 있다.In addition, the stacked semiconductor package according to the present invention is characterized in that a plurality of upper and lower semiconductor chips are die-bonded on a first inner lead of a plurality of first and second inner leads, and a bonding pad and a second pad of the upper semiconductor chip. The inner lead is wire bonded, the bonding pad of the lower semiconductor chip and the first inner lead are wire bonded, and the package body is formed by molding an epoxy resin to protect the semiconductor chip from the external environment.

또한, 본 발명에 따른 적층형 반도체 패키지의 다른 특징은, 복수 개의 제1 및 제2 내부리드중 제1 내부리드상에 복수 개의 상부/하부 반도체 칩이 다이본딩 되고, 상부 반도체 칩의 본딩패드와 제2 내부리드가 와이어 본딩되며, 하부 반도체 칩의 본딩패드와 제1 내부리드가 볼 본딩되고, 상기 반도체 칩을 외부 환경으로 부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸체가 형성된 점에 있다.In addition, another feature of the stacked semiconductor package according to the present invention is that a plurality of upper / lower semiconductor chips are die-bonded on a first inner lead of the plurality of first and second inner leads, and a bonding pad and a first pad of the upper semiconductor chip are formed. 2, the inner lead is wire bonded, the bonding pad of the lower semiconductor chip and the first inner lead are ball bonded, and the package body is formed by molding the epoxy chip with an epoxy resin to protect the semiconductor chip from the external environment.

이하, 본 발명에 따른 적층형 반도체 리드 프레임 및 그를 이용한 반도체 패키지의 바람직한 일 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a preferred embodiment of a stacked semiconductor lead frame and a semiconductor package using the same according to the present invention will be described in detail with reference to the accompanying drawings.

제3a도는 본 발명의 적층형 반도체 패키지에 적용되는 리드 프레임의 평면도이고, 제3b도는 본 발명의 적층형 반도체 패키지에 적용되는 리드 프레임의 부분 확대 사시도이다.3A is a plan view of a lead frame applied to the stacked semiconductor package of the present invention, and FIG. 3B is a partially enlarged perspective view of the lead frame applied to the stacked semiconductor package of the present invention.

제3a도는 본 발명의 적층형 반도체 패키지에 적용되는 리드 프레임의 평면도이고, 제3b도는 본 발명에 따라 리드 프레임에 상부/하부 반도체 칩이 실장된 구조를 나타내는 부분 확대 사시도이다.3A is a plan view of a lead frame applied to the stacked semiconductor package of the present invention, and FIG. 3B is a partially enlarged perspective view illustrating a structure in which upper and lower semiconductor chips are mounted on the lead frame according to the present invention.

리드 프레임(30)은 플래시 메모리에 사용하기에 적합한 구조를 가지고 있다. 예컨대 하나의 플래시 메모리를 조립하는 데에 사용되는 리드 프레임인 경우 번지 입력과 데이터 출력이 이루어지는 8개의 입출력 핀 I/O0~I/O7과, 4개의 전원 핀 Vcc1, Vcc2, Vssl, Vss2과, 접지핀 흥, 제어 신호 입출력 핀 LE(Command Latch Enabel), ALE(Address Latch Enable), WE(Write Enable), CE(Chip Enable), R/B(Ready/Busy) 등에 해당하는 리드가 반도체 칩의 해당 본딩패드와 와이어 등에 의해 전기적으로 연결되어 있어야 한다. 한편, 전기적으로 연결되지 않는(NC) 핀들은 예컨대 특정 메모리 셀이 결함인 것으로 밝혀진 경우 이것을 여분의 메모리 셀로 대체하기 위해 높은 전류를 흘리는 데에 사용된다.The lead frame 30 has a structure suitable for use in a flash memory. For example, in the case of a lead frame used to assemble one flash memory, eight input / output pins I / O0 to I / O7 with address input and data output, four power pins Vcc1, Vcc2, Vssl, Vss2, and ground Leads corresponding to pin boom, control signal input / output pin LE (Command Latch Enabel), ALE (Address Latch Enable), WE (Write Enable), CE (Chip Enable), R / B (Ready / Busy), etc. It should be electrically connected by bonding pads and wires. Pins that are not electrically connected (NC), on the other hand, are used to flow high currents, for example, to replace a spare memory cell if a particular memory cell is found to be defective.

본 발명은 이러한 NC핀이 많은 플래시 메모리를 하나의 리드 프레임을 사용하여 적층 패키지 소자를 구현하는 것이다. 본 발명의 리드 프레임(30)은 하부 반도체 칩(35)과 접속되는 제1내부리드(33)와 상부 반도체 칩(36)과 전기적으로 연결되는 제2 내부리드(34)를 구비하고 있다. 제1내부리드(33)는 하부 반도체 칩(35)의 표면 위로 올라오며 갈고리 형상으로 구부러져서 반도체 칩(35)의 해당 본딩패드와 와이어 본딩이 가능하다. 하부 반도체 칩(35)은 절연성 접착제(37a)에 의해 제1내부리드(33)의 하면에 부착되고 상부 반도체 칩(36)도 절연성 접착재에 의해 제1내부리드(33)의 상면에 부착된다.The present invention implements a multilayer package device using a single lead frame for a flash memory having many NC pins. The lead frame 30 of the present invention includes a first internal lead 33 connected to the lower semiconductor chip 35 and a second internal lead 34 electrically connected to the upper semiconductor chip 36. The first inner lead 33 may rise above the surface of the lower semiconductor chip 35 and bend in a hook shape to allow wire bonding with a corresponding bonding pad of the semiconductor chip 35. The lower semiconductor chip 35 is attached to the lower surface of the first inner lead 33 by the insulating adhesive 37a, and the upper semiconductor chip 36 is also attached to the upper surface of the first inner lead 33 by the insulating adhesive.

점선(39)은 상하부 반도체 칩(35,36)이 실장되는 영역을 표시하는데, 이 영역 바깥에 배열되어 잇는 제2내부리드(34)는 상부 반도체 칩(36)과의 와이어 본딩이 용이하도록 끝부분이 구부러진 앵커 형상을 하고 있다. 상하부 반도체 칩(35,36)의 다이 본딩과 와이어 본딩이 끝나면 몰딩 공정 등에 의해 패키지 몸체를 형성하는데, 이 패키지 몸체는 쇄선(31)으로 나타낸 영역에 형성된다.The dotted line 39 indicates a region where the upper and lower semiconductor chips 35 and 36 are mounted, and the second inner lead 34 arranged outside the region ends to facilitate wire bonding with the upper semiconductor chip 36. The part has the shape of the bent anchor. After die bonding and wire bonding of the upper and lower semiconductor chips 35 and 36 are completed, a package body is formed by a molding process or the like, which is formed in the region indicated by the chain line 31.

이렇게 형성된 본 발명의 적층형 반도체 패키지는 동일 핀에 대해 두 개의 외부리드를 갖는데, 입출력 핀 I/O0∼I/O7에 해당하는 외부리드를 제외한 나머지 외부리드에 대해서는 동일 기능을 갖는 2개의 외부리드에 공통으로 신호를 연결하면 두 배의 메모리 용량을 갖는 적층형 플래시 메모리의 구현이 가능하다.The stacked semiconductor package according to the present invention has two external leads for the same pin, except for the external leads corresponding to the input / output pins I / O0 to I / O7. Connecting signals in common enables the implementation of stacked flash memories with twice the memory capacity.

제4도는 상기와 같은 제3a도의 리드 프레임을 적용한 본 발명의 적층형 반도체 패키지의 일 실시예를 나타낸 단면도이다.FIG. 4 is a cross-sectional view illustrating an exemplary embodiment of a stacked semiconductor package of the present invention to which the lead frame of FIG. 3a is applied.

제4도를 참조하면, 본 발명의 적층형 반도체 패키지(30)는 제1 및 제2 내부리드 (33)(34)중 제1내부리드(33) 상하면에 상부/하부 반도체 칩(35)(36)이 다이본딩되고, 상부 반도체 칩(36)의 본딩패드와 제2 내부리드(34)가 와이어(32a)로 본딩되며, 하부 반도체 칩(35)의 본딩패드와 제1 내부리드(33)가 와이어(32b)로 본딩되고, 반도체 칩들(35)(36)을 외부 환경으로부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸채(31)가 형성된 구조이다. 미설명된 38은 반도체 패키지 실장에 적합하도록 절곡 형성된 외부리드를 나타낸다.Referring to FIG. 4, the stacked semiconductor package 30 of the present invention has upper and lower semiconductor chips 35 and 36 disposed on upper and lower surfaces of the first inner lead 33 of the first and second inner leads 33 and 34. ) Is bonded, the bonding pad of the upper semiconductor chip 36 and the second inner lead 34 are bonded with the wire 32a, the bonding pad and the first inner lead 33 of the lower semiconductor chip 35 The package 32 is bonded to the wire 32b and formed by molding an epoxy resin to protect the semiconductor chips 35 and 36 from an external environment. 38, which is not described, refers to an outer lead bent to be suitable for semiconductor package mounting.

이때, 상부/하부 반도체 칩(36)(35)들은 제1 내부리드(33) 상하에 절연성 접착제(37a)(37b)에 의해 다이본딩되어 있다.At this time, the upper and lower semiconductor chips 36 and 35 are die bonded by insulating adhesives 37a and 37b above and below the first inner lead 33.

제5도는 제3도의 리드 프레임을 적용한 본 발명의 적층형 반도체 패키지의 다른 실시예를 나타낸 단면도이다.5 is a cross-sectional view showing another embodiment of the stacked semiconductor package of the present invention to which the lead frame of FIG. 3 is applied.

제5도를 참조하면, 본 발명의 적층형 반도체 패키지(40)는 제1 및 제2내부리드 (43)(44)중 제1내부리드(43) 상하에 상부/하부 반도체 칩(46)(45)이 다이본딩되고, 상부 반도체 칩(46)의 본딩패드와 제2 내부리드(44)가 와이어(42)로 본딩되며, 하부 반도체 칩(45)의 본딩패드와 제1 내부리드 (43)가 범프(49)에 의해 본딩되며, 반도체 칩(45)(46)을 외부 환경으로부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸체(41)가 형성된 구조이다. 마찬가지로 미설명된 48은 반도체 패키지 실장에 적합하도록 절곡 형성된 외부리드를 나타낸다.Referring to FIG. 5, the stacked semiconductor package 40 of the present invention includes upper and lower semiconductor chips 46 and 45 above and below the first inner lead 43 of the first and second inner leads 43 and 44. ), The bonding pad of the upper semiconductor chip 46 and the second inner lead 44 are bonded with the wire 42, and the bonding pad and the first inner lead 43 of the lower semiconductor chip 45 Bonded by the bumps 49, the semiconductor chip 45 and 46 are molded with an epoxy resin to protect the external chip from the external environment, thereby forming the package body 41. Similarly, 48, which is not described, indicates an outer lead bent to be suitable for semiconductor package mounting.

이때, 상부/하부 반도체 칩(46)(45)들은 제1 내부리드(43)상에 폴리이미드 테이프 (47a)(47b)에 의해 다이본딩되어 있다.At this time, the upper and lower semiconductor chips 46 and 45 are die-bonded on the first inner lead 43 by polyimide tapes 47a and 47b.

제6도는 제3도의 리드 프레임을 적용한 본 발명의 적층형 반도체 패키지의 또 다른 실시예를 나타낸 단면도이다.6 is a cross-sectional view illustrating still another embodiment of the stacked semiconductor package of the present invention to which the lead frame of FIG. 3 is applied.

제6도를 참조하면, 본 발명의 적층형 반도체 패키지(50)는 제1 및 제2 내부리드(53)(54)중 제1 내부리드(53)에 상부/하부 반도체 칩(56)(55)이 다이본딩 되고, 상부 반도체 칩(56)의 본딩패드와 제2 내부리드(54)가 와이어(52)로 본딩되며, 하부 반도체 칩(55)의 본딩패드과 제1 내부리드(53)가 범프(59)에 의해 본딩되며, 반도체 칩(55)(56)을 외부 환경으로부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸체(51)가 형성된 구조이다. 마찬가지로 미설명된 58은 반도체 패키지 실장에 적합하도록 절곡 형성된 외부리드를 나타낸다.Referring to FIG. 6, the stacked semiconductor package 50 of the present invention may have upper and lower semiconductor chips 56 and 55 on the first inner lead 53 of the first and second inner leads 53 and 54. The die bonding is performed, the bonding pad of the upper semiconductor chip 56 and the second inner lead 54 are bonded to the wire 52, and the bonding pad and the first inner lead 53 of the lower semiconductor chip 55 are bumped ( 59, the package body 51 is formed by molding the semiconductor chips 55 and 56 with an epoxy resin to protect the semiconductor chips 55 and 56 from external environments. Similarly, 58, which is not described, indicates an outer lead bent to be suitable for semiconductor package mounting.

이때, 상부/하부 반도체 칩(56)(55)들은 제1 내부리드(53)상에 절연성 코팅재 (57a)(57b)에 의해 다이본딩되어 있다.At this time, the upper and lower semiconductor chips 56 and 55 are die-bonded on the first inner lead 53 by insulating coatings 57a and 57b.

제7도는 제4도 내지 제6도에 적용되는 반도체 패키지의 회로적인 블록도 이다.7 is a circuit block diagram of a semiconductor package applied to FIGS. 4 to 6.

제7도를 참조하면, 상기한 반도체 패키지는 반도체 칩(IC1)(IC2)의 데이터 입출력에 사용되는 입/출력 단자(I/O0-I/O7)(I/O8-I/O15)를 각각 분리하고, 그 입출력 단자들을 제외한 다른 단자들을 신호의 전송에 공통으로 사용함으로써 메모리 용량의 확장이 가능하도록 한 것이다. 신호를 선택적으로 전송하기 위한 별도의 리드 설계가 필요하지 않으면서 데이타 입/출력 단자(I/O0∼I/O7)(I/O8-I/Ol5)를 분리시키는 방법으로 적층형 패키지의 구현이 가능한 것이다.Referring to FIG. 7, the semiconductor package may include input / output terminals I / O0-I / O7 and I / O8-I / O15 used for data input and output of the semiconductor chips IC1 and IC2, respectively. By separating and using other terminals except the input / output terminals in common for signal transmission, memory capacity can be expanded. It is possible to implement a stacked package by separating the data input / output terminals (I / O0 to I / O7) (I / O8-I / O5) without requiring a separate lead design for selectively transmitting signals. will be.

상술한 바와 같이, 본 발명에 따른 적층형 반도체 리드 프레임 및 그를 이용한 반도체 패키지는, 제1내부리드의 상/하면으로 반도체 칩을 실장하고 신호의 전송을 분리하는 것이 자체적으로 가능한 구조를 갖는다. 특히, 본 발명에 따른 리드 프레임은 하나의 반도체 칩을 이용하여 패키지를 제조할 때 전기적 접속에 사용되지 않는 내부리드를 활용하여 반도체 칩 내의 신호의 전송을 분리할 수 있어 메모리 용량의 확장이 가능한 이점이 있다. 또한, 하나의 리드 프레임에 상하로 반도체 칩이 실장되어 봉지될 수 있어 종래의 적층형 패키지에 비해 크기가 감소되는 이점도 있다.As described above, the stacked semiconductor lead frame and the semiconductor package using the same according to the present invention have a structure in which the semiconductor chip is mounted on the upper and lower surfaces of the first inner lead and the signal transmission can be separated. In particular, the lead frame according to the present invention can expand the memory capacity by separating the transmission of the signal in the semiconductor chip by using an internal lead that is not used for electrical connection when manufacturing a package using a single semiconductor chip There is this. In addition, since the semiconductor chip may be mounted and encapsulated in one lead frame up and down, there is an advantage that the size is reduced compared to the conventional stacked package.

Claims (6)

반도체 칩이 실장되고 갈고리 형상을 갖는 제1 내부리드와, 상기 제1내부리드의 외측에 배열되어 있으며 앵커 형상을 갖는 제2내부리드를 포함하는 것을 특징으로 하는 적층형 반도체 리드 프레임.A stacked semiconductor lead frame comprising a first inner lead on which a semiconductor chip is mounted and having a hook shape, and a second inner lead arranged outside the first inner lead and having an anchor shape. 제1 및 제2 내부리드중 제1내부리드에 복수개의 상부/하부 반도체 칩이 다이본딩 되고, 상기 상부 반도체 칩의 본딩패드와 제2 내부리드가 와이어 본딩되며, 상기 하부 반도체 칩의 본딩패드와 제1 내부리드가 와이어 본딩되며, 상기 반도체 칩을 외부 환경으로부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸체를 형성한 것을 특징으로 하는 적층형 반도체 패키지.A plurality of upper and lower semiconductor chips are die-bonded to the first inner lead of the first and second inner leads, the bonding pad of the upper semiconductor chip and the second inner lead are wire bonded, and the bonding pads of the lower semiconductor chip. The first semiconductor package is wire bonded, and the package body is formed by molding an epoxy resin to protect the semiconductor chip from the external environment to form a package body. 복수의 본딩패드를 갖는 상부 반도체 칩과, 복수의 본딩패드를 가지며, 상기 상부 반도체 칩과 동일한 기능과 용량을 갖는 하부 반도체 칩과, 상기 상부 반도체 칩이 부착되는 상부면과 상기 하부 반도체 칩이 부착되는 하부면을 가지며 상기 하부 반도체 칩과 전기적으로 연결되는 제1내부리드와, 상기 제1내부리드와 일체형으로 형성되며 상기 상부 반도체 칩과 연결되는 제2내부리드를 갖는 리드 프레임과, 상기 상부 및 하부 반도체 칩과 상기 제1, 제2 내부리드를 보호하는 패키지 몸체를 구비하는 적층형 반도체 패키지.An upper semiconductor chip having a plurality of bonding pads, a lower semiconductor chip having a plurality of bonding pads and having the same function and capacity as the upper semiconductor chip, an upper surface to which the upper semiconductor chip is attached, and the lower semiconductor chip are attached A lead frame having a first inner lead electrically connected to the lower semiconductor chip and a second inner lead integrally formed with the first inner lead and connected to the upper semiconductor chip; A stacked semiconductor package having a lower semiconductor chip and a package body to protect the first and second internal leads. 제3 항에 있어서, 상기 상부/하부 반도체 칩들은 제1 내부리드상에 절연성 코팅재에 의해 다이본딩됨을 특징으로 하는 적층형 반도체 패키지.4. The stacked semiconductor package of claim 3, wherein the upper and lower semiconductor chips are die bonded by an insulating coating on the first inner lead. 제3 항에 있어서, 상기 상부/하부 반도체 칩들은 제1 내부리드상에 폴리이미드 테이프에 의해 다이본딩됨을 특징으로 하는 적층형 반도체 패키지.4. The stacked semiconductor package of claim 3, wherein the upper and lower semiconductor chips are die-bonded by polyimide tape on a first inner lead. 제3 항에 있어서, 상기 상부/하부 반도체 칩들은 제1 내부리드상에 절연성 접착제에 의해 다이본딩됨을 특징으로 하는 적층형 반도체 패키지.4. The stacked semiconductor package of claim 3, wherein the upper and lower semiconductor chips are die bonded by an insulating adhesive on the first inner lead.
KR1019950039735A 1995-11-04 1995-11-04 Stack semiconductor leadframe and semiconductor package using it KR0156332B1 (en)

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