KR970030725A - Stacked Semiconductor Lead Frames and Semiconductor Packages Using the Same - Google Patents

Stacked Semiconductor Lead Frames and Semiconductor Packages Using the Same Download PDF

Info

Publication number
KR970030725A
KR970030725A KR1019950039735A KR19950039735A KR970030725A KR 970030725 A KR970030725 A KR 970030725A KR 1019950039735 A KR1019950039735 A KR 1019950039735A KR 19950039735 A KR19950039735 A KR 19950039735A KR 970030725 A KR970030725 A KR 970030725A
Authority
KR
South Korea
Prior art keywords
bonded
inner lead
semiconductor chip
semiconductor
die
Prior art date
Application number
KR1019950039735A
Other languages
Korean (ko)
Other versions
KR0156332B1 (en
Inventor
안민철
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950039735A priority Critical patent/KR0156332B1/en
Publication of KR970030725A publication Critical patent/KR970030725A/en
Application granted granted Critical
Publication of KR0156332B1 publication Critical patent/KR0156332B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 중앙부에 캐비티 영역을 가지며 실장되는 반도체 칩 본딩패드를 중심으로 대향되는 다수의 내부리드를 갖는 리드프레임의 상/하면으로 반도체 칩을 양면 실장하여 더블 본딩에 의해 외부리드와 전기적으로 접속하며 에폭시 수지로 본딩하여 패키지 몸체를 형성시킴으로써, 접속되지 않는 핀을 이용하여 각각의 반도체 칩내의 신호의 전송을 분리 전송함으로써 메모리 용량의 확장이 가능하도록 한 적층형 반도체 패키지에 관한 것이다.According to the present invention, the semiconductor chip is mounted on both sides of the lead frame having a plurality of internal leads facing the center of the semiconductor chip bonding pads having a cavity area at the center thereof, and electrically connected to the external leads by double bonding. By forming a package body by bonding with epoxy resin, the present invention relates to a stacked semiconductor package that enables the expansion of memory capacity by separating and transmitting the transmission of signals in each semiconductor chip using pins that are not connected.

Description

적층형 반도체 리드 프레임 및 그를 이용한 반도체 패키지Stacked Semiconductor Lead Frames and Semiconductor Packages Using the Same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 3도는 이 발명의 적층형 반도체 패키지에 적용되는 리드 프레임의 평면도.3 is a plan view of a lead frame applied to the stacked semiconductor package of the present invention.

제 4도는 이 발명의 적층형 반도체 패키지의 일 실시예를 나타낸 단면도.4 is a cross-sectional view showing an embodiment of the stacked semiconductor package of the present invention.

제 5도는 이 발명의 적층형 반도체 패키지의 다른 실시예를 나타낸 단면도.5 is a cross-sectional view showing another embodiment of the stacked semiconductor package of the present invention.

제 6도는 이 발명의 적층형 반도체 패키지의 또다른 실시예를 나타낸 단면도.6 is a cross-sectional view showing yet another embodiment of the stacked semiconductor package of the present invention.

Claims (6)

중앙부에 캐비티 영역을 가지며 갈고리 형상의 내부리드를 갖는 반도체 칩 실장 영역과, 상기 반도체 침의 실장영역과 대향되어 배치되며 상기 내부리드와 더블 본딩이 되도록 앵커 형상으로 형성된 또 다른 내부리드를 포함하는 것을 특징으로 하는 적층형 반도체 리드 프레임.A semiconductor chip mounting region having a cavity region in the center and having a hook-shaped inner lead, and another inner lead disposed opposite to the mounting region of the semiconductor needle and formed in an anchor shape to be double bonded with the inner lead; A laminated semiconductor lead frame characterized by the above-mentioned. 제 1 및 제 2내부리드 중 제 1내부리드상에 복수개의 상부/하부 반도체 칩이 다이본딩 되고, 상기 상부 반도체 칩의 본딩패드와 제 2내부리드가 와이어 본딩되며, 상기 하부 반도체 칩의 본딩패드와 제 1내부리드가 와이어 본딩되며, 상기 반도체 칩을 외부 환경으로 부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸체를 형성한 것을 특징으로 하는 적층형 반도체 패키지.A plurality of upper and lower semiconductor chips are die-bonded on the first inner lead among the first and second inner leads, the bonding pads of the upper semiconductor chip and the second inner leads are wire bonded, and the bonding pads of the lower semiconductor chip. And a first inner lead are wire bonded, and a package body is formed by molding an epoxy resin to protect the semiconductor chip from an external environment. 복수개의 제 1 및 제 2내부리드 중 제 1내부리드상에 복수개의 상부/하부 반도체 칩이 다이본딩되고, 상기 상부 반도체 칩의 본딩패와, 제 2내부리드가 와이어 본딩되며, 상기 하부 반도체 칩의 본딩패드와 제 1내부리드가 볼 본딩되며, 상기 반도체 칩을 외부 환경으로 부터 보호하기 위하여 에폭시 수지로 몰딩하여 패키지 몸체를 형성한 것을 특징으로 하는 적층형 반도체 패키지.A plurality of upper / lower semiconductor chips are die-bonded on the first inner lead of the plurality of first and second inner leads, a bonding pad of the upper semiconductor chip and a second inner lead are wire-bonded, and the lower semiconductor chip is The bonding pad and the first internal lead of the ball-bonded, laminated semiconductor package, characterized in that the package body is formed by molding with an epoxy resin to protect the semiconductor chip from the external environment. 제 3항에 있어서, 상기 상부/하부 반도체 칩들은 제 1내부리드상에 절연성 코팅재에 의해 다이본딩됨을 특징으로 하는 적층형 반도체 패키지.4. The stacked semiconductor package of claim 3, wherein the upper and lower semiconductor chips are die bonded by an insulating coating on the first inner lead. 제 3항에 있어서, 상기 상부/하부 반도체 칩들은 제 1내부리드상에 폴리이미드 테이프에 의해 다이본딩됨을 특징으로 하는 적층형 반도체 패키지.4. The stacked semiconductor package of claim 3, wherein the upper and lower semiconductor chips are die-bonded by polyimide tape on a first inner lead. 제 3항에 있어서, 상기 상부/하부 반도체 칩들은 제 1내부리드상에 절연성 접착제에 의해 다이본딩됨을 특징으로 하는 적층형 반도체 패키지.4. The stacked semiconductor package of claim 3, wherein the upper and lower semiconductor chips are die bonded by an insulating adhesive on the first inner lead. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950039735A 1995-11-04 1995-11-04 Stack semiconductor leadframe and semiconductor package using it KR0156332B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950039735A KR0156332B1 (en) 1995-11-04 1995-11-04 Stack semiconductor leadframe and semiconductor package using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950039735A KR0156332B1 (en) 1995-11-04 1995-11-04 Stack semiconductor leadframe and semiconductor package using it

Publications (2)

Publication Number Publication Date
KR970030725A true KR970030725A (en) 1997-06-26
KR0156332B1 KR0156332B1 (en) 1998-10-15

Family

ID=19432979

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950039735A KR0156332B1 (en) 1995-11-04 1995-11-04 Stack semiconductor leadframe and semiconductor package using it

Country Status (1)

Country Link
KR (1) KR0156332B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100337345B1 (en) * 1999-10-29 2002-05-21 이계안 Hypoid gear meshing adjusting device for transfer case

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100337345B1 (en) * 1999-10-29 2002-05-21 이계안 Hypoid gear meshing adjusting device for transfer case

Also Published As

Publication number Publication date
KR0156332B1 (en) 1998-10-15

Similar Documents

Publication Publication Date Title
US5689135A (en) Multi-chip device and method of fabrication employing leads over and under processes
JP4195804B2 (en) Dual die package
US6277673B1 (en) Leads under chip in conventional IC package
KR0179803B1 (en) Lead-exposured semiconductor package
KR20040011348A (en) Semiconductor device
US20020117764A1 (en) Lead-on-chip type of semiconductor package with embedded heat sink
KR950007068A (en) Method for manufacturing stacked semiconductor device and semiconductor package thereof
KR20010022174A (en) Semiconductor device and method for manufacturing the same
US5811875A (en) Lead frames including extended tie-bars, and semiconductor chip packages using same
JP2908350B2 (en) Semiconductor device
KR970030725A (en) Stacked Semiconductor Lead Frames and Semiconductor Packages Using the Same
KR970077602A (en) A padless leadframe having a tie bar integrally formed with a chip bonding portion and a semiconductor chip package
KR100216065B1 (en) Multi-lead on chip package
JPH0529528A (en) Semiconductor integrated circuit device and lead frame used for same
KR0185571B1 (en) Leadframe and semiconductor chip package
KR0135889Y1 (en) Complex-type semiconductor package
KR20000003001A (en) Multi chip package using double sided tape
KR960032658A (en) Semiconductor package device
KR20000050381A (en) Lead on chip package
KR950002001A (en) Semiconductor package
KR20030055834A (en) Ball grid array type semiconductor chip package using leadframe and stack package
KR200154510Y1 (en) Lead on chip package
KR940008056A (en) Semiconductor device and manufacturing method thereof
KR200286322Y1 (en) Semiconductor package
KR970053649A (en) Wireless Semiconductor Package

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090714

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee