Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/402—Field plates
  • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/401—Multistep manufacturing processes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
  • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

• the present disclosure relates generally to the fabrication of field plate dielectrics for high-voltage semiconductors and, more specifically, the present disclosure relates to the fabrication of tapered field plate dielectrics for high-voltage semiconductor devices.
• ac high-voltage alternating current
• a power converter or power supply can be utilized to transform the high voltage ac input into a well regulated direct current (dc) output through an energy transfer element.
• dc direct current
• One type of power converter is a switch mode power converter, which is commonly used due to its high efficiency, small size, and low weight to power many of today's electronics.
• Many switch mode power converters that provide electricity to electronics, such as tablet computers, smart phones, and LED lights rely on power semiconductor devices that can handle high-voltages. For example, semiconductor devices in cell phone chargers may be required to handle peak voltages of up to 600 V without breaking down.
• VTS HVFET vertical thin silicon
• FIG. 1 depicts an example VTS HVFET 10 built on wafer 11.
• VTS HVFET 10 includes source regions 15a and 15b, body region 14, and drain regions 12 and 13 (which include a long drain extension) in a silicon pillar.
• a potential applied to gates 17a and 17b may modulate a channel in body region 14 and control conduction between source regions 15a and 15b and drain regions 12 and 13.
• FIGS. 1-10 illustrate the formation of a tapered oxide by depositing and etching in multiple stages.
• FIGS. 11-23 illustrate the formation of a tapered oxide by depositing a thick oxide in multiple stages.
• FIGS. 2A–2C depict the formation of a hardmask according to an example process for forming a tapered field plate dielectric region.
• FIGS. 3A and 3B depict the etching of a trench according to the example process for forming the tapered field plate dielectric region.
• FIGS. 4A and 4B depict a first cycle of deposition and etching of an insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIGS. 5A and 5B depict a second cycle of deposition and etching of an insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIGS. 5A and 5B depict a second cycle of deposition and etching of an insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIG. 6A and 6B depict a third cycle of deposition and etching of an insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIG. 7 depicts a tapered field plate dielectric region ready to receive a conductive material to form an example tapered field plate according the example process.
• FIG. 8 depicts a cross-section of another tapered field plate dielectric region with a different profile.
• FIG. 9 depicts the conductive material deposited into the tapered region formed by the tapered field plate dielectric region to form the tapered field plate dielectric region.
• FIG. 10 depicts a flow chart for an example process for forming a tapered field plate dielectric region. [0017] FIG.
• FIGS. 12A and 12B depict the formation of a mask for etching a trench for a tapered field plate and field plate dielectric region according to an example process for forming the tapered field plate dielectric region.
• FIGS. 13A and 13B depict the etching of a trench according the example process for forming the tapered field plate dielectric region.
• FIGS. 14A and 14B depict depositing a first insulating layer and filling a gap in the insulating layer with a mask layer according to the example process for forming the tapered field plate dielectric region.
• FIG. 12A and 12B depict the formation of a mask for etching a trench for a tapered field plate and field plate dielectric region according to an example process for forming the tapered field plate dielectric region.
• FIGS. 13A and 13B depict the etching of a trench according the example process for forming the tapered field plate dielectric region.
• FIGS. 14A and 14B depict depositing a first insulating layer and filling a
• FIGS. 16A and 16B depict an isotropic etch of the insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIGS. 17A and 17B depict a second iteration of etching the mask layer according to the example process for forming the tapered field plate dielectric region.
• FIGS. 18A and 18B depict a second iteration of an isotropic etch of the insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIGS. 16A and 16B depict an isotropic etch of the insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIGS. 17A and 17B depict a second iteration of etching the mask layer according to the example process for forming the tapered field plate dielectric region.
• FIGS. 18A and 18B depict a second iteration of an isotropic etch of the insulating layer according to the example process for forming the tapered field plate dielectric region.
• FIG. 19A and 19B depict a third iteration of etching the mask layer according to the example process for forming the tapered field plate dielectric region.
• FIG. 20 depicts a tapered field plate dielectric region after several more iterations of etching the insulating layer and etching the mask layer according to the example process for forming the tapered field plate dielectric region.
• FIG. 21 depicts a tapered field plate dielectric region having a less ideal profile.
• FIGS. 22A and 22B depict deposition of a conductive material used to form the tapered field plate according to the example process for forming the tapered field plate dielectric region.
• FIG. 20 depicts a tapered field plate dielectric region after several more iterations of etching the insulating layer and etching the mask layer according to the example process for forming the tapered field plate dielectric region.
• FIG. 21 depicts a tapered field plate dielectric region having a less ideal profile.
• FIGS. 22A and 22B depict deposition of a
• FIG. 1 depicts field plate 18 with field plate dielectric 19 that is substantially the same thickness along the depth of field plate 18.
• a graded doping profile for the extended drain region 13 may be necessary.
• the graded doping of drain region 13 may be gradually reduced along the depth as the surface of VTS device 10 is approached. In this manner, VTS device 10 is able to deplete between the extended drain region 13 and oxide 19 such that VTS device 10 is capable of supporting the maximum breakdown voltage.
• one disadvantage of having a graded doping profile may be having lighter doping closer to the surface of VTS device 10 that may cause a higher specific resistance and reduced efficiency.
• the field plate dielectric thickness is varied along the depth of the device.
• the oxide thickness is minimal at the surface and increases along the depth of the device 10 until it approaches the bottom which allows for increased doping of extended drain region 13 near the surface of VTS device 10.
• the specific resistance of VTS device10 may be reduced by a factor of up to 3 to 4 times.
• specific on resistance may be defined as the resistance that is inherent, based on material and design of the semiconductor, when there is substantially zero volts between the drain and source of VTS device 10. It may be appreciated that to improve efficiency of the semiconductor device, the specific resistance may be reduced to reduce power dissipation when the device is conducting.
• a varying thickness of the field plate dielectric could be accomplished by tapering. In this manner, a constant distribution of doping may be accomplished.
• FIG. 1 An example process for forming a tapered field plate dielectric in a semiconductor substrate is described below. This example process may be useful with processes that form a variety of types of devices, such as Schottky diodes, HVFETs, JFET, IGBT, bipolar transistors and the like.
• the tapered field plate dielectric fabrication is described with respect to figures depicting various stages of the example process. For ease of discussion, the example process is described with respect to the fabrication of one field plate dielectric region. However, it should be understood that only a portion of the substrate is depicted in the figures. In practice, many devices (e.g., HVFETs) with field plates having tapered field plate dielectric regions may be formed in parallel across the substrate.
• FIG. 1 An example process for forming a tapered field plate dielectric in a semiconductor substrate is described below. This example process may be useful with processes that form a variety of types of devices, such as Schottky diodes, HVFETs, JFET, IGBT, bipolar transistors
• Wafer 202 may be made of a variety of materials, such as, for example, silicon, silicon carbide, diamond, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and the like. Wafer 202 may also be made of multiple different materials to form a hetero structure. Wafer 202 may also be formed of a base wafer (e.g., a silicon wafer) with other layers (e.g., epitaxilally grown layers) grown on top of the base wafer. In one example, wafer 202 may be a thickness of 700 -1000 ⁇ m.
• protective layer 204 is deposited on the surface of wafer 202 to protect the surface of wafer 202 from defects and damage during processing.
• Protective layer 204 and mask layer 206 may be optional in some variations of the example process.
• the tapered oxide can be formed without mask layer 206 and the silicon pillar itself may be used as the hard mask for the oxide.
• protective layer 204 may be, for example, thermally grown oxide with a thickness of about 200 A.
• Mask layer 206 may be a hard mask (e.g., polysilicon, nitride, and the like).
• Mask layer 206 may be selected to have different etching properties as the insulating material that will be used to form the field plate dielectric. By choosing mask layer 206 to have different etching properties than the field plate dielectric, an etch with a high selectivity to the field plate dielectric material over mask layer 206 may be used, which allows for mask layer 206 to be used throughout the formation of the tapered field plate dielectric. For example, poly silicon may be used for mask layer 206. If the field plate dielectric material will be oxide, then it should be possible to select an etch recipe that has an etch selectivity of oxide to silicon of 10:1 or 20:1.
• mask layer 206 may be about 2–5 ⁇ m thick, although other thicknesses may be possible depending on the selectivity of the etch recipe used for etching the field plate dielectric material.
• FIG. 2B depicts substrate 200 after mask layer 208 has been deposited and patterned to define the location of the trench and field plate dielectric adjacent the silicon pillar where the semiconductor device will be located (these pillars will roughly be under the remaining portions of mask layer 208).
• Mask layer 208 is a photo resist mask.
• protective layer 204 and mask layer may not be used and photoresist layer may be deposited directly on surface of silicon wafer 202.
• FIG. 2C depicts substrate 200 after mask layer 206 and protective layer 204 have been etched to expose the surface of wafer 202 in the region where the trench will be etched, as defined by mask layer 208.
• the exposed portion of waver 202 is d EXPOSED and may be about 10–12 ⁇ m wide.
• FIG. 3A depicts substrate 200 after a trench 302 has been formed.
• a deep reactive ion etch (DRIE) step is used, which results in the formation of scallops 304 on the sidewalls 306 of trench 302.
• Trench 302 may be etched to depth 308, which, in one example, may be about 60 ⁇ m deep.
• DRIE deep reactive ion etch
• FIG. 3B depicts substrate 200 after mask layer 208 has been removed. Removing mask layer 208 may be accomplished with various steps. For example, if mask layer 208 is a photoresist mask, then a plasma ashing step may be used. In another example, if nitride or oxide are used, a phosphoric acid or hydrofluoric acid, respectively, etch step may be used.
• FIG. 4A depicts substrate 200 after insulating layer 402 is deposited. As stated above, a field plate dielectric comprises one or more insulating layers 402.
• the process for depositing insulating layer 402 may be conformal so that approximately a thickness of d DEP1 of insulating material is present on exposed surfaces which are both vertical (e.g., sidewalls 306) and horizontal surfaces (e.g., the bottom of trench 302 and on top of mask layer 206).
• Insulating layer 402 may be silicon dioxide, silicon nitride, boron phosphide silicate glass, and the like. Processes, such as low pressure chemical vapor deposition, high density plasma, plasma enhanced chemical vapor deposition, and the like, may be used to deposit insulating layer 402.
• the thickness d DEP1 may be determined in response to temperature, time, and light in processes. In another example d DEP1 is approximately 0.5 ⁇ m.
• FIG. 4B depicts substrate 200 after etching a thickness, d ETCH1 of insulating layer 402 with a highly anisotropic etch. In other words, horizontal surfaces of the substrate are etched substantially more than vertical surfaces.
• the etch ratio of vertical to horizontal which may also be known as directionality of the etch, can be 100 to 1.
• d ETCH1 may be a distance of 4 ⁇ m in the vertical direction.
• the etch recipe used for etching insulating layer 402 may be selected such that the etch rate of insulating layer 402 is much higher than the etch rate of mask layer 206 or wafer 202. If the selectively of the etch recipe is high enough, the same mask layer 206 may be used throughout the process of forming the tapered field plate dielectric.
• the etch recipe for etching insulating layer 402 may have a similar selectivity for the material of insulating layer 402 over both the exposed portions of semiconductor wafer 202 at the bottom of trench 302 and mask layer 206 at the surface of semiconductor wafer 202. For example, a selectivity of at least 10:1 or even 20:1 may be used. [0043] As shown in FIG. 4B, d ETCH1 may be greater than d DEP1 such that the portions of insulating layer 402 on horizontal surfaces (e.g. top surface of mask layer 202 and bottom portion of trench 302) will be completely removed.
• the portions of insulating layer 402 on vertical surfaces will be etched down by approximately d ETCH1 or in some cases, an amount less than d ETCH1 , as depicted on sidewalls 306 of trench 302.
• d ETCH1 an amount less than d ETCH1
• only an upper portion, which is proportional in depth to d ETCH1 , of insulating layer 402 on vertical surfaces is removed (e.g., the portion of insulating layer 402 on the sidewalls 306 in trench 302).
• scallops 304 do not appear in FIG. 4A. The scallops may be removed from the sidewalls of trench 302 prior to the deposition of insulating layer 402.
• FIG. 5A depicts substrate 200 after insulating layer 502 has been deposited on substrate 202. Insulating layer 502 may be deposited on top of insulating layer 402 on sidewalls 306 of trench 302 where insulating layer 402 had not been previously removed.
• the process for depositing insulating layer 502 may be conformal so that approximately a thickness of d DEP2 of insulating material 502 is deposited on both vertical and horizontal surfaces.
• Insulating layer 502 may be the same material deposited with the same technique to the same thickness as insulating layer 402.
• insulating layer 502 may be a different material, deposited with a different technique, or have a different thickness. Portions of sidewalls 306 that did not have insulating layer 402 removed may now have approximately a total thickness of d DEP1 + d DEP2 of insulating material.
• FIG. 5B depicts substrate 200 after etching a thickness, d ETCH2 , of insulating layer 502 and some of insulating layer 402 with an anisotropic etch (e.g., the same etch used to etch insulating layer 402 as discussed with respect to FIG. 4B).
• FIG. 6A depicts substrate 200 after insulating layer 602 has been deposited on substrate 202.
• the process for depositing insulating layer 602 may be conformal so that approximately a thickness of d DEP3 of insulating material 602 is deposited on both vertical and horizontal surfaces.
• Insulating layer 602 may be the same material deposited with the same technique to the same thickness as insulating layer 402 or insulating layer 502.
• insulating layer 602 may be a different material, deposited with a different technique, or have a different thickness. Portions of sidewalls 306 that did not have insulating layers 402 and 502 removed may now have approximately a total thickness of d DEP1 + d DEP2 + d DEP3 of insulating material. However, portions of wafer 202 that are exposed at the bottom of trench 302 have a thickness of only approximately d DEP3 of insulating material. As shown, a first region 609 includes only portions of insulating layer 602 and the insulating material is a thickness of d DEP3 .
• a second region 611 includes portions of insulating layer 402 and 602 and the total thickness of insulating material along sidewalls 306 in region 611 is d DEP1 + d DEP3 .
• a third region 613 includes portions of insulating layer 402, 502, and 602 and the total thickness of insulating material along sidewalls 306 in region 613 is equal to d DEP1 + d DEP2 +d DEP3 .
• FIG. 6B depicts substrate 200 after etching a thickness d ETCH3 of insulating layer 602 (and some of insulating layer 402 and insulating layer 502) with an anisotropic etch (e.g., the same etch used to etch insulating layer 402 as discussed with respect to FIG.
• a first region 615 contains only insulating layer 402 and the insulating material in first region 615 is a thickness of d DEP1 .
• a second region 617 includes portions of insulating layer 402 and 502 along sidewalls 306 and the total thickness of insulating material in region 617 is d DEP1 + d DEP2 .
• a third region 619 includes portions of insulating layers 402, 502, and 602, and the total thickness of insulating material along sidewalls 306 in region 619 is equal to d DEP1 + d DEP2 +d DEP3 .
• the process of depositing and etching dielectric may be repeated as many time as necessary to fill trench 302.
• nine cycles of depositing and etching were used to fill the trench depicted in FIG. 7.
• the nine cycles are associated with insulating layer 402, 502, and 602 described above and six additional cycles that produce insulating layers 701-706.
• the slope, m OX , of the tapered field plate dielectric region may be approximated by d ETCHX /d DEPX .
• the profile of the tapered field plate dielectric region may be different. For example, by using different thicknesses of insulating layers and etching different amounts of the insulating layers, the profile of the tapered field plate dielectric region may be controlled.
• the profile of the tapered field plate dielectric region will have multiple different slopes along the profile of the tapered field plate dielectric region.
• the tapered field plate dielectric region has been depicted to have well-defined steps, with one step representing each deposition/etch cycle. However, in practice, it should be understood that the well-defined steps may not be present.
• the profile of the tapered field plate dielectric region may have a more linear shape.
• FIG.8 depicts substrate 800 that has another example of a profile for a tapered field plate dielectric that is not as ideal as the profile shown in FIG. 7. [0052] FIG.
• Conductive material 902 may be any number of materials, such as amorphous silicon, polycrystalline silicon, metal, and the like. If using a semiconductor for conductive material 902, then conductive material 902 may be in-situ doped as it is being deposited. The top of conductive material 902 may be then be planarized using a chemical mechanical polishing (CMP) or etch-back step. Electrical contact may then be made to the remaining portion of conductive material 902, which forms the tapered field plate.
• CMP chemical mechanical polishing
• FIG. 10 depicts a flow chart for example process 1000 (similar to the example process described above with respect to Figs. 2–9) for forming a tapered field plate dielectric region in a semiconductor substrate.
• a silicon wafer is obtained.
• the silicon wafer may have different layers of doping created with, for example, epitaxially grown layers of silicon.
• step 1004 a thin layer of oxide is grown on the surface of the silicon wafer to form a protective layer that protects the surface of the silicon wafer from processing damage and debris.
• a polysilicon hardmask is deposited (e.g., see FIG. 2A).
• the polysilicon hardmask may be used throughout the formation of the tapered field plate dielectric region that surrounds the tapered field plate.
• Polysilicon may be preferred for the hardmask because etch recipes may be readily available that provide high selectivity to etching oxide (or other insulating materials) over polysilicon.
• the hardmask is then patterned and etched using a photolithography step (e.g., see FIGS. 2B and 2C).
• step 1010 a DRIE (or Bosch etch) step is performed to define the trench for the sloped field plate (e.g., see FIG. 3A).
• steps 1008 and 1010 may be combined into one step.
• step 1012 any photoresist that is left from steps 1008 or 1010 is removed with a plasma ashing step (e.g., see FIG. 3B).
• step 1014 a layer of oxide is deposited over vertical and horizontal surfaces of the substrate, including the sidewalls and bottom of the trench formed in step 1010 (e.g., see FIGS. 4A, 5A, and 6A).
• step 1016 an anisotropic etch is performed to remove a certain thickness of the oxide deposited in step 1014 (e.g., see FIGS. 4B, 5B, and 6B). Because the etch is anisotropic (i.e., substantially anisotropic), the oxide on horizontal surfaces of the wafer is completely removed while only the upper most portion of the oxide on vertical sides is removed. Accordingly, most of the oxide deposited on the sidewalls of the trench (e.g. all the oxide on the sidewalls except for the upper most portion) will remain.
• step 1018 it is determined whether the trench is sufficiently filled with oxide to receive the material that forms the tapered field plate (e.g., see FIG. 7).
• step 1020 once the tapered field plate dielectric has been formed in the trench, polysilicon is deposited in the trench to form the tapered field plate (e.g., see FIG. 9). A planarization step may be needed to ensure that the field plate and the surface of the wafer are coplanar.
• step 1022 a semiconductor process flow is performed to form a HVFET in the silicon pillar adjacent the trench that contains the sloped field plate.
• FIG. 11 depicts an example VTS HVFET 1100 built on wafer (N+ substrate) 1110.
• VTS HVFET 1100 includes source regions 1150 (N+), body region 1140 (P Body), and 1130 (N extended drain region), which include a long drain extension in a silicon pillar.
• a potential applied to gates 1170 may modulate a channel in body region 1140 and control conduction between source regions 1150 and drain regions.
• HVFET 1100 also has field plate 1180 separated from the silicon pillar by field plate dielectric 1190 (Ox).
• Field plate 1180 allows for an increase in breakdown voltage by spreading high voltage drops over larger areas in the extended drain region (i.e., spreading out electric fields).
• Field plate dielectric 1190 is substantially the same thickness along the depth of field plate 1180. To develop a reliable device optimally, it may be suitable to maintain a constant electric field along extended drain region 1130. In order to maintain a constant electric field, a graded doping profile for the extended drain region 1130 may be necessary. In particular, the graded doping of drain region 1130 may be gradually reduced along the depth as the surface of VTS device 1100 is approached. In this manner, VTS device 1100 is able to deplete between the extended drain region 1130 and oxide 1190 such that VTS device 1100 is capable of supporting the maximum breakdown voltage.
• FIG. 12A depicts substrate 1200, which includes wafer 1202.
• Wafer 1202 may be made of a variety of materials, such as, for example, silicon, silicon carbide, diamond, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and the like. Wafer 1202 may also be made of multiple different materials to form a hetero structure.
• Wafer 1202 may also be formed of a base wafer (e.g., a silicon wafer) with other layers (e.g., epitaxially grown layers) grown on top of the silicon wafer.
• FIG. 12B depicts substrate 1200 after mask layer 1204 has been deposited and patterned to define the location of the trench and field plate dielectric adjacent the silicon pillar where the semiconductor device will be located ,which is roughly under the remaining portions of mask layer 1204.
• Mask layer 1204 may be a hardmask or a softmask.
• a soft mask may be a photoresist layer.
• a protective layer may be deposited on the surface of wafer 1202 prior to deposition and patterning of mask layer 1204.
• the protective layer may protect the surface of wafer 1202 from defects and damage during processing. If the example process does not use a protective layer (as depicted in FIG. 12B), a restoration step may be used to remove damage or clean defects from the surface of wafer 1202 prior to performing other processing that involves the surface of wafer 1202.
• a protective layer (not shown) may be, for example, a thermally grown oxide with a thickness of about 200 A.
• mask layer 1204 segment may have a length d MSEG of 1-3 ⁇ m.
• FIG. 13A depicts substrate 1200 after trench 1302 has been formed.
• FIG. 13B depicts substrate 1200 after mask layer 1204 has been removed.
• DRIE deep reactive ion etch
• Removing mask layer 1204 may be accomplished with various steps. For example, if mask layer 1204 is a photoresist mask, then a plasma ashing step may be used. In another example, if nitride or oxide are used for mask layer 1204, then a phosphoric acid or hydrofluoric acid, respectively, etch step may be used. [0062] FIG. 14A depicts substrate 1200 after insulating layer 1402 is deposited. The process for depositing insulating layer 1402 may be conformal so that approximately a thickness of d 1 of insulating material is present on vertical sidewalls 1306, the bottom of trench 1302, and on top of silicon pillars 1407. Insulating layer 1402 will also form gap 1404.
• Insulating layer 1402 may include silicon dioxide, silicon nitride, boron phosphide silicate glass, and the like. Processes, such as low pressure chemical vapor deposition, high density plasma, plasma enhanced chemical vapor deposition, and the like, may be used to deposit insulating layer 1402. In one example, d 1 may be between 0.5 ⁇ m and 10 ⁇ m and gap 1404 may be approximately 10 ⁇ m across. [0063] Note that scallops 1304 do not appear in FIG. 14A. The scallops may be removed from the sidewalls 1306 of trench 1302 prior to deposition of insulating layer 1402.
• FIG. 14B depicts substrate 1200 after a fill mask layer 1406 has been deposited on substrate 1200.
• the thickness d 2 of fill mask layer 1406 may be selected to ensure that gap 1404 is completely filled. In other variations of the example process, mask layer 1406 may not completely fill in gap 1404.
• gap 1404 may be pinched off, leaving a portion of gap 1404 unfilled (not shown).
• material of fill mask layer 1406 should have different etch properties as compared to the material of insulating layer 1402 so that an etch recipe is available that is highly selective to etching the material of insulating layer 1402 over the material of fill mask layer 1406. For example, if insulating layer 1402 is oxide, then mask layer 1406 may be polysilicon. [0065] FIG.
• FIG. 15 depicts substrate 1200 after mask layer 1406 has gone through a planarized etch to remove fill mask layer 1406 from the top surface of insulating layer 1402 and from a portion of sidewalls of insulating layer 1402 to recreate a portion of gap 1404 (represented by region 1502).
• FIG. 15 depicts a starting point of substrate 1200 before proceeding with alternating cycles of etching insulating layer 1402 and etching fill mask 1406 to create a tapered field dielectric region.
• FIGS. 16A and 16B depict substrate 1200 before and after an amount, e 1, of insulating layer 1402 is isotropically etched, which means that approximately the same amount of material is etched regardless of the slope of the surface where the etching is taking place.
• the amount of insulating layer 1402 that is etched from horizontal surfaces is approximately the same as the amount of insulating layer 1402 that is etched from vertical surfaces.
• the isotropic nature of the etch is illustrated by line 1602 that approximates the amount of insulating layer 1402 that is removed from FIG. 16A to FIG. 16B during the etch.
• the thickness e 1 of insulating material removed is approximately constant across the surface of insulating layer 1402. If the etch for insulating layer 1402 is selected properly, such that the etch may be selected to have a high selectivity to insulating layer 1402 over fill mask layer 1406, very little of mask layer 1406 should be etched.
• FIGS. 17A and 17B depict substrate 1200 before and after etching a thickness e 2 of fill mask layer 1406.
• a region 1702 defined by the newly exposed sidewalls of insulating material 1402 is formed below region 1502. Region 1702 is narrower than region 1502 and has roughly the same width as region 1502 had when it was first formed (see FIG.
• FIGS. 18A and 18B depict substrate 1200 before and after a thickness e 3 of insulating layer 1402 is isotropically etched, which allows for approximately the same amount of material to be etched regardless of the slope of the surface where the etching is taking place. In other words, the amount of insulating layer 1402 that is etched from horizontal surfaces is approximately the same as the amount of insulating layer 1402 that is etched from vertical surfaces. The isotropic nature of the etch is illustrated by line 1802 that approximates the amount of insulating layer 1402 that is removed from FIG. 18A to FIG. 18B during the etch.
• the amount of insulating material removed is approximately constant across the surface of insulating layer 1402. If the etch for insulating layer 1402 is selected properly, very little of mask layer 1406 should be etched (e.g., the same etch discussed with respect to FIGS. 16A and 16B). Note that because the sidewalls of insulating layer 1402 adjacent regions 1502 and 1702 were exposed, the width of region 1502 grew by approximately 2 * e 3 more (or 2 * e 3 + 2 * e 1 total from the initial width of region 1502), and the width of region 1702 grew by approximately 2 * e 3 (or 2 * e 3 total from the initial width of region 1702).
• FIGS. 19A and 19B depict substrate 1200 before and after etching a thickness e 4 of fill mask layer 1406.
• region 1902 defined by the newly exposed sidewalls of insulating material 1402 is formed below regions 1502 and 1702.
• Region 1902 is narrower than region 1702 and has roughly the same width as regions 1502 and 1702 had when first formed (see FIG. 15 and FIG. 17, respectively) because the initial width of regions 1902, 1702, and 1502 are all determined by the width of gap 1404 (FIG. 14A).
• Iterations of etching insulating layer 1402 and mask layer 1406 may continue until the desired taper of insulating layer 1402 has been achieved.
• the process of alternating the two etches may continue for some fixed number of iterations known to produce the desired taper.
• the process of alternating the two etches may continue until mask layer 1406 is gone or has a thickness below some threshold.
• FIG. 20 depicts substrate 1200 after six total iterations of etching mask layer 1406 and insulating layer 1402.
• the slope, m TAPER of the taper of insulation layer 1402 may be about e 1 /e 2 .
• the profile of insulating layer 1402 may be different.
• the profile of the insulating region may be controlled.
• the profile of insulating layer 1402 will have multiple different slopes along the exposed sidewall of insulating layer 1402.
• the insulating material has been depicted to have well-defined steps, with one step representing each deposition/etch cycle. However, in practice, it should be understood that the well-defined steps may not be present.
• the profile of the insulating region may have a more linear shape.
• FIG. 21 depicts substrate 2100 that has another example of a profile for a tapered field plate dielectric that is not as ideal as the profile shown in FIG. 20. [0074] FIG.
• FIG. 22A depicts substrate 1200 after all iterations of the alternating etch steps have been completed and any remaining portion of fill mask layer 1406 has been removed. It should be understood that in variations of the example process, all of fill mask layer 1406 may be etched during the iterations of the alternative etch steps. Other variations of the example process may also leave any remaining portions of fill mask layer 1406 to be part of the field plate that is formed after deposition of a conductive material in the trench formed by the taper in insulating layer 1402 (see FIG. 22B). [0075] FIG. 22B depicts substrate 1200 after deposition of conductive material 2202 which fills the rest of trench 1302 (not labeled) that was not filled by insulating layer 1402 or was etched during the formation of the taper.
• Conductive material 2202 may be any number of materials, such as amorphous silicon, polycrystalline silicon, metal, and the like. If using a semiconductor for conductive material 2202, then conductive material 2202 may be in-situ doped as it is being deposited. The top of conductive material 2202 may be then be planarized using a chemical mechanical polishing (CMP) or etch-back step. Electrical contact may then be made to the remaining portion of conductive material 2202, which forms the tapered field plate. Once the field plate is formed, insulating layer 1402 becomes tapered field plate dielectric region 2204.
• CMP chemical mechanical polishing
• FIG. 23 depicts a flow chart for example process 2300 (similar to the example process described above with respect to FIGS.12-22, for forming a tapered field plate dielectric region in a semiconductor process.
• step 2302 a silicon wafer is obtained.
• the silicon wafer may have different layers of doping created with, for example, epitaxially grown layers of silicon (e.g., see FIG. 12A).
• a photoresist mask is patterned (e.g., see FIG. 12B). The photoresist mask defines the location and size of the trench that contains the tapered field plate and tapered field plate dielectric region.
• a DRIE (or Bosch etch) step is performed to define the trench for the tapered field plate (e.g., see FIG. 13A) and any remaining photoresist is striped (e.g. see FIG. 13B).
• a layer of oxide is deposited over vertical and horizontal surfaces of the substrate (e.g., see FIG. 14A).
• a poly silicon masking layer is deposited over the wafer and in the gap formed by the oxide deposition of step 2308 (e.g., see FIG. 14B).
• an etch of the polysilicon mask is performed to expose a portion of the sidewalls of the oxide layer in the gap (e.g., see FIG. 15).
• an isotropic oxide etch is performed to remove a certain thickness of the oxide deposited in step 2308 (e.g., see FIGS. 16A and 18A).
• step 2316 the polysilicon mask is etched by a further amount to expose a new portion of the sidewall of the oxide layer from step 2308 in the gap (e.g., see FIGS. 17B and 19B).
• step 2318 it is determined whether the taper of the oxide layer has been completed (e.g., see FIG. 20). For example, this may be determined based on the number of oxide etch/poly etch iterations that have been performed. As another example, iterations of steps 2314 and 2316 may be repeated until a threshold thickness of poly (or no poly) remains.
• step 2320 once the tapered field plate dielectric has been formed in the trench, polysilicon is deposited in the trench to form the tapered field plate (e.g., see FIG. 22B). A planarization step may be needed to ensure that the field plate and the surface of the wafer are coplanar.
• step 2322 a MOSFET process flow is performed to form a HVFET in the silicon pillar adjacent the trench that contains the sloped field plate.

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