WO2014012321A1 - P型、n型半导体出光垂直传导发光二极管的制造方法 - Google Patents

P型、n型半导体出光垂直传导发光二极管的制造方法 Download PDF

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Publication number
WO2014012321A1
WO2014012321A1 PCT/CN2012/086085 CN2012086085W WO2014012321A1 WO 2014012321 A1 WO2014012321 A1 WO 2014012321A1 CN 2012086085 W CN2012086085 W CN 2012086085W WO 2014012321 A1 WO2014012321 A1 WO 2014012321A1
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Prior art keywords
light
substrate
layer
gallium nitride
emitting
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PCT/CN2012/086085
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English (en)
French (fr)
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廖丰标
顾玲
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江苏扬景光电有限公司
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Publication of WO2014012321A1 publication Critical patent/WO2014012321A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials

Definitions

  • the present invention relates to the field of manufacturing light-emitting diodes, and more particularly to a method of fabricating a p-type, n-type semiconductor light-emitting vertical-conduction light-emitting diode.
  • the substrate used for nitride light-emitting diodes is a sapphire material (A1 2 0 3 ), which is an insulator, it is necessary to remove the sapphire substrate or to punch holes in the sapphire substrate to achieve vertical conduction. Since the sapphire substrate has the function of supporting the semiconductor device, the semiconductor device and the sapphire substrate are attached to other substrate materials such as Si, metal, etc. before removing the sapphire substrate, and then the sapphire substrate is removed. Although the heat dissipation characteristics of the new substrate materials are generally superior to those of the sapphire substrate, the process of attaching and sapphire removal has a great influence on the yield. Substrate drilling is a better option.
  • the non-light-emitting surface is bonded to the heat-dissipating metal, which is very helpful for heat dissipation of the LED.
  • the prior art uses a sapphire substrate to punch holes, but the design of the electrodes fails to achieve optimum light output. Summary of the invention
  • an object of the present invention is to provide a method for fabricating a p-type, n-type semiconductor light-emitting vertical-conduction light-emitting diode, which uses an etched sapphire substrate and an electrode having a light-emitting and reflecting surface. Designed to increase the amount of light emitted by vertical-conducting nitride LEDs (light-emitting diodes) and luminous efficiency.
  • a first technical solution adopted by the present invention is a method for manufacturing a p-type semiconductor light-emitting vertical conduction light-emitting diode, comprising the following steps:
  • the substrate epitaxially growing a light emitting structure of the light emitting diode on a front surface of the substrate, the light emitting structure comprising a gallium nitride buffer layer and a gallium nitride light emitting diode epitaxial layer formed in sequence, wherein the gallium nitride light emitting diode
  • the epitaxial layer includes an n-type gallium nitride layer, a light-emitting layer, and a P-type gallium nitride layer disposed in sequence;
  • the n-electrode structure including a transparent electrode, a reflective metal layer, and a bonding metal layer which are sequentially disposed.
  • the step of punching the back surface of the substrate comprises: 1) using a laser to complete most of the opening of the nitride device substrate, the target depth of the opening is no more than 10 microns;
  • a protective layer is first formed on the back surface of the opening surface of the semiconductor wafer; and the step 3) is further included: removing the protective layer.
  • the angle between the bottom of the opening and the wall of the hole is greater than 90 degrees. More preferably, the angle between the wall of the hole and the horizontal plane gradually increases from the bottom of the opening to the surface of the substrate.
  • a protective layer is first formed on the back surface of the opening surface of the semiconductor wafer; and the step (3) is further included: removing the protective layer.
  • the protective layer has a thickness of ⁇ . ⁇ to 5 ⁇ . More preferably, the protective layer has a thickness of ⁇ . ⁇ to 3 ⁇ . Most preferably, the protective layer has a thickness of ⁇ . ⁇ to 1 ⁇ .
  • the light source of the laser is a pulsed laser.
  • the wavelength of the laser light is preferably 200 nm to 11 ⁇ m. More preferably, the wavelength of the laser light is from 240 nm to 1.6 ⁇ m.
  • the power of the laser is preferably not more than 2W. More preferably, the power of the laser does not exceed 1 W.
  • step 1) when the nitride device substrate is opened using a laser, the gas is blown onto the laser processing portion for cooling.
  • the second technical solution adopted by the present invention is a method for manufacturing an n-type semiconductor light-emitting vertical conduction light-emitting diode, comprising the following steps:
  • the substrate epitaxially growing a light emitting structure of the light emitting diode on a front surface of the substrate, the light emitting structure comprising a gallium nitride buffer layer and a gallium nitride light emitting diode epitaxial layer formed in sequence, wherein the gallium nitride light emitting diode
  • the epitaxial layer includes an n-type gallium nitride layer, a light-emitting layer, and a P-type gallium nitride layer disposed in sequence;
  • n-electrode structure is formed on the back surface of the substrate, and the n-electrode structure includes a transparent electrode and an n-pad which are sequentially disposed.
  • the step of punching the back surface of the substrate comprises:
  • the target depth of the opening is not more than 10 microns
  • step 1) a protective layer is first formed on the back surface of the opening surface of the semiconductor wafer; Also included is step 3): removing the protective layer.
  • the angle between the bottom of the opening and the wall of the hole is greater than 90 degrees. More preferably, the angle between the wall of the hole and the horizontal plane gradually increases from the bottom of the opening to the surface of the substrate.
  • a protective layer is first formed on the back surface of the opening surface of the semiconductor wafer; and the step (3) is further included: removing the protective layer.
  • the protective layer has a thickness of ⁇ . ⁇ ⁇ to 5 ⁇ . More preferably, the protective layer has a thickness of ⁇ . ⁇ ⁇ to 3 ⁇ . Most preferably, the protective layer has a thickness of ⁇ . ⁇ ⁇ to 1 ⁇ .
  • the light source of the laser is a pulsed laser.
  • the wavelength of the laser light is preferably 200 nm to 1 1 ⁇ . More preferably, the wavelength of the laser light is from 240 nm to 1.6 ⁇ m.
  • the power of the laser is preferably not more than 2W. More preferably, the power of the laser does not exceed 1 W.
  • step 1) when the nitride device substrate is opened using a laser, the gas is blown onto the laser processing portion for cooling.
  • the present invention adopts a sapphire substrate perforation and has an electrode design of a light-emitting and reflecting surface to increase the light-emitting amount and luminous efficiency of the vertically-conductive nitride LED.
  • the invention firstly uses a laser to open most of the holes, and then etches them to a predetermined position by dry etching, which not only ensures the efficiency of the overall opening, but also ensures the precision requirement and improves the yield.
  • FIG. 1 is a schematic view showing a first step of a method for fabricating a p-type semiconductor light-emitting vertical conduction light-emitting diode, wherein the oblique portion is a gallium nitride buffer layer, the same below;
  • FIG. 2 is a schematic view showing the second step of the manufacturing method of the p-type semiconductor light-emitting vertical conduction light-emitting diode
  • FIG. 3 is a schematic view showing the third step of the manufacturing method of the p-type semiconductor light-emitting vertical conduction light-emitting diode
  • FIG. 4 is a schematic diagram of the p-type semiconductor light-emitting vertical conduction light-emitting. Schematic diagram of the structure of the diode, the arrow in the figure indicates the direction of light, the same below;
  • Figure 5 is a plan view of Figure 4.
  • Figure 6 is a bottom view of Figure 4.
  • Figure 7 is a schematic view showing a predetermined opening stop face of the nitride semiconductor in which the opening is stopped on the substrate;
  • Figure 8 is a schematic view showing the structure of the nitride semiconductor in which the opening is stopped on the substrate, and the laser is opened.
  • Figure 9 is a schematic view showing the structure of the nitride semiconductor in which the opening is stopped on the substrate, and the opening is completed by dry etching;
  • Figure 10 is a schematic view showing the structure of the nitride semiconductor in which the opening is stopped on the substrate, and the protective layer is removed;
  • Figure 1 is a schematic structural view of the opening portion;
  • FIG. 12 is a schematic structural view of an n-type semiconductor light-emitting vertical conduction light-emitting diode
  • Figure 13 is a bottom view of Figure 12;
  • Figure 14 is a plan view of Figure 12 .
  • the vertical conduction light-emitting diodes punched by the sapphire substrate can be divided into two types: P-type semiconductor light-emitting and n-type semiconductor light-emitting.
  • Example 1 p-type semiconductor light
  • a sapphire substrate is provided, and a light emitting structure of the light emitting diode is epitaxially grown on a front surface of the substrate, and the light emitting structure includes a GaN buffer layer sequentially formed and a GaN LED epitaxial layer, wherein the GaN LED epitaxial layer comprises an n-type gallium nitride layer and a multi-quantum well active layer (MQW active layer) And a p-type gallium nitride layer;
  • MQW active layer multi-quantum well active layer
  • a P-electrode structure is formed on the p-type gallium nitride layer, and the P-electrode structure includes a transparent electrode and a P-pad which are sequentially disposed, and can pass through the p-pad Wire the external circuit.
  • the material of the transparent electrode may be, for example, an alloy of nickel oxide and gold (NiO/Au), indium tin oxide (ITO), zinc oxide ( ⁇ ) or aluminum zinc oxide (Aluminum Zinc Oxide, AlZnO).
  • the semiconductor layer forms an ohmic contact; the material of the p-pad may be, for example, an alloy of Ti and Al, an alloy of Ti and Au, or an alloy of Ti, Al and Au.
  • the transparent electrode and the P-pad of the light-emitting surface each need to use a lithography process to define the transparent electrode region and the p-pad of the light surface, respectively.
  • a transparent electrode having a smooth surface is produced, first, transparent electrode evaporation, sputtering, or electroplating is performed on the surface of the wafer, and then a photosensitive material (photo-adhesive) is applied, and a photomask is placed over the wafer.
  • a photosensitive material photo-adhesive
  • an exposure step is performed to selectively illuminate the photosensitive material through the reticle, and the pattern on the reticle is completely transferred to the crystal.
  • the photoresist when the development is used after exposure, the photoresist can be obtained in the same or complementary pattern as the mask pattern.
  • the transparent electrode etching is performed, and after the etching is completed, the residual photo-adhesive is removed.
  • the pattern is then exposed (Exposure) step, so that the parallel light is selectively sensitized to the photosensitive material through the reticle, so that the pattern on the reticle is completely transferred to the wafer, and then developed and developed after exposure (Development)
  • the photoresist can be obtained in the same or complementary pattern as the reticle pattern.
  • Metal evaporation, sputtering or electroplating is then carried out, after which the unwanted metal is removed using a conventional Liftoff process.
  • the back surface of the substrate is perforated and stays in the n-type gallium nitride layer; the specific process is as follows:
  • a water-soluble resist was uniformly applied to the entire surface by a spin coater, and dried to form a protective film having a thickness of 2 ⁇ m.
  • the scattering of the dirt is intense, and it adheres to the surface and the back surface of the semiconductor wafer during processing.
  • the dirt is analyzed by electron microscopy (FE-SEM) for EDX (Energy Dispersive X-ray, X-ray energy spectrum quantitative analysis), and is Al, 0, C, Cl, Si having a composition of a compound semiconductor and a substrate. The composition of at least one element. Therefore, the back side of the machined surface is covered with a protective layer before laser processing.
  • a resist As the protective layer, a resist, a transparent resin, a glass, a metal or an insulating film can be used without any limitation.
  • the resist may be a water-soluble resist or the like used in photoetching.
  • the transparent resin may be acrylic resin, polyester, polyimide, vinyl chloride or silicone. In terms of metal, it may be nickel or titanium.
  • the insulating film may be silicon oxide or silicon nitride.
  • the thickness of the protective layer is preferably 0.001 ⁇ ⁇ or more, more preferably 0.01 ⁇ ⁇ or more.
  • the upper limit of the thickness is preferably 5 ⁇ ⁇ or less, more preferably 3 ⁇ ⁇ or less, and even more preferably ⁇ ⁇ ⁇ or less.
  • the laser is used to complete most of the openings with a target depth of no more than 10 microns.
  • the semiconductor wafer is fixed on the platform of the pulse laser processing machine using a vacuum chuck.
  • the platform is movable in the X-axis (left and right) and ⁇ -axis (front and rear) directions and is a rotatable construction.
  • After fixing adjust the optical system by focusing the laser on the machined surface.
  • the power, pulse length, and spot size of each pulse remain constant.
  • the etching depth of a certain area is proportional to the total number of pulses in the area. Therefore, the number of pulses of the pulsed laser, the relative position of the laser to the substrate, and the degree of coincidence of the spots can be controlled to produce the desired shape of the opening.
  • the subsequent process is usually to deposit, sputter or plate the metal layer on the hole surface of the substrate. It is desirable that the metal in the opening and the metal outside the hole are connected to form a whole electrode region.
  • the angle ⁇ of the bottom of the opening and the etched wall is greater than 90 degrees, and it is desirable that the angle between the etched wall and the horizontal plane ⁇ ' gradually increases from the bottom of the opening to the surface of the substrate, thus avoiding the hole
  • the metal and the metal outside the hole are not connected, as shown in FIG. Most of the openings must be completed (ie, the bottom of the opening is no more than 10 microns from the target depth), otherwise the residual substrate is not sufficient to support it after all openings have been completed. After processing is complete, the vacuum chuck is released and the wafer is removed from the platform.
  • the type of the laser light source is not particularly limited, and specifically, a C0 2 laser, a YAG laser, an excimer laser, a pulsed laser, or the like can be used.
  • a pulsed laser is preferred.
  • a solid laser such as Nd : YAG laser, Nd : YV04 laser, Yb : YAG laser or Ti : sapphire laser; fiber laser and harmonics thereof; excimer A gas laser such as light or a co 2 laser.
  • a short-pulse laser having a small heat influence or a laser having an oscillation wavelength of an ultraviolet region strongly absorbed by a hard and brittle material is preferably used.
  • the wavelength of the laser light may be 355 nm, 266 nm or the like, and a shorter wavelength may be used, and it is preferably adjusted to be Mn ⁇ ⁇ or less below 200 nm, and particularly preferably adjusted to be 240 nm or more and 1600 nm or less. Since the excess laser output damages the compound semiconductor, the power of the laser light is preferably 2 W or less, more preferably 1 W or less.
  • Solid-state lasers are generally available.
  • Q-switched Nd: YV04 lasers or Nd: YAG lasers which contain harmonic frequency generators, such as LB0 (lithium triborate), which are produced by solid-state lasers doped with germanium.
  • harmonic frequency generators such as LB0 (lithium triborate)
  • One of the second, third, fourth or fifth harmonic frequencies of the 1064 nanowire provides the output of the laser.
  • a third harmonic frequency of approximately 355 nanometers is provided.
  • the pulse wave has an energy density of between about 10 and 100 joules per square centimeter, a pulse duration between about 10 and 30 nanoseconds, and a spot size between about 5 and 25 microns.
  • the repetition rate of the pulse wave is greater than 5 kHz, preferably in the range of about 10 kHz and 50 kHz or higher.
  • the sapphire substrate moves at a rate of motion, causing the pulse waves to overlap by a number of 50 to 99 percent.
  • the oscillation mode of the laser pulse oscillation is not particularly limited, and examples thereof include pulse oscillation with a pulse width of about 0. lps to 20 ns, and Q-switch pulse oscillation. Further, in the Q-switch pulse oscillation, an A/0 component for high-speed repetition or an E/0 component for short-pulse oscillation can be used. Further, even if the continuous wave oscillates, a pulsed oscillation output of about several tens of KHz can be obtained by using an A/0-Q switch or the like.
  • the gas is blown onto the laser processing portion to cool the periphery of the processed portion of the compound semiconductor layer, thereby reducing thermal damage of the compound semiconductor layer. Moreover, the melted material produced by the processing is not attached to the machined surface.
  • Oxygen, nitrogen, helium, hydrogen, etc. can be used without any restrictions on the gas to be attached to the laser processing section. In particular, although helium gas, hydrogen gas, nitrogen gas or the like having a high cooling effect can be used, it is preferable to use inexpensive nitrogen gas.
  • the blowing of the gas is preferably such that the nozzle diameter of the front end is fine. When the nozzle diameter is finer, the blowing can be performed locally, and the flow velocity of the airflow can be made faster.
  • Dry Etching also known as Plasma Etching, uses gas as the main etching medium, such as C1 2 /BC1 3 , and drives the reaction by plasma energy. After etching the sapphire substrate, it stops. Living in a nitride semiconductor on a substrate.
  • the protective layer is removed together with the dirt attached to the surface.
  • the method of removal is not particularly limited, and any method can be used. As long as the protective layer can be completely removed, the ultrasonic wave, the jet stream, the rinsing, the immersion, the etching, the scrubbing, and the like can be used without any limitation.
  • the semiconductor wafer is placed on the platform of the cleaning machine to continuously rotate the semiconductor wafer in the semiconductor
  • the formed protective layer is removed by the flow of the rinse water on the layer side. Finally, it is rotated at a high number of revolutions to blow off the rinse water and dry.
  • a spin coater can form a protective layer having a uniform film thickness on the entire surface of the wafer, and after the processing, it can be easily washed and removed by water.
  • a photoresist is used on the protective layer, after the formation of the groove, it is immersed in phosphoric acid, sulfuric acid, hydrochloric acid, etc., and the stain of the processed portion is selectively removed by wet etching, and then the wafer is removed using an organic solvent such as acetone. It is preferred that the photoresist of the surface is completely removed.
  • an n-electrode structure is formed on the back surface of the substrate, the n-electrode structure including a transparent electrode, a reflective metal layer and a bonding metal layer which are sequentially plated, and an external circuit can be connected through the bonding metal layer.
  • the material of the reflective metal layer may be, for example, nickel (Ni), palladium (Pd), chromium (Cr), platinum Pt, aluminum (A1) or silver (Ag) for reflecting light emitted by the epitaxial layer of the gallium nitride light emitting diode.
  • the material of the bonding metal layer may be, for example, aluminum (Al), gold (Au) or gold alloy (Au alloy:).
  • Fig. 5 is a plan view of Fig. 4 showing the light-emitting surface (front side, P-electrode side) of the p-type semiconductor light-emitting vertical conduction light-emitting diode.
  • Fig. 6 is a bottom view of Fig. 4 showing the reverse side (n-electrode side) of the p-type semiconductor light-emitting vertical conduction light-emitting diode, see only the opening, and the broken line is the pattern of the front transparent electrode.
  • the difference between this embodiment and the embodiment 1 is that: the structure of the P-electrode in this embodiment is exactly the structure of the n-electrode in the embodiment 1, and the structure of the n-electrode in this embodiment is just implemented.
  • the pad in this embodiment is not a P-pad but an n-pad.
  • Figure 13 is a bottom plan view of Figure 12 showing the light-emitting surface (reverse side, n-electrode side) of the n-type semiconductor light-emitting vertical conduction light-emitting diode.
  • Figure 14 is a plan view of Figure 12 showing the front side (P-electrode side) of the n-type semiconductor light-emitting vertical conduction light-emitting diode, and the broken line is the pattern of the n-pad and sapphire holes on the reverse side.

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Abstract

本发明公开了一种p型半导体出光垂直传导发光二极管的制造方法，包括如下步骤：提供一衬底，在该衬底的正面外延成长发光二极管的发光结构，该发光结构包括依次形成的氮化镓缓冲层和氮化镓发光二极管磊晶层，其中氮化镓发光二极管磊晶层包括依次设置的n型氮化镓层、发光层和p型氮化镓层；在p型氮化镓层上形成p-电极结构，该p-电极结构包括依次设置的透明电极和p-焊盘；在衬底背面打孔，停留在n型氮化镓层；在衬底背面形成n-电极结构，该n-电极结构包括依次设置的透明电极、反射金属层和接合金属层。本发明还公开了一种n型半导体出光垂直传导发光二极管的制造方法。本发明能增加垂直传导氮化物LED的出光量与发光效率。

Description

说 明 书
p型、 n型半导体出光垂直传导发光二极管的制造方法 技术领域
本发明涉及发光二极管的制造领域， 特别涉及 p型、 n型半导体出光垂直传 导发光二极管的制造方法。
背景技术
垂直传导发光二极管的优点： 1.电流路径短， 因此顺向电压小； 2.电流分布 均匀， 减少电流拥塞（current crowding)现象； 3.可以减少打线数目； 4.非出光 面可接合散热层， 减少光衰。
因为氮化物发光二极管习用的衬底是蓝宝石材料 (A1203)， 属于绝缘体， 要 达到垂直传导必需移除蓝宝石衬底，或在蓝宝石衬底打孔。 因为蓝宝石衬底具支 撑半导体器件的作用， 移除蓝宝石衬底前需先将半导体器件连同蓝宝石衬底贴 附在其他衬底材料上，例如 Si、 金属等，之后，再移除蓝宝石衬底。 虽然一般新的 衬底材料的散热特性比蓝宝石衬底优越，但是贴附与蓝宝石移除的制程对良率的 影响巨大。衬底打孔是较优的选项，非出光面接合散热金属，对发光二极管散热很 有帮助，但是在蓝宝石衬底打孔并不容易，而且打孔后，出光与反射面的电极设计 关系发光效率。现有技术使用蓝宝石衬底打孔，但电极的设计未能得到最佳出光。 发明内容
发明目的： 针对上述现有技术存在的问题和不足， 本发明的目的是提供 p 型、 n型半导体出光垂直传导发光二极管的制造方法， 采取蓝宝石衬底打孔， 并 有出光与反射面的电极设计， 以增加垂直传导氮化物 LED (发光二极管） 的出 光量与发光效率。
技术方案： 为实现上述发明目的， 本发明采用的第一种技术方案为一种 p 型半导体出光垂直传导发光二极管的制造方法， 包括如下步骤：
( 1 ) 提供一衬底， 在该衬底的正面外延成长发光二极管的发光结构， 该发 光结构包括依次形成的氮化镓缓冲层和氮化镓发光二极管磊晶层，其中氮化镓发 光二极管磊晶层包括依次设置的 n型氮化镓层、 发光层和 P型氮化镓层；
(2) 在 p型氮化镓层上形成 P-电极结构， 该 P-电极结构包括依次设置的透 明电极和 P-焊盘；
( 3 ) 在衬底背面打孔， 停留在 n型氮化镓层；
( 4)在衬底背面形成 n-电极结构，该 n-电极结构包括依次设置的透明电极、 反射金属层和接合金属层。
进一步地， 所述步骤 （3 ) 中， 在衬底背面打孔的步骤包括： 1) 使用激光完成对氮化物器件衬底的大部分开孔， 距离开孔的目标深度不 大于 10微米；
2) 采用干蚀刻完成对氮化物器件衬底剩余部分的开孔， 该剩余部分的深度 不大于 10微米。
进一步地， 所述步骤 1) 中， 先在半导体晶圆开孔面的背面， 产生保护层； 还包括步骤 3) ： 去除保护层。
优选地， 所述开孔底部与孔壁的夹角大于 90度。 更优选地， 孔壁与水平面 的夹角从开孔底部逐渐增加直到衬底表面。
进一步地， 所述步骤 1) 中， 先在半导体晶圆开孔面的背面， 产生保护层； 还包括步骤（3) ： 去除保护层。优选地， 所述保护层的厚度为 Ο.ΟΟΙμηι至 5μηι。 更优选地， 所述保护层的厚度为 Ο.ΟΙμηι至 3μηι。 最优选地， 所述保护层的厚度 为 Ο.ΟΙμηι至 1μηι。
进一步地，所述步骤 1)中，激光的光源为脉冲激光。激光的波长优选 200nm 至 11μηι。更优选地，激光的波长为 240nm至 1.6μηι。激光的功率优选不超过 2W。 更优选地， 激光的功率不超过 1W。
进一步地， 所述步骤 1) 中， 在使用激光对氮化物器件衬底进行开孔时， 将 气体吹到激光加工部上进行冷却。
本发明采用的第二种技术方案为一种 n 型半导体出光垂直传导发光二极管 的制造方法， 包括如下步骤：
(1) 提供一衬底， 在该衬底的正面外延成长发光二极管的发光结构， 该发 光结构包括依次形成的氮化镓缓冲层和氮化镓发光二极管磊晶层，其中氮化镓发 光二极管磊晶层包括依次设置的 n型氮化镓层、 发光层和 P型氮化镓层；
(2) 在 p型氮化镓层上形成 P-电极结构， 该 P-电极结构包括依次设置的透 明电极、 反射金属层和接合金属层；
(3) 在衬底背面打孔， 停留在 n型氮化镓层；
(4)在衬底背面形成 n-电极结构， 该 n-电极结构包括依次设置的透明电极 和 n-焊盘。
进一步地， 所述步骤 （3) 中， 在衬底背面打孔的步骤包括：
1) 使用激光完成对氮化物器件衬底的大部分开孔， 距离开孔的目标深度不 大于 10微米；
2) 采用干蚀刻完成对氮化物器件衬底剩余部分的开孔， 该剩余部分的深度 不大于 10微米。
进一步地， 所述步骤 1) 中， 先在半导体晶圆开孔面的背面， 产生保护层； 还包括步骤 3 ) ： 去除保护层。
优选地， 所述开孔底部与孔壁的夹角大于 90度。 更优选地， 孔壁与水平面 的夹角从开孔底部逐渐增加直到衬底表面。
进一步地， 所述步骤 1 ) 中， 先在半导体晶圆开孔面的背面， 产生保护层； 还包括步骤（3 ) ： 去除保护层。优选地， 所述保护层的厚度为 Ο.ΟΟΙ μηι至 5μηι。 更优选地， 所述保护层的厚度为 Ο.ΟΙ μηι至 3μηι。 最优选地， 所述保护层的厚度 为 Ο.ΟΙ μηι至 1 μηι。
进一步地，所述步骤 1 )中，激光的光源为脉冲激光。激光的波长优选 200nm 至 1 1 μηι。更优选地，激光的波长为 240nm至 1.6μηι。激光的功率优选不超过 2W。 更优选地， 激光的功率不超过 1W。
进一步地， 所述步骤 1 ) 中， 在使用激光对氮化物器件衬底进行开孔时， 将 气体吹到激光加工部上进行冷却。
有益效果： 本发明采取蓝宝石衬底打孔， 并有出光与反射面的电极设计， 以 增加垂直传导氮化物 LED的出光量与发光效率。本发明先用激光开大部分的孔， 再用干蚀刻精确蚀刻到预定的位置， 既保证了整体开孔的效率， 又能确保达到精 度的需求， 提高良品率。
附图说明
图 1为 p型半导体出光垂直传导发光二极管的制造方法第一步的示意图，图 中打斜线的部分是氮化镓缓冲层， 下同；
图 2为 p型半导体出光垂直传导发光二极管的制造方法第二步的示意图； 图 3为 p型半导体出光垂直传导发光二极管的制造方法第三步的示意图； 图 4为 p型半导体出光垂直传导发光二极管的结构示意图，图中箭头表示出 光方向， 下同；
图 5为图 4的俯视图；
图 6为图 4的仰视图；
图 7为开孔停住在衬底上的氮化物半导体中， 预定的开孔停止面的示意图； 图 8为开孔停住在衬底上的氮化物半导体中， 激光开孔后的结构示意图； 图 9为开孔停住在衬底上的氮化物半导体中，干蚀刻完成开孔后的结构示意 图；
图 10为开孔停住在衬底上的氮化物半导体中，去除保护层后的结构示意图； 图 1 1为开孔部分的结构示意图；
图 12为 n型半导体出光垂直传导发光二极管的结构示意图；
图 13为图 12的仰视图； 图 14为图 12的俯视图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本发明， 应理解这些实施例仅用于 说明本发明而不用于限制本发明的范围，在阅读了本发明之后， 本领域技术人员 对本发明的各种等价形式的修改均落于本申请所附权利要求所限定的范围。
蓝宝石衬底打孔的垂直传导发光二极管可分为 P型半导体出光与 n型半导体 出光两大类。
实施例 1 : p型半导体出光
p型半导体出光垂直传导发光二极管的制造方法：
( 1 ) 如图 1所示， 提供一蓝宝石 (sapphire)衬底， 在该衬底的正面外延成长 发光二极管的发光结构， 该发光结构包括依次形成的氮化镓缓冲层 (GaN buffer layer)和氮化镓发光二极管磊晶层， 其中氮化镓发光二极管磊晶层包括依次设置 的 n型氮化镓层、多层量子井主动层 (multi— quantum well active layer,MQW active layer, 即发光层)和 p型氮化镓层；
(2) 如图 2所示， 在 p型氮化镓层上形成 P-电极结构， 该 P-电极结构包括 依次设置的透明电极和 P-焊盘 （bonding pad), 可通过 p-焊盘打线连接外部电路。 透明电极的材料可例如为氧化镍和金的合金 (NiO/Au)、 氧化铟锡 (Indium Tin Oxide, ITO)、 氧化鋅 (ΖηΟ)或氧化铝鋅 (Aluminum Zinc Oxide, AlZnO), 用以与 半导体层形成欧姆接触 (ohmic contact); p-焊盘的材料可例如为 Ti和 A1的合金、 Ti和 Au的合金或 Ti、 A1和 Au的合金。出光面的透明电极及 P-焊盘各需要使用 一微影蚀亥 ^photolithography) 制程来分别定义出光面的透明电极区域及 p-焊盘。 制作出光面的透明电极时， 首先于晶圆的表面进行透明电极蒸镀、 溅镀或电镀， 接着涂布感光材料 (光胶)， 并于晶圆上方放置光罩， 该光罩上设有相对于出光面 的透明电极区域之图形及数量的图案， 再进行曝光 (Exposure)步骤， 使平行光经 过光罩对感光材料进行选择性的感光， 于是光罩上的图案便完整的转移至晶圆 上， 当曝光后再利用显影 (Development),可使光阻获得与光罩图案相同或互补之 图形。 再进行透明电极蚀刻， 蚀刻完成后， 移除残留的光胶。 制作 P-焊盘时， 首 先于晶圆的表面， 接着涂布感光材料 (光胶)， 并于晶圆上方放置光罩， 该光罩上 设有相对于 P-焊盘区域之图形及数量的图案， 再进行曝光 (Exposure)步骤， 使平 行光经过光罩对感光材料进行选择性的感光，于是光罩上的图案便完整的转移至 晶圆上， 当曝光后再利用显影 (Development),可使光阻获得与光罩图案相同或互 补之图形。 再进行金属蒸镀、溅镀或电镀， 之后， 再使用习知的托举 (Liftoff)工艺 移除不要的金属。 (3 )如图 3所示， 在衬底背面打孔， 停留在 n型氮化镓层； 具体制程如下：
1 ) 如图 7所示， 开孔的另一面保护住。
在半导体晶圆加工面的背面，以旋涂机将水溶性之抗蚀剂均匀地涂布在表面 全体上， 并予以干燥而形成厚度为 2 μ πι之保护膜。
激光加工机照射时， 其污物的飞散激烈， 而在加工时附着到半导体晶圆的表 面及背面。 污物以电子显微镜（FE— SEM)作 EDX (Energy Dispersive X-ray, X 射线能谱定量分析）分析之结果， 是为具有化合物半导体及衬底的成分之 Al、 0、 C, Cl、 Si等之至少一个元素的成分。 因此在激光加工前将加工面的背面以保护 层覆盖。
保护层方面， 可无任何限制而使用抗蚀剂、 透明树脂、 玻璃、 金属或绝缘膜 等。例如， 抗蚀剂方面可为光蚀刻术中所使用的水溶性之抗蚀剂等。透明树脂方 面， 可为亚克力树脂、 聚酯、 聚亚酰胺、 氯乙烯及硅树脂等。 金属方面， 可为镍 及钛等。 绝缘膜方面， 可为氧化硅或氮化硅等。 该等之保护层可藉由涂布法、 蒸 镀法及溅镀法等周知之方法而形成。
保护层的厚度， 其下限为 0. 001 μ πι以上较佳， 更佳为 0. 01 μ πι以上。 厚度的 上限是以 5 μ πι以下较佳， 更佳为 3 μ πι以下， 尤其更佳为 Ι μ πι以下。
2) 如图 8所示， 使用激光， 完成大部份开孔， 距离目标深度不大于 10微米。 将 UV (紫外光）胶带黏贴在半导体晶圆的蓝宝石衬底侧之后， 使用真空夹头 将半导体晶圆固定在脉冲激光加工机之平台上。 平台可朝向 X轴（左右)及 Υ轴（前 后）方向移动， 且为可转动的构造。 固定之后， 使激光的焦点对加工面的方式而 调整光学系。 典型脉冲激光蚀刻衬底时，每个脉冲的功率，脉冲长度，光点大小保 持一定。 以脉冲激光扫描欲开孔区域时，某区域的蚀刻深度和该区域的总脉冲数 目成正比。 因此控制脉冲激光的脉冲数目、激光与衬底的相对位置、光点的重合 程度， 可以产生所要的开孔形状。 因为衬底开孔后，后续工序常是在衬底的挖孔 面蒸镀、溅镀或电镀金属层，希望开孔中的金属和孔外的金属是相连的，而形成一 整片电极区域，所以，希望开孔底部与蚀刻壁 （即孔壁） 的角度 Θ大于 90度，而且 希望蚀刻壁与水平面的夹角 Θ ' 从开孔底部逐渐增加直到衬底表面，如此，避免 孔中的金属和孔外的金属不相连的情况， 如图 11所示。必须完成大部分开孔（即 开孔底部距离目标深度不大于 10微米）， 否则完成全部开孔后， 残留衬底不足以 做为支撑。 加工完成后， 将真空夹头释放， 并将晶圆从平台取下。
激光光源之种类， 并无特别限定， 具体上， 可使用 C02激光、 YAG激光、 准 分子激光及脉冲激光等。其中以脉冲激光较佳。例如可举出 Nd : YAG激光、 Nd : YV04 激光、 Yb : YAG激光或 Ti : 蓝宝石激光等固体激光； 光纤激光及其谐波； 准分子激 光或 co2 激光等气体激光。 其中， 较佳为采用热影响少之短脉冲激光或具有被硬 脆性材料强力吸收之紫外区之振荡波长的激光。激光的波长可使用 355nm、 266nm 等， 亦可使用更短的波长，较佳为调整在 200nm以上 Ι ΐ μ πι以下， 特别是调整在 240nm以上 1600nm以下更佳。 过剩的激光输出会对化合物半导体构成损伤， 因此 激光的功率以 2W以下较佳， 1W以下更佳。
一般可用固态激光. 例如 Q切换的 Nd : YV04激光或 Nd : YAG激光，其中包含谐波 频率产生器， 诸如 LB0 (三硼酸锂） 的非线性结晶， 使得在以掺杂钕的固态激光 所产生之 1064纳米线的第二、 第三、 第四或第五谐波频率之一提供激光的输出。 在特殊系统中， 提供约 355纳米的第三谐波频率。 脉波具有在每平方厘米约 10与 100焦尔之间的能量密度、 在约 10与 30毫微秒之间的脉波持续时间及在约 5与 25 微米之间的光点尺寸。 脉波的重复率大于 5千赫， 较佳为在自约 10千赫与 50千赫 或更高的范围内。蓝宝石衬底以一运动速率移动， 造成脉波以 50至 99百分比的数 量重迭。
激光脉冲振荡之振荡形态， 并无特别限定， 例如可举出脉冲宽度为 0. lps〜 20ns左右之脉冲振荡、 Q开关脉冲振荡等。 又， 于该 Q开关脉冲振荡， 亦可采用高 速反复用之 A/0组件或短脉冲振荡用之 E/0组件。此外， 即使连续波振荡， 藉由使 用 A/0-Q开关等， 亦可得到约数十 KHz反复之脉冲状振荡输出。
激光加工机照射时，将气体吹附到激光加工部上， 使化合物半导体层之加工 部周边冷却， 可降低化合物半导体层之热损伤。又， 在加工产生的熔解物不会附 着于加工面上。 吹附到激光加工部的气体方面， 可无任何限制使用氧气、 氮气、 氦气、 氢气等。 尤其虽然可使用冷却效果高的氦气、 氢气、 氮气等， 但是仍以价 廉氮气为较佳。气体的吹附， 以前端之喷嘴径为细之程度者较佳。 喷嘴径越细之 时， 可局部地进行吹附， 且可使气流的流速变快。
3)如图 9所示， 改用干蚀刻。此时， 采用无屏蔽蚀刻， 即干蚀刻的蚀刻深度 不大于 10微米， 衬底同时减薄相同厚度。
干蚀刻（Dry Etching)又称电浆蚀刻（Plasma Etching) , 系利用气体为主要 的蚀刻媒介， 例如 C12/BC13， 并藉由电浆能量来驱动反应， 蚀刻该蓝宝石衬底后， 停住于衬底上氮化物半导体中。
4) 如图 10所示， 去保护层。
加工后，与附着于表面之污物一起将保护层除去。除去的方法并未特别限定， 任何方法均可。 只要可将保护层完全除去的话， 可无任何限制使用超声波、 喷射 水流、 冲洗、 浸泡、 蚀刻、 擦洗干净等方法。
将半导体晶圆设置于洗净机的平台上，将半导体晶圆连续地转动， 在半导体 层侧上藉由冲洗水之流动， 将形成的保护层除去。最后， 在高转数下转动以将冲 洗水吹散并干燥。
水溶性的抗蚀剂，使用旋涂机可在晶圆之表面全体上形成均匀的膜厚之保护 层， 加工后， 可简单地以水洗净除去为较佳。 或者， 在保护层上使用光阻剂之情 形， 在割沟形成后浸泡于磷酸、 硫酸、 盐酸等， 将加工部之污物以湿式蚀刻选择 地除去， 其后使用丙酮等有机溶剂将晶圆表面之光阻剂完全地除去为较佳。
( 4)如图 4所示， 在衬底背面形成 n-电极结构， 该 n-电极结构包括依次镀 上的透明电极、 反射金属层和接合金属层， 可通过接合金属层连接外部电路。 反 射金属层的材料可例如为镍 (Ni)、 钯 (Pd)、 铬 (Cr)、 铂 Pt、 铝 (A1)或银 (Ag)， 用以 反射氮化镓发光二极管磊晶层发出的光及作为扩散阻碍层；接合金属层的材料可 例如为铝 (Al)、 金 (Au)或金合金 (Au alloy：)。 图 5是图 4的俯视图， 示出了 p型半 导体出光垂直传导发光二极管的出光面 （正面， P-电极侧）。 图 6是图 4的仰视 图， 示出了 p型半导体出光垂直传导发光二极管的反面（n-电极侧）， 只见开孔， 虚线是正面透明电极的图案。
实施例 2: n型半导体出光
如图 12所示， 本实施例与实施例 1的区别在于： 本实施例中 P-电极的结构 恰为实施例 1中 n-电极的结构， 本实施例中 n-电极的结构恰为实施例 1中 P-电 极的结构， 本实施例中的焊盘不是 P-焊盘， 而是 n-焊盘。 图 13是图 12的仰视 图， 示出了 n型半导体出光垂直传导发光二极管的出光面 （反面， n-电极侧）。 图 14是图 12的俯视图， 示出了 n型半导体出光垂直传导发光二极管的正面（P- 电极侧）， 虚线是反面的 n-焊盘和蓝宝石孔的图案。

Claims

权 利 要 求 书
1、 一种 p型半导体出光垂直传导发光二极管的制造方法， 包括如下步骤：
( 1 ) 提供一衬底， 在该衬底的正面外延成长发光二极管的发光结构， 该发 光结构包括依次形成的氮化镓缓冲层和氮化镓发光二极管磊晶层，其中氮化镓发 光二极管磊晶层包括依次设置的 n型氮化镓层、 发光层和 p型氮化镓层；
(2) 在 p型氮化镓层上形成 P-电极结构， 该 P-电极结构包括依次设置的透 明电极和 P-焊盘；
(3) 在衬底背面打孔， 停留在 n型氮化镓层；
( 4)在衬底背面形成 n-电极结构，该 n-电极结构包括依次设置的透明电极、 反射金属层和接合金属层。
2、 根据权利要求 1所述 p型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 所述步骤 （3) 中， 在衬底背面打孔的步骤包括：
1 ) 使用激光完成对氮化物器件衬底的大部分开孔， 距离开孔的目标深度不 大于 10微米；
2) 采用干蚀刻完成对氮化物器件衬底剩余部分的开孔， 该剩余部分的深度 不大于 10微米。
3、 根据权利要求 2所述 p型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 所述步骤 1 ) 中， 先在半导体晶圆开孔面的背面， 产生保护层； 还 包括步骤 3) ： 去除保护层。
4、 根据权利要求 2所述 p型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 所述开孔底部与孔壁的夹角大于 90度。
5、 根据权利要求 4所述 p型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 孔壁与水平面的夹角从开孔底部逐渐增加直到衬底表面。
6、 一种 n型半导体出光垂直传导发光二极管的制造方法， 包括如下步骤：
( 1 ) 提供一衬底， 在该衬底的正面外延成长发光二极管的发光结构， 该发 光结构包括依次形成的氮化镓缓冲层和氮化镓发光二极管磊晶层，其中氮化镓发 光二极管磊晶层包括依次设置的 n型氮化镓层、 发光层和 P型氮化镓层；
(2) 在 p型氮化镓层上形成 P-电极结构， 该 P-电极结构包括依次设置的透 明电极、 反射金属层和接合金属层；
(3) 在衬底背面打孔， 停留在 n型氮化镓层；
( 4)在衬底背面形成 n-电极结构， 该 n-电极结构包括依次设置的透明电极 和 n-焊盘。
7、 根据权利要求 6所述 n型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 所述步骤 （3) 中， 在衬底背面打孔的步骤包括： 1 ) 使用激光完成对氮化物器件衬底的大部分开孔， 距离开孔的目标深度不 大于 10微米；
2 ) 采用干蚀刻完成对氮化物器件衬底剩余部分的开孔， 该剩余部分的深度 不大于 10微米。
8、 根据权利要求 7所述 n型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 所述步骤 1 ) 中， 先在半导体晶圆开孔面的背面， 产生保护层； 还 包括步骤 3 ) ： 去除保护层。
9、 根据权利要求 7所述 n型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 所述开孔底部与孔壁的夹角大于 90度。
10、 根据权利要求 9所述 n型半导体出光垂直传导发光二极管的制造方法， 其特征在于： 孔壁与水平面的夹角从开孔底部逐渐增加直到衬底表面。
PCT/CN2012/086085 2012-07-16 2012-12-06 P型、n型半导体出光垂直传导发光二极管的制造方法 WO2014012321A1 (zh)

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