WO2014008767A1 - 具有阶梯式多重不连续场板的ldmos器件及制造方法 - Google Patents

具有阶梯式多重不连续场板的ldmos器件及制造方法 Download PDF

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WO2014008767A1
WO2014008767A1 PCT/CN2013/072795 CN2013072795W WO2014008767A1 WO 2014008767 A1 WO2014008767 A1 WO 2014008767A1 CN 2013072795 W CN2013072795 W CN 2013072795W WO 2014008767 A1 WO2014008767 A1 WO 2014008767A1
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field
field plates
field plate
gate
ldmos device
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PCT/CN2013/072795
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English (en)
French (fr)
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马强
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苏州远创达科技有限公司
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Publication of WO2014008767A1 publication Critical patent/WO2014008767A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole

Definitions

  • LDMOS device with stepped multiple discontinuous field plate and manufacturing method The present application claims to be filed on July 10, 2012 with the Chinese Patent Office, application number 201210237362.3, and the invention name is "LDMOS device with stepped multiple discontinuous field plate and The priority of the Chinese Patent Application, the entire disclosure of which is incorporated herein by reference.
  • Technical field is "LDMOS device with stepped multiple discontinuous field plate and The priority of the Chinese Patent Application, the entire disclosure of which is incorporated herein by reference.
  • the present invention relates to an LDMOS device having a stepped multiple discontinuous field plate and a corresponding processing method thereof.
  • a power LDMOS device In a power LDMOS device, it is required to reduce the source-drain on-resistance Rds of the device as low as possible while satisfying the source-drain breakdown voltage BVdss.
  • the prior art reduces the power consumption of the device to improve the operating efficiency of the device.
  • the optimization requirements for source-drain breakdown voltage and on-resistance are contradictory.
  • field plate technology In RF LDMOS power devices, field plate technology is often used to alleviate this contradiction.
  • the commonly used single field plate technology has greater limitations because the distance between the horizontal portion of the field plate and the semiconductor surface is constant, as shown in Figure 1, but the ideal field plate requires that the distance between the field plate and the device surface should not be Single. Summary of the invention
  • the object of the present invention is to provide an LDMOS device having a stepped multiple discontinuous field plate and a manufacturing method thereof, which can better alleviate the contradiction between the source-drain breakdown voltage and the optimization requirement of the on-resistance, and improve the LDMOS device. performance.
  • An LDMOS device having a stepped multiple discontinuous field plate, comprising a semiconductor body, the semiconductor body comprising a lowermost semiconductor substrate region, and a semiconductor a semiconductor epitaxial layer and a topmost semiconductor dielectric layer on the bottom region, a channel region and a drain drift region are formed between the semiconductor epitaxial layer and the semiconductor dielectric layer, and a gate and a gate extending along the channel region are disposed in the semiconductor dielectric layer.
  • At least two field plates sequentially disposed in a horizontal direction of the drain drift region, and a first field plate adjacent to the gate There is a horizontal extension on the leakage drift region, and the remaining field plates not adjacent to the grid are horizontal strips, and there is no coverage between the field plates, and the distance between the second field plate adjacent to the first field plate and the leakage drift interval The distance between the horizontal extension portion of the first field plate and the leakage drift interval is larger than that of the remaining horizontal strip field plate and the leakage drift interval.
  • an oxide layer is deposited on the surface of the semiconductor body above the gate, and an oxide layer is deposited on the surface of the previous oxide layer above the field plate.
  • the vertical spacing between the field plates is equal to the thickness of the oxide layer, and the thickness of the oxide layer is greater than or equal to The thickness of the field plate.
  • the horizontal distance between the at least two field plates is greater than zero.
  • the at least two field plates are both located above the drain drift region of the semiconductor body.
  • the first field plate adjacent the gate extends over at least a portion of the gate.
  • the at least two field plates may be connected to a positive or negative voltage or ground for adjusting the electric field charge, more specifically for adjusting the electric field charge of the drain drift region.
  • the front end of the field plate which is not adjacent to the grid in at least two of the field plates has an L-shaped protrusion, but the horizontal distance between the field plates is still greater than zero.
  • the present invention also provides a processing method for fabricating the above LDMOS device having a stepped multiple discontinuous field plate, characterized in that the processing method comprises the steps of: processing a semiconductor body, including formation of a gate;
  • step 3 repeats 3) according to the number of field plates you need to make. If only two field plates need to be processed, it is not necessary to repeat the operation of step 3). If the number of field plates to be processed is greater than or equal to three, continue to repeat step 3) to achieve the required number of processing fields.
  • the vertical spacing between the field plates is equal to the thickness of the oxide layer, and the thickness of the oxide layer is greater than the thickness of the field plate.
  • the conductive medium of the conductive layer plate is titanium or tungsten.
  • the advantages of the present invention over the prior art solutions are:
  • the LDMOS device with stepped multiple discontinuous field plate described in the present invention has a single field plate with the same on-resistance under the same structural parameters of all other devices.
  • the multi-field LDMOS device has a higher source-drain breakdown voltage than a single-field plate breakdown voltage (eg, grounded under equivalent device structure conditions)
  • the single-field LDMOS device has a source-drain breakdown voltage of 61V, while the multi-field LDMOS device has a source-drain breakdown voltage of 73V.
  • the LDMOS device with multiple field plates can increase the doping concentration of the N-type drift region, and the on-resistance of the device can be significantly improved.
  • FIG. 1 is a schematic structural view of a conventional single field plate LDMOS device
  • FIG. 2 is a schematic structural view of a specific embodiment of the present invention.
  • FIG. 3 is another schematic structural view of a specific embodiment of the present invention.
  • FIG. 4 is still another schematic structural diagram of a specific embodiment of the present invention.
  • FIG. 11 are schematic views showing the formation of a laminate for a method of processing an LDMOS device according to an embodiment of the present invention.
  • Figure 12 is a diagram showing the electric field distribution in the drain drift region 11 of three types of LDMOS devices according to an embodiment of the present invention. Among them: 1. Semiconductor body; 11. Leakage drift region; 12. P-type heavily doped village bottom region; 13. P-type epitaxial layer; 14. P-type doped connection or trench filled with conductive material; Type heavily doped source region; 16, P-type doped channel region; 17, N-type heavily doped source region; 18, N-type heavily doped drain region; 19, gate; 110, leakage ohmic contact region; Source ohmic contact region; 21, first field plate; 22, second field plate; 23, third field plate; 210, conductive layer plate; 220, conductive layer plate; 3. semiconductor dielectric layer; 31, oxide layer; , oxide layer; 33, oxide layer.
  • the structure of the LDMOS device having the stepped multiple discontinuous field plate described in this embodiment is as shown in FIG. 2, and includes a semiconductor body 1 including a lowermost P-type heavily doped substrate 12, which is disposed at P The P-type epitaxial layer 13 on the heavily doped substrate 12 and the uppermost semiconductor dielectric layer 3, the P-type heavily doped source region 15 and the P-type doping are formed between the P-type epitaxial layer 13 and the semiconductor dielectric layer 3. a channel region 16, an N-type doped drain drift region 11 and an N-type heavily doped drain region 18, wherein the P-type heavily doped source region 15 and the P-type doped channel region 16 are connected to each other to form an N-type heavy Doped source region 17.
  • a P-type doped connection or a trench 14 filled with a conductive material is disposed between the P-type heavily doped source region 15 and the P-type heavily doped substrate, and the P-type doping or conductive material in the trench 14 is The P-shaped heavily doped village is in contact with each other.
  • the source ohmic contact region 111 is disposed on the upper surface of the P-type heavily doped source region and the N-type heavily doped impurity source region 17, and the drain ohmic contact region 110 is disposed on the upper surface of the N-type heavily doped drain region 18.
  • the semiconductor dielectric layer 3 is provided with a gate 19 extending along the P-type doped channel region 16 and three field plates sequentially disposed from the gate 19 toward the drain drift region 11 in the horizontal direction, which are sequentially named as the first field plate 21,
  • the second field plate 22, the third field plate 23, and the three field plates are all located above the drain drift region 11 of the semiconductor body, and the first field plate 21 adjacent to the gate 19 has a horizontal extension on the drain drift region 11,
  • a first field plate 21 adjacent to the grid 19 extends over at least a portion of the grid 19.
  • the remaining field plates (the second field plate 22 and the third field plate 23) not adjacent to the grid 19 are horizontal strips, and the first field plate 21 and the second field plate 22, the second field plate 22 and the third field
  • the horizontal distance between the plates 23 is greater than zero, and the distance B between the second field plate 22 and the drain drift region 11 is greater than the distance A between the horizontal extension portion of the first field plate 21 and the drain drift region 11, and the third field plate 23 is The distance C between the drain drift regions 11 is greater than the distance B between the second field plate 22 and the drain drift region 11.
  • an oxide layer 31 is deposited on the surface of the semiconductor body over the gate 19, and an oxide layer 32 is deposited on the surface of the front oxide layer 31 over the first field plate 21, and is oxidized on the surface of the second field plate 22
  • the surface of layer 32 is also deposited with an oxide layer 33, which is disposed along the edge of the oxide layer, as shown in FIG. 2, and the vertical spacing between the field plates is equal to the thickness of the oxide layer, and the thickness of the oxide layer is greater than or equal to the field plate.
  • the thickness of the field plates is equal to the thickness of the conductive layer.
  • the thickness of the conductive layer is equal to the thickness of the field plate. This reduces the parasitic capacitance (Cds) generated by the field plate.
  • the first field plate 21, the second field plate 22, and the third field plate 23 may be connected to a positive or negative voltage, or may be grounded.
  • the field plate is generally only grounded, and the connection method of the field plate in the present invention is more flexible.
  • the edge of the field plate is not necessarily in the lithographic corrosion, which may cause an inverted L-shaped step along the oxide layer of the field plate.
  • the projections, or the field plates have vertical projections at their edges which form an L-shape with the horizontal field plate.
  • the field plates (the second field plate 22 and the third field plate 23) which are not adjacent to the gate 19 are positioned to the left when the lithography is etched, that is, the lithographic corrosion position is closer to the gate, resulting in two fields.
  • the front end has an inverted L-shaped projection, but the horizontal distance between the first field plate 21 and the second field plate 22, the second field plate 22 and the third field plate 23 is still greater than zero.
  • the front ends of the field plates (the second field plate 22, the third field plate 23) not adjacent to the grid 19 have vertical protrusions, but the first field plate 21 and the second field plate 22, the second The horizontal distance between the field plate 22 and the third field plate 23 is still greater than zero.
  • the invention is particularly suitable for use in LDMOS devices with source-drain breakdown voltages greater than 40-50V, which alleviates the contradiction between source-drain breakdown voltage and on-resistance optimization requirements, and improves the performance of LDMOS devices.
  • the present embodiment only uses three field plates as an example for description. However, in practical applications, the number of field plates can be adjusted according to the application environment. Generally, as long as the number of field plates is greater than 2, and The arrangement is such that the horizontal direction extends to the drift, the horizontal direction has a pitch, and the distance from the drift region has a height difference, which is the gist of the invention.
  • the embodiment further describes a processing method for fabricating the LDMOS device having the stepped multiple discontinuous field plate in the above embodiment.
  • the processing method in the embodiment includes the following steps: processing the semiconductor body, including forming the gate;
  • An oxide layer 31 (shown in FIG. 5) is deposited on the surface of the semiconductor body over the gate, and a conductive layer 210 (shown in FIG. 6) is deposited on the oxide layer 31.
  • Photolithography and etching processes form a first field plate 21 (shown in Figure 7);
  • an oxide layer 32 (shown in FIG. 8) is deposited in turn, and a conductive layer 220 (shown in FIG. 9) is deposited on the oxide layer 32.
  • the conductive layer 220 is then subjected to photolithography and etching processes.
  • Forming a second field plate 22 (shown in FIG. 10)
  • the vertical spacing between the second field plate and the first field plate field is equal to the thickness of the conductive layer 220
  • the thickness of the conductive layer 220 is equal to the thickness of the field plate
  • the number of field plates produced in the present invention is three, and step 3 is repeated, and the oxide layer 33 and the guide are sequentially deposited.
  • the electrical layer board, the conductive layer board is further formed into a third field plate 23 via photolithography and etching process, and finally a desired LDMOS device having a triple field plate is obtained (see FIG. 11).
  • Figure 12 shows the electric field distribution in the drain drift region 11 of the three types of LDMOS devices, which are shown in the P-type doped channel region 16 and the drain drift region 11 measured at a constant gate voltage and a maximum supply voltage.
  • the surface of the P-type epitaxial layer 13 serves as a transverse electric field E as a function of the distance X from the N-type heavily doped source region.
  • curve 1 represents the electric field distribution of only one field plate LDMOS device
  • the transverse electric field E of the single field plate LDMOS device shows the first peak A" and the second peak B", and the first peak A" of the transverse electric field E is located in the drain The edge position of the drift region, and the second peak B" of the transverse electric field E is located at the edge of the horizontal portion of the single field plate
  • curve 2 represents the electric field distribution of the LDMOS device with two field plates and overlapping between the field plates, with two fields
  • the transverse electric field E of the LDMOS device with overlap between the plates and the field plates shows the first peak A, the second peak B, and the third peak C, the first peak A of the transverse electric field E, located at the edge of the drain drift region.
  • the second peak B of the transverse electric field E, the third peak C respectively located at the edge of the horizontal portion of the first field plate and the horizontal portion of the second field plate;
  • the curve 3 indicates that there are two field plates and there is no overlap between the field plates and
  • the electric field distribution of LDMOS devices having a certain distance from each other in the horizontal direction, the transverse electric field E of the LDMOS device having two field plates and no overlap between the field plates shows the first peak A, the second peak B, and the third peak C , the first of the transverse electric field E
  • the peak A is located at the edge position of the drain drift region, and the second peak B and the third peak C of the transverse electric field E are respectively located at the horizontal portion of the first field plate and the edge of the second field plate.
  • the second peak B' of the transverse electric field of the LDMOS device with two field plates and overlapping between the field plates is lower than the second peak B" of the transverse electric field of the single field plate LDMOS device.
  • the second peak B of the transverse electric field of the LDMOS device with two field plates and no overlap between the field plates is the second peak B of the transverse electric field of the LDMOS device with two field plates and overlapping between the field plates.
  • the value of is lower, and the third peak C of the transverse electric field of the LDMOS device with two field plates and no overlap between the field plates is also the same as the transverse electric field of the LDMOS device with two field plates and overlapping between the field plates.
  • the value of the triple peak C is lower, which is a beneficial effect one.
  • the electric field of the LDMOS device having two field plates and having no overlap between the field plates and the electric field phase of the LDMOS device having two field plates and overlapping between the field plates In comparison, the electric field change is smaller and the change is more gradual, which is beneficial effect 2; in addition, the transverse electric field distribution along the leakage drift region is more gradual.
  • the lateral breakdown voltage of the LDMOS device the above three beneficial effects are not changed. Leakage drift region doping In the case of concentration, the lateral breakdown voltage of the LDMOS device is effectively increased, and thus, the improvement of the source-drain breakdown voltage and the optimization of the on-resistance can be realized.

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Abstract

一种具有阶梯式多重不连续场板的LDMOS器件及制造方法，该LDMOS器件包括半导体本体，半导体本体包括从下至上依次设置的半导体村底区、半导体外延层以及半导体介质层，在半导体介质层内设有沿沟道区延伸的栅以及从栅朝向漏漂移区的水平方向上依次设置的至少两个场板，与栅相邻的第一场板在漏漂移区上具有水平延伸，其余与栅不相邻的场板均为水平条状，场板之间距离大于零，与第一场板相邻的第二场板与漏漂移区间的距离大于第一场板水平延伸部分与漏漂移区间的距离，其余水平条状场板与漏漂移区间的距离逐次递增。本发明缓解了源漏击穿电压与导通电阻的优化要求之间的矛盾，改善LDMOS器件的性能。

Description

具有阶梯式多重不连续场板的 LDMOS器件及制造方法 本申请要求于 2012 年 7 月 10 日提交中国专利局、 申请号为 201210237362.3、发明名称为"具有阶梯式多重不连续场板的 LDMOS器件 及制造方法"的中国专利申请的优先权，其全部内容通过引用结合在本申请 中。 技术领域
本发明涉及一种具有阶梯式多重不连续场板的 LDMOS器件及其对应 加工方法。
背景技术
在功率 LDMOS器件中， 要求在满足源漏击穿电压 BVdss的前提下， 尽可能低降低器件的源漏导通电阻 Rds, 现有技术以降低器件的功率消耗 来提高器件的工作效率。 但是源漏击穿电压和导通电阻的优化要求却是相 互矛盾的，在射频 LDMOS功率器件中， 常采用场板技术来緩和这一矛盾。 但是常用的单一场板技术有着较大的局限性， 因为场板的水平部分与半导 体表面间的距离恒定， 如图 1所示， 但是理想的场板要求场板与器件表面 的距离不应是单一的。 发明内容
本发明目的在于提供一种具有阶梯式多重不连续场板的 LDMOS器件 及制造方法， 其 4艮好地緩解了源漏击穿电压与导通电阻的优化要求之间的 矛盾， 改善 LDMOS器件的性能。
为了解决现有技术中的这些问题， 本发明提供的技术方案是： 一种具有阶梯式多重不连续场板的 LDMOS器件， 包括半导体本体， 半导体本体包括最下层的半导体村底区、 设于半导体村底区上的半导体外 延层以及最上层的半导体介质层， 半导体外延层与半导体介质层之间形成 有沟道区、 漏漂移区， 半导体介质层内设有沿沟道区延伸的栅以及从栅朝 向漏漂移区的水平方向上依次设置的至少两个场板， 与栅相邻的第一场板 在漏漂移区上具有水平延伸， 其余与栅不相邻的场板均为水平条状， 场板 之间均无覆盖， 与第一场板相邻的第二场板与漏漂移区间的距离大于第一 场板水平延伸部分与漏漂移区间的距离， 其余水平条状场板与漏漂移区间 的 巨离逐次递增。
对于上述技术方案， 发明人具有进一步的优化措施。
进一步， 在位于栅的上方于半导体本体表面沉积有氧化层， 在场板上 方于前一氧化层表面同样沉积有氧化层， 场板间的竖直间距等于氧化层的 厚度， 氧化层的厚度大于等于场板的厚度。
进一步， 所述至少两个场板之间的水平距离大于零。
进一步， 所述至少两个场板均位于半导体本体的漏漂移区的上方。 作为优化， 与栅相邻的第一场板在栅的至少一部分上延伸。
作为优化， 所述至少两个场板均可接正负电压或接地用于调节电场电 荷， 更确切地说是用于调节漏漂移区的电场电荷。
更进一步， 至少两个场板中的与栅不相邻的场板的前端具有 L形的突 起， 但场板间的水平距离仍大于零。
本发明还提供了一种用于制作上述具有阶梯式多重不连续场板的 LDMOS器件的加工方法， 其特征在于， 所述加工方法包括如下步骤： 加工半导体本体， 包括栅的形成；
在位于栅的上方于半导体本体表面沉积一个氧化层， 再于氧化层上沉 积一个导电层板， 所述导电层板再经由光刻与腐蚀工艺形成第一场板； 紧接着再依次沉积一个氧化层和导电层板， 所述导电层板经由光刻与 腐蚀工艺形成第二场板；
根据需要制作的场板的个数重复步骤 3 )。 如果只需要加工两个场板， 则无需重复步骤 3 ) 的操作， 如需加工的场板数大于等于三个， 则继续重 复步骤 3 ) 的操作达到所需加工场板数即可。
进一步， 场板间的竖直间距等于氧化层的厚度， 氧化层的厚度大于等 于场板的厚度。
进一步， 所述导电层板的导电介质为钛或者钨。
相对于现有技术中的方案， 本发明的优点是： 本发明所描述的具有阶梯式多重不连续场板的 LDMOS器件， 在所有 其他器件结构参数相同的条件下， 对于具有相同导通电阻的单重场板
LDMOS器件和本发明的具有阶梯式多重不连续场板的 LDMOS器件， 多 重场板 LDMOS器件的源漏击穿电压要高于单重场板击穿电压 （如在同等 器件结构条件下， 具有接地的单重场板 LDMOS 器件的源漏击穿电压为 61V, 而多重场板 LDMOS器件的源漏击穿电压为 73V )。 在相同的源漏击 穿电压要求下，运用多重场板的 LDMOS器件可以增加 N型漂移区的掺杂 浓度， 器件的导通电阻因而可以得到显著的改善。
附图说明
图 1为现有单重场板 LDMOS器件的结构示意图；
图 2为本发明具体实施例的结构示意图；
图 3为本发明具体实施例的另一结构示意图；
图 4为本发明具体实施例的又一结构示意图
图 5至图 11为本发明实施例中 LDMOS器件的加工方法的层板形成示 意图；
图 12为本发明实施例三类 LDMOS器件的漏漂移区 11中的电场分布。 其中： 1、 半导体本体； 11、 漏漂移区； 12、 P型重掺杂村底区； 13、 P型外延层； 14、 P型掺杂连接或用导电物填充的沟槽； 15、 P型重掺杂源 区； 16、 P型掺杂沟道区； 17、 N型重掺杂源区； 18、 N型重掺杂漏区； 19、 栅； 110、 漏欧姆接触区； 111、 源欧姆接触区； 21、 第一场板； 22、 第二场板； 23、 第三场板； 210、 导电层板； 220、 导电层板； 3、 半导体介 质层； 31、 氧化层； 32、 氧化层； 33、 氧化层。
具体实施方式
以下结合具体实施例对上述方案做进一步说明。 应理解， 这些实施例 是用于说明本发明而不限于限制本发明的范围。 实施例中采用的实施条件 可以根据具体厂家的条件做进一步调整， 未注明的实施条件通常为常规实 验中的条件。 实施例：
本实施例所描述的具有阶梯式多重不连续场板的 LDMOS器件的结构 如图 2所示， 其包括半导体本体 1 , 半导体本体 1包括最下层的 P型重掺 杂村底 12、设于 P型重掺杂村底 12上的 P型外延层 13以及最上层的半导 体介质层 3, P型外延层 13与半导体介质层 3之间形成有 P型重掺杂源区 15、 P型掺杂沟道区 16、 N型掺杂漏漂移区 11和 N型重掺杂漏区 18, 其 中 P型重掺杂源区 15和 P型掺杂沟道区 16相连的位置上形成有 N型重掺 杂源区 17。 P型重掺杂源区 15和 P型重掺杂村底之间设置有 P型掺杂连 接或用导电物填充的沟槽 14, 这一沟槽 14内的 P型掺杂或者导电物与 P 形重掺杂村底相接触。 源欧姆接触区 111设于 P型重掺杂源区和 N型重掺 杂源区 17的上表面， 漏欧姆接触区 110设于 N型重掺杂漏区 18上表面。
半导体介质层 3内设有沿 P型掺杂沟道区 16延伸的栅 19以及从栅 19 朝向漏漂移区 11的水平方向上依次设置的三个场板，依次命名为第一场板 21、 第二场板 22、 第三场板 23, 三个场板均位于半导体本体的漏漂移区 11的上方， 与栅 19相邻的第一场板 21在漏漂移区 11上具有水平延伸， 与栅 19相邻的第一场板 21在栅 19的至少一部分上延伸。 其余与栅 19不 相邻的场板（第二场板 22、 第三场板 23 ) 均为水平条状， 第一场板 21与 第二场板 22、 第二场板 22与第三场板 23之间的水平距离均大于零， 第二 场板 22与漏漂移区 11间的距离 B大于第一场板 21水平延伸部分与漏漂 移区 11间的距离 A,第三场板 23与漏漂移区 11间的距离 C大于第二场板 22与漏漂移区 11间的距离 B。
另外， 在位于栅 19的上方于半导体本体表面沉积有氧化层 31 , 在第 一场板 21上方于前一氧化层 31表面同样沉积有氧化层 32,在第二场板 22 上方于前一氧化层 32表面同样沉积有氧化层 33, 所述三场板均沿氧化层 边缘设置， 如图 2所示， 并且场板间的竖直间距等于氧化层的厚度， 氧化 层的厚度大于等于场板的厚度， 场板间的竖直间距等于导电层板的厚度， 导电层板的厚度等于场板的厚度， 如此可降低场板所产生的寄生电容 ( Cds )。
第一场板 21、 第二场板 22、 第三场板 23可接正负电压， 也可以接地。 而在普通的具有单个场板的 LDMOS器件中， 场板一般只接地， 而本发明 中场板的连接方法更为灵活。
另外，由于场板下所设的氧化层还有光刻腐蚀存在一定的工作精度差， 场板边缘在光刻腐蚀时位置不一定， 会造成场板沿氧化层可能出现一段倒 L形的阶梯状突起， 或者场板在其边缘有竖直突起， 该突起与水平场板构 成 L形。 如图 3所示， 与栅 19不相邻的场板 (第二场板 22、 第三场板 23 ) 在光刻腐蚀时位置偏左即光刻腐蚀位置离栅较近， 造成两场板的前端具有 倒 L形的突起， 但第一场板 21与第二场板 22、 第二场板 22与第三场板 23之间的水平距离仍大于零。 如图 4所述， 与栅 19不相邻的场板 (第二 场板 22、 第三场板 23 ) 的前端具有竖直突起， 但第一场板 21与第二场板 22、 第二场板 22与第三场板 23之间的水平距离仍大于零。
本发明尤其适合源漏击穿电压大于 40-50V的 LDMOS器件使用，緩解 了源漏击穿电压与导通电阻的优化要求之间的矛盾， 改善了 LDMOS器件 的性能。
需要注意的是， 本实施方式仅以 3个场板作为举例加以说明， 然而于 现实应用中， 该场板的数量可以视应用环境做调整， 一般情况下只要场板 数量大于 2块， 且其设置方式为以水平方向往漂移延伸， 在水平方向有一 间距， 与漂移区的距离有一高度差， 即为本发明的发明主旨。
本实施例还描述了一种用于制作上述实施例具有阶梯式多重不连续场 板的 LDMOS器件的加工方法， 本实施例中所述加工方法包括如下步骤： 加工半导体本体， 包括栅的形成；
在位于栅的上方于半导体本体表面沉积一个氧化层 31 (如图 5所示 ), 再于氧化层 31上沉积一个导电层板 210 (如图 6所示 ),所述导电层板 210 再经由光刻与腐蚀工艺形成第一场板 21 (如图 7所示）；
紧接着再依次沉积一个氧化层 32 (如图 8所示 ), 再于氧化层 32上沉 积一个导电层板 220 (如图 9所示）， 所述导电层板 220再经由光刻与腐蚀 工艺形成第二场板 22 (如图 10所示）， 该第二场板与第一场板场板间的竖 直间距等于导电层板 220的厚度， 导电层板 220的厚度等于场板的厚度； 本发明中制作的场板数为三个， 重复步骤 3 , 依次沉积氧化层 33和导 电层板， 所述导电层板再经由光刻与腐蚀工艺形成第三场板 23, 最终得到 所需的具有三重场板的 LDMOS器件（如图 11 )。
图 12示出了三类 LDMOS器件的漏漂移区 11中的电场分布， 其中示 出了在恒定栅极电压和最大供电电压下测量的在 P型掺杂沟道区 16和漏漂 移区 11中的 P型外延层 13的表面作为与 N型重掺杂源区的距离 X的函数 的横向电场 E。 其中， 曲线 1表示只有一个场板 LDMOS器件的电场分布， 单场板 LDMOS器件的横向电场 E显示出了第一峰值 A" 和第二峰值 B" , 横向电场 E的第一峰值 A"位于漏漂移区的边缘位置， 而横向电场 E的第 二峰值 B" 位于单个场板水平部分的边缘； 曲线 2表示有两个场板且场板 间有重叠的 LDMOS 器件的电场分布， 有两个场板且场板间有重叠的 LDMOS器件的横向电场 E显示出了第一峰值 A，、 第二峰值 B， 以及第三 峰值 C , 横向电场 E的第一峰值 A， 位于漏漂移区的边缘位置， 而横向电 场 E的第二峰值 B，、 第三峰值 C， 分别位于第一场板水平部分以及第二场 板水平部分的边缘； 曲线 3表示有两个场板且场板间无重叠并且彼此在水 平方向上有一定间距的 LDMOS器件的电场分布， 有两个场板且场板间无 重叠的 LDMOS器件的横向电场 E显示出了第一峰值 A、第二峰值 B以及 第三峰值 C, 横向电场 E的第一峰值 A位于漏漂移区的边缘位置， 而横向 电场 E的第二峰值 B、 第三峰值 C分别位于第一场板水平部分以及第二场 板的边缘。从图 12中我们可以看出，有两个场板且场板间有重叠的 LDMOS 器件的横向电场的第二峰值 B' 比单场板 LDMOS器件的横向电场的第二 峰值 B" 具有更低的值， 但是有两个场板且场板间无重叠的 LDMOS器件 的横向电场的第二峰值 B则比有两个场板且场板间有重叠的 LDMOS器件 的横向电场的第二峰值 B， 的值更低， 另外有两个场板且场板间无重叠的 LDMOS器件的横向电场的第三峰值 C也比有两个场板且场板间有重叠的 LDMOS 器件的横向电场的第三峰值 C 的值更低， 此为有益效果一。 而 且， 有两个场板且场板间无重叠的 LDMOS器件的电场与有两个场板且场 板间有重叠的 LDMOS器件的电场相比，其电场变化更小， 变化更为平緩， 此为有益效果二； 另外， 沿漏漂移区的横向电场分布更为平緩。 对于 LDMOS 器件的横向击穿电压， 上述三个有益效果在不改变漏漂移区掺杂 浓度的情况下有效提高 LDMOS器件的横向击穿电压， 如此， 也就可以再 实现对源漏击穿电压的提高以及导通电阻的优化。
上述实例只为说明本发明的技术构思及特点， 其目的在于让熟悉此项 技术的人是能够了解本发明的内容并据以实施， 并不能以此限制本发明的 保护范围。 凡根据本发明精神实质所做的等效变换或修饰， 都应涵盖在本 发明的保护范围之内。

Claims

权 利 要 求
1、一种具有阶梯式多重不连续场板的 LDMOS器件，包括半导体本体， 半导体本体包括最下层的半导体村底区、 设于半导体村底区上的半导体外 延层以及最上层的半导体介质层， 半导体外延层与半导体介质层之间形成 有沟道区、 漏漂移区， 其特征在于， 半导体介质层内设有沿沟道区延伸的 栅以及从栅朝向漏漂移区的水平方向上依次设置的至少两个场板， 与栅相 邻的第一场板在漏漂移区上具有水平延伸， 其余与栅不相邻的场板均为水 平条状， 场板之间的水平距离大于零， 与第一场板相邻的第二场板与漏漂 移区间的距离大于第一场板水平延伸部分与漏漂移区间的距离， 其余水平 条状场板与漏漂移区间的距离逐次递增。
2、根据权利要求 1所述的具有阶梯式多重不连续场板的 LDMOS器件， 其特征在于， 在位于栅的上方于半导体本体表面沉积有氧化层， 在场板上 方于前一氧化层表面同样沉积有氧化层， 场板间的竖直间距等于氧化层的 厚度， 氧化层的厚度大于等于场板的厚度。
3、根据权利要求 1所述的具有阶梯式多重不连续场板的 LDMOS器件， 其特征在于， 所述至少两个场板均位于半导体本体的漏漂移区的上方。
4、根据权利要求 1所述的具有阶梯式多重不连续场板的 LDMOS器件， 其特征在于， 与栅相邻的第一场板在栅的至少一部分上延伸。
5、根据权利要求 1所述的具有阶梯式多重不连续场板的 LDMOS器件， 其特征在于，所述至少两个场板均可接正负电压或接地用于调节电场电荷。
6、根据权利要求 1所述的具有阶梯式多重不连续场板的 LDMOS器件， 其特征在于，至少两个场板中的与栅不相邻的场板的前端具有 L形的突起， 但场板间的水平距离仍大于零。
7、 一种用于制作如权利要求 1 所述的具有阶梯式多重不连续场板的 LDMOS器件的加工方法， 其特征在于， 所述加工方法包括如下步骤： 加工半导体本体， 包括栅的形成；
在位于栅的上方于半导体本体表面沉积一个氧化层， 再于氧化层上沉 积一个导电层板， 所述导电层板再经由光刻与腐蚀工艺形成第一场板； 紧接着再依次沉积一个氧化层和导电层板， 所述导电层板经由光刻与 腐蚀工艺形成第二场板， 使该第二场板与第一场板在水平方向上具有一定 间距；
根据需要制作的场板的个数重复步骤 3 )。
8、根据权利要求 7所述的具有阶梯式多重不连续场板的 LDMOS器件 的加工方法， 其特征在于， 场板间的竖直间距等于氧化层的厚度， 氧化层 的厚度大于等于场板的厚度。
9、根据权利要求 7所述的具有阶梯式多重不连续场板的 LDMOS器件 的加工方法， 其特征在于， 所述导电层板的导电介质为钛或者钨。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102790086B (zh) * 2012-07-10 2016-03-30 苏州远创达科技有限公司 具有阶梯式多重不连续场板的ldmos器件及制造方法
US9059281B2 (en) 2013-07-11 2015-06-16 International Business Machines Corporation Dual L-shaped drift regions in an LDMOS device and method of making the same
CN104638003B (zh) * 2013-11-14 2019-04-09 上海华虹宏力半导体制造有限公司 射频ldmos器件及工艺方法
CN104733525B (zh) * 2013-12-19 2018-02-06 上海华虹宏力半导体制造有限公司 射频ldmos器件及工艺方法
CN104752512B (zh) * 2015-01-09 2018-11-13 电子科技大学 一种具有多电极结构的横向高压器件
CN106611786A (zh) * 2015-10-23 2017-05-03 苏州远创达科技有限公司 一种mos管器件
US10418480B2 (en) * 2016-03-11 2019-09-17 Mediatek Inc. Semiconductor device capable of high-voltage operation
CN106972060B (zh) * 2017-03-23 2023-05-26 苏州远创达科技有限公司 半导体功率器件
CN107871778B (zh) * 2017-10-30 2020-09-04 济南大学 带有电位浮动型场板的横向双扩散金属氧化物半导体场效应管
CN109980011A (zh) * 2017-12-28 2019-07-05 无锡华润上华科技有限公司 一种半导体器件及其制作方法
CN109411540A (zh) * 2018-10-31 2019-03-01 电子科技大学 具有低比导通电阻的横向高压器件
CN113140635B (zh) * 2020-01-20 2022-09-16 无锡华润上华科技有限公司 半导体器件及其制备方法
CN113675262B (zh) * 2020-05-14 2023-12-05 苏州华太电子技术股份有限公司 应用于半导体器件的场板结构及其制作方法和应用
CN112786685B (zh) * 2021-02-08 2022-10-21 成都芯源系统有限公司 一种具有多阶场板的横向双扩散晶体管及其制造方法
WO2023050085A1 (en) * 2021-09-28 2023-04-06 Innoscience (Suzhou) Technology Co., Ltd. Nitride-based semiconductor device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299437A (zh) * 2007-05-01 2008-11-05 冲电气工业株式会社 场效应晶体管
CN201540894U (zh) * 2009-11-03 2010-08-04 苏州远创达科技有限公司 多重场板ldmos器件
US20110266619A1 (en) * 2010-04-29 2011-11-03 Nxp B.V. Semiconductor transistor comprising two electrically conductive shield elements
CN102790086A (zh) * 2012-07-10 2012-11-21 苏州远创达科技有限公司 具有阶梯式多重不连续场板的ldmos器件及制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279744B2 (en) * 2003-11-14 2007-10-09 Agere Systems Inc. Control of hot carrier injection in a metal-oxide semiconductor device
CN202888188U (zh) * 2012-07-10 2013-04-17 苏州远创达科技有限公司 具有阶梯式多重不连续场板的ldmos器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299437A (zh) * 2007-05-01 2008-11-05 冲电气工业株式会社 场效应晶体管
CN201540894U (zh) * 2009-11-03 2010-08-04 苏州远创达科技有限公司 多重场板ldmos器件
US20110266619A1 (en) * 2010-04-29 2011-11-03 Nxp B.V. Semiconductor transistor comprising two electrically conductive shield elements
CN102790086A (zh) * 2012-07-10 2012-11-21 苏州远创达科技有限公司 具有阶梯式多重不连续场板的ldmos器件及制造方法

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